- Email: [email protected]
Electrical reliability of ultra thin remote plasma deposited oxides on silicon
MICROELECTRONIC ENOINEER,UqO
ELSEVIER
Microelectronic Engineering 36 (1997) 65-67
Electrical Reliability of Ultra Thin Remote Plasma Deposited Oxides on Silicon L-/~. Ragnarsson, P. Lundgren, and A. Jauhialnen Department of Solid State Electronics, Chalmers University of Technology, S-412 96 Gfteborg, Sweden The degradation of ultra thin remote plasma enhanced chemical vapor deposition (RPECVD) oxides during direct tunneling electron injection was studied and compared to that of thermally grown oxides. The deposited oxides were found to detoriate during injection and to recover afterwards in the same way as thermally grown ones. Also found was that the energy loss at the interface of the injected electrons is a much better parameter than the injected current density for estimating the generated charge density.
1.
INTRODUCTION
The electrical characteristics of Metal-Oxide-Silicon (MOS) structures manufactured by depositing the silicon dioxide in a Remote Plasma Enhanced Chemical Vapour Deposition (RPECVD) process have been shown to match those of thermal oxides for the case of oxide thicknesses above -5 nm [1,2]. We now extend the comparison to ultra thin oxides and monitor the degradation of RPECVD oxides during electron injection in the direct tunneling regime. The main conclusion is that the deposited oxides are indistinguishable from thermal ones where the effects of electrical stress at room temperature are concerned. 2.
EXPERIMENTAL
MOS devices were fabricated on <100>, n-type (-5 f~cm) and p-type (-5 f~cm) substrate silicon wafers. A mixture of 15 seem oxygen and 800 seem helium was excited with a plasma power of 250 W to prepare the surface prior to deposition and mixed downstream with a 12 sccm flow of 10% Sill 4 in helium to deposit the SiO 2 film. The substrate temperature was 300 °C and the pressure was 0.4 mbar. Under these conditions the deposition rate was approximately 6 nm/min, and the resulting oxide thicknesses were electrically estimated to -2.5 and -3 nm using the capacitance-voltage (C-V) characteristics. The thickness of the p-type 2.5 nm samples was slightly thinner than the n-type samples. The 0167-9317/97/$17.00 © Elsevier Science B.V. All rights reserved. PII: S0167-9317(97)00016-6
devices were subjected to a 350 °C, 15 minute postmetallization anneal after the aluminum gate evaporation, which is known to improve device integrity[3].
3.
THEORY
Figure 1 schematically depicts the stressing conditions for p-type and n-type substrate devices. In the p-type case the electrons are injected from the aluminum gate and for the n-type devices the electrons are injected from the substrate. Since the potential bartier for hole tunneling is much larger than for the electrons, the transport of the latter ones will constitute the measured current. We have previously shown that the current increase occurring during electrical stress is adequately modeled by assuming that it is proportional to the number of positive charges in the oxide. This assumption was verified by correlating measures of the C-V shift with the current increase in ultra thin thermal oxides[4]. The influence of a point charge on the current is due to the local modification of the potential barrier in the vicinity of the ion. A first order approximation validates the use of the fractional increase in current density AI/J o as a voltage independent measure of the charge density per unit area in the oxide: Let ~ denote a local effective barrier height for tunneling, modified by the voltage and locally modified by the presence of an ion in the oxide, so that: OF(p) : • 0 - AOv(V ) - AOion(P) '
66
L.-A. Ragnarsson et al. / Microelectronic Engineering 36 (1997) 65-67
where AOion is due to the ion, p is the lateral distance from the ion in a plane parallel to the Si--SiO 2 interface and V is the applied voltage. From the super-position principle the influence of the ion on the effective barrier is independent on the voltage drop over the oxide. The current is approximately exponentially dependent on the square root of the barrier height [5]:
metal or semiconductor after tunneling is marked in figure 1 as Ein t. We estimate the loss according to: Eim = Iqvgl
(n-type)
Ein t = IqVgl - E c
(p-type)
for n- and p-type samples respectively. E G is the (2)
J - e -at°x 4r~F,
silicon
~
where tox is the oxide thickness and (z -
2 22 - i h
bandgap
,
energy.
Direct electron
tunneling
. . . . .
(3)
qV
where fi is Plancks constant and m.1 is the effective mass of the tunneling electron. A first order expansion, assuming that AOv and AtI)ion are sufficiently small compared to D 0 gives: ( a . to x
( ~
Eint AI SiO 2 p-Si
\
AI
SIO21n-Si
/
/
A(I)ion'~'~
J- e
(4)
With Jo being the current for AtI)ion= 0 we have:
Figure 1) Schematic band diagrams of electrical stressing conditions.
At~ion
j
~tox
4.
2,/~,,
- - -- e
,
Jo which is voltage independent. The excess current, Alion, through the local area, AA, where the ion has significant impact can then be expressed by integrating the current density over this area and subtracting the current for the ion-free case:
A/ion = Jo
l,
ct. tox • 2 ~ o
""
e
~.AA
)
d p d g - AA ,
(6)
which is the same as A/ion = Jo C ,
(7)
where C is a voltage independent constant which depends on where in the oxide the ion appears [5]. W i t h nOT being the area densit X of ions and assuming that the mean value of C, C, is independent of nOT the total excess current density due to the ions is:
AJ = n o r J o C
or
RESULTS AND DISCUSSION
(5)
AJ
j---~*, n o r
(8)
independent of the applied voltage. The energy loss for an electron emerging into the
The devices were stressed at room temperature with applied voltages in the range 1 V to 2.7 V for ntype and -2 V to -3.7 V for p-type samples. Also included in the study were -2.5 nm thermally grown oxides. Since no significant differences between the deposited and thermal oxides could be found, we make no distinction between the two types in figures 2 and 3. The current was measured with an HP4140 pA meter during the stress. In figure 2 the time in seconds needed to induce a fractional increase of the current, A J / J o , of ~5%, is plotted versus the initial current density, J0- From the figure it is clear that for a given device type, the time needed to create a specific amount of charge decreases with increasing current. However, it is also clear that for a given time, the current needed to create the same amount of charge spans as much as six decades in magnitude for the different devices. This further stresses the previously found result[6] that, whether injected from the Si--SiO 2 or the AI--SiO 2 interface, the current is not a viable parameter for determining the created amount of positive oxide charge after a given time of stress.
L.-.4. Ragnarsson et al. / Microelectronic Engineering 36 (1997) 65-67
the relaxation time, as has been observed previously [7] and the deposited and thermally grown oxides have very similar relaxation dynamics. Additional measurements are needed to verify this for n-type devices as well.
to 10 4
~
67
103
f
~
m
,
~ t
,_, 1 . 1 |
........ , ,
'"'"1
'
''"'"1
'
''"'"1
'
''"'"1
........
.
o
8 10 -7
10 "~
0.001
0.1
10
do(Ncm2)
~ 0.8
Figure 2) Stress time versus Jo for AJ/J o = 0.05.
am
•
[] o
•
~" 0.7 ~/
In figure 3, the time needed to induce the same amount of charge as above is shown as a function of the electron energy loss (Eint) at the interface. From the figure, it is evident that a higher energy loss at the Si--SiO 2 or the AI--SiO 2 interface is correlated to a decrease in the time needed to create the same amount of oxide charge, and that Ein t is a much better parameter for determining the generated charge density. This holds for all included components, regardless of their thickness or whether the injection is from the gate or the silicon.
tO 10 4 0
0
,,,i,,,,i,,,,i,,,,i,,,,i,,,,=.= =
...°1 0
0
10 2 '-
[] •
" 0 .~ 10 r • "-
1 I , .... ,,,I,, 0 0.5
•
1. o p3nrfi-~0 3nm i'm p2.5nm [3-~r-I.Eiil~. n2.5nm 0
-i " ,
y! , , I , , , , I , , , , I , , ,
:
1
1.5 2 Eint(ev)
2.5
3
06
"
10 "1
........' 10 °
H.,,I
101
, ,,,,,.,I
, ,,,,,,J
102
, ,,~,,,,I
.....
103 104
10 s
Time (s)
Figure 4) Normalized current relaxation measured at -1.7 V after 500 s of stress at -3 V for various devices with p-type substrates. The temperature was 150 K. J(t) is the current during relaxation, Jo is the steadystate current at -1.7 V before stressing and to is a reference time, here set to 1 s. Filled symbols correspond to deposited oxides and open symbols to thermally grown ones. 5.
CONCLUSIONS
In conclusion, we have studied the degradation of ultra thin RPECVD oxides during direct tunneling electron injection from either substrate or gate; effects which give rise to an increase in the net amount of unstable positive charge in the oxide layer. The manner in which the charging and relaxation occurs is virtually indistinguishable from previously and presently observed phenomena in thermally grown oxides of the same thicknesses.
Figure 3) StresstimeversusEintfor&J/Jo=O.05.
REFERENCES
When interrupting the stressing, the positive charge is partly neutralized for the p-type devices. Figure 4 addresses the relaxation in current after electrical stress towards its pre-stress value at the non-stressing voltage of -1.7 V. The excess current, J(t)-J o, has been normalized to an early value of the excess current, J(t=l s)-J 0, in order to show the similarity in relaxation dynamics for the various devices, independent of differences in current increase after stress. As is evident from the figure, the fractional recovery goes approximately logarithmically with
1. D. R. Lee et al., Microel. Eng. 28, 117 (1995). 2. C. G. Parker et al., Microel. Eng. 28, 137 (1995). 3. L-/~ Ragnarsson et al., Proc. MRS fall meeting, Boston 1996. 4. P. Lundgren et al., Mieroel. Eng. 28, 67 (1995). 5. F. W. Schmidlin, J. Appl. Phys. 37, 2823 (1966). 6. K. R. Farmer et al., Appl. Phys. Lett. 60, 730 (1992). 7. P. Lundgren et al., J. Non-Crystalline Solids 187, 140 (1995).
ELSEVIER
Microelectronic Engineering 36 (1997) 65-67
Electrical Reliability of Ultra Thin Remote Plasma Deposited Oxides on Silicon L-/~. Ragnarsson, P. Lundgren, and A. Jauhialnen Department of Solid State Electronics, Chalmers University of Technology, S-412 96 Gfteborg, Sweden The degradation of ultra thin remote plasma enhanced chemical vapor deposition (RPECVD) oxides during direct tunneling electron injection was studied and compared to that of thermally grown oxides. The deposited oxides were found to detoriate during injection and to recover afterwards in the same way as thermally grown ones. Also found was that the energy loss at the interface of the injected electrons is a much better parameter than the injected current density for estimating the generated charge density.
1.
INTRODUCTION
The electrical characteristics of Metal-Oxide-Silicon (MOS) structures manufactured by depositing the silicon dioxide in a Remote Plasma Enhanced Chemical Vapour Deposition (RPECVD) process have been shown to match those of thermal oxides for the case of oxide thicknesses above -5 nm [1,2]. We now extend the comparison to ultra thin oxides and monitor the degradation of RPECVD oxides during electron injection in the direct tunneling regime. The main conclusion is that the deposited oxides are indistinguishable from thermal ones where the effects of electrical stress at room temperature are concerned. 2.
EXPERIMENTAL
MOS devices were fabricated on <100>, n-type (-5 f~cm) and p-type (-5 f~cm) substrate silicon wafers. A mixture of 15 seem oxygen and 800 seem helium was excited with a plasma power of 250 W to prepare the surface prior to deposition and mixed downstream with a 12 sccm flow of 10% Sill 4 in helium to deposit the SiO 2 film. The substrate temperature was 300 °C and the pressure was 0.4 mbar. Under these conditions the deposition rate was approximately 6 nm/min, and the resulting oxide thicknesses were electrically estimated to -2.5 and -3 nm using the capacitance-voltage (C-V) characteristics. The thickness of the p-type 2.5 nm samples was slightly thinner than the n-type samples. The 0167-9317/97/$17.00 © Elsevier Science B.V. All rights reserved. PII: S0167-9317(97)00016-6
devices were subjected to a 350 °C, 15 minute postmetallization anneal after the aluminum gate evaporation, which is known to improve device integrity[3].
3.
THEORY
Figure 1 schematically depicts the stressing conditions for p-type and n-type substrate devices. In the p-type case the electrons are injected from the aluminum gate and for the n-type devices the electrons are injected from the substrate. Since the potential bartier for hole tunneling is much larger than for the electrons, the transport of the latter ones will constitute the measured current. We have previously shown that the current increase occurring during electrical stress is adequately modeled by assuming that it is proportional to the number of positive charges in the oxide. This assumption was verified by correlating measures of the C-V shift with the current increase in ultra thin thermal oxides[4]. The influence of a point charge on the current is due to the local modification of the potential barrier in the vicinity of the ion. A first order approximation validates the use of the fractional increase in current density AI/J o as a voltage independent measure of the charge density per unit area in the oxide: Let ~ denote a local effective barrier height for tunneling, modified by the voltage and locally modified by the presence of an ion in the oxide, so that: OF(p) : • 0 - AOv(V ) - AOion(P) '
66
L.-A. Ragnarsson et al. / Microelectronic Engineering 36 (1997) 65-67
where AOion is due to the ion, p is the lateral distance from the ion in a plane parallel to the Si--SiO 2 interface and V is the applied voltage. From the super-position principle the influence of the ion on the effective barrier is independent on the voltage drop over the oxide. The current is approximately exponentially dependent on the square root of the barrier height [5]:
metal or semiconductor after tunneling is marked in figure 1 as Ein t. We estimate the loss according to: Eim = Iqvgl
(n-type)
Ein t = IqVgl - E c
(p-type)
for n- and p-type samples respectively. E G is the (2)
J - e -at°x 4r~F,
silicon
~
where tox is the oxide thickness and (z -
2 22 - i h
bandgap
,
energy.
Direct electron
tunneling
. . . . .
(3)
qV
where fi is Plancks constant and m.1 is the effective mass of the tunneling electron. A first order expansion, assuming that AOv and AtI)ion are sufficiently small compared to D 0 gives: ( a . to x
( ~
Eint AI SiO 2 p-Si
\
AI
SIO21n-Si
/
/
A(I)ion'~'~
J- e
(4)
With Jo being the current for AtI)ion= 0 we have:
Figure 1) Schematic band diagrams of electrical stressing conditions.
At~ion
j
~tox
4.
2,/~,,
- - -- e
,
Jo which is voltage independent. The excess current, Alion, through the local area, AA, where the ion has significant impact can then be expressed by integrating the current density over this area and subtracting the current for the ion-free case:
A/ion = Jo
l,
ct. tox • 2 ~ o
""
e
~.AA
)
d p d g - AA ,
(6)
which is the same as A/ion = Jo C ,
(7)
where C is a voltage independent constant which depends on where in the oxide the ion appears [5]. W i t h nOT being the area densit X of ions and assuming that the mean value of C, C, is independent of nOT the total excess current density due to the ions is:
AJ = n o r J o C
or
RESULTS AND DISCUSSION
(5)
AJ
j---~*, n o r
(8)
independent of the applied voltage. The energy loss for an electron emerging into the
The devices were stressed at room temperature with applied voltages in the range 1 V to 2.7 V for ntype and -2 V to -3.7 V for p-type samples. Also included in the study were -2.5 nm thermally grown oxides. Since no significant differences between the deposited and thermal oxides could be found, we make no distinction between the two types in figures 2 and 3. The current was measured with an HP4140 pA meter during the stress. In figure 2 the time in seconds needed to induce a fractional increase of the current, A J / J o , of ~5%, is plotted versus the initial current density, J0- From the figure it is clear that for a given device type, the time needed to create a specific amount of charge decreases with increasing current. However, it is also clear that for a given time, the current needed to create the same amount of charge spans as much as six decades in magnitude for the different devices. This further stresses the previously found result[6] that, whether injected from the Si--SiO 2 or the AI--SiO 2 interface, the current is not a viable parameter for determining the created amount of positive oxide charge after a given time of stress.
L.-.4. Ragnarsson et al. / Microelectronic Engineering 36 (1997) 65-67
the relaxation time, as has been observed previously [7] and the deposited and thermally grown oxides have very similar relaxation dynamics. Additional measurements are needed to verify this for n-type devices as well.
to 10 4
~
67
103
f
~
m
,
~ t
,_, 1 . 1 |
........ , ,
'"'"1
'
''"'"1
'
''"'"1
'
''"'"1
........
.
o
8 10 -7
10 "~
0.001
0.1
10
do(Ncm2)
~ 0.8
Figure 2) Stress time versus Jo for AJ/J o = 0.05.
am
•
[] o
•
~" 0.7 ~/
In figure 3, the time needed to induce the same amount of charge as above is shown as a function of the electron energy loss (Eint) at the interface. From the figure, it is evident that a higher energy loss at the Si--SiO 2 or the AI--SiO 2 interface is correlated to a decrease in the time needed to create the same amount of oxide charge, and that Ein t is a much better parameter for determining the generated charge density. This holds for all included components, regardless of their thickness or whether the injection is from the gate or the silicon.
tO 10 4 0
0
,,,i,,,,i,,,,i,,,,i,,,,i,,,,=.= =
...°1 0
0
10 2 '-
[] •
" 0 .~ 10 r • "-
1 I , .... ,,,I,, 0 0.5
•
1. o p3nrfi-~0 3nm i'm p2.5nm [3-~r-I.Eiil~. n2.5nm 0
-i " ,
y! , , I , , , , I , , , , I , , ,
:
1
1.5 2 Eint(ev)
2.5
3
06
"
10 "1
........' 10 °
H.,,I
101
, ,,,,,.,I
, ,,,,,,J
102
, ,,~,,,,I
.....
103 104
10 s
Time (s)
Figure 4) Normalized current relaxation measured at -1.7 V after 500 s of stress at -3 V for various devices with p-type substrates. The temperature was 150 K. J(t) is the current during relaxation, Jo is the steadystate current at -1.7 V before stressing and to is a reference time, here set to 1 s. Filled symbols correspond to deposited oxides and open symbols to thermally grown ones. 5.
CONCLUSIONS
In conclusion, we have studied the degradation of ultra thin RPECVD oxides during direct tunneling electron injection from either substrate or gate; effects which give rise to an increase in the net amount of unstable positive charge in the oxide layer. The manner in which the charging and relaxation occurs is virtually indistinguishable from previously and presently observed phenomena in thermally grown oxides of the same thicknesses.
Figure 3) StresstimeversusEintfor&J/Jo=O.05.
REFERENCES
When interrupting the stressing, the positive charge is partly neutralized for the p-type devices. Figure 4 addresses the relaxation in current after electrical stress towards its pre-stress value at the non-stressing voltage of -1.7 V. The excess current, J(t)-J o, has been normalized to an early value of the excess current, J(t=l s)-J 0, in order to show the similarity in relaxation dynamics for the various devices, independent of differences in current increase after stress. As is evident from the figure, the fractional recovery goes approximately logarithmically with
1. D. R. Lee et al., Microel. Eng. 28, 117 (1995). 2. C. G. Parker et al., Microel. Eng. 28, 137 (1995). 3. L-/~ Ragnarsson et al., Proc. MRS fall meeting, Boston 1996. 4. P. Lundgren et al., Mieroel. Eng. 28, 67 (1995). 5. F. W. Schmidlin, J. Appl. Phys. 37, 2823 (1966). 6. K. R. Farmer et al., Appl. Phys. Lett. 60, 730 (1992). 7. P. Lundgren et al., J. Non-Crystalline Solids 187, 140 (1995).