- Email: [email protected]
Electrochemical polishing of monocrystalline silicon with specific crystallographic planes
Materials Science in Semiconductor Processing 67 (2017) 8–13
Contents lists available at ScienceDirect
Materials Science in Semiconductor Processing journal homepage: www.elsevier.com/locate/mssp
Electrochemical polishing of monocrystalline silicon with specific crystallographic planes
MARK
⁎
Chen Haoran, Liu Zhidong , Shen Lida, Qiu Mingbo, Tian Zongjun, Ge Mengxing College of Mechanical and Electrical Engineering, Nanjing University of Aeronautics and Astronautics, YuDao Street, 210016 Nanjing, China
A R T I C L E I N F O
A B S T R A C T
Keywords: Monocrystalline silicon Electrochemical polishing Influence factor Polishing characteristic
In this study, an electrolytic polishing experimental system was developed to obtain a uniform, flat-surfaced monocrystalline silicon with specific crystallographic planes. Several key factors reflecting specific electrolytic polishing on monocrystalline silicon with specific crystallographic planes were summarized. These factors, including electrolyte, conduction mode, Schottky barrier, semiconductor body resistance, and unidirectional conductivity, were analyzed comprehensively through energy spectrum analysis, theoretical modeling, and potential simulation. The effects of electrolytic polishing process were obtained, and corresponding solutions were proposed. Finally, the electrolytic polishing experiment for monocrystalline silicon with specific crystallographic planes was conducted. A uniform, flat-surfaced monocrystalline silicon with no metamorphic layer was then obtained. The flatness error of the center area was less than 0.201 µm. Furthermore, the crystallographic planes of monocrystalline silicon wafers showed no change.
1. Introduction With the development and progress of modern science and technology, monocrystalline silicon has been widely used in optical detection. The core components of hard X-ray calibration device [1], single crystal X-ray diffractometer [2], LIGA [3], and other devices are made of monocrystalline silicon with specific crystallographic planes. The surface quality of silicon wafers directly affects the performance and life of optical devices. WEDM is an important means of specific crystallographic plane cutting, which presents no mechanical force in machining and can process silicon wafers with accurate crystal orientation. However, WEDM is a combination of thermal explosive force, magnetic fluid power, and fluid power [4], which will inevitably cause damages, such as discharge craters, cracks, residual stresses, and lattice distortions on silicon wafers [5]. The damaged layer and any small change in the physical and chemical properties of the surface can cause scraps on silicon devices; consequently, the damaged layer can seriously affect device performance [6]. The surface of single crystal silicon wafer without damage needs follow-up grinding and polishing, which remove the metamorphic layer. At present, chemical mechanical polish (CMP) technology is unsuitable for polishing silicon with nonplanar surfaces. The electrolytic polishing is more practical, and it suits nonplanar surface polishing, although which has few applications for silicon crystal material. In this paper, the electrolytic polishing process for monocrystalline
⁎
silicon is discussed. This paper provides a theoretical and practical basis for a good and fast removal of metamorphic layers of semiconductor materials. 2. Experiment device and process parameters An electrolytic polishing experiment system was developed. The schematic diagram is shown in Fig. 1. The workpiece is often horizontally placed and immersed in electrolyte during electrochemical machining. In this study, the workpiece is used in an upright position, as shown in Fig. 1, to facilitate a timely electrolytic product flushing away from the machining area and ensure the purity of the electrolytic surface and an efficient and sustainable electrochemical reaction. The locating device of liquid pipe can be adjusted freely in a vertical plane position. The position can be changed between the liquid pipe and the center of interelectrode gap. The machining voltage in this experiment is 90 V. When interelectrode gap, current density, and contrast experiment results are taken into consideration, the electrolyte pressure is 0.1 MPa. The main processing parameters are shown in Table 1. 3. Specific electrochemical polishing for semiconductors The characteristics of semiconductor materials are taken into consideration during electrolytic polishing. These characteristics in-
Correspondence to: College of Mechanical and Electrical Engineering, Nanjing University of Aeronautics and Astronautics, No. 345, 210016 Nanjing, China. E-mail address: [email protected] (L. Zhidong).
http://dx.doi.org/10.1016/j.mssp.2017.04.027 Received 7 February 2017; Received in revised form 21 March 2017; Accepted 26 April 2017 1369-8001/ © 2017 Elsevier Ltd. All rights reserved.
Materials Science in Semiconductor Processing 67 (2017) 8–13
C. Haoran et al.
ClSi4+
H2
H+ Na+ F-
Copper
P-type crystalline silicon Conduction part
Fig. 1. Schematic diagram of an electrolytic polishing experiment system.
Fig. 4. Schematic diagram of the electrochemical reaction. Table 1 Electrolytic processing parameters. Parameter
Parameter value
Polarity Workpiece material Cathode materials Interelectrode gap Current density Processing time Electrolyte temperature Electrolyte pressure Dielectric fluid
Workpiece (+) 1.2 Ω cm P-type monocrystalline silicon Pure copper 1 mm 4 A/cm2 10 min 25 °C 0.1 MPa 4%NaCl+92%H2O +4%NaF
spectrum (Fig. 3) confirmed that the white precipitate is silicon fluoride and can dissolve in solutions. Thus, F is involved in the electrolytic process. NaCl is added to improve the electrical conductivity of the solution and utilization rate of power supply and to enhance the reaction efficiency. In addition, NaCl electrolyte contains active ions Cl−, which can cause the difficulty in generating passivation membrane. This study used electrolytic polishing of semiconductor, which presents characteristics regarding electricity and electrode reaction. Electrochemical reaction that occurred during electrolytic polishing will be presented to further understand the electrolytic polishing process. Fig. 4 shows the schematic diagram of the electrochemical reaction that occurred during electrolytic polishing of monocrystalline silicon according to the electrolyte formula, coupled with an anode material (monocrystalline silicon). The reaction on the two poles will be discussed separately, and the corresponding standard electrode potential value will be illustrated. The electrode reaction at the anode side and the corresponding standard electrode potential value are as follows: Si ⇋ Si4+ + 4e
E°SiO2/Si = −0.84 V
2Cl−–2e ⇋ Cl2↑
E°Cl2/Cl− = +1.3583 V
2F−–2e ⇋ F2↑
E°F2/F− = +2.87 V
The value of E°SiO2/Si is the lowest among values. Thus, the electrode reaction in which single crystal silicon is dissolved will most probably occur in the anode. Similarly, the possible electrode reactions and corresponding standard electrode potential values at the cathode side are shown below.
Fig. 2. Classification diagram of specific electrochemical polishing for semiconductors.
clude the presence of a specific electrolyte, passivation phenomenon on the electricity side during the electrolytic process, semiconductor body resistance, and unidirectional conductivity (Fig. 2).
2H++2e⇋H2↑
E°H+/H2=0 V
3.1. Specific electrolyte
Na++e⇋Na
E°Na+/Na=−2.713 V
The electrolyte contains 40 g/L sodium fluoride and sodium chloride. Extensive experimental verification showed that F ion can effectively remove monocrystalline silicon and separate white precipitates at the silicon surface (anode). Analysis of this silicon layer via energy
E°H+/H2 exceeds E°Na+/Na by about 2.7 V, which is a large difference in electrode potential. Therefore, only hydrogen escapes at the cathode rather than the electrode reaction of sodium deposition. On the basis of above analysis, two basic chemical reaction
Fig. 3. Energy spectrum analysis of the precipitation product at the anode.
9
Materials Science in Semiconductor Processing 67 (2017) 8–13
C. Haoran et al.
Dc
Dsm1
R¦Ä Dsm2
Rl
Fig. 5. Equivalent circuit model of silicon electrochemical polishing. Fig. 8. Explosive view of the fixture.
electrolyte
P-type crystalline silicon
copper
metal into electricity Fig. 9. Temperature change curve of monocrystalline silicon during electrolytic polishing. Fig. 6. Principle diagram of the current loop of silicon electrochemical polishing.
electrolyte
P-type crystalline silicon
copper
metal into electricity
Fig. 10. Diagram of validation experiment for unidirectional conductivity.
Fig. 7. Chemical reaction diagram for the into electricity side.
contact barrier formed by junction of monocrystalline silicon and metal into electricity, which is shown as a schottky diode [7]. The body resistance of semiconductor materials is shown as the variable resistance Rδ. During the electrolytic process, electrolyte contains a large number of anions and cations, which move along a certain direction under an applied electric field. To simplify the electrolytic model, the interface between the semiconductor and electrolyte can be the same as the Schottky diode (Dsm2). The double-electric layer potential formed on the semiconductor/solution interface can be used with a Zener diode Dc [8]. The resistance of the electrolyte is expressed with a variable resistance R1. The principle diagram of the current circuit is shown in Fig. 6. The effect of into the electricity side on the electrolytic polishing mainly reflects on the two aspects which is the potential distribution and the passivation phenomenon on the into electricity side. To
equations can be used to express the whole reaction process: Si+4F−+2H+→SiF4↑+H2↑
(1)
SiO2+4F−+4H+→SiF4↑+2H2O
(2)
When the surface of single crystal silicon after WEDM is mainly composed of silicon oxide during electrolytic process, the main chemical reaction is shown in Eq. (2). When the electrolytic reaction is in the matrix, the main chemical reaction is shown in Eq. (1). 3.2. Electricity The equivalent circuit model for electrolytic polishing of monocrystalline silicon can be established, as shown in Fig. 5. Dsm1 is the 10
Materials Science in Semiconductor Processing 67 (2017) 8–13
C. Haoran et al.
Fig. 14. SEM photograph of the monocrystalline silicon surface.
Fig. 11. V–ampere characteristic curve.
Fig. 15. EDS analysis report.
maintained to avoid electrical passivation. In this study, the into electric device produced by 3D printing exhibits a good sealing characteristic, which makes it durable. Consequently, electrical passivation is avoided. This experiment also used 3D printing to create workpiece fixtures. The explosion picture of the fixture (Fig. 8) is fabricated with a 3D software to present a good display of various parts. The prominent area of the thin copper is connected with one end of the wire, and copper is fixed in the groove, which is in the middle of the workpiece holder. Subsequently, the monocrystalline silicon is sealed with a waterproof tape. After that press it in the groove which is in the middle of the workpiece holder and firmly compacted with copper.
Fig. 12. Schematic diagram of the crystal orientation measurement position.
guarantee the uniformity of electrolytic polishing, each polishing surface should have the same potential. Potential simulation showed that different ways of the contact on the into electricity side has a huge effect on the potential distribution. The body resistance of monocrystalline silicon causes a non-uniform potential distribution on its surface during electrolytic polishing, which directly results in an uneven electrolytic polishing surface. This experiment used the characteristics of copper with monocrystalline silicon samples that are all fit to avoid the above problem effectively. Passivation phenomenon on the into electricity side is common during semiconductor fabrication. On the EDM of semiconductor, the workpiece must be in contact with the metal to form a processing circuit, and the electric copper brush and semiconductor should fit closely. However, no mutual movement is observed. When electrical discharge machining is continued, the electrochemical reactions constantly occur on the electric copper brush and workpiece under an external power source (Fig. 7). A high resistivity passivation membrane, which interrupts the process, is produced on the surface of the silicon and copper brush. In the electrolytic polishing process, reasonable means of sealing should be used. The electricity side must be dry, and the value of the current should be controlled. Moreover, a good contact between the monocrystalline silicon material and the into electricity side must be
3.3. Body resistance Semiconductor body resistance changes mainly with change in processing temperature. This change will significantly affect the value of the machining current, thereby the significant effect on electrolytic polishing efficiency. During the experiment, the thermocouple probe is placed into the gap between the monocrystalline silicon and the copper into electricity using the multichannel temperature monitor (Thermocouple Thermometer with Datalogger 4ch), as shown in Fig. 9. Consequently, the temperature of monocrystalline silicon samples during electrolytic polishing is monitored real-time. The monitored data are shown in a continuous variation graph in Fig. 9. The body resistance reduces, and the machining current increases during electrolytic polishing when the single crystal silicon sample temperature gradually increases. The voltage must be reduced to
Fig. 13. Change in crystal orientation of monocrystalline silicon samples in different positions before and after polishing.
11
Materials Science in Semiconductor Processing 67 (2017) 8–13
C. Haoran et al.
Fig. 16. Summary of flatness measurement for the whole polished surface and adjacent area of monocrystalline silicon.
wafers should be verified. In this experiment, three different positions on monocrystalline silicon surface (Fig. 12) before and after the electrolytic polishing are measured using X-ray crystal orientation instrument. Data summary is shown in Fig. 13. The crystal orientation of the monocrystalline silicon surface in three different positions changes within 3′ (the allowed error value) before and after electrolytic polishing. Thus, electrolytic polishing exerts no effect on the crystal orientation of monocrystalline silicon wafer. On the basis of the proposed electrolytic polishing of single crystal silicon using the optimization parameters, a uniform brightness in the center area of monocrystalline silicon surface is finally obtained. To facilitate the comparison with the surface morphology of monocrystalline silicon before and after electrolytic polishing, the SEM photograph for the transitional position of monocrystalline silicon surface after electrolytic polishing (Fig. 14) is taken. The monocrystalline silicon surface is considerably smooth and uniform after electrolytic polishing. However, intensive discharge holes caused by WEDM processing are present on the region without electrolytic polishing. Further analysis of the EDS (Fig. 15) showed that Si content on the single crystal silicon surface after electrolytic polishing reaches 95.56%, and the O content is only 4.44%. SiF4 generated in the electrolytic polishing exhibits a high moisture absorption rate. Therefore, a timely cleaning and drying of monocrystalline silicon after electrolytic polishing, which can effec-
maintain the stability of the current density, or electrolytic time must be controlled in a reasonable range to effectively avoid surface quality problem caused by the increased processing current. 3.4. Unidirectional conductivity The diagram of validation experiment for unidirectional conductivity is shown in Fig. 10. The p-type semiconductor is used in the experiment. Current change is detected through voltage adjustment and polarity change to analyze the unidirectional conductivity of the p-type silicon. The volt–ampere characteristic curve for the p-type monocrystalline silicon is shown in Fig. 11. When the p-type monocrystalline silicon is used as the anode, the current is significantly increased with increasing voltage. When p-type monocrystalline silicon is used as cathode, the current increases slowly when the voltage increases gradually. This result confirmed that semiconductor possesses a unidirectional conductivity during the electrolytic process. 4. Actual application effect Monocrystalline silicon with specific crystal orientation is widely used in aerospace and optical fields; thus, whether electrolytic polishing method will change the crystal orientation of monocrystalline silicon 12
Materials Science in Semiconductor Processing 67 (2017) 8–13
C. Haoran et al.
silicon wafer surface before and after electrolysis process using the method of X-ray back swing curve is used [9]. Values of 53 and 0 µm were obtained before and after the electrolytic process, respectively. On the basis of fixed-point electrolytic polishing, the characteristics of monocrystalline silicon during electrolytic polishing were investigated. Electrolytic polishing should be further studied to explore the ratio of electrolytes, monocrystalline silicon characteristics, power supply, control strategy, and other factors affecting the polishing process. Furthermore, polishing of the whole surface of monocrystalline silicon should be comprehensively researched. 5. Conclusions 1. The specific electrochemical polishing of monocrystalline silicon, which affects electric field, flow field, specific electrolyte, the into electricity theory [10], body resistance, and unidirectional conductivity, should be considered for a uniform polishing of monocrystalline silicon. 2. Electrolytic polishing can effectively remove the metamorphic layer of monocrystalline silicon surface caused by WEDM. 3. Results show that electrolytic polishing cannot change the crystal orientation of silicon wafer surface. 4. Under the experimental conditions of this study, a monocrystalline silicon polishing surface with no metamorphic layer is obtained. The flatness error of the central area is less than 0.201 µm. Acknowledgement The project is supported by the National Natural Science Foundation of China (Grant No. U1532106, No. 51675272, No. 51575271, No. 11275274), Funding of Jiangsu Innovation Program for Graduate Education (“the Fundamental Research Funds for the Central Universities”) (Grant No. KYLX15_0291). We also extend our sincere thanks to all who contributed in the preparation of these instructions.
Fig. 17. 3D morphology comparison chart.
tively avoid F contamination, are important. To further illustrate the surface flatness of silicon samples after electrolytic process, the flatness measurement should be used from both global and local viewpoints. Fig. 16 presents the summary of measurement results. After electrolytic polishing, the longitudinal and transverse flatness of silicon samples is at 200 nm, which is significantly decreased compared with the surface flatness of both ends that are not polished. Among them, the transverse measurement of polished surface in the range of 2–6.5 mm shows higher flatness and variation range of less than 150 nm. The 3D morphology changes before and after electrolytic polishing on the same area of single crystal silicon surface were observed and recorded, as shown in Fig. 17. The surface without electrolysis process presents an uneven surface because of the large amounts of discharge holes. The largest flatness error is 26.684 µm. Nevertheless, the overall surface after electrolysis is considerably smooth, and the maximum error of flatness is 0.812 µm. The flatness error of the central area is less than 0.201 µm. Finally, the metamorphic layer thickness measurement for the
References [1] [2] [3] [4] [5] [6] [7] [8] [9] [10]
13
X. Zhou, X.Q. Li, Y.N. Xie, et al., Exp. Astron. 38 (3) (2014) 433–441. J. Słowik, A. Zięba, Nucl. Instrum. Methods Phys. Res. 551 (1) (2005) 73–77. C.K. Malek, V. Saile, Microelectron. J. 35 (2) (2004) 131–143. M.H. Li, The Theoretical Basis of Electrical Discharge Machining, National Defense Industry Press, Beijing, 1989, pp. 25–30. Z.D. Liu, W. Wang, M.B. Qiu, et al., Acta Energiae Sol. Sin. 30 (5) (2009) 619–623. U. Bismayer, E. Brinksmeier, B. Guttler, et al., Precis. Eng. 16 (2) (1994) 139–143. Haoran Chen, Zhidong Liu, et al., Mater. Sci. Semicond. Process. 32 (2015) 125–130. Liu Zhidong, Non-Traditional Machining, Peaking University Press, 2013. Mengxing Ge, Zhidong Liu, Lida Shen, et al., J. Mater. Sci.: Mater. Electron. (2016). Liu Zhidong, Cao Yinfeng, Qiu Mingbo, et al., China Mech. Eng. 23 (6) (2012) 725–728.
Contents lists available at ScienceDirect
Materials Science in Semiconductor Processing journal homepage: www.elsevier.com/locate/mssp
Electrochemical polishing of monocrystalline silicon with specific crystallographic planes
MARK
⁎
Chen Haoran, Liu Zhidong , Shen Lida, Qiu Mingbo, Tian Zongjun, Ge Mengxing College of Mechanical and Electrical Engineering, Nanjing University of Aeronautics and Astronautics, YuDao Street, 210016 Nanjing, China
A R T I C L E I N F O
A B S T R A C T
Keywords: Monocrystalline silicon Electrochemical polishing Influence factor Polishing characteristic
In this study, an electrolytic polishing experimental system was developed to obtain a uniform, flat-surfaced monocrystalline silicon with specific crystallographic planes. Several key factors reflecting specific electrolytic polishing on monocrystalline silicon with specific crystallographic planes were summarized. These factors, including electrolyte, conduction mode, Schottky barrier, semiconductor body resistance, and unidirectional conductivity, were analyzed comprehensively through energy spectrum analysis, theoretical modeling, and potential simulation. The effects of electrolytic polishing process were obtained, and corresponding solutions were proposed. Finally, the electrolytic polishing experiment for monocrystalline silicon with specific crystallographic planes was conducted. A uniform, flat-surfaced monocrystalline silicon with no metamorphic layer was then obtained. The flatness error of the center area was less than 0.201 µm. Furthermore, the crystallographic planes of monocrystalline silicon wafers showed no change.
1. Introduction With the development and progress of modern science and technology, monocrystalline silicon has been widely used in optical detection. The core components of hard X-ray calibration device [1], single crystal X-ray diffractometer [2], LIGA [3], and other devices are made of monocrystalline silicon with specific crystallographic planes. The surface quality of silicon wafers directly affects the performance and life of optical devices. WEDM is an important means of specific crystallographic plane cutting, which presents no mechanical force in machining and can process silicon wafers with accurate crystal orientation. However, WEDM is a combination of thermal explosive force, magnetic fluid power, and fluid power [4], which will inevitably cause damages, such as discharge craters, cracks, residual stresses, and lattice distortions on silicon wafers [5]. The damaged layer and any small change in the physical and chemical properties of the surface can cause scraps on silicon devices; consequently, the damaged layer can seriously affect device performance [6]. The surface of single crystal silicon wafer without damage needs follow-up grinding and polishing, which remove the metamorphic layer. At present, chemical mechanical polish (CMP) technology is unsuitable for polishing silicon with nonplanar surfaces. The electrolytic polishing is more practical, and it suits nonplanar surface polishing, although which has few applications for silicon crystal material. In this paper, the electrolytic polishing process for monocrystalline
⁎
silicon is discussed. This paper provides a theoretical and practical basis for a good and fast removal of metamorphic layers of semiconductor materials. 2. Experiment device and process parameters An electrolytic polishing experiment system was developed. The schematic diagram is shown in Fig. 1. The workpiece is often horizontally placed and immersed in electrolyte during electrochemical machining. In this study, the workpiece is used in an upright position, as shown in Fig. 1, to facilitate a timely electrolytic product flushing away from the machining area and ensure the purity of the electrolytic surface and an efficient and sustainable electrochemical reaction. The locating device of liquid pipe can be adjusted freely in a vertical plane position. The position can be changed between the liquid pipe and the center of interelectrode gap. The machining voltage in this experiment is 90 V. When interelectrode gap, current density, and contrast experiment results are taken into consideration, the electrolyte pressure is 0.1 MPa. The main processing parameters are shown in Table 1. 3. Specific electrochemical polishing for semiconductors The characteristics of semiconductor materials are taken into consideration during electrolytic polishing. These characteristics in-
Correspondence to: College of Mechanical and Electrical Engineering, Nanjing University of Aeronautics and Astronautics, No. 345, 210016 Nanjing, China. E-mail address: [email protected] (L. Zhidong).
http://dx.doi.org/10.1016/j.mssp.2017.04.027 Received 7 February 2017; Received in revised form 21 March 2017; Accepted 26 April 2017 1369-8001/ © 2017 Elsevier Ltd. All rights reserved.
Materials Science in Semiconductor Processing 67 (2017) 8–13
C. Haoran et al.
ClSi4+
H2
H+ Na+ F-
Copper
P-type crystalline silicon Conduction part
Fig. 1. Schematic diagram of an electrolytic polishing experiment system.
Fig. 4. Schematic diagram of the electrochemical reaction. Table 1 Electrolytic processing parameters. Parameter
Parameter value
Polarity Workpiece material Cathode materials Interelectrode gap Current density Processing time Electrolyte temperature Electrolyte pressure Dielectric fluid
Workpiece (+) 1.2 Ω cm P-type monocrystalline silicon Pure copper 1 mm 4 A/cm2 10 min 25 °C 0.1 MPa 4%NaCl+92%H2O +4%NaF
spectrum (Fig. 3) confirmed that the white precipitate is silicon fluoride and can dissolve in solutions. Thus, F is involved in the electrolytic process. NaCl is added to improve the electrical conductivity of the solution and utilization rate of power supply and to enhance the reaction efficiency. In addition, NaCl electrolyte contains active ions Cl−, which can cause the difficulty in generating passivation membrane. This study used electrolytic polishing of semiconductor, which presents characteristics regarding electricity and electrode reaction. Electrochemical reaction that occurred during electrolytic polishing will be presented to further understand the electrolytic polishing process. Fig. 4 shows the schematic diagram of the electrochemical reaction that occurred during electrolytic polishing of monocrystalline silicon according to the electrolyte formula, coupled with an anode material (monocrystalline silicon). The reaction on the two poles will be discussed separately, and the corresponding standard electrode potential value will be illustrated. The electrode reaction at the anode side and the corresponding standard electrode potential value are as follows: Si ⇋ Si4+ + 4e
E°SiO2/Si = −0.84 V
2Cl−–2e ⇋ Cl2↑
E°Cl2/Cl− = +1.3583 V
2F−–2e ⇋ F2↑
E°F2/F− = +2.87 V
The value of E°SiO2/Si is the lowest among values. Thus, the electrode reaction in which single crystal silicon is dissolved will most probably occur in the anode. Similarly, the possible electrode reactions and corresponding standard electrode potential values at the cathode side are shown below.
Fig. 2. Classification diagram of specific electrochemical polishing for semiconductors.
clude the presence of a specific electrolyte, passivation phenomenon on the electricity side during the electrolytic process, semiconductor body resistance, and unidirectional conductivity (Fig. 2).
2H++2e⇋H2↑
E°H+/H2=0 V
3.1. Specific electrolyte
Na++e⇋Na
E°Na+/Na=−2.713 V
The electrolyte contains 40 g/L sodium fluoride and sodium chloride. Extensive experimental verification showed that F ion can effectively remove monocrystalline silicon and separate white precipitates at the silicon surface (anode). Analysis of this silicon layer via energy
E°H+/H2 exceeds E°Na+/Na by about 2.7 V, which is a large difference in electrode potential. Therefore, only hydrogen escapes at the cathode rather than the electrode reaction of sodium deposition. On the basis of above analysis, two basic chemical reaction
Fig. 3. Energy spectrum analysis of the precipitation product at the anode.
9
Materials Science in Semiconductor Processing 67 (2017) 8–13
C. Haoran et al.
Dc
Dsm1
R¦Ä Dsm2
Rl
Fig. 5. Equivalent circuit model of silicon electrochemical polishing. Fig. 8. Explosive view of the fixture.
electrolyte
P-type crystalline silicon
copper
metal into electricity Fig. 9. Temperature change curve of monocrystalline silicon during electrolytic polishing. Fig. 6. Principle diagram of the current loop of silicon electrochemical polishing.
electrolyte
P-type crystalline silicon
copper
metal into electricity
Fig. 10. Diagram of validation experiment for unidirectional conductivity.
Fig. 7. Chemical reaction diagram for the into electricity side.
contact barrier formed by junction of monocrystalline silicon and metal into electricity, which is shown as a schottky diode [7]. The body resistance of semiconductor materials is shown as the variable resistance Rδ. During the electrolytic process, electrolyte contains a large number of anions and cations, which move along a certain direction under an applied electric field. To simplify the electrolytic model, the interface between the semiconductor and electrolyte can be the same as the Schottky diode (Dsm2). The double-electric layer potential formed on the semiconductor/solution interface can be used with a Zener diode Dc [8]. The resistance of the electrolyte is expressed with a variable resistance R1. The principle diagram of the current circuit is shown in Fig. 6. The effect of into the electricity side on the electrolytic polishing mainly reflects on the two aspects which is the potential distribution and the passivation phenomenon on the into electricity side. To
equations can be used to express the whole reaction process: Si+4F−+2H+→SiF4↑+H2↑
(1)
SiO2+4F−+4H+→SiF4↑+2H2O
(2)
When the surface of single crystal silicon after WEDM is mainly composed of silicon oxide during electrolytic process, the main chemical reaction is shown in Eq. (2). When the electrolytic reaction is in the matrix, the main chemical reaction is shown in Eq. (1). 3.2. Electricity The equivalent circuit model for electrolytic polishing of monocrystalline silicon can be established, as shown in Fig. 5. Dsm1 is the 10
Materials Science in Semiconductor Processing 67 (2017) 8–13
C. Haoran et al.
Fig. 14. SEM photograph of the monocrystalline silicon surface.
Fig. 11. V–ampere characteristic curve.
Fig. 15. EDS analysis report.
maintained to avoid electrical passivation. In this study, the into electric device produced by 3D printing exhibits a good sealing characteristic, which makes it durable. Consequently, electrical passivation is avoided. This experiment also used 3D printing to create workpiece fixtures. The explosion picture of the fixture (Fig. 8) is fabricated with a 3D software to present a good display of various parts. The prominent area of the thin copper is connected with one end of the wire, and copper is fixed in the groove, which is in the middle of the workpiece holder. Subsequently, the monocrystalline silicon is sealed with a waterproof tape. After that press it in the groove which is in the middle of the workpiece holder and firmly compacted with copper.
Fig. 12. Schematic diagram of the crystal orientation measurement position.
guarantee the uniformity of electrolytic polishing, each polishing surface should have the same potential. Potential simulation showed that different ways of the contact on the into electricity side has a huge effect on the potential distribution. The body resistance of monocrystalline silicon causes a non-uniform potential distribution on its surface during electrolytic polishing, which directly results in an uneven electrolytic polishing surface. This experiment used the characteristics of copper with monocrystalline silicon samples that are all fit to avoid the above problem effectively. Passivation phenomenon on the into electricity side is common during semiconductor fabrication. On the EDM of semiconductor, the workpiece must be in contact with the metal to form a processing circuit, and the electric copper brush and semiconductor should fit closely. However, no mutual movement is observed. When electrical discharge machining is continued, the electrochemical reactions constantly occur on the electric copper brush and workpiece under an external power source (Fig. 7). A high resistivity passivation membrane, which interrupts the process, is produced on the surface of the silicon and copper brush. In the electrolytic polishing process, reasonable means of sealing should be used. The electricity side must be dry, and the value of the current should be controlled. Moreover, a good contact between the monocrystalline silicon material and the into electricity side must be
3.3. Body resistance Semiconductor body resistance changes mainly with change in processing temperature. This change will significantly affect the value of the machining current, thereby the significant effect on electrolytic polishing efficiency. During the experiment, the thermocouple probe is placed into the gap between the monocrystalline silicon and the copper into electricity using the multichannel temperature monitor (Thermocouple Thermometer with Datalogger 4ch), as shown in Fig. 9. Consequently, the temperature of monocrystalline silicon samples during electrolytic polishing is monitored real-time. The monitored data are shown in a continuous variation graph in Fig. 9. The body resistance reduces, and the machining current increases during electrolytic polishing when the single crystal silicon sample temperature gradually increases. The voltage must be reduced to
Fig. 13. Change in crystal orientation of monocrystalline silicon samples in different positions before and after polishing.
11
Materials Science in Semiconductor Processing 67 (2017) 8–13
C. Haoran et al.
Fig. 16. Summary of flatness measurement for the whole polished surface and adjacent area of monocrystalline silicon.
wafers should be verified. In this experiment, three different positions on monocrystalline silicon surface (Fig. 12) before and after the electrolytic polishing are measured using X-ray crystal orientation instrument. Data summary is shown in Fig. 13. The crystal orientation of the monocrystalline silicon surface in three different positions changes within 3′ (the allowed error value) before and after electrolytic polishing. Thus, electrolytic polishing exerts no effect on the crystal orientation of monocrystalline silicon wafer. On the basis of the proposed electrolytic polishing of single crystal silicon using the optimization parameters, a uniform brightness in the center area of monocrystalline silicon surface is finally obtained. To facilitate the comparison with the surface morphology of monocrystalline silicon before and after electrolytic polishing, the SEM photograph for the transitional position of monocrystalline silicon surface after electrolytic polishing (Fig. 14) is taken. The monocrystalline silicon surface is considerably smooth and uniform after electrolytic polishing. However, intensive discharge holes caused by WEDM processing are present on the region without electrolytic polishing. Further analysis of the EDS (Fig. 15) showed that Si content on the single crystal silicon surface after electrolytic polishing reaches 95.56%, and the O content is only 4.44%. SiF4 generated in the electrolytic polishing exhibits a high moisture absorption rate. Therefore, a timely cleaning and drying of monocrystalline silicon after electrolytic polishing, which can effec-
maintain the stability of the current density, or electrolytic time must be controlled in a reasonable range to effectively avoid surface quality problem caused by the increased processing current. 3.4. Unidirectional conductivity The diagram of validation experiment for unidirectional conductivity is shown in Fig. 10. The p-type semiconductor is used in the experiment. Current change is detected through voltage adjustment and polarity change to analyze the unidirectional conductivity of the p-type silicon. The volt–ampere characteristic curve for the p-type monocrystalline silicon is shown in Fig. 11. When the p-type monocrystalline silicon is used as the anode, the current is significantly increased with increasing voltage. When p-type monocrystalline silicon is used as cathode, the current increases slowly when the voltage increases gradually. This result confirmed that semiconductor possesses a unidirectional conductivity during the electrolytic process. 4. Actual application effect Monocrystalline silicon with specific crystal orientation is widely used in aerospace and optical fields; thus, whether electrolytic polishing method will change the crystal orientation of monocrystalline silicon 12
Materials Science in Semiconductor Processing 67 (2017) 8–13
C. Haoran et al.
silicon wafer surface before and after electrolysis process using the method of X-ray back swing curve is used [9]. Values of 53 and 0 µm were obtained before and after the electrolytic process, respectively. On the basis of fixed-point electrolytic polishing, the characteristics of monocrystalline silicon during electrolytic polishing were investigated. Electrolytic polishing should be further studied to explore the ratio of electrolytes, monocrystalline silicon characteristics, power supply, control strategy, and other factors affecting the polishing process. Furthermore, polishing of the whole surface of monocrystalline silicon should be comprehensively researched. 5. Conclusions 1. The specific electrochemical polishing of monocrystalline silicon, which affects electric field, flow field, specific electrolyte, the into electricity theory [10], body resistance, and unidirectional conductivity, should be considered for a uniform polishing of monocrystalline silicon. 2. Electrolytic polishing can effectively remove the metamorphic layer of monocrystalline silicon surface caused by WEDM. 3. Results show that electrolytic polishing cannot change the crystal orientation of silicon wafer surface. 4. Under the experimental conditions of this study, a monocrystalline silicon polishing surface with no metamorphic layer is obtained. The flatness error of the central area is less than 0.201 µm. Acknowledgement The project is supported by the National Natural Science Foundation of China (Grant No. U1532106, No. 51675272, No. 51575271, No. 11275274), Funding of Jiangsu Innovation Program for Graduate Education (“the Fundamental Research Funds for the Central Universities”) (Grant No. KYLX15_0291). We also extend our sincere thanks to all who contributed in the preparation of these instructions.
Fig. 17. 3D morphology comparison chart.
tively avoid F contamination, are important. To further illustrate the surface flatness of silicon samples after electrolytic process, the flatness measurement should be used from both global and local viewpoints. Fig. 16 presents the summary of measurement results. After electrolytic polishing, the longitudinal and transverse flatness of silicon samples is at 200 nm, which is significantly decreased compared with the surface flatness of both ends that are not polished. Among them, the transverse measurement of polished surface in the range of 2–6.5 mm shows higher flatness and variation range of less than 150 nm. The 3D morphology changes before and after electrolytic polishing on the same area of single crystal silicon surface were observed and recorded, as shown in Fig. 17. The surface without electrolysis process presents an uneven surface because of the large amounts of discharge holes. The largest flatness error is 26.684 µm. Nevertheless, the overall surface after electrolysis is considerably smooth, and the maximum error of flatness is 0.812 µm. The flatness error of the central area is less than 0.201 µm. Finally, the metamorphic layer thickness measurement for the
References [1] [2] [3] [4] [5] [6] [7] [8] [9] [10]
13
X. Zhou, X.Q. Li, Y.N. Xie, et al., Exp. Astron. 38 (3) (2014) 433–441. J. Słowik, A. Zięba, Nucl. Instrum. Methods Phys. Res. 551 (1) (2005) 73–77. C.K. Malek, V. Saile, Microelectron. J. 35 (2) (2004) 131–143. M.H. Li, The Theoretical Basis of Electrical Discharge Machining, National Defense Industry Press, Beijing, 1989, pp. 25–30. Z.D. Liu, W. Wang, M.B. Qiu, et al., Acta Energiae Sol. Sin. 30 (5) (2009) 619–623. U. Bismayer, E. Brinksmeier, B. Guttler, et al., Precis. Eng. 16 (2) (1994) 139–143. Haoran Chen, Zhidong Liu, et al., Mater. Sci. Semicond. Process. 32 (2015) 125–130. Liu Zhidong, Non-Traditional Machining, Peaking University Press, 2013. Mengxing Ge, Zhidong Liu, Lida Shen, et al., J. Mater. Sci.: Mater. Electron. (2016). Liu Zhidong, Cao Yinfeng, Qiu Mingbo, et al., China Mech. Eng. 23 (6) (2012) 725–728.