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Electron Beam Direct Writing technology for LSI prototyping business
Microelectronic Engineering 87 (2010) 1131–1134
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Electron Beam Direct Writing technology for LSI prototyping business Yasuhide Machida a,*, Takashi Maruyama a, Yoshinori Kojima a, Shinji Sugatani a, Haruo Tsuchikawa a, Kozo Ogino b, Hiromi Hoshino b a b
e-Shuttle, Inc. 1-1, Kamikodanaka 4-chome, Nakahara-ku, Kawasaki 211-8588, Japan Fujitsu Microelectronics Limited, 50 Fuchigami, Akiruno, Tokyo 197-0833, Japan
a r t i c l e
i n f o
Article history: Received 14 September 2009 Received in revised form 5 November 2009 Accepted 9 November 2009 Available online 14 November 2009 Keywords: EBDW Lithography Hybrid exposure PLFD Mask cost Prototyping CP PEC Proximity effect
a b s t r a c t When manufacturing prototype devices or small volume production custom logic LSIs, the products are being less profitable because of the skyrocketing mask and design costs recent technology node. For 65 nm technology node and beyond, the reduction of mask cost becomes critical issue for logic devices especially. We have applied to Electron Beam Direct Writing (EBDW) technology mainly to critical interconnect layers which are more cost sensitive than other layers. We required a breakthrough to apply EBDW technology to a production environment, and we overcame some difficult issues. We have already started EBDW technology for 65 nm node business with sufficient yield and process margin of production level. In this paper, our technical outputs to achieve practical use of EBDW for 65 nm node and beyond, and our future prospects for EBDW evolution to play a principal part in next generation lithography will be discussed. Ó 2009 Elsevier B.V. All rights reserved.
1. Introduction Quickly manufacturing prototype devices or small volume production custom logic LSIs is increasingly required for system LSIs. In view of these trends, mask-less lithography can create a development environment that can reduce costs and shorten production periods. The mask price is almost skyrocketing as technology node advances. We think that one of the solution overcome those issues by following approach; (a) shuttle scheme provides cost sharing platform, (b) e-beam lithography (EBL) enables mask-less prototyping. We have already started EBDW technology for 65 nm node business with sufficient yield and process margin of production level [1]. Our 300 mm e-beam (EB) writer system named F3000 is supplied from ADVANTEST CORPORATION, acceleration voltage is 50 keV, and character projection (CP) [1] is available. The stencil mask contains 12 different sites. There are 100 characters par site. The most expensive parts for 65 nm mask set are the fine interconnection layers. If all fine layers are replaced by EBL, 60% of mask cost will be saved. First of all, we aimed to replace these layers to EBL. We developed EB technology for 65 nm node fine interconnection layers. Furthermore, if the layers, where the transistors are
* Corresponding author. E-mail address: [email protected] (Y. Machida). 0167-9317/$ - see front matter Ó 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2009.11.037
formed, in the front end of line (FEOL) process are replaced by EBL, total turn around time will be shortened. We have required a breakthrough to apply EBDW technology to a production environment, and we overcame some difficult issues. We show the practical process issues and countermeasures of EBDW technology at 65 nm node and beyond. First issue is proximity effect at 50 keV. The large amount of total backscattering electrons from the multiple interconnection layers causes huge proximity effect. We previously proposed the simplified electron energy flux (SEEF) model [2] based on multilayer proximity effect correction (PEC). However, even if multilayer PEC is effective in most patterns, there is a critical point of low contrast in specific pattern combination. Therefore, we have proposed the hybrid exposure [3] technique by EB and Krypton fluoride laser (KrF) stepper in addition to multilayer PEC. Second issue is the compatibility between EBL and photolithography. Using a different exposure technology causes different physical phenomena to occur in the lithography process, and different images are formed. These differences have an effect on the characteristics of the semiconductor device being made. Therefore, we proposed a photolithography friendly compatibility design (PLFD) technique [4] for obtaining the same printed image even if the printed images were produced by either EBL or photolithography. PLFD technique was applied to actual 65 nm SRAM layouts, and the exposure results were shown. Third issue is the exposure throughput. If we use only the variable
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of large pattern, and dummy patterns for chemical mechanical polishing (CMP). EB data are composed of edge of large pattern and fine patterns. In this hybrid process, KrF patterns are so rough that it could use low cost mask. Pattern density of EB data is very low. This causes good resist profile and low shot count. EB resist has enough patterning ability with KrF exposure. Low pattern density causes good shapes of EB patterns. Narrow isolation pattern could be finely performed with hybrid exposure.
2. EBDW technology for LSI prototyping business
2.2. Compatibility between EB lithography and photolithography
2.1. EB/KrF hybrid exposure with multilayer proximity effect correction
Second issue is the compatibility between EBL and photolithography. EBL has better printability than photolithography. The accuracy of the transistor shape or wire width is a factor that has a significant effect on the device characteristics. Transistor shape has effects on transistor characteristics; Vth, Ion, and Ioff. Wire shape has effects on wire characteristics; Capacitance, Resistance, via resistance, and Dielectric. It is necessary to make the same printed image even if the image is produced by different lithography system. Therefore, we proposed the PLFD technique [4], in which we can obtain the same shapes by modifying the design data to the target of contour based on photolithography. The modified patterns produced with PLFD are almost the same as the original design patterns in photolithography. By using this PLFD technique, no additional changes are required except for switching to the lithography process. EBL draws patterns more precisely than photolithography; in the case of a square pattern, for example, EB draws it almost as a square form, while photolithography draws it as a circle. PLFD changes the original pattern shape to a shape that consists of many vertexes and minute edges. The complicated shape produced by PLFD causes a decrease in exposure throughput because it increases the number of exposure shots for EBL, and makes the precision deteriorate because of exposing them using minute beams. However, these obstacles and faults can be resolved by using CP exposure method. An increase in the number of shots and the requirement of high resolution can be satisfied by using CP cells. We applied the PLFD technique to actual 65 nm SRAM cell layouts. Because SRAM have high repeatability, they are exposed by the CP method to shorten the writing time. In addition, SRAM is one of the cells that are the most sensitive to device characteristics. We manufactured a PLFD CP mask as shown in Fig. 2b. Fig. 2a is original CP mask. Moreover, we exposed a wafer using this PLFD CP mask. We show the exposure results. Both of scanning electron microscope (SEM) images were exposed with the same dose on
Energy Intensity Distribution
As is well known, PEC on copper (Cu) multiple interconnection layers, which behaves as deteriorated factor to the resolution of high dense line patterns, is key development issue. The large amount of total backscattering electrons from the multiple interconnection layers causes huge proximity effect. The relative difference in the critical dimensions (CD) variation is due to layer variation through different structures. PEC in the multilayer structures should be taken into account the composite of the multiple interconnection layers. If the electron trajectories describe precisely in the layers, the soluble model becomes so complex. It is difficult to handle with calculations. To solve this issue, our proposed SEEF model [2] is considered by only two parameters at each layer in order to simplify the calculation. Two parameters are involved the transmitted electron energy fluxes and the reflected electron energy fluxes at each layer. Practical PEC computation time has been achieved by using this simplified model. We have good CD uniformity through all structures by using SEEF model. Thus, SEEF model has been confirmed to correct powerfully the proximity effect in the multilayer structures. However, even if PEC based on SEEF model is effective in most patterns, there is a critical point of low contrast in specific pattern combination. When the narrow isolation patterns surrounded by largely opened patterns are exposed, the contrast of these patterns is affected by huge backscattering electrons. Therefore, we have proposed the EB/KrF hybrid exposure [3] technique as shown in Fig. 1 in addition to PEC based on SEEF model. Only edge of large patterns and fine patterns are exposed by EB. The total amount of the backscattering electrons is decreased and the contrast of energy intensity profile is improved. KrF patterns and EB patterns are developed simultaneously as same as double patterning in photolithography. Original data are going to be split into two data. One is KrF data, the other is EB data. KrF data are composed of inner area
Eth Low contrast
Total energy
Energy intensity from individual EB patterns
Energy Intensity Distribution
shaped beam (VSB) technique, we can not get enough throughputs to make prototype chips. So we reduced the exposure shots using several methods [1] of CP. Finally, we discuss the patterning results and our technical outputs to achieve practical use of EBDW for 65 nm node and beyond. Moreover, our future prospects for EBDW evolution to play a principal part in next generation lithography will be discussed.
High contrast
KrFExp. Energy intensity
EB data KrFexposure area
Fig. 1. Energy intensity distribution by EB exposure and by EB/KrF hybrid exposure. Hybrid exposure technique is shown. Red area is exposed by EB system, green area is exposed by KrF scanner. (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)
Y. Machida et al. / Microelectronic Engineering 87 (2010) 1131–1134
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Fig. 2. Results of PLFD, which are SEM images of 65 nm node SRAM pattern on mask and on wafer are shown. (a) is original CP cell on mask, (b) is CP cell with PLFD on mask. (c) is resist pattern exposed by EB without PLFD on wafer. (d) is resist pattern exposed by EB with PLFD on wafer.
the wafer. There is the remarkable difference in shape between the original CP cell and the PLFD CP cell as shown in Fig. 2c and d. The resist pattern on the wafer can observe that the PLFD result in Fig. 2d conforms to the target of contour based on photolithography very well.
common CP mask is applied to SRAM, ROM, repeated via, CMP dummy patterns and so on. As shot count shares the largest factor in the throughput component, practical throughput has been attained with CP method. The reduction ratio versus VSB summarized for each target layer of 65 nm device. By reducing the exposure shots down to rate of 0.26, the available exposure speed of 0.5 wafers per hour to meet our target device had been achieved.
2.3. Exposure throughput There are two modes in CP exposure [1]. One is the fully illuminated mode and the other is partially illumination mode named partial CP. In the view of productivity and quality, usage of CP exposure scheme is the key item for the production. The shot number reduction using partial CP scheme is effective to attain enough throughput. If we use these combinations, it makes more flexibility in pattern combination. This lead to shot count reduction using this technique. via layer result mainly could be attained with using partial CP exposure. As for metal interconnect layer, the method by
3. Results and discussions 3.1. 65 nm node device Several prototype devices have been manufactured. We show the patterning results of 65 nm node device. Top view of via shape and line patterns after etching are shown in Fig. 3. Cross sectional view of via shape after etching are shown. SEM images of exposure results by Argon fluoride laser (ArF) stepper are shown for reference. via
Fig. 3. SEM photographs of patterning results of 65 nm node patterns with EB and ArF. Top view of via shape and line patterns, and cross sectional view of via shape after etching are shown.
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Fig. 4. SEM photographs of 45 nm node patterns, which include gate of flip-flop part and contact of SRAM part. Resist patterns are finely performed with CP which shows enough potential of resolutions.
shape and line patterns of EBDW after etching has no particular difference with ArF. We have confirmed that 65 nm node basic device structures were performed with EBL. Also, good electrical measurement results were obtained within CD control limit in each layer. Enough yields for our target device were attained. By manufacturing lots trends of overlay and CD in EBDW processing, we have confirmed good productivity within control limit. EBDW could keep the same stability as ArF. EBDW for 65 nm node in production level has been well established.
3.2. 45 nm node and beyond Fig. 4 shows SEM photographs of EB patterning results for 45 nm node patterns, which include gate of flip-flop part and contact of SRM part. Resist patterns are finely performed with CP which shows enough potential of resolution and 45 nm node device application. But there are many issues ahead of us. First of all, number of shots is increased as the technology node proceeds. Secondly resist sensitivity is gradually falling down as the technology node proceeds. This means that further throughput improvement must be required. Those background lead to manufacturing efficiency lower. Design for EB (DFEB) [5] is the shot count reduction approach through the front-to-back design flow. If the GDS is generated using DEFB cell libraries, total number of exposure shot counts can be reduced. We show our scenario of throughput improvement. Within a few years, we will achieve throughput improvement using single beam system with DFEB. And finally, we will achieve drastic improvement using multi column cell (MCC) system [6] with design for manufacturability (DFM) for EB. Of course, not only MCC but also other mask-less lithography (ML2) systems is candidate in our scenario. And we think that mul-
ti column based equipment with CP based design will be able to play a role as next generation lithography candidate. 4. Conclusions Since EBDW for 65 nm node in production level has been well established, the effectiveness of EB/KrF hybrid exposure technique with multilayer PEC method, PLFD technique, and several CP methods has been successfully proved. Experimental level exposure for 45 nm node is also available. For 45 nm node, especially trade-off between throughput and resolution is the most critical. The lower contrast due to beam blur in fine beam size in 45 nm node makes resist sensitivity largely dropped. We are considering compensate resist sensitivity with another approach, such as the increase of EB machine current density and the compaction of shot number with design for EB approach for small volume custom LSIs. We believe that multi column based equipment combining with CP based design will be able to play a principal part in next generation lithography. Acknowledgement The authors wish to acknowledge Toppan Printing Inc. for their help in manufacturing the CP mask. References [1] [2] [3] [4] [5] [6]
T. Maruyama et al., Proc. SPIE. 6921 (2008) 69210H. K. Ogino et al., Jpn. J. Appl. Phys. 43 (2004) 3762. C. Hohle et al., EIPBN (2007) PN-8. H. Hoshino et al., Proc. SPIE 6921 (2008) 69212K. T. Maruyama et al., EIPBN (2009) 2C-1. A. Yamada et al., J. Vac. Sci. Technol. B 26 (2008) 2025.
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Electron Beam Direct Writing technology for LSI prototyping business Yasuhide Machida a,*, Takashi Maruyama a, Yoshinori Kojima a, Shinji Sugatani a, Haruo Tsuchikawa a, Kozo Ogino b, Hiromi Hoshino b a b
e-Shuttle, Inc. 1-1, Kamikodanaka 4-chome, Nakahara-ku, Kawasaki 211-8588, Japan Fujitsu Microelectronics Limited, 50 Fuchigami, Akiruno, Tokyo 197-0833, Japan
a r t i c l e
i n f o
Article history: Received 14 September 2009 Received in revised form 5 November 2009 Accepted 9 November 2009 Available online 14 November 2009 Keywords: EBDW Lithography Hybrid exposure PLFD Mask cost Prototyping CP PEC Proximity effect
a b s t r a c t When manufacturing prototype devices or small volume production custom logic LSIs, the products are being less profitable because of the skyrocketing mask and design costs recent technology node. For 65 nm technology node and beyond, the reduction of mask cost becomes critical issue for logic devices especially. We have applied to Electron Beam Direct Writing (EBDW) technology mainly to critical interconnect layers which are more cost sensitive than other layers. We required a breakthrough to apply EBDW technology to a production environment, and we overcame some difficult issues. We have already started EBDW technology for 65 nm node business with sufficient yield and process margin of production level. In this paper, our technical outputs to achieve practical use of EBDW for 65 nm node and beyond, and our future prospects for EBDW evolution to play a principal part in next generation lithography will be discussed. Ó 2009 Elsevier B.V. All rights reserved.
1. Introduction Quickly manufacturing prototype devices or small volume production custom logic LSIs is increasingly required for system LSIs. In view of these trends, mask-less lithography can create a development environment that can reduce costs and shorten production periods. The mask price is almost skyrocketing as technology node advances. We think that one of the solution overcome those issues by following approach; (a) shuttle scheme provides cost sharing platform, (b) e-beam lithography (EBL) enables mask-less prototyping. We have already started EBDW technology for 65 nm node business with sufficient yield and process margin of production level [1]. Our 300 mm e-beam (EB) writer system named F3000 is supplied from ADVANTEST CORPORATION, acceleration voltage is 50 keV, and character projection (CP) [1] is available. The stencil mask contains 12 different sites. There are 100 characters par site. The most expensive parts for 65 nm mask set are the fine interconnection layers. If all fine layers are replaced by EBL, 60% of mask cost will be saved. First of all, we aimed to replace these layers to EBL. We developed EB technology for 65 nm node fine interconnection layers. Furthermore, if the layers, where the transistors are
* Corresponding author. E-mail address: [email protected] (Y. Machida). 0167-9317/$ - see front matter Ó 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2009.11.037
formed, in the front end of line (FEOL) process are replaced by EBL, total turn around time will be shortened. We have required a breakthrough to apply EBDW technology to a production environment, and we overcame some difficult issues. We show the practical process issues and countermeasures of EBDW technology at 65 nm node and beyond. First issue is proximity effect at 50 keV. The large amount of total backscattering electrons from the multiple interconnection layers causes huge proximity effect. We previously proposed the simplified electron energy flux (SEEF) model [2] based on multilayer proximity effect correction (PEC). However, even if multilayer PEC is effective in most patterns, there is a critical point of low contrast in specific pattern combination. Therefore, we have proposed the hybrid exposure [3] technique by EB and Krypton fluoride laser (KrF) stepper in addition to multilayer PEC. Second issue is the compatibility between EBL and photolithography. Using a different exposure technology causes different physical phenomena to occur in the lithography process, and different images are formed. These differences have an effect on the characteristics of the semiconductor device being made. Therefore, we proposed a photolithography friendly compatibility design (PLFD) technique [4] for obtaining the same printed image even if the printed images were produced by either EBL or photolithography. PLFD technique was applied to actual 65 nm SRAM layouts, and the exposure results were shown. Third issue is the exposure throughput. If we use only the variable
1132
Y. Machida et al. / Microelectronic Engineering 87 (2010) 1131–1134
of large pattern, and dummy patterns for chemical mechanical polishing (CMP). EB data are composed of edge of large pattern and fine patterns. In this hybrid process, KrF patterns are so rough that it could use low cost mask. Pattern density of EB data is very low. This causes good resist profile and low shot count. EB resist has enough patterning ability with KrF exposure. Low pattern density causes good shapes of EB patterns. Narrow isolation pattern could be finely performed with hybrid exposure.
2. EBDW technology for LSI prototyping business
2.2. Compatibility between EB lithography and photolithography
2.1. EB/KrF hybrid exposure with multilayer proximity effect correction
Second issue is the compatibility between EBL and photolithography. EBL has better printability than photolithography. The accuracy of the transistor shape or wire width is a factor that has a significant effect on the device characteristics. Transistor shape has effects on transistor characteristics; Vth, Ion, and Ioff. Wire shape has effects on wire characteristics; Capacitance, Resistance, via resistance, and Dielectric. It is necessary to make the same printed image even if the image is produced by different lithography system. Therefore, we proposed the PLFD technique [4], in which we can obtain the same shapes by modifying the design data to the target of contour based on photolithography. The modified patterns produced with PLFD are almost the same as the original design patterns in photolithography. By using this PLFD technique, no additional changes are required except for switching to the lithography process. EBL draws patterns more precisely than photolithography; in the case of a square pattern, for example, EB draws it almost as a square form, while photolithography draws it as a circle. PLFD changes the original pattern shape to a shape that consists of many vertexes and minute edges. The complicated shape produced by PLFD causes a decrease in exposure throughput because it increases the number of exposure shots for EBL, and makes the precision deteriorate because of exposing them using minute beams. However, these obstacles and faults can be resolved by using CP exposure method. An increase in the number of shots and the requirement of high resolution can be satisfied by using CP cells. We applied the PLFD technique to actual 65 nm SRAM cell layouts. Because SRAM have high repeatability, they are exposed by the CP method to shorten the writing time. In addition, SRAM is one of the cells that are the most sensitive to device characteristics. We manufactured a PLFD CP mask as shown in Fig. 2b. Fig. 2a is original CP mask. Moreover, we exposed a wafer using this PLFD CP mask. We show the exposure results. Both of scanning electron microscope (SEM) images were exposed with the same dose on
Energy Intensity Distribution
As is well known, PEC on copper (Cu) multiple interconnection layers, which behaves as deteriorated factor to the resolution of high dense line patterns, is key development issue. The large amount of total backscattering electrons from the multiple interconnection layers causes huge proximity effect. The relative difference in the critical dimensions (CD) variation is due to layer variation through different structures. PEC in the multilayer structures should be taken into account the composite of the multiple interconnection layers. If the electron trajectories describe precisely in the layers, the soluble model becomes so complex. It is difficult to handle with calculations. To solve this issue, our proposed SEEF model [2] is considered by only two parameters at each layer in order to simplify the calculation. Two parameters are involved the transmitted electron energy fluxes and the reflected electron energy fluxes at each layer. Practical PEC computation time has been achieved by using this simplified model. We have good CD uniformity through all structures by using SEEF model. Thus, SEEF model has been confirmed to correct powerfully the proximity effect in the multilayer structures. However, even if PEC based on SEEF model is effective in most patterns, there is a critical point of low contrast in specific pattern combination. When the narrow isolation patterns surrounded by largely opened patterns are exposed, the contrast of these patterns is affected by huge backscattering electrons. Therefore, we have proposed the EB/KrF hybrid exposure [3] technique as shown in Fig. 1 in addition to PEC based on SEEF model. Only edge of large patterns and fine patterns are exposed by EB. The total amount of the backscattering electrons is decreased and the contrast of energy intensity profile is improved. KrF patterns and EB patterns are developed simultaneously as same as double patterning in photolithography. Original data are going to be split into two data. One is KrF data, the other is EB data. KrF data are composed of inner area
Eth Low contrast
Total energy
Energy intensity from individual EB patterns
Energy Intensity Distribution
shaped beam (VSB) technique, we can not get enough throughputs to make prototype chips. So we reduced the exposure shots using several methods [1] of CP. Finally, we discuss the patterning results and our technical outputs to achieve practical use of EBDW for 65 nm node and beyond. Moreover, our future prospects for EBDW evolution to play a principal part in next generation lithography will be discussed.
High contrast
KrFExp. Energy intensity
EB data KrFexposure area
Fig. 1. Energy intensity distribution by EB exposure and by EB/KrF hybrid exposure. Hybrid exposure technique is shown. Red area is exposed by EB system, green area is exposed by KrF scanner. (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)
Y. Machida et al. / Microelectronic Engineering 87 (2010) 1131–1134
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Fig. 2. Results of PLFD, which are SEM images of 65 nm node SRAM pattern on mask and on wafer are shown. (a) is original CP cell on mask, (b) is CP cell with PLFD on mask. (c) is resist pattern exposed by EB without PLFD on wafer. (d) is resist pattern exposed by EB with PLFD on wafer.
the wafer. There is the remarkable difference in shape between the original CP cell and the PLFD CP cell as shown in Fig. 2c and d. The resist pattern on the wafer can observe that the PLFD result in Fig. 2d conforms to the target of contour based on photolithography very well.
common CP mask is applied to SRAM, ROM, repeated via, CMP dummy patterns and so on. As shot count shares the largest factor in the throughput component, practical throughput has been attained with CP method. The reduction ratio versus VSB summarized for each target layer of 65 nm device. By reducing the exposure shots down to rate of 0.26, the available exposure speed of 0.5 wafers per hour to meet our target device had been achieved.
2.3. Exposure throughput There are two modes in CP exposure [1]. One is the fully illuminated mode and the other is partially illumination mode named partial CP. In the view of productivity and quality, usage of CP exposure scheme is the key item for the production. The shot number reduction using partial CP scheme is effective to attain enough throughput. If we use these combinations, it makes more flexibility in pattern combination. This lead to shot count reduction using this technique. via layer result mainly could be attained with using partial CP exposure. As for metal interconnect layer, the method by
3. Results and discussions 3.1. 65 nm node device Several prototype devices have been manufactured. We show the patterning results of 65 nm node device. Top view of via shape and line patterns after etching are shown in Fig. 3. Cross sectional view of via shape after etching are shown. SEM images of exposure results by Argon fluoride laser (ArF) stepper are shown for reference. via
Fig. 3. SEM photographs of patterning results of 65 nm node patterns with EB and ArF. Top view of via shape and line patterns, and cross sectional view of via shape after etching are shown.
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Y. Machida et al. / Microelectronic Engineering 87 (2010) 1131–1134
Fig. 4. SEM photographs of 45 nm node patterns, which include gate of flip-flop part and contact of SRAM part. Resist patterns are finely performed with CP which shows enough potential of resolutions.
shape and line patterns of EBDW after etching has no particular difference with ArF. We have confirmed that 65 nm node basic device structures were performed with EBL. Also, good electrical measurement results were obtained within CD control limit in each layer. Enough yields for our target device were attained. By manufacturing lots trends of overlay and CD in EBDW processing, we have confirmed good productivity within control limit. EBDW could keep the same stability as ArF. EBDW for 65 nm node in production level has been well established.
3.2. 45 nm node and beyond Fig. 4 shows SEM photographs of EB patterning results for 45 nm node patterns, which include gate of flip-flop part and contact of SRM part. Resist patterns are finely performed with CP which shows enough potential of resolution and 45 nm node device application. But there are many issues ahead of us. First of all, number of shots is increased as the technology node proceeds. Secondly resist sensitivity is gradually falling down as the technology node proceeds. This means that further throughput improvement must be required. Those background lead to manufacturing efficiency lower. Design for EB (DFEB) [5] is the shot count reduction approach through the front-to-back design flow. If the GDS is generated using DEFB cell libraries, total number of exposure shot counts can be reduced. We show our scenario of throughput improvement. Within a few years, we will achieve throughput improvement using single beam system with DFEB. And finally, we will achieve drastic improvement using multi column cell (MCC) system [6] with design for manufacturability (DFM) for EB. Of course, not only MCC but also other mask-less lithography (ML2) systems is candidate in our scenario. And we think that mul-
ti column based equipment with CP based design will be able to play a role as next generation lithography candidate. 4. Conclusions Since EBDW for 65 nm node in production level has been well established, the effectiveness of EB/KrF hybrid exposure technique with multilayer PEC method, PLFD technique, and several CP methods has been successfully proved. Experimental level exposure for 45 nm node is also available. For 45 nm node, especially trade-off between throughput and resolution is the most critical. The lower contrast due to beam blur in fine beam size in 45 nm node makes resist sensitivity largely dropped. We are considering compensate resist sensitivity with another approach, such as the increase of EB machine current density and the compaction of shot number with design for EB approach for small volume custom LSIs. We believe that multi column based equipment combining with CP based design will be able to play a principal part in next generation lithography. Acknowledgement The authors wish to acknowledge Toppan Printing Inc. for their help in manufacturing the CP mask. References [1] [2] [3] [4] [5] [6]
T. Maruyama et al., Proc. SPIE. 6921 (2008) 69210H. K. Ogino et al., Jpn. J. Appl. Phys. 43 (2004) 3762. C. Hohle et al., EIPBN (2007) PN-8. H. Hoshino et al., Proc. SPIE 6921 (2008) 69212K. T. Maruyama et al., EIPBN (2009) 2C-1. A. Yamada et al., J. Vac. Sci. Technol. B 26 (2008) 2025.