Electron Beam probing for design verification at Intel

Microelectronic Elsevier

Engineering

25

24 (1994) 25-34

Electron Beam probing for design verification

at Intel

Val1uri.R.M. Rao and Avtar Saini Intel Corporation 2200 Mission College Blvd Santa Clara, CA 95052 ABSTRACT Electron Beam probing is an integral part of the design verification flow that new products undergo at Intel. We have found that the part of the flow that utilizes EBeam probing extensively is circuit characterization and debug. Because of this we are finding that the performance of the E-Beam probers is driven primarily by the silicon process technology (Linewidths, Metallization layers) and design technology (operating voltage, frequency). In this paper we will describe the overall verification flow that new products undergo and describe in detail that portion of the flow that utilizes E-Beam probing. We will conclude with some thoughts for the future. 1. INTRODUCTION The most complex Chips manufactured by Intel are full custom Integrated Circuits such as microprocessors that currently integrate more than 3 million transistors on one piece of silicon. Such chips are really complete systems on a piece of silicon and the problems of verifying and debugging them are similar to those encountered in large digital systems. Verification (Architectural, logic and circuit) is an integral part of the chip design process and utilizes a variety of simulators which use models of the chip at various levels of hierarchy. After silicon is manufactured the verification process continues but now utilizes the real design as opposed to chip models. The most challenging of all the chip models tend to be the ones at the circuit level since these require one to accurately simulate the structural implementation in the silicon and the complex effects of routing with multiple levels of metallization. With chips of the complexity level that Intel builds it is not possible to perform full chip circuit simulation. The electron beam prober is really another verification tool that is utilized after the design is available in silicon and “probes” internal chip circuitry to verify the accuracy of the simulations at the circuit and physical levels and to help resolve the origin of circuit related bugs. Generally if full chip circuit simulations were feasible and the simulations were perfect and all possible circuit problems and their relation to all test patterns were known and understood there would be no need to probe the silicon. Since Intel is continually pushing the limits of circuit design and process technology, this is currently not the case and at Intel we have found that E-Beam probers have a very important role to play as circuit verification tools. In the next section we describe the overall verification process. Subsequently we focus on portions that use E-Beam probing. Elsevier Science B.V.

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V.R.M. Rao, A. Saini J E-beam probing for design veriJicution at Intel

2. THE OVERALL CHIP VERIFICATION FLOW The verification of ICs is performed at several design phase.

levels

of hierarchy

during

the chip

Firstly Architectural verification ensures that the chip will perform as designed from a system perspective. This phase will ensure that the new design is bug free and also satisfies compatibility requirements with previously designed products. Architectural verification is performed by executing system level tests and application programs on a simulator using a model of the chip. The model is usually a software model but more recently hardware emulation [I] has been used to enable the simulation to run at a faster rate. The next level is logic verification which ensures that the logical implementation of the system is correct. This portion uses logic simulators (generally with hardware acceleration to increase speed). Logic synthesis which is used extensively in today’s designs is self verifying since it generates logic that is correct by construction. The final part of the verification flow is circuit verification, This part is the closest to the final chip implementation in silicon. Generally a variety of simulators (such as circuit simulators, static timing analyzers) are used to ensure that the chip meets certain performance goals. Since it is not possible to circuit simulate the entire chip small portions are simulated and interconnections are analyzed with static timing analyzers. After layout, parasitic extraction is used to refine the circuit implementations. The combination of synthesis and auto placement and routing will generate circuits that are correct by construction. Generally the likelihood of incorrect logic implementation tends to be relatively low because of the detailed architectural and logic verification steps that are used, We therefore find that when a coupled with “correct by construction” synthesis. signal fails due to a wrong logic level, the failure is usually caused by a subtle circuit problem and not by errors in the logic design. When this happens the failing signal is rapidly localized with the help of on chip testability features (such as scan and BIST) or by comparing the chip response to test patterns, as measured with a verification tester versus logic simulation. At Intel it is therefore rare for the E-Beam prober to used for pure logic debug but is often used for circuit debug. Device problems that arise during chip debug can be caused by a variety of reasons; the circuit design itself, circuit design/fab process sensitivities and Understanding and resolving the manufacturing defects (random or systematic). circuit design problems and circuit/FAB sensitivities has the highest impact to product performance and yield. Therefore this is the arena where E-Beam probers have had maximum impact at Intel and we see this continuing into the future. Analyzing manufacturing defects generally falls into the realm of Yield improvement in which the primary concern is defect location and defect reduction. This is also an important application for E-Beam probing - particularly for improving systematic manufacturing problems.

V.R.M. Rae, A. Saini I E-beam probing for design verification at Intel

27

3. BASIC IMPLEMENTATION OF E-BEAM PROBING Electron Beam probers utilize a low voltage (typically 1keV) focused electron beam to probe ICs. E-beam probers have become popular because they do not load the circuits being probed and they do not damage the device under test. In addition they can probe metallization that is less than 1 pm wide with high measurement bandwidth (approximately 2-3 GHz with today’s conventional systems). Many of the early problems with E-Beam probers such as operation of high pin count devices at high speed in vacuum and the problems associated with heating/cooling in vacuum have largely been solved by moving the Electron Beam column while keeping the In DUT fixed and permanently connected to the tester without the use of cables. addition E-beam probers today are much more user friendly than in the past and their ability to integrate Netlists/Schematics and layouts into the machine operation has had a major impact in reducing the time required for chip debug by simplifying the task of locating nodes in a complex chip [2], [3]. At Intel, all major centers are equipped with an E-Beam prober, a Focused Ion Beam (FIB) machine, a Reactive Ion Etcher (RIE), verification testers and a variety of equipment for sample preparation. The typical infrastructure we have put in place to achieve this is illustrated in Figure.1.

PECIMEN PREPARATlON - Decapsulation - Plasma Clean, - Passivation Removal - Ion Mill to access nodes

CAD -Layout Database - Netlists, Schematics - Cross reference files from Intel CVS

E-Beam Installation A TESTER INTERFACE Device exerciser (verification tester, production ATE)

Physical interface (high speed 50 Ohm, high pincount tester to chip interface) Generation of short loops, strobes and expect data for comparison Figure 1. E-Beam probing infrastructure at Intel At Intel chip debug is currently performed at the package level rather than at the wafer level. We have found it simpler and more reliable to operate a high pincount device at full speed inside the E-Beam machine at the package level rather than at

the wafer level. This is particularly true with regards to speed and working distance. All of our high performance devices are packaged into Inverted Cavity ceramic PGA devices. These devices are the most challenging to work with since in operation the surface of the silicon is generally no less than IO mm from the E-beam lens. In order to achieve the smallest working distance the DUT card is designed to perform also as the socket. In this way the chip is inserted directty into the DUT card and the distance between the prober and the silicon surface is minimized. Circuit characterization generally needs relatively good measurement accuracy. We find that this generally occurs when the device is depassivated. We mostly try to work with depassivated devices {4]. If the removal of passivation affects the circuit we generally open up probe holes with an FIB machine and perform measurements on clean metal. The FIB is also used to expose nodes when they are buried under top level metal. At Intel we have integrated CAD navigation into our proprietary CAD tools. Our proprietary layout verification tool is fully hierarchical and generate all the cross reference files which map internal signal nets to the corresponding polygons. These files are available when the chip “tapes out” and ensures that CAD navigation is in place when silicon becomes available. CAD navigation enables one to rapidly locate signals in the chip and is absolutely essential when one is probing chips containing millions of transistors. The signal to be probed is selected in the netlist window. This signal name is then “looked up” in the cross reference dictionary and the polygons corresponding to that net are extracted and hightighted in the layout window. The navigation software communicates with the stage X-Y stage controller in the E-Beam prober so that the image of the chip follows the view of the chip in the layout window and the SEM image and the layout track each other. Currently the largest chip for which navigation has been successfully accomplished contains over 3 million transistors. We generally tend to use both verification and or production testers to stimulate the Device Under Test (DUTJ. Aft implementat;ons utilize a cable-less (hard dock) interface to connect the DUT to the test head. The entire interface from the test head to the pins of the DUT is impedance controlled to 50 Ohms to eliminate reflections. The DUT cards that we use are circular since a radial signal pattern leads to better control for equal length traces and minimizes trace length when the pin count is high. These precautions are essential when the part being probed is operating in the 700 MHz regime inside the E-Beam prober. In addition the interfaces include heating and cooling modules to enable the temperature of the This is necessary since there chip to be controlled during circuit characterization. is no convective cooling inside the E-beam prober vacuum chamber. Our systems currently achieve cooling through the use of Joule Thompson cooling that arises when Carbon Dioxide gas expands through a nozzle.

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V.R.M. Rao, A. Saini I E-beam probing for design verification at Intel

4. TRADEOFFS

DURING

MEASUREMENTS

When an E-beam prober is used as a circuit characterization tool (as opposed to a logic analyzer type of tool) there are many important tradeoffs that come into play. These can be classified firstly into tradeoffs that arise because of the fundamental limitations of E-Beam probing technologies and secondly due to practical limitations in the probing environment. The fundamental limits will first be discussed followed by the practical limits E-beam probing is a sampling (stroboscopic) technique and so the chip must be made to exercise a precisely repeating test loop during the measurement. The typical method used in measuring a waveform is illustrated in Figure.2.

Repetative Waveform to be measured

Sampling Pulses(T~l00

2To+6T

TO

pS and up)

3To+26T

4To+36T

3To+26T

4To+36T

Reconstituted Waveform

V

2To+6T

TO

Figure

2. Stroboscopic

measurement

of waveforms

with an E-Beam

While the chip is exercising a repeating test loop the electron beam is pulsed “on” once per test cycle at one instant in time. The position of the E-Beam pulse is scanned in time to cover the time range of interest to measure the waveform. The fastest on chip signal transition time that can be measured with this technique is limited by the width of the E-beam pulse. If the E-Beam pulse width is z, and the true rise time of an internal signal is rt then the measured rise time rm of the signal

30

V.R.M. Rao, A. Saini I E-beam probing for design verification nt Intel

is approximately 11(2,* + zy). The E-Beam probe oscilloscope with an approximate bandwidth of 0.36/r,.

can be thought

of as an

With stroboscopic measurement the system bandwidth, the measurement noise and the test loop length can be traded off against each other for a given beam current and measurement time. The beam current can also be traded off against spatial resolution. For a given measurement time, the measurement noise falls as the square root of the total number of electrons in each pulse and linearly with decreasing length of the test loop. Since the number of electrons per pulse is fixed by the beam current, then for a given measurement time and given loop length the noise is inversely proportional to the square root of the beam pulse width (or proportional to the square root of the effective scope bandwidth). Because the noise is linearly dependent on the test loop length there is large payback from making the loop length as short as possible. In practice the ideal performance is not always achieved due to practical limitations. These include non optimal working distances, beam drift, contamination build up, dielectric charge up and global field beam deflections. Most high performance products that Intel manufactures are packaged into inverted cavity PGA packages. These packages are the worst case for E-Beam probing since they pose the largest working distance for the prober (typically IOmm or greater). For these devices the collection efficiency is not optimal and the noise performance will be worse than with package types which enable shorter working distances to be used. At longer working distance adjacent line crosstalk could also increase. Another very practical reason for minimizing the program loop length (and hence the measurement time) is to minimize the likelihood that the beam will move off the line while the measurement is in progress - particularly a sub-micron wide line. Contamination build up will change the surface conditions and thereby give rise to measurement The presence of dielectric (such as passivation and Inter layer amplitude errors. Dielectric) also lead to amplitude errors. At Intel we overcome some of these limitations through the use of a Focused Ion Beam to generate probe points or we coat the sample with a thin (IOnm) film of carbon to inhibit charging. Finally global field beam deflections cause a movement of the beam dynamically while the measurement is taking place. Currently we manually correct for this by measuring a Logic State Map over the required time window prior to taking the waveform. In this way we either confirm that there are no beam movements or we partition the waveform into portions that do not suffer any movements. 5. CASE STUDIES The case studies outlined in this section are meant to illustrate the type of problems that are typically analyzed with the E-beam prober and are not meant to illustrate the detailed methodology adopted. The first case (shown in Figure.3) is a classic race condition/speed microprocessor chip. The circuitry in question is shown in Figure. 3.

path inside a

31

V.R.M. Rae, A. Saini I E-beam probing for design verification at Intel

P A

-I

C

-I-

E

K

I

.’

I A

Figure.3

Case Study

++?d+

......

...’ i

:

.

..’ .........’

:+L

. . . .. . .

1

The problem was first logically isolated separately to the suspected circuitry shown. The race Waveforms were then measured from the various internal nodes. between signals A and B causes a pulse (E) which normally would not be a problem with the two phase clocking scheme since this pulse is not latched into subsequent circuitry. However in this instance a heavy capacitive load on the node H delayed this pulse sufficiently that it was erroneously transmitted through to the output (K). The passing and failing conditions were generated by varying the timing between the signals A and B both of which were controllable. In the second case (Shown in Figure.4) a circuit/process sensitivity caused an error in an internal circuit which caused a sense amplifier to flip to the wrong state as

32

V.R.M. Rae, A. Saini I E-beam probing for design verification at Intel

shown in the figure. This flipped bit subsequently caused controf signals to become incorrect leading to wrong data output from the circuit.

Incorrect Data Incorrect control Incorrect Control

... L :

‘.. : :

,.....:

:,,

..,... : :

.:.. :

Figure.4

Time

j .,,,.. : :

: : .._.

: :

:

: :

E ;

Incorrect Sit/E

transition

Correct Bit/Bit

Transition

i .: ::

:: ..,., ......... ...,,,. : : __ __.,, : : :: ,. .,...... .,.... :: :: :: : :

Case study 2

6. FUTURE DIRECTIONS multiple metallization layers, higher clock speeds, shrinking power supply voltages and shrinking geometries are already posing major challenges for Electron Beam Production This wilt only become worse in the future. probing systems. technologies today employ 3 to 4 metallization layers and node observability becomes very poor unless probe points are designed in or a Focused Ion Beam (FIB) system is utilized to cut holes in overpaying metal layers to generate probe points. A combination of these two methods is best. An example of FIB generated Higher clock speeds translate to faster probe holes are illustrated in Figure.5. internal rise times and shorter internal delays. remembering the tradeoffs between time and voltage resolution and signal averaging time in the stroboscopic Method, the only way in which time resolution can be improved without sacrificing the other two variables is to increase the number of electrons in the E-beam pulse. This can

V.R.M. Rao, A. Saini I E-beam probing for design verification at Intel

33

be achieved with a higher beam current through the use of higher brightness electron sources such as Field Emission [5]. Very high peak beam currents can also be achieved with photoemission sources [6]. Shrinking power supply voltages require better voltage resolution and accuracy from the machine for accurate measurements. Again this can be achieved with higher beam currents. The measurement noise improves as the square root of the beam current. Finally the requirement to probe shrinking geometries may not be as urgent as the others needs.

Figure.5

FIB generated

probe holes for E-Beam

probing

This is because the narrowest linewidths tend to exist on lower level metal or polysilicon layers, Since these will not be accessible to the E-Beam anyway the need to probe ultra small structures (< 0.5 ltm) may not arise (at least in production ICs) in the near future, since most routine probing will be performed on probe pads or upper level metallizations. For this reason it is anticipated that the use higher brightness sources is primarily driven by the need for higher time and voltage resolutions rather than for higher spatial resolution. 7. CONCLUSIONS AND ACKNOWLEDGMENTS We have presented in this paper how E-Beam probing has been utilized at Intel for design verification. We have demonstrated that at Intel E-beam probing has had maximum impact in resolving circuit related problems. We have presented in detail

34

V.R.M. Rae, A. Saini ! E-beam probing for design verification at Intel

the infrastructure that exists at Intel for efficient utilization of this technology and have presented some case studies to illustrate applications. Finally we have mentioned some thoughts for the future. The following people at Intel are acknowledged for contributions to this paper: Bob Gottlieb, Jason Stinson and Rick Livengood. REFERENCES 1. Azam Barkatullah et al “Pre-Silicon Validation of Pentium CPU” , Proc of the Hot chips Symposium, Stanford University, Stanford, CA, August 1993 2. S.Concina, N. Richardson: “Workstation Driven E-beam Tester”’ Proc of 1987 International Test Conference , pp.554~560, (Sept.1987) 3. A. Hu, H. Niijima: “New approach to integrate LSI Design Database with E-Beam Tester”, Proc. of 1990 International Test Conference , pp. 1040-I 048, (Sep.1 990) 4. W. Baerg, V.R.M. Rao, R.L. Livengood, “Selective removal of dielectrics from integrated Circuits for Electron Beam Probing” , Proc of 30th annual IRPS conference (1992) pp 320-326 5. Swanson. L et. al. “The Role of Field Emission in Submicron Electron Beam Testing”, This Solid Films 106 (1983) pp 241-255 6. P. May. J-M. Halbout and G. Chiu “A picosecond photoelectron scanning electron microscope for non contact I.C. testing ” Applied physics letters, July 1987