Electron mobility extraction in triangular gate-all-around Si nanowire junctionless nMOSFETs with cross-section down to 5 nm

Solid-State Electronics xxx (2014) xxx–xxx

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Electron mobility extraction in triangular gate-all-around Si nanowire junctionless nMOSFETs with cross-section down to 5 nm Mohammad Najmzadeh a,⇑, Matthieu Berthomé a, Jean-Michel Sallese b, Wladek Grabinski a, Adrian M. Ionescu a a b

Nanoelectronic Devices Laboratory, Swiss Federal Institute of Technology (EPFL), CH-1015 Lausanne, Switzerland STI Scientists Group, Swiss Federal Institute of Technology (EPFL), CH-1015 Lausanne, Switzerland

a r t i c l e

i n f o

Article history: Available online xxxx The review of this paper was arranged by Prof. S. Cristoloveanu Keywords: Si nanowire Gate-all-around Mobility extraction Corner effect Junctionless TCAD Sentaurus Device simulation

a b s t r a c t In this paper, we report the first systematic study on electron mobility extraction in equilateral triangular gate-all-around Si nanowire junctionless nMOSFETs with cross-section down to 5 nm. 1  1019 cm3 ntype channel doping, 5–20 nm Si nanowire width together with 2 nm SiO2 gate oxide thickness were used in the quasistationary TCAD device simulations of 100 nm long channel devices (VDS = 100 mV, T = 300 K). All the extensive studies were performed in strong accumulation regime, as a first step, using a constant electron mobility model (100 cm2/V s). The effects of non-uniform electron density due to corners and quantum confinement effects are investigated. Suppressing the bias-dependency of various key MOSFET parameters e.g. series resistance, by contact engineering, and the product of channel width and gate-channel capacitance, CWeff, by rounding the sharp corners, to improve the accuracy of mobility extraction in strong accumulation is addressed in details. A significant bias-dependent series resistance modulation is reported in GAA Si nanowire junctionless nMOSFETs, leading to a significant electron mobility extraction inaccuracy of 50% in strong accumulation regime. Ó 2014 Elsevier Ltd. All rights reserved.

1. Introduction Multi-gate devices such as gate-all-around (GAA) Si nanowires (NW) and FinFETs are promising candidates for aggressive CMOS downscaling. Optimum subthreshold slope, immunity against short channel effects and optimized power consumption are the major benefits of such architectures due to the best electrostatic control on the channel [1]. Lately, highly and heavily doped architectures with a single-type doping profile from source to drain, called junctionless (JL) and accumulation-mode (AM) devices, are proposed to significantly simplify the fabrication process, address a few technical limitations e.g. ultra-abrupt junctions in order to fabricate shorter channel length devices [2,3]. Multi-gate devices (except circular cross-sections, that can be achievable by stress-limited oxidation [4] or hydrogen annealing [5]) usually have corners (e.g. [6–12]). Precise carrier mobility extraction in such multi-gate devices especially with a deeply scaled cross-section is not simple due to the non-uniform electron density and the normal electric field variation in the channel mainly due to the corners (see e.g. [13–15]). Two major mobility ⇑ Corresponding author. Tel.: +41 21 693 5633; fax: +41 21 693 3640. E-mail address: [email protected]fl.ch (M. Najmzadeh).

extraction methods were reported previously: Y-function (ID/ pffiffiffiffiffiffi g m ) [16] and split-CV [17]. Split-CV is the most available accurate method for carrier mobility extraction, needing both C–V and ID–VG measurements. Note that the C–V measurements require a pretty large device (e.g. a large array of devices operating in parallel, see [18]), hardly feasible using a single nanoscaled device. On the other hand, applying the Y-function on a single scaled device is pretty straightforward, needing only an ID–VG measurement, but requires an accurate estimation of the key device parameters such as the gate-channel capacitance (Cgc) and the effective channel width (Weff) (see e.g. [7,19]). Note that both methods are typically suited to single-gate long channel devices with linear charge accumulation. Therefore, performing a precise carrier mobility extraction assessment in such GAA architectures, especially on sub10 nm cross-sections, would be necessary. In this work, we report the first systematic study on electron mobility extraction in equilateral triangular gate-all-around Si nanowire junctionless nMOSFETs with cross-section down to 5 nm. We intentionally mainly focus on strong accumulation regime, having a channel doping level of 1  1019 cm3 and different channel cross-section dimensions (5–20 nm nanowire width) at VDS = 100 mV (T = 300 K), including the impact of corners. A channel length of 100 nm (>6 times longer than the natural length

http://dx.doi.org/10.1016/j.sse.2014.04.007 0038-1101/Ó 2014 Elsevier Ltd. All rights reserved.

Please cite this article in press as: Najmzadeh M et al. Electron mobility extraction in triangular gate-all-around Si nanowire junctionless nMOSFETs with cross-section down to 5 nm. Solid State Electron (2014), http://dx.doi.org/10.1016/j.sse.2014.04.007

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2. 3D TCAD numerical device simulation TCAD Sentaurus Device (G.2012-06) was used for quasistationary numerical simulation of GAA Si nanowire nMOSFETs, adapting the 3D TCAD Si nanowire simulation platform that we developed earlier in [15] with the current geometrical dimensions (see Fig. 1-top). For all the nanowire widths (5, 10 and 20 nm), the gate length and SiO2 gate oxide thickness are 100 and 2 nm, respectively. The channel doping is 1  1019 cm3. The source/drain extensions are 20 nm long and the doping levels are either 1  1020 cm3 (contact engineered) or 1  1019 cm3 (similar to the channel). A fixed mid-gap gate workfunction of 4.5 eV was used as well. Using electrostatic and quasi-Fermi potential equations, the local carrier current and carrier density in a 3D architecture nMOSFET can be extracted at each bias voltage. The density gradient quantization model is coupled to the Poisson equation [26,27] to include the 3D quantization effects. A Fermi–Dirac statistics was used, considering both degenerate and non-degenerate regimes [27]. Finally, the semi-classical Slotboom bandgap narrowing model was used for the heavily doped Si regime [27,28]. 2.1. Subthreshold to strong accumulation with a constant mobility model To assess the accuracy of the typical mobility extraction methodologies, we perform quasistationary TCAD Device simulations at a constant mobility of e.g. 100 cm2/V s in the entire channel crosssection as a first step, considering both classical (CE) and quantum (QE) electrons. In this case, series resistance would be the only effective channel mobility attenuation or transconductance degradation mechanism in the device characteristics, plotted in Fig. 1-bottom. Afterward, this study can be extended considering field-dependent mobility models [27] including bias and

Z

X

Y

-4

10

VDS=100 mV

QE CE

-5

10

12.0 10.0

-6

10

-7

-8

10

6.0

-9

10

WNW=5 to 20 nm

-10

ID (µA)

8.0

10

ID (A)

[15,20] of the widest nanowire) was chosen to provide a clear short channel free mobility extraction assessment in such architectures. Such studies can be extended further to the shorter channel junctionless devices e.g. [12]. Note that a triangular cross-section was chosen mainly due to the narrowest corner angle among the symmetrical architectures and therefore, more significant corner effects. Two source/drain doping levels would be considered: 1  1020 cm3 (contact engineered) and 1  1019 cm3 (the same doping as channel). No contact engineering causes a strong biasdependent series resistance in strong accumulation (diffusion of electrons from the channel ends to the source/drain extensions) [21] and accounting for such series resistances in the I–V characteristics is not straightforward. Therefore and as a first step, mobility extraction assessment is done on the contact engineered nMOSFETs, considering a constant carrier mobility model. This study can be extended further including the recently observed bias and widthdependent screening effects in heavily doped regime of junctionless devices [22–24] that could lead to obtain even higher carrier mobility than bulk Si without using CMOS boosters e.g. strain [25]. Therefore, the effective series resistance in strong accumulation can be assumed constant in the contact engineered junctionless devices, somehow similar to the typical inversion-mode (IM) devices. This is mainly to investigate the accuracy of the low-field mobility extraction procedures, using both split-CV and Y-function methods in case of high non-uniform electron density in the channel cross-section due to the corner effects. Lastly, mobility extraction assessment would be done on a junctionless nMOSFET without contact engineering, performing a bias-dependent series resistance correction in strong accumulation using quasi-Fermi potentials over the channel.

4.0

10

-11

10

2.0

-12

10

-13

10

-0.5

0.0

0.5

1.0

0.0 1.5

VGS (V) Fig. 1. The equilateral triangular GAA 10 nm wide Si nanowire nMOSFET used for 3D TCAD simulations (top) and transfer characteristics of GAA Si nanowire junctionless nMOSFETs with engineered contacts at VDS = 100 mV (bottom). CE and QE correspond to classical and quantum electrons, respectively.

width-dependent screening effects in heavily doped regime [22–24], auto-orientation to support various Si nanowire surfaces [27] and in the presence of a corner-based non-uniform normal electric field in the channel cross-section (see e.g. Fig. 2).

2.2. Operation of GAA Si nanowire junctionless nMOSFETs The flat-band voltage is the voltage that the conduction mechanism changes from depletion (below flat-band) to accumulation (above flat-band). In addition, below flat-band, most of the carriers flow inside the channel, while above flat-band, in addition to the bulk current, a surface conduction occurs. Therefore, the current

-1

0.01 0.009 0.008

Z [um]

2

0.007

Abs(ElectricField)[V*cm ] 3.0E+06 4.8E+05 7.5E+04 1.2E+04 1.9E+03 3.0E+02

0.006 0.005 0.004 0.003 0.002

-0.004

-0.002

0

0.002

0.004

Y [um] Fig. 2. Cross-sectional absolute electric field pattern at the middle of the GAA 10 nm wide Si nanowire junctionless nMOSFET with engineered contact in strong accumulation at VDS = 100 mV (oxide is not shown, VGS = 1.500 V).

Please cite this article in press as: Najmzadeh M et al. Electron mobility extraction in triangular gate-all-around Si nanowire junctionless nMOSFETs with cross-section down to 5 nm. Solid State Electron (2014), http://dx.doi.org/10.1016/j.sse.2014.04.007

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in accumulation regime is the sum of bulk and accumulation currents (see [6,29]). 3. Extraction of key MOSFET parameters in GAA Si nanowire JL nMOSFETs with scaled cross-section Fig. 3 depicts ID–VGS and QG–VGS characteristics of a 20 nm wide nanowire junctionless nMOSFET with engineered contact including quantization at VDS = 100 mV and 0 V, respectively, including quantization. The figure includes the corresponding derivatives while all the curves were normalized to the maximum values. Table 1 reports the numerical values of the extracted key MOSFET parameters for the simulated devices, using the described methodologies in Sections 3 and 4. 3.1. Threshold voltage extraction method The threshold voltage of a GAA Si nanowire junctionless MOSFET can be extracted from the peak of the second derivative of drain current [30], quasi-independent of series resistance and conduction mechanism (see also [6]). The quantization-based threshold and flat-band voltage upshifts in Table 1 are due to the higher quantized sub-band energies [6,15,31,32].

Similar to [15], the effective flat-band voltage for the entire device can be extracted from QG–VGS simulations at VDS = 0 V (x1C intercept, no fitting or extrapolation), called V 1Q FB and V FB for both quantum and classical cases, respectively (see Fig. 3). Obviously, the flat-band condition can be reached for the classical case in all the Si nanowires with various widths and at VGS = 0.360 V (uninform electrostatic potential in the entire channel crosssection, even in the corners), that is called V CFB . The slight difference C between V 1C FB and V FB in a sub-1 mV range, due to the extraction methodology, can be used to report a more accurate effective flat-band voltage for the quantum electrons, called V QFB . 3.3. Gate-channel capacitance and effective channel width Using the QG–VGS simulations at VDS = 0 V, the total gate-channel capacitance (CG) can be extracted by:

Normalized quantities to maximum

dQ G ðV GS Þ dV GS

WNW=20 nm

0.9

0.7 0.6 0.5

ID

0.4

QG

0.3

dQG/dVGS

Q

VTH

0.2

gm

1Q

VFB

0.1

dgm/dVGS

0.0

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

VGS (V) Fig. 3. Normalized characteristics of the GAA 20 nm wide Si nanowire junctionless nMOSFET with engineered contact including quantization (normalization to the corresponding maximum value). The maximum numeric values of ID, gm, dgm/dVGS at VDS = 100 mV and QG and dQG/dVGS at VDS = 0 V are 1.04  105 A, 7.52  106 A/V, 2.04  105 A/V2, 1.00  1016 C and 9.84  1017 F, respectively.

C G ðV GS Þ L

ð2Þ

4. Electron mobility extraction assessment in GAA Si nanowire JL nMOSFETs with engineered contact Figs. 4 and 5 show local classical and quantum electron densities in the channel cross-sections and at the middle of the gate (x = L/2) in strong accumulation (VGS = 1.5 V). Quantization induces a higher local electron accumulation in the corner regions together with a strong electron pattern redistribution in the 5 nm wide nanowire in comparison to the wider cross-sections. 4.1. Electron mobility extraction using split-CV method Similar to the split-CV method in inversion-mode MOSFETs while operating in linear inversion regime [17], it is feasible to show that using the derived ID–VGS analytical formula in [29], the effective electron mobility in linear accumulation regime (VGS– VFB > VDS, VGS > VFB) for a junctionless/accumulation-mode nMOSFET can be calculated using both transfer and charge–voltage characteristics by:

leff ðV GS Þ ¼

0.8

ð1Þ

According to Fig. 3, this capacitance is varying by gate voltage, even in strong accumulation (e.g. 13% variation from VGS = 1.0 to 1.5 V in Fig. 3). The gate-oxide capacitance is typically a geometrical parameter for long bulk single-gate MOSFETs (depending on the gate-oxide thickness and geometry). Quantum confinement [33], Debye broadening effect [34] and the depletion layer below the flat-band voltage are the effects that modify the total gate-channel capacitance from subthreshold to strong accumulation. On the other hand, the effective channel width for both classic and quantum cases are not the same due to the modifications in the electron density pattern in the channel cross-section by quantum confinement. The effective channel width, even for the classical case, can vary with the gate voltage due to the corner effect (non-uniform local accumulation of electrons in the channel cross-section). Therefore, to simplify the parameter extraction method, we consider an effective product of the channel-gate capacitance with the channel width, called CWeff. This product, a bias-dependent parameter, can be extracted from the total gate-channel capacitance by (L: channel length):

CWeff ðV GS Þ ¼

3.2. Flat-band voltage extraction method

1.0

C G ðV GS Þ ¼

3

2 Iacc D ðV GS Þ  L acc Q G ðV GS Þ  V DS

ð3Þ

The contribution arising from the accumulation current above flatband can be obtained by subtracting the drain current at flat-band (V CFB or V QFB in Table 1) from the total drain current. Fig. 6 depicts the bias-dependency of the effective electron mobility above flat-band for the three Si nanowire devices. Series resistance is the only transconductance or effective mobility drop mechanism in this paper due to using a constant electron mobility model. Therefore, a simple series resistance correction (see e.g. [35] for the inversion-mode MOSFETs) can be done to estimate the numeric value of low-field electron mobility (l0 ). By neglecting slight bias-dependency of MOSFET parameters over strong accumulation regime (e.g. CWeff and series resistance), assuming a linear charge accumulation above flat-band, an almost symmetric source/drain series resistance on the both channel sides and finally, the accumulation current as the dominant current component in strong accumulation regime, the bias-dependency of the effective carrier mobility can be estimated by:

Please cite this article in press as: Najmzadeh M et al. Electron mobility extraction in triangular gate-all-around Si nanowire junctionless nMOSFETs with cross-section down to 5 nm. Solid State Electron (2014), http://dx.doi.org/10.1016/j.sse.2014.04.007

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M. Najmzadeh et al. / Solid-State Electronics xxx (2014) xxx–xxx

Table 1 Key MOSFET parameters extracted from device simulations of GAA Si nanowire junctionless nMOSFETs with engineered contact. WNW V CTH

V QTH

V 1C FB

V 1Q FB

V CFB

V QFB

CW0:5C eff

(nm) (V)

(V)

(V)

(V)

(V)

(V)

(pF/cm) (pF/cm) (pF/cm) (pF/cm) (cm2/V s) (1/V) (cm2/V s) (1/V) (kX)

20 10 5

0.096 0.092 0.361 0.399 0.360 0.398 9.99 0.202 0.219 0.361 0.413 0.360 0.412 5.32 0.320 0.397 0.361 0.454 0.360 0.453 2.94

CW1:0C eff 10.2 5.48 3.05

0:5Q CWeff

9.22 4.72 2.61

1:0Q CWeff

9.77 5.20 2.97

lC0 92.5 91.6 92.0

eDensity [cm-3]

0.018

2.3E+20

0.009

1.0E+20 4.8E+19

0.008

2.2E+19 1.0E+19

0.012

Z [um]

Z [um]

0.014

0.01

lQ0

0.143 91.2 0.275 90.6 0.593 92.4

0.01

5.0E+20

0.016

hC

0.007

hQ

RCSD

RQSD

0:5C RSD

1:0C RSD

lYC 0

(kX)

(kX)

(kX)

(cm2/V s) (cm2/V s)

0.122 1.53 1.41 1.35 1.35 89.9 0.239 5.55 5.31 5.29 5.26 89.0 0.547 21.56 21.23 21.71 21.65 89.1

lYQ 0 84.7 80.0 76.4

eDensity [cm-3] 5.0E+20 2.3E+20 1.0E+20 4.8E+19 2.2E+19 1.0E+19

0.006

0.008

0.005

0.006

0.004

0.004

0.003 0.002

0.002 -0.01

-0.005

0

0.005

0.01

Y [um]

-0.004

-0.002

0

0.002

0.004

Y [um]

Fig. 4. Cross-sectional local classical electron density pattern at the middle of the GAA Si nanowire junctionless nMOSFETs with engineered contact and different nanowire widths (top left: 20 nm, top right: 10 nm, bottom: 5 nm) in strong accumulation at VDS = 100 mV (oxide is not shown, VGS = 1.500 V).

leff ðV GS Þ 

l0 1 þ h  ðV GS  V FB Þ

ð4Þ

The h parameter, effective mobility attenuation factor, can be estimated by:

h

RSD  l0  CWeff L

ð5Þ

Using least-square approximation fitting of the 1/leff (VGS) curves in Fig. 6 over 0.5–1.0 V of VGS–VFB bias range, the numeric values of both l0 and h are extracted and afterward, reported in Table 1. Based on the observed results, this method provides an almost precise estimation on low-field mobility (a sub-9% inaccuracy) for the three nanowire architectures. Note that this slight inaccuracy is mainly due to neglecting the bias-dependency of the key MOSFET parameters over strong accumulation regime, slight actual VGS variation by series resistance at low VDS (100 mV) while using both

QG–VGS and ID–VGS device characteristics and finally, key device parameter extraction methodologies.

4.2. Series resistance and effective electron mobility attenuation Using Eq. (5), the approximate effective series resistance numeric values for each device are calculated based on the extracted h numeric values in Table 1 and reported in the same table (called RCSD and RQSD ). The results reflect an increase in the effective series resistance by cross-section shrinkage while the effective series resistance increases do not vary exactly by the cross-section downscaling factor. This is mainly due to the slight bias-dependency of MOSFET parameters e.g. slight actual gate length modulation by gate voltage due to the fringing electric fields at the both channel ends. Finally and as a comparison, the total resistance of the source/ drain extensions for all the devices are calculated based on the

Please cite this article in press as: Najmzadeh M et al. Electron mobility extraction in triangular gate-all-around Si nanowire junctionless nMOSFETs with cross-section down to 5 nm. Solid State Electron (2014), http://dx.doi.org/10.1016/j.sse.2014.04.007

5

M. Najmzadeh et al. / Solid-State Electronics xxx (2014) xxx–xxx eDensity [cm-3]

eDensity [cm-3]

0.018

0.01

2.0E+20 1.1E+20

0.016

0.009

6.0E+19 3.3E+19

0.014

0.008

1.0E+19

0.012

Z [um]

Z [um]

1.8E+19

0.01

0.007

9.6E+19 5.5E+19 3.1E+19 1.8E+19 1.0E+19

0.006

0.008

0.005

0.006

0.004

0.004

0.003

0.002

1.7E+20

0.002 -0.01

-0.005

0

0.005

0.01

-0.004

-0.002

Y [um]

0

0.002

0.004

Y [um] eDensity [cm-3]

0.007

1.6E+20 9.1E+19 5.2E+19 3.0E+19

0.006

1.7E+19

Z [um]

1.0E+19

0.005

0.004

0.003 -0.002

-0.001

0

0.001

0.002

Y [um] Fig. 5. Cross-sectional local quantum electron density pattern at the middle of the GAA Si nanowire junctionless nMOSFETs with engineered contact and different nanowire widths (top left: 20 nm, top right: 10 nm, bottom: 5 nm) in strong accumulation at VDS = 100 mV (oxide is not shown, VGS = 1.500 V).

100 90

16

12

WNW=5 to 20 nm

3.0x10

2.5x10-3

50

0.5 0.5

40 30

10

-3

20

QE CE

10 0.0

0.2

8

2.0x10-3

6

1.5x10-3 1.0x10-3

WNW↓

5.0x10-4 0.0 0.0

0.5

VGS-VFB(V)

0.4

0.6

0.8

1.0

2

70

1/µeff(mV.s/cm )

14

Y(A .V )

2

µeff(cm /V.s)

80

60

4.3. Electron mobility extraction using Y-function method

18

VDS=100 mV

WNW↑

4 2 0 1.0

VGS-VFB(V) Fig. 6. Effective electron mobility and its reverse vs. VGS–VFB for GAA Si nanowire junctionless nMOSFETs with engineered contact (5, 10, 20 nm nanowire width). The inset shows the Y-function vs. VGS–VFB for the three architectures.

classical quasi-Fermi potentials at the nanowire channel ends at both 0.5 and 1.0 V of VGS–VFB (called R0:5C and R1:0C SD SD , respectively) and later on, reported in Table 1. According to this table, the total resistance of the source/drain extensions is slightly bias-dependent, a sub-0.7% modulation for all the architectures, over the mentioned bias regime.

Considering the earlier developed analytical formula for the accumulation current in linear accumulation regime of a junctionless MOSFET [29] (see also [6]), and its similarity to the inversionmode MOSFETs, it is possible to show that the Y-function at each bias voltage can be calculated by:

Iacc ðV GS Þ YðV GS Þ ¼ pDffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi  g m ðV GS Þ

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi W l0  C gc  V DS  eff  ðV GS  V FB Þ L

ð6Þ

Note that this method, despite the split-CV (that is based on the actual accumulated charges to estimate the effective carrier mobility), is based on a linear charge accumulation in the channel over strong accumulation regime, neglecting the slight bias-dependency of both effective channel width (Weff) and gate-channel capacitance (Cgc). Fig. 6-inset shows the Y-function vs. VGS–VFB for all the Si nanowire architectures. An accurate estimation on low-field electron mobility using the Y-function method requires a precise estimation on both Weff and Cgc parameters. Therefore and considering the strong link between the gate-channel capacitance and the actual channel width, despite using an approximate analytical formula to extract each parameter separately (see e.g. [19]), the average numeric value of CWeff over 0.5–1.0 V of VGS–VFB range from the 1:0 QG–VGS device simulations (called CW0:5 eff and CWeff , respectively, in Table 1) can be used to extract the numeric value of low-field electron mobility. As reported in Table 1, the extracted classical

Please cite this article in press as: Najmzadeh M et al. Electron mobility extraction in triangular gate-all-around Si nanowire junctionless nMOSFETs with cross-section down to 5 nm. Solid State Electron (2014), http://dx.doi.org/10.1016/j.sse.2014.04.007

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low-field electron mobility values (lYC 0 ) are almost close to the actual constant electron mobility value (a sub-11% under-estimation) and a sub-3% under-estimation from the lC0 numeric values extracted using the split-CV method.

According to Table 1, due to the strong quantization effect in the 3D structures with sharp corners and therefore, the higher biasdependency of CWeff, especially for the 5 nm wide nanowire, the Y-function shows a higher deviation from the actual constant electron mobility value in comparison to the classical case (up to 24%). In this section, quantized device simulations were done using the prior device architectures but with rounded channel and oxide corners, with a nanowire corner radius of 1 nm. The low-field mobility values are extracted using the prior mentioned methods and reported in Table 2. Due to a smaller bias-dependency of the quantized CWeff parameter while rounding the corners (sub-6% vs. sub14% over 0.5–1.0 V of VGS–VFB range, respectively; see Fig. 7), the Yfunction shows a sub-15% under-estimation from the actual constant mobility value and a sub-8% under-estimation from the split-CV method. 5. Electron mobility extraction assessment in a GAA Si nanowire JL nMOSFET without engineered contact Fig. 8 depicts the classical ID–VGS and QG–VGS characteristics of a GAA 20 nm wide Si nanowire junctionless nMOSFET without contact engineering, at VDS = 100 mV and 0 V, respectively, together with the corresponding derivatives. The doping profile is constant along the device from source to drain (1  1019 cm3). The effective electron mobility values, extracted using the split-CV method, are plotted in Fig. 9 (called direct split-CV in the figure). According to his figure, there is an unexpected significant effective electron mobility drop in comparison to Fig. 6 over strong accumulation regime. The extracted low-field electron mobility numeric value, using Eq. (4), over 0.5–1.0 V of VGS–VFB range is 56 cm2/V s, a 44% under-estimation from the actual constant electron mobility value. Applying the Y-function method over 0.5–1.0 V of VGS–VFB range (see Fig. 8) also results a low-field electron mobility value of 48 cm2/V s, 52% under-estimation from the actual constant electron mobility value. This high under-estimation on electron mobility is mainly due to the significant total source/drain extension resistance modulation by gate voltage over strong accumulation (13.2–13.4 k X, over 0.5–1.0 V of VGS–VFB range, 30 times higher than the corresponding resistance modulation in the case of contact engineering). The correction of this bias-dependent series resistance on device characteristics is not straightforward. Fig. 9-inset shows the actual source and drain quasi-Fermi potentials over the both channel ends (V D and V S ) vs. gate voltage. Using V DS (bias-dependent) instead of VDS (= 100 mV), the numeric value of effective electron mobility at each gate voltage can be calculated using Eq. (3) and the results are plotted in Fig. 9 (called modified split-CV in this figure). According to this figure, the effective electron mobility numeric values after cancelling the series resistance effect are

VDS=0 V

8

CWeff (pF/cm)

4.4. Accuracy of quantized Y-function and sharp corners

10

CE QE QE-rounded

6

4

2

WNW=5 to 20 nm 0 0.0

0.2

0.4

0.6

0.8

1.0

VGS-VFB(V) Fig. 7. Bias-dependency of CWeff for GAA Si nanowire junctionless nMOSFETs including sharp and rounded corners with engineered contact. The bias-dependency of quantized CWeff above flat-band can be suppressed significantly by rounding the corners.

now close to the constant electron mobility value, a sub-5% under-estimation over 0.5–1.0 V of V GS –VFB range and mainly, due to the device parameter extraction methodology. 5.1. Origin of significant bias-dependency of series resistance in Si nanowire junctionless nMOSFETs A constant doping level profile along the device from source to drain leads to diffusion of electrons from the channel ends to the source/drain extensions in strong accumulation, causing a high bias-dependent series resistance in this bias regime. Note that this gate voltage-based resistance modulation of the source/drain extensions in strong accumulation regime can be considered as a bias-dependent channel length modulation, representing a device with a longer actual channel length than its nominal (or physical) channel length. Since both the split-CV and the Y-function methods to extract the electron mobility numeric value are based on a constant series resistance, can be translated to a constant gate length as well, a precise electron mobility extraction using both methods would not be straightforward. Increasing the source/drain doping level, called contact engineering in this paper, would suppress this issue, while adds an ion implantation/dopant activation step to the Si nanowire process flow. 6. Discussion and possible future works This paper addresses the first systematic study on electron mobility extraction in 100 nm long channel GAA Si nanwoire junctionless nMOSFETs with cross-section down to 5 nm and including corners, using 3D TCAD device simulations. We performed all the analyses in accumulation regime as a first step due to its more linear ID–VGS relationship in comparison to bulk regime (see e.g. [29,36]). This study can be extended to the GAA Si nanowire junctionless/accumulation-mode devices below flat-band or to the inversion-mode MOSFETs in strong inversion regime. Note that in

Table 2 Electron mobility extraction in the engineered contact GAA Si nanowire junctionless nMOSFETs with rounded corners (nanowire corner radius: 1 nm). WNW

V CTH

V QTH

V CFB

V QFB

0:5Q CWeff

CW1:0Q eff

lQ0

lYQ 0

(nm)

(V)

(V)

(V)

(V)

(pF/cm)

(pF/cm)

(cm2/V s)

(cm2/V s)

20 10 5

0.094 0.202 0.323

0.089 0.221 0.402

0.360 0.360 0.360

0.395 0.407 0.452

8.60 4.29 2.17

8.98 4.55 2.28

92.2 91.4 91.7

87.2 84.7 86.7

Please cite this article in press as: Najmzadeh M et al. Electron mobility extraction in triangular gate-all-around Si nanowire junctionless nMOSFETs with cross-section down to 5 nm. Solid State Electron (2014), http://dx.doi.org/10.1016/j.sse.2014.04.007

Normalized quantities to maximum

M. Najmzadeh et al. / Solid-State Electronics xxx (2014) xxx–xxx

bias and width-dependent carrier mobility models [22–24] can be the next clear steps.

WNW=20 nm

1.0 0.9 0.8

7. Conclusion

0.7 0.6

ID

0.5

QG

0.4

dQG/dVGS gm

0.3 C

VTH

0.2

dgm/dVGS

1C

VFB

0.1

Y-function

0.0 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

VGS(V) Fig. 8. Normalized classical characteristics of the GAA 20 nm wide nanowire nMOSFET (normalized to the corresponding maximum value) without contact engineering. The maximum numeric values of ID, gm, dgm/dVGS, Y at VDS = 100 mV; QG and dQG/dVGS at VDS = 0 V are 4.80  106 A, 4.63  106 A/V, 1.88  105 A/V2, 2.59  103 A0.5 V0.5, 1.13  1016 C, 1.03  1016 F, respectively (V CTH ¼ 0:102 V, V CFB ¼ V 1C FB ¼ 0:360 V).

100

25 0 0.0

2

WNW=20 nm * VS

0.5

1.0

30

1.5

VG(V)

40 15 20

Direct split CV Modified split CV 0

Acknowledgements

45 2

50

VDS=100 mV

* VDS

1/µeff(mV.s/cm )

60

* * * VS, VD, VDS(mV)

80

* VD

75

In this paper, electron mobility extraction assessment was done on equilateral triangular GAA Si nanowire junctionless nMOSFETs with the nanowire cross-section down to 5 nm. This study was performed addressing the bias-dependency of various key MOSFET parameters, non-linear charge accumulation due to corners and in accumulation regime. Suppressing the bias-dependency of some key MOSFET parameters to extract electron mobility properly, e.g. by contact engineering or rounding the sharp corners, were addressed in details in this paper. We showed that this can lead to extract electron mobility by sub-9% and sub-15% inaccuracies, using the split-CV and the Y-function methods, respectively, in the GAA Si nanowire junctionless nMOSFETs with cross-section down to 5 nm in strong accumulation regime.

This work is supported by Swiss National Science Foundation (SNSF). The authors would like to thank Prof. Andreas Schenk, Swiss Federal Institute of Technology (ETHZ), Zurich, Switzerland, for advice on 3D quantized device simulations at nanoscale.

60 100

µeff (cm /V.s)

7

0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

* -V (V) VGS-VFB(V), VGS FB Fig. 9. Effective electron mobility vs. VGS–VFB (direct split-CV) or V GS –VFB (modified split-CV) for the GAA 20 nm wide Si nanowire junctionless nMOSFET without contact engineering. The inset shows source and drain quasi-Fermi potentials at the both channel ends.

bulk regime (above threshold and below flat-band), the CWeff parameter is highly bias-dependent (see e.g. Fig. 3), due to the surface and local volume charge depletion specially in the corners [15] leading to shrinkage on both gate-channel capacitance and effective channel cross-section. Since the Y-function is based on almost constant key device parameters e.g. Cgc and Weff, the split-CV method might be the major applicable method to extract mobility in bulk regime. In this paper, we showed that bias-dependency of some key MOSFET parameters e.g. CWeff and series resistance can lead to a high inaccuracy in electron mobility estimation in GAA Si nanowire junctionless nMOSFETs. Studying and possible modeling of such bias-dependencies at various channel lengths, channel and source/drain doping levels, gate-oxide thicknesses and channel geometries (e.g. various polygons, rounded polygons, circular) would be interesting. Note that such Si nanowire cross-sections can be experimentally achievable e.g. [6,7,37–39]. Finally, studying precise device analysis and mobility extraction in short-channel devices for the scaled cross-sectional Si nanowire MOSFETs, in the presence of corners, and studying the electron mobility extraction in such devices using electric field-dependent [27] as well as

References [1] Kuhn KJ. Considerations for ultimate CMOS scaling. IEEE Trans Electron Dev 2012;59:1813–28. [2] Colinge J-P et al. Nanowire transistors without junctions. Nature Nanotechnol 2010;5:225–9. [3] Colinge J-P et al. Properties of accumulation-mode multi-gate field-effect transistors. Jpn J Appl Phys 2009;48:034502. [4] Liu HI, Biegelsen DK, Johnson NM, Ponce FA, Pease RFW. Self-limiting oxidation of Si nanowires. J Vac Sci Technol B 1993;11:2532–7. [5] Lee M-CM, Wu MC. Thermal annealing in hydrogen for 3-D profile transformation on silicon-on-insulator and sidewall roughness reduction. J Microelectromech Syst 2006;15:338–43. [6] Najmzadeh M, Bouvet D, Grabinski W, Sallese J-M, Ionescu AM. Accumulationmode gate-all-around Si nanowire nMOSFETs with sub-5 nm cross-section and high uniaxial tensile strain. Solid-State Electron 2012;74:114–20. [7] Najmzadeh M, Tsuchiya Y, Bouvet D, Grabinski W, Ionescu AM. Multigate buckled self-aligned dual Si nanowire MOSFETs on bulk Si for high electron mobility. IEEE Trans Nanotechnol 2012;11:902–6. [8] Najmzadeh M, Tsuchiya Y, Bouvet D, Grabinski W, Ionescu AM. Gate-allaround buckled dual Si nanowire nMOSFETs on bulk Si for transport enhancement and digital logic. Microelectron Eng 2013;110:278–81. [9] Najmzadeh M, Bouvet D, Grabinski W, Ionescu, AM. Uniaxially tensile strained accumulation-mode gate-all-around Si nanowire nMOSFETs. In: IEEE DRC; 2011. p. 145–6. [10] Najmzadeh M, Bouvet D, Grabinski W, Ionescu AM. Accumulation-Mode GAA Si NW nFET with sub-5 nm cross-section and high uniaxial tensile strain. In: IEEE ESSDERC; 2011. p. 311–4. [11] Najmzadeh M, Bouvet D, Grabinski W, Ionescu AM. Local stressors to accommodate 1.2 to 5.6 GPa uniaxial tensile stress in suspended gate-allaround Si nanowire nMOSFETs by elastic local buckling. In: IEEE ISDRS; 2011. p. 1–2. [12] Barraud S, Berthomé M, Coquand R, Cassé M, Ernst T, Samson M-P, et al. Scaling of trigate junctionless nanowire MOSFET with gate length down to 13 nm. IEEE Electron Dev Lett 2012;33:1225–7. [13] Fossum JG, Yang JW, Trivedi VP. Suppression of corner effects in triple-gate MOSFETs. IEEE Electron Dev Lett 2003;24:745–7. [14] Garcia Ruiz FJ, Godoy A, Gamiz F, Sampedro C, Donetti L. A comprehensive study of the corner effects in pi-gate MOSFETs including quantum effects. IEEE Trans Electron Dev 2007;54:3369–77. [15] Najmzadeh M, Sallese J-M, Berthomé M, Grabinski W, Ionescu AM. Local volume depletion/accumulation in GAA Si nanowire junctionless nMOSFETs. IEEE Trans Electron Dev 2012;59:3519–26. [16] Ghibaudo G. New method for the extraction of MOSFET parameters. Electron Lett 1988;24:543–5. [17] Sodini CG, Ekstedt TW, Moll JL. Charge accumulation and mobility in thin dielectric MOS transistors. Solid-State Electron 1982;25:833–41. [18] Gunawan O, Sekaric L, Majumdar A, Rooks M, Appenzeller J, Sleight JW, et al. Measurement of carrier mobility in silicon nanowires. Nano Lett 2008;8: 1566–71.

Please cite this article in press as: Najmzadeh M et al. Electron mobility extraction in triangular gate-all-around Si nanowire junctionless nMOSFETs with cross-section down to 5 nm. Solid State Electron (2014), http://dx.doi.org/10.1016/j.sse.2014.04.007

8

M. Najmzadeh et al. / Solid-State Electronics xxx (2014) xxx–xxx

[19] Moselund KE, Najmzadeh M, Dobrosz P, Olsen SH, Bouvet D, De Michielis L, et al. The high-mobility bended n-channel silicon nanowire transistor. IEEE Trans Electron Dev 2010;57:866–76. [20] Colinge J-P. FinFETs and other multigate transistors. Springer; 2007. [21] Najmzadeh M, Sallese J-M, Berthomé M, Grabinski W, Ionescu AM. Mobility extraction assessment in GAA Si NW JL FETs with cross-section down to 5 nm. In: IEEE ULIS; 2013. p. 105-8. [22] Jeon D-Y, Park SJ, Mouis M, Berthomé M, Barraud S, Kim GT, et al. Electrical characterization and revisited parameter extraction methodology in junctionless transistors. In: EuroSOI; 2011. p. 109–10. [23] Goto K-I, Yu T-H, Wu J, Diaz CH, Colinge JP. Mobility and screening effect in heavily doped accumulation-mode metal oxide-semiconductor field-effect transistors. Appl Phys Lett 2012;101:073503. [24] Rudenko T, Nazarov A, Ferain I, Das S, Yu R, et al. Mobility enhancement effect in heavily doped junctionless nanowire silicon on-insulator metal-oxidesemiconductor field-effect transistors. Appl Phys Lett 2012;101:213502. [25] Chu M, Sun Y, Aghoram U, Thompson SE. Strain: a solution for higher carrier mobility in nanoscale MOSFETs. Ann Rev Mater Res 2009;39:203–29. [26] Ancona MG, Iafrate GJ. Quantum correction to the equation of state of an electron gas in a semiconductor. Phys Rev B 1989;39:9536–40. [27] Sentaurus Device User Guide Version G-2012.06. Synopsys, Mountain View, CA; 2012. [28] Klaassen DBM, Slotboom JW, de Graaff HC. Unified apparent bandgap narrowing in n- and p-type silicon. Solid-State Electron 1992;35:125–9. [29] Sallese J-M, Chevillon N, Lallement C, Iniguez B, Pregaldiny F. Charge-based modeling of junctionless double-gate field-effect transistors. IEEE Trans Electron Dev 2011;58:2628–37.

[30] Wong H-S, White MH, Krutsick TJ, Booth RV. Modeling of transconductance degradation and extraction of threshold voltage in thin oxide MOSFET’s. SolidState Electron 1987;30:953–68. [31] Majima H, Ishikuro H, Hiramoto T. Experimental evidence for quantum mechanical narrow channel effect in ultra-narrow MOSFET’s. IEEE Electron Dev Lett 2000;21:396–8. [32] Yuan Y, Yu B, Song J, Taur Y. An analytic model for threshold voltage shift due to quantum confinement in surrounding gate MOSFETs with anisotropic effective mass. Solid-State Electron 2009;53:140–4. [33] Uchida K, Koga J, Ohba R, Numata T, Takagi SI. Experimental evidences of quantum-mechanical effects on low-field mobility, gate-channel capacitance, and threshold voltage of ultrathin body SOI MOSFETs. In: IEEE IEDM; 2001. p. 29.4.1–29.4.4. [34] Grove AS, Deal BE, Snow EH, Sah CT. Investigation of thermally oxidised silicon surfaces using metal-oxide-semiconductor structures. Solid-State Electron 1965;8:145–63. [35] Schroder DK. Semiconductor material and device characterization. John Wiley and Sons; 2006. [36] Berthomé M, Barraud S, Ionescu AM, Ernst T. Physically-based, multiarchitecture, analytical model for junctionless transistors. In: IEEE ULIS; 2010. p. 1–4. [37] Li C-P, Lee C-S, Ma X-L, Wang N, Zhang R-Q, Lee S-T. Growth direction and cross-sectional study of silicon nanowires. Adv Mater 2003;15:607–9. [38] Wu Y, Cui Y, Huynh L, Barrelet CJ, Bell DC, Lieber CM. Controlled growth and structures of molecular-scale silicon nanowires. Nano Lett 2004;4:433–6. [39] Tachi K, Relationship between mobility and high-k interface properties in advanced Si and SiGe nanowires. In: IEEE IEDM; 2009. p. 1–4.

Please cite this article in press as: Najmzadeh M et al. Electron mobility extraction in triangular gate-all-around Si nanowire junctionless nMOSFETs with cross-section down to 5 nm. Solid State Electron (2014), http://dx.doi.org/10.1016/j.sse.2014.04.007