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Electronic properties of polycrystalline ceramic cadmium sulphide
’
003X-I lOl/X5 $3 00 + 00 19X5 Pcrgamon Prc\\ Ltd
ELECTRONIC PROPERTIES OF POLYCRYSTALLINE CERAMIC CADMIUM SULPHIDE H. SAHA Department
of Physics,
University
of Kalyani,
Kalyani,
West Bengal, 741235, India
and S. DAS University
Service and Instrumentation
Centre, University 741235, India
of Kalyani,
Kalyani.
West Bengal,
(Receiued 4 Ju!v 1984: it1reuisedform 5 October 19X4) Abstract-An
attempt has been made to explain the current transport mechanism of ceramic cadmium sulphide layers using a semiconductor-grain boundary-semiconductor barrier model. It is shown that a sine-hyperbolic current-voltage relationship holds good for ceramic cadmium sulphide. Grain boundary parameters like potential barrier ($a) and average one-electron trapping state density (N,) in the grain boundary are determined experimentally for the first time for ceramic cadmium sulphide through the study of the current-voltage characteristics and zero-bias capacitances. The variation of +a and N, with temperature (28°C to -120°C) and bias voltage has also been investigated. It is concluded that the thermionic field emission components of current play a major role in the current transport characteristics of a ceramic cadmium sulphide layer
NOTATION
A AZ Cl c mg
c,
C mb C” d Em; F-m f G,,
4 N,(E) F:(
E,) 2
Q: 4
T
TE TFE
Planar area of the polycrystalline layer. Linear dimension of the cubic grain. Effective Richardson coefficient. Intergrain capacitance. Total equivalent capacitance of the polycrystalline layer. Individual grain boundary capacitance per unit area. Individual grain Schottky barrier capacitance. Overall capacitance of the total polycrystalline layer in presence of a Schottky barrier. Zero-bias high-frequency barrier capacitance per unit area. Thickness of the polycrystalline layer. Position of the Fermi level in the grain bulk. Position of the Fermi level within the grain boundary. Packing fraction of the grains. Zero-bias conductance of the polycrystalline layer. Current density. Boltzmann constant. Effective density of states in the conduction band. Donor concentration in the grain bulk. Square root of the number of grains on the top or bottom surface of the layer. Number of grains along the thickness of the
layer. EfTective density of trapping states of energy
E in the grain boundary region. Average value of NT( EF) at zero bias voltage. Electronic charge. Net charge density in the grain boundary region. Net charge density in the space charge region on both sides of the grain boundary. Applied bias voltage. Temperature in “K. Thermionic emission current. Thermionic field emission current through the space charge potential.
Thermionic field emission through the grain boundary scattering potential. Width of the grain boundary potential barrier. Exponential coefficient of temperature. Separation of the Fermi level below the conduction band. Band bending at the grain boundary interface. Zero-bias band bending at the grain boundary interface. Grain boundary potential barrier height. Exponential coefficient of doping concentration. Fitting factor. Resistivity.
1. INTRODUCI’ION
Polycrystalline semiconducting materials have gained importance for their use in many electronic devices like photocells and solar cells, varistors, thin-film diodes, transistors, etc. The electronic properties of polycrystalline semiconductors differ significantly from that of the single-crystal counterpart on account of the major role played by the grain boundaries. The atoms in the neighbourhood of the grain boundaries are disordered, giving rise to a large number of defects, and trapping states are created due to incomplete atomic bonding[l]. These trapping states are capable of trapping the free carriers causing a depletion layer and a potential barrier around the grain boundary region which in turn results in a non-ohmic behaviour of the I-V characteristics of a polycrystalline semiconductor. The well-known nonlinear current-voltage characteristics of high-quality ZnO varistors and ceramic semiconductors like BaTiO, can thus be extended to any polycrystalline semiconductor, the degree of nonlin1077
107x
earity being controlled by the grain boundary parameters like potential barrier, tapping state density, etc. Most of the theoretical and experimental work about the role of grain boundaries on the electronic properties have been limited to silicon[335] and germanium[6]. A number of investigations have also been reported for thin films of cadmium sulphide where the grain boundary potential barrier has been estimated through the study of the variation of conductivity and electron mobility with temperature[7-111. However, very little information about the grain boundary parameters of ceramic cadmium sulphide is available, although it has many applications in photoconductive and photovoltaic cells, piezoelecttic materials, varistors. etc. In this paper an attempt has been made to characterise the electronic properties of ceramic CdS layers by identifying the parameters associated with the grain boundaries. A simplified model of grain boundary geometry and the related capacitance is first proposed in Section 2. The necessary equations relating the different grain boundary parameters with the measurable quantities are identified in Section 3. In Section 4 the experimental arrangements are reported. In Section 5 the experimental observations and the resulting computations of the different grain boundary parameters are discussed and finally, in Section 6, the conclusions of this exercise are described. 2. GRAIN ROUNDARY
thickness of the polycrystalline one can write
layer
respectively.
A = u’N,+f, tl= uN,f.
(1)
where Ni is the number of grains on the top or bottom surface of the layer and Nh is the number of grains along the thickness of the layer, and f is the packing fraction of the grains. The grains are separated from each other by an intermediate grain boundary zone, having a capacitance of C, in between two grains, The total equivalent capacitance of the polycrystalline layer then becomes
c;,,,= $ c, \ Combining
(1) and (2). one gets
The individual grain boundary arca ( Cg) is therefore obtained
capacitance as
per unit
CAPACI’I’ANCE
The geometrical structure of the polycrystalline ceramic cadmium sulphide layer is shown in Fig. 1. For the sake of simplicity of polycrystalline film is assumed to be constituted of a large number of identical cubic grains, each of dimension o, connected in a series and parallel manner as shown in Fig. 1. If A and d are the planar area and the
It is interesting to note that it is C,,,& that is measured as the capacitance of the polycrystalline sample and the grain boundary capacitance per unit area can he obtained through the relationship of equation (4). When a Schottky barrier (SB) is formed on the polycrystalline sample by plating a suitable material
1079
Properties of polycrystalline ceramic cadmium sulphide on its top surface (say), a SB capacitance comes into play in addition to the grain boundary (GB) capacitance. If C, is the individual grain SB capacitance, the overall capacitance (C,,,,) of the total polycrystalline layers in presence of a Schottky barrier becomes
(5)
Usually, C, +Z Cp since the SB potential is much greater than the GB potential barrier. This leads to
cm, c, A
3.1 Current-voltnge churucteristics In general, the current through the grain boundary consists of the three components, namely thermionic emission (TE), thermionic field emission through the space charge potential (TFE) and thermionic field emission through the grain boundary scattering potential (TFES). Following Lu et al. it can be shown that the current density in a polycrystalline semiconductor can be expressed as [5]
a'/'
or in other words, assuming the packing fraction to be almost unity for the sake of simplicity, the SB grain capacitance per unit area is exactly equal to the measured overall Schottky barrier capacitance per unit area of the polycrystalline sample. 3.
grain boundary material, space charge potential barrier, and the crystalline bulk if the grain is not totally depleted.
GRAIN BOUNDARY
PARAMETERS
A generalised potential-energy diagram of an ntype poly-CdS grain in the ceramic sample is shown in Fig. 2, assuming a symmetrical Schottky barrier (SSB) model. A planar array of majority carriers trapped by the grain boundary trapping states leads to a positively charged depletion region (in case of an n-type semiconductor). E,,; and E,, refer to the positions of Fermi levels in the grain bulk and within the grain boundary respectively. Under thermal equilibrium, one obtains +eo = E,,; - E,, where +nO is the band bending at the grain boundary interface [14]. A rectangular potential barrier of height x and finite width 6 represents the grain boundary scattering effect between two space charge potential barriers [5]. The effects of image forces on this interfacial potential barrier are assumed to be negligible[l2]. It is further assumed that the applied voltage (V,) across the layer is dropped equally among all the grains (iv’,). Each grain voltage falls in series across the
Fig. 2. Potential-energy
diagram
(7) where A* is the effective Richardson constant, and VP is the voltage across each grain and [ is the Fermi level energy below the conduction band. Equation (7) has been derived using (a) Maxwell-Boltzmann statistics for the distribution of majority carriers in energy, (b) time-independent WKB approximation for calculating the transmission coefficient through the space charge and grain boundary potential barriers and (c) abrupt depletion approximation at the grain boundary space charge region. A semiquantitative relationship between the sum of the different current components and the space charge potential barrier B can be approximated as [5] [ TFE + TFES + TE] = exp ( - ~~‘“6~‘~) exp ( 3)
(8) where 721 and X>l,and x isinvoltsand 8 isin angstroms. Both n and X are the exponential coeflicients and are functions of temperature and doping concentration. Suitable values of n and h can be
of an n-type polycrystalline
CdS grain under thermal
equilibrium.
H. SAHA and S. DAS
10x0
chosen for fitting the theoretical computations with the experimental data[l3]. Combining (7) and (8). one gets a sine-hyperbolic current-voltage relationship as follows:
xexp(
45 -x ‘/Tsl/h) sinh ~2tN,kT’
(9)
where 6 is a fitting factor. E/V, gives the eflective number of grains between the resistor and contacts. The zero-bias conductance of the polycrystalline semiconductor is therefore obtained as G,, = lim (J/v,) I’-0
where hO is the potential barrier of the boundary space charge region at zero bias. Combination of (9) and (10) leads to
adjacent grains. However, very little information about Nr( E) is available for polycrystalline semiconductors like ceramic CdS. It would be therefore interesting to have an order of magnitude estimate of Nr( E) in ceramic CdS using the current-voltage deconvolution technique developed by Pike and Seager [14]. As the detailed structure of grain boundary regions and the distribution of the trapping state cncrgy densities are not known, a convenient approach will be to define a one-electron two-dimensional trap state density Nr( E) without bothering about its actual nature or distribution. From the conditions of charge neutrality at finite distance from the semiconductor-grain boundary interface, it follows that the net amount of positive charge (Q,,) in the space charge region on both sides of the grain boundary must be equal to the net negative charge ( Qgh ) trapped inside the grain boundary by its trapping states. Assuming an abrupt depletion approximation in the space charge region, it can be shown [15] that the thermally smeared trap state density vr( E,) about the Fermi level E, is given by
grain I’?
(11) For small bias voltage V, < 2 N,kT/q, one gets linear current voltage characteristics that are often borne out in experiments with polycrystalline samples. The slope of G,,/T on an Arrhenious plot is given bY
where +rr is the band bending at x = 0 corresponding to a bias voltage V, c is the dielectric constant of the semiconductor, and G’,~= @,,/aV. The zero bias value of Nr( E,:) is therefore given by
a( x’, w,A) d(l/kT)
(‘2) Equation (12) indicates that the slope of (C;,,/T) on an Arrhenious plot is not in general constant and does not yield the zero bias barrier height ($,so). In fact, it is less than G,~,, since both x and 6 are strongly increasing functions of temperature[5]. It is interesting to note that almost identical conclusions have been arrived at by Pike and Seager from an entirely different consideration[l4]. 3.2 Trapping stute densicv in the gruin
(14) where %,, = [ i?+,,,/JV], _i,. The zero bias space charge potential barrier can be obtained from the zero-bias high-frequency barrier capacitance per unit area from the following equation:
hounduq
region
The etl’ective density of the trapping states (N,(L)) in the grain boundary region is the most important parameter of a polycrystalline semiconductor that determines the height of the space charge potential barrier across the grain boundary by trapping the majority carriers from the crystalline bulk of the
N, being the effective density of states in the conduction band and N,, the donor concentration in the bulk grain. In order to determine N,( I:, ). it ix
Properties of polycrystalline ceramic cadmium sulphide
1081
ce11[7]. In fact, Fig. 4 clearly brings out an excellent fit of the experimentally observed data with the theoretically curve computed on the basis of eqn (11) using .$N, (= 325) as a fitting parameter and the experimentally measured values of G,, and ( +a0 +u) at 0°C. The validity of the generalised model used for the current transport in this analysis is thus confirmed. The zero-bias conductance G, is an important parameter that has been determined from the slope of the current-voltage characteristics around l!, = 0 at different temperatures. Figure 5 shows the .I = G,,I/,exp (16) Arrhenious plot of ln(G,/T) vs 1000/T which is exactly similar in nature to that reported by Seager for polysilicon samples[14]. The Arrhenious plot of from (15) and Knowledge of $aO as determined would be (15a), along with the experimentally observed J- V In( Go/T) with reciprocal of temperature linear but for the existence of the factor containing x characteristics, would lead to the determination of and S in eqn (10). The nonlinearity in Fig. 5 can be +a at different voltages from which qB and @‘aa can explained easily by noting that both x and 6 are be computed. strongly increasing functions of temperature. Thus, one can conclude that the TFES through the scatter4. EXPERIMENTAL ARRANGEMENTS ing potential barrier at the grain boundary cannot be The ceramic CdS layer was fabricated in the same ignored in comparison to the TE and TFE through manner reported earlier[16]. A CdS pellet of about the space charge layer of the grain boundary of 15 mm diameter and thickness 1.02 mm was pressed ceramic CdS. Furthermore, Fig. 6 showing the non(about 60 tons/cd) and then sintered at 800°C for linear variation of the logarithm of the bulk resistivabout 3 h in an inert atmosphere. The layers were cut ity (In p) with the reciprocal of temperature also into pieces and properly lapped and etched and then conforms with this picture. It is interesting to note annealed in hydrogen atmosphere at 400°C for 1 h. that this result is at variance with that reported for a Indium was vacuum coated on both faces and then thin film of CdS having a linear log p vs l/T charair annealed at 180°C for 45 min for ensuring good acteristics [14]. ohmic contents [17]. The I- V characteristics of the The zero-bias space charge potential barrier (+uO) CdS layer was then plotted by using an electronic across the grain boundary is the single most imI- V plotter fitted with an X-Y recorder and highly portant parameter controlling the electrical properstabilised low-voltage variable power supply. The ties of the polycrystalline semiconductors. The most temperature of the sample was varied from 0°C to direct method is to measure the zero-bias frequency - 120°C by putting the CdS sample in an evacuated capacitance of the samples at different temperatures sample holder placed inside a variable-temperature and then utilise (15) to compute the values of $a,,. It liquid nitrogen Ultra Cryostat. In order to determine should be noted that in using (15) care should be the doping density, an Au-CdS Schottky barrier is taken to estimate C, as discussed in Section 2. C,, is formed by evaporating thin layer of Au on to one obtained from the measured value of capacitance face of the sample while the other face is coated with C,_ through the use of (3) where the values of the indium for ohmic back contact. The capacisamples area, thickness, and average grain size are tance-voltage characteristics was determined by known. The typical values used in study are d = 0.7 using a high-precision L-C-R bridge for both mm, A = 0.38 cm’, and a = 1.5/u as obtained from Au-CdS-In and In-CdS-In samples at different the SEM studies [3]. The energy gap between the temperature. fermi level and the flat bottom of the conduction band can be easily computed provided the doping 5. DISCUSSIONS concentration Nd is known and not too large. The determination of Nd has been carried out by forming Figure 3 shows typical 1-V plots of the ceramic a Au-CdS Schottky barrier and measuring its l/C* CdS samples measured at the temperature range vs voltage characteristics. Nd has been found to be between 28°C and -120°C. The curves are almost 1.5 x 10lh cmm3, which agrees readily with the relinear upto about 500 mV, while they show considersults reported previously for identical ceramic CdS able nonlinearity in the range of a few volts. A much samples where it was estimated from the simultabetter insight of the nature of the relationship beof resistivity and mobility [16]. tween the current and voltage can be obtained by neous measurements Table 1 shows the computed values of GRO and G, plotting log J vs V of the ceramic CdS. This is shown for a typical ceramic CdS sample at different temperin Fig. 4 for 0°C. One notes that the current follows atures as estimated from the measured values of a sine-hyperbolic relationship with voltage as has zero-bias capacitances. One observes that the values been reported for the polycrystalline silicon solar
necessary to know $‘a. In principle, @‘a (= @+/al’) can be obtained from the capacitance dependence on bias voltage V. However, as pointed out in [15], the expression for the grain boundary capacitance is rather complicated and is difficult to determine experimentally as the real part of the barrier current increases with increasing bias. An alternative approach is therefore pursued here to determine the bias dependence of +a. For bias voltage 1/, GZ 2[N,kT/q eqn (11) yields
H. SAHA and S. DAS
1082
28oc
150
o”c -3ooc
I
-60oC
100
- 90°C
Q
-1207
E c .-
50
I
0
V in mV Fig. 3. Current-voltage
characteristics
5000
-
of the ceramic
CdS samples
---------Theoret
at different
temperatures.
icol Experimental
Temp. = O’C
curve curve
4000
1000
V Fig. 4. Experimental
I
4000
3000
2000
1000
I
and theoretical
5000
inmVU log J vs V characteristics
at 0°C of the ceramic
CdS layer.
Properties
of polycrystalline
ceramic
cadmium
sulphide
1083
-03 r,
3
5
6
7
1000/T Fig. 5. G,,/T
vs reciprocal
temperature
of +a0 for the ceramic Cd!3 are almost similar to those reported for thin film CdS [7]. A plot of $uO vs temperature is also indicated in Fig. 7. Since by definition @uO= E,,; - E,, [14], one can see that the variation of +a0 with temperature is largely accounted for by the variation of the bulk Fermi level EFo with temperature (see equation 15(a)) indicating that the gram boundary Fermi level
of ceramic
CdS layer.
E FR is not a strong function of temperature. This result is consistent with the variation of density of trapping states in the grain boundary with temperature as discussed below. Once +a0 is known, the variation of the space charge potential barrier +” at small applied bias voltage (VT 5 q[AJ,/2kT) can be estimated through the eqn (16). Figure 8 shows the variation of +R with
9oc
700
T
500
E
2 C .W
300
100 3
5
4
6
1000/TFig. 6. Variation
of bulk resistivity
with reciprocal
of temperature.
7
1084
H.
SAHAand S. DAS
Table 1. Computation of $I,~,,with temperature
Temp. (“Cl 0
30 ~ 60 - 90 120
Measured capacitance (PF)
Zero-bias capacitance C,, (P F/cm’ )
Zero-b& conductance CG) (mho/cm’ )
Zero-bias potential barrier
Q,,(,(volt\)
1500 950 500 310 280
1.24 1.18 0.62 0.385 0.348
0.030 0.022 0.014 0.010 0.007
0.155 0.140 0.121 0.106 0.0x9
Sample thickness (d) = 0.7 mm, area (A) = 0.3X cm?, average grain size u = I .5 p. and doping density Nd = 1.5 x 10lh cm ’
I-‘) with temperature as a parameter. It is interesting to note that the change in +” with the applied bias voltage is very small and gradual, much less than one would have expected had the applied bias been dropped across the space charge layer only. This implies that most of the applied voltage is dropped across the grain boundary region of width 6 and not across the adjacent space charge layer. It emphasises further the importance of the TFES component of current through the grain boundary scattering barrier in the case of ceramic cadmium sulphide. From Fig. 8, +‘a (= %$,/aV,) at any temperature and voltage can be computed. Once $& is known at zero bias voltages the average one-electron trap density N:( EF) can be estimated in a straightforward
manner through the use of (14). The NT ( E,; ) computed in this fashion for different temperature are shown in Fig. 9. The increase of NT( EF) with decreasing temperature is consistent with the fact that as the temperature is decreased, E,,, moves upwards towards the conduction band edge while E,, remains approximately invariant, thereby filling up a greater number of trapping states within the grain boundary region with the electrons from the bulk of the grain. In other words, as the temperature is decreased c#B”,,is reduced, leading to an increase in N,( EF). A further interesting behaviour of N,( EF) can be inferred by studying its dependence on the bias voltage. The results of such a computation at a
0'02 ! 3
4
5
6
7
1000/T Fig. 7. Variation of zero-bias grain boundaq space charge potential ture.
barrier
with reciprocal
of tempera
Properties
of polycrystalline
ceramic
cadmium
1085
sulphide
160 4 0°C * 1404 -30°C * -6O'C * -90°C
,
-12oOc
80 I 500
0
V, Fig. 8. Variation
of grain boundary
3
I
I 2500
I 2000
I 1500
I 1000
3000
in mA-
space charge potential
barrier
with applied bias voltage.
I
I
I
I
4
5
6
7
1000/T Fig.
9. Variation
of the zero-bias
trapping
density in the grain temperature.
boundary
(@)
with
reciprocal
of
H.
1086
andS.
DAS
600
LOO
200
0
SAHA
800
1000
Vin mV+ Fig. 10
Variation
of the trapping
density
in the gmin boundary
particular temperature (0°C) is shown in Fig. 10. The decrease of NT( E,) with increasing applied bias is consistent with the previous conclusion that most of the applied bias is dropped across the grain boundary region, thereby lowering effectively E,,, and N,( E, ) in turn. 6. CONCLUSION Important
information
about
the
grain
boundary
parameter of ceramic polycrystalline CdS has been obtained for the first time from the simple I- V and C- V measurements summarised as follows: (4 A ceramic CdS layer follows a sine-hyperbolic current-voltage relationship similarly to that followed by polycrystalline silicon. (b) TFE and TFES components of current play major roles in the overall current transport characteristics of the polycrystalline ceramic CdS. Cc) The average one-electron state density (N,( E, )) in the grain boundary region of ceramic CdS is about three orders of magnitude larger than that reported for polysilicon.
(d)
( ST ) v.ith applied hiah \.olt3gc
The nature of variation of zero-bias conductance, zero-bias potential barrier, and the zcrobias trapping state density in the grain boundary of ceramic CdS are almost similar to those reported for polycrystalline silicon.
‘l~,X,1*,,r,le~~rn2~,1rv~~The authors wsh to acknowledge Dr A. I_. Bhattacharya and Sri Narayan of the Department of l’hysich. University of Kalyani for their help in providing cxpcrimental facilities for measurcment~ at lov tempera-
tL,res.
REFERENCES
1. W. E. Taylor. x\;. H. Odell. and N. Y. Fan, r/r, $ /
Properties
of polycrystalline
10. P. Besomi and B. Wessels, J. Appl. Phvs. 51, 4305 (1980). 11. W. P. Bleha, W. H. Hartman, R. L. Jimenez, and R. N. Peacock, J. Vuc. Sci. Technol. 7, 135 (1970). 12. C.-Y. Lu and N. C.-C. Lu, Solid Srure Elecrronics 26, 549 (1983). 13. H. C. Card and E. H. Rhode&k. J. Phys. D. Appl. Phys. 4, 1589 (1971). 14. C. E. Pike and C. H. Seager, J. Appl. Phys. SO, 3414 (1979).
ceramic
cadmium
15. C. E. Pike,
sulphide C. H. Seager,
1087 and
Leamy
(eds.), Grain (1982). SO/U Cell. 4, 135
boundaries in Semiconductors, p. 85. Elsevier
16. K. Mukhopadhyay and H. Saha, (1981). 17. S. Banerjee and H. Saha, J. Phys. D, 16, 185 (1985). 18. N. C.-C. Lu, C.-Y. Lu, M.-K. Lee, and C. Chng, Proc. Internutionul Electron Devices Meeting. Dec. 1982. p. 781. 19. S. Banerjee and H. Saha, Ind. J. Pure Appl. Phys. 21, 205 (1985).
003X-I lOl/X5 $3 00 + 00 19X5 Pcrgamon Prc\\ Ltd
ELECTRONIC PROPERTIES OF POLYCRYSTALLINE CERAMIC CADMIUM SULPHIDE H. SAHA Department
of Physics,
University
of Kalyani,
Kalyani,
West Bengal, 741235, India
and S. DAS University
Service and Instrumentation
Centre, University 741235, India
of Kalyani,
Kalyani.
West Bengal,
(Receiued 4 Ju!v 1984: it1reuisedform 5 October 19X4) Abstract-An
attempt has been made to explain the current transport mechanism of ceramic cadmium sulphide layers using a semiconductor-grain boundary-semiconductor barrier model. It is shown that a sine-hyperbolic current-voltage relationship holds good for ceramic cadmium sulphide. Grain boundary parameters like potential barrier ($a) and average one-electron trapping state density (N,) in the grain boundary are determined experimentally for the first time for ceramic cadmium sulphide through the study of the current-voltage characteristics and zero-bias capacitances. The variation of +a and N, with temperature (28°C to -120°C) and bias voltage has also been investigated. It is concluded that the thermionic field emission components of current play a major role in the current transport characteristics of a ceramic cadmium sulphide layer
NOTATION
A AZ Cl c mg
c,
C mb C” d Em; F-m f G,,
4 N,(E) F:(
E,) 2
Q: 4
T
TE TFE
Planar area of the polycrystalline layer. Linear dimension of the cubic grain. Effective Richardson coefficient. Intergrain capacitance. Total equivalent capacitance of the polycrystalline layer. Individual grain boundary capacitance per unit area. Individual grain Schottky barrier capacitance. Overall capacitance of the total polycrystalline layer in presence of a Schottky barrier. Zero-bias high-frequency barrier capacitance per unit area. Thickness of the polycrystalline layer. Position of the Fermi level in the grain bulk. Position of the Fermi level within the grain boundary. Packing fraction of the grains. Zero-bias conductance of the polycrystalline layer. Current density. Boltzmann constant. Effective density of states in the conduction band. Donor concentration in the grain bulk. Square root of the number of grains on the top or bottom surface of the layer. Number of grains along the thickness of the
layer. EfTective density of trapping states of energy
E in the grain boundary region. Average value of NT( EF) at zero bias voltage. Electronic charge. Net charge density in the grain boundary region. Net charge density in the space charge region on both sides of the grain boundary. Applied bias voltage. Temperature in “K. Thermionic emission current. Thermionic field emission current through the space charge potential.
Thermionic field emission through the grain boundary scattering potential. Width of the grain boundary potential barrier. Exponential coefficient of temperature. Separation of the Fermi level below the conduction band. Band bending at the grain boundary interface. Zero-bias band bending at the grain boundary interface. Grain boundary potential barrier height. Exponential coefficient of doping concentration. Fitting factor. Resistivity.
1. INTRODUCI’ION
Polycrystalline semiconducting materials have gained importance for their use in many electronic devices like photocells and solar cells, varistors, thin-film diodes, transistors, etc. The electronic properties of polycrystalline semiconductors differ significantly from that of the single-crystal counterpart on account of the major role played by the grain boundaries. The atoms in the neighbourhood of the grain boundaries are disordered, giving rise to a large number of defects, and trapping states are created due to incomplete atomic bonding[l]. These trapping states are capable of trapping the free carriers causing a depletion layer and a potential barrier around the grain boundary region which in turn results in a non-ohmic behaviour of the I-V characteristics of a polycrystalline semiconductor. The well-known nonlinear current-voltage characteristics of high-quality ZnO varistors and ceramic semiconductors like BaTiO, can thus be extended to any polycrystalline semiconductor, the degree of nonlin1077
107x
earity being controlled by the grain boundary parameters like potential barrier, tapping state density, etc. Most of the theoretical and experimental work about the role of grain boundaries on the electronic properties have been limited to silicon[335] and germanium[6]. A number of investigations have also been reported for thin films of cadmium sulphide where the grain boundary potential barrier has been estimated through the study of the variation of conductivity and electron mobility with temperature[7-111. However, very little information about the grain boundary parameters of ceramic cadmium sulphide is available, although it has many applications in photoconductive and photovoltaic cells, piezoelecttic materials, varistors. etc. In this paper an attempt has been made to characterise the electronic properties of ceramic CdS layers by identifying the parameters associated with the grain boundaries. A simplified model of grain boundary geometry and the related capacitance is first proposed in Section 2. The necessary equations relating the different grain boundary parameters with the measurable quantities are identified in Section 3. In Section 4 the experimental arrangements are reported. In Section 5 the experimental observations and the resulting computations of the different grain boundary parameters are discussed and finally, in Section 6, the conclusions of this exercise are described. 2. GRAIN ROUNDARY
thickness of the polycrystalline one can write
layer
respectively.
A = u’N,+f, tl= uN,f.
(1)
where Ni is the number of grains on the top or bottom surface of the layer and Nh is the number of grains along the thickness of the layer, and f is the packing fraction of the grains. The grains are separated from each other by an intermediate grain boundary zone, having a capacitance of C, in between two grains, The total equivalent capacitance of the polycrystalline layer then becomes
c;,,,= $ c, \ Combining
(1) and (2). one gets
The individual grain boundary arca ( Cg) is therefore obtained
capacitance as
per unit
CAPACI’I’ANCE
The geometrical structure of the polycrystalline ceramic cadmium sulphide layer is shown in Fig. 1. For the sake of simplicity of polycrystalline film is assumed to be constituted of a large number of identical cubic grains, each of dimension o, connected in a series and parallel manner as shown in Fig. 1. If A and d are the planar area and the
It is interesting to note that it is C,,,& that is measured as the capacitance of the polycrystalline sample and the grain boundary capacitance per unit area can he obtained through the relationship of equation (4). When a Schottky barrier (SB) is formed on the polycrystalline sample by plating a suitable material
1079
Properties of polycrystalline ceramic cadmium sulphide on its top surface (say), a SB capacitance comes into play in addition to the grain boundary (GB) capacitance. If C, is the individual grain SB capacitance, the overall capacitance (C,,,,) of the total polycrystalline layers in presence of a Schottky barrier becomes
(5)
Usually, C, +Z Cp since the SB potential is much greater than the GB potential barrier. This leads to
cm, c, A
3.1 Current-voltnge churucteristics In general, the current through the grain boundary consists of the three components, namely thermionic emission (TE), thermionic field emission through the space charge potential (TFE) and thermionic field emission through the grain boundary scattering potential (TFES). Following Lu et al. it can be shown that the current density in a polycrystalline semiconductor can be expressed as [5]
a'/'
or in other words, assuming the packing fraction to be almost unity for the sake of simplicity, the SB grain capacitance per unit area is exactly equal to the measured overall Schottky barrier capacitance per unit area of the polycrystalline sample. 3.
grain boundary material, space charge potential barrier, and the crystalline bulk if the grain is not totally depleted.
GRAIN BOUNDARY
PARAMETERS
A generalised potential-energy diagram of an ntype poly-CdS grain in the ceramic sample is shown in Fig. 2, assuming a symmetrical Schottky barrier (SSB) model. A planar array of majority carriers trapped by the grain boundary trapping states leads to a positively charged depletion region (in case of an n-type semiconductor). E,,; and E,, refer to the positions of Fermi levels in the grain bulk and within the grain boundary respectively. Under thermal equilibrium, one obtains +eo = E,,; - E,, where +nO is the band bending at the grain boundary interface [14]. A rectangular potential barrier of height x and finite width 6 represents the grain boundary scattering effect between two space charge potential barriers [5]. The effects of image forces on this interfacial potential barrier are assumed to be negligible[l2]. It is further assumed that the applied voltage (V,) across the layer is dropped equally among all the grains (iv’,). Each grain voltage falls in series across the
Fig. 2. Potential-energy
diagram
(7) where A* is the effective Richardson constant, and VP is the voltage across each grain and [ is the Fermi level energy below the conduction band. Equation (7) has been derived using (a) Maxwell-Boltzmann statistics for the distribution of majority carriers in energy, (b) time-independent WKB approximation for calculating the transmission coefficient through the space charge and grain boundary potential barriers and (c) abrupt depletion approximation at the grain boundary space charge region. A semiquantitative relationship between the sum of the different current components and the space charge potential barrier B can be approximated as [5] [ TFE + TFES + TE] = exp ( - ~~‘“6~‘~) exp ( 3)
(8) where 721 and X>l,and x isinvoltsand 8 isin angstroms. Both n and X are the exponential coeflicients and are functions of temperature and doping concentration. Suitable values of n and h can be
of an n-type polycrystalline
CdS grain under thermal
equilibrium.
H. SAHA and S. DAS
10x0
chosen for fitting the theoretical computations with the experimental data[l3]. Combining (7) and (8). one gets a sine-hyperbolic current-voltage relationship as follows:
xexp(
45 -x ‘/Tsl/h) sinh ~2tN,kT’
(9)
where 6 is a fitting factor. E/V, gives the eflective number of grains between the resistor and contacts. The zero-bias conductance of the polycrystalline semiconductor is therefore obtained as G,, = lim (J/v,) I’-0
where hO is the potential barrier of the boundary space charge region at zero bias. Combination of (9) and (10) leads to
adjacent grains. However, very little information about Nr( E) is available for polycrystalline semiconductors like ceramic CdS. It would be therefore interesting to have an order of magnitude estimate of Nr( E) in ceramic CdS using the current-voltage deconvolution technique developed by Pike and Seager [14]. As the detailed structure of grain boundary regions and the distribution of the trapping state cncrgy densities are not known, a convenient approach will be to define a one-electron two-dimensional trap state density Nr( E) without bothering about its actual nature or distribution. From the conditions of charge neutrality at finite distance from the semiconductor-grain boundary interface, it follows that the net amount of positive charge (Q,,) in the space charge region on both sides of the grain boundary must be equal to the net negative charge ( Qgh ) trapped inside the grain boundary by its trapping states. Assuming an abrupt depletion approximation in the space charge region, it can be shown [15] that the thermally smeared trap state density vr( E,) about the Fermi level E, is given by
grain I’?
(11) For small bias voltage V, < 2 N,kT/q, one gets linear current voltage characteristics that are often borne out in experiments with polycrystalline samples. The slope of G,,/T on an Arrhenious plot is given bY
where +rr is the band bending at x = 0 corresponding to a bias voltage V, c is the dielectric constant of the semiconductor, and G’,~= @,,/aV. The zero bias value of Nr( E,:) is therefore given by
a( x’, w,A) d(l/kT)
(‘2) Equation (12) indicates that the slope of (C;,,/T) on an Arrhenious plot is not in general constant and does not yield the zero bias barrier height ($,so). In fact, it is less than G,~,, since both x and 6 are strongly increasing functions of temperature[5]. It is interesting to note that almost identical conclusions have been arrived at by Pike and Seager from an entirely different consideration[l4]. 3.2 Trapping stute densicv in the gruin
(14) where %,, = [ i?+,,,/JV], _i,. The zero bias space charge potential barrier can be obtained from the zero-bias high-frequency barrier capacitance per unit area from the following equation:
hounduq
region
The etl’ective density of the trapping states (N,(L)) in the grain boundary region is the most important parameter of a polycrystalline semiconductor that determines the height of the space charge potential barrier across the grain boundary by trapping the majority carriers from the crystalline bulk of the
N, being the effective density of states in the conduction band and N,, the donor concentration in the bulk grain. In order to determine N,( I:, ). it ix
Properties of polycrystalline ceramic cadmium sulphide
1081
ce11[7]. In fact, Fig. 4 clearly brings out an excellent fit of the experimentally observed data with the theoretically curve computed on the basis of eqn (11) using .$N, (= 325) as a fitting parameter and the experimentally measured values of G,, and ( +a0 +u) at 0°C. The validity of the generalised model used for the current transport in this analysis is thus confirmed. The zero-bias conductance G, is an important parameter that has been determined from the slope of the current-voltage characteristics around l!, = 0 at different temperatures. Figure 5 shows the .I = G,,I/,exp (16) Arrhenious plot of ln(G,/T) vs 1000/T which is exactly similar in nature to that reported by Seager for polysilicon samples[14]. The Arrhenious plot of from (15) and Knowledge of $aO as determined would be (15a), along with the experimentally observed J- V In( Go/T) with reciprocal of temperature linear but for the existence of the factor containing x characteristics, would lead to the determination of and S in eqn (10). The nonlinearity in Fig. 5 can be +a at different voltages from which qB and @‘aa can explained easily by noting that both x and 6 are be computed. strongly increasing functions of temperature. Thus, one can conclude that the TFES through the scatter4. EXPERIMENTAL ARRANGEMENTS ing potential barrier at the grain boundary cannot be The ceramic CdS layer was fabricated in the same ignored in comparison to the TE and TFE through manner reported earlier[16]. A CdS pellet of about the space charge layer of the grain boundary of 15 mm diameter and thickness 1.02 mm was pressed ceramic CdS. Furthermore, Fig. 6 showing the non(about 60 tons/cd) and then sintered at 800°C for linear variation of the logarithm of the bulk resistivabout 3 h in an inert atmosphere. The layers were cut ity (In p) with the reciprocal of temperature also into pieces and properly lapped and etched and then conforms with this picture. It is interesting to note annealed in hydrogen atmosphere at 400°C for 1 h. that this result is at variance with that reported for a Indium was vacuum coated on both faces and then thin film of CdS having a linear log p vs l/T charair annealed at 180°C for 45 min for ensuring good acteristics [14]. ohmic contents [17]. The I- V characteristics of the The zero-bias space charge potential barrier (+uO) CdS layer was then plotted by using an electronic across the grain boundary is the single most imI- V plotter fitted with an X-Y recorder and highly portant parameter controlling the electrical properstabilised low-voltage variable power supply. The ties of the polycrystalline semiconductors. The most temperature of the sample was varied from 0°C to direct method is to measure the zero-bias frequency - 120°C by putting the CdS sample in an evacuated capacitance of the samples at different temperatures sample holder placed inside a variable-temperature and then utilise (15) to compute the values of $a,,. It liquid nitrogen Ultra Cryostat. In order to determine should be noted that in using (15) care should be the doping density, an Au-CdS Schottky barrier is taken to estimate C, as discussed in Section 2. C,, is formed by evaporating thin layer of Au on to one obtained from the measured value of capacitance face of the sample while the other face is coated with C,_ through the use of (3) where the values of the indium for ohmic back contact. The capacisamples area, thickness, and average grain size are tance-voltage characteristics was determined by known. The typical values used in study are d = 0.7 using a high-precision L-C-R bridge for both mm, A = 0.38 cm’, and a = 1.5/u as obtained from Au-CdS-In and In-CdS-In samples at different the SEM studies [3]. The energy gap between the temperature. fermi level and the flat bottom of the conduction band can be easily computed provided the doping 5. DISCUSSIONS concentration Nd is known and not too large. The determination of Nd has been carried out by forming Figure 3 shows typical 1-V plots of the ceramic a Au-CdS Schottky barrier and measuring its l/C* CdS samples measured at the temperature range vs voltage characteristics. Nd has been found to be between 28°C and -120°C. The curves are almost 1.5 x 10lh cmm3, which agrees readily with the relinear upto about 500 mV, while they show considersults reported previously for identical ceramic CdS able nonlinearity in the range of a few volts. A much samples where it was estimated from the simultabetter insight of the nature of the relationship beof resistivity and mobility [16]. tween the current and voltage can be obtained by neous measurements Table 1 shows the computed values of GRO and G, plotting log J vs V of the ceramic CdS. This is shown for a typical ceramic CdS sample at different temperin Fig. 4 for 0°C. One notes that the current follows atures as estimated from the measured values of a sine-hyperbolic relationship with voltage as has zero-bias capacitances. One observes that the values been reported for the polycrystalline silicon solar
necessary to know $‘a. In principle, @‘a (= @+/al’) can be obtained from the capacitance dependence on bias voltage V. However, as pointed out in [15], the expression for the grain boundary capacitance is rather complicated and is difficult to determine experimentally as the real part of the barrier current increases with increasing bias. An alternative approach is therefore pursued here to determine the bias dependence of +a. For bias voltage 1/, GZ 2[N,kT/q eqn (11) yields
H. SAHA and S. DAS
1082
28oc
150
o”c -3ooc
I
-60oC
100
- 90°C
Q
-1207
E c .-
50
I
0
V in mV Fig. 3. Current-voltage
characteristics
5000
-
of the ceramic
CdS samples
---------Theoret
at different
temperatures.
icol Experimental
Temp. = O’C
curve curve
4000
1000
V Fig. 4. Experimental
I
4000
3000
2000
1000
I
and theoretical
5000
inmVU log J vs V characteristics
at 0°C of the ceramic
CdS layer.
Properties
of polycrystalline
ceramic
cadmium
sulphide
1083
-03 r,
3
5
6
7
1000/T Fig. 5. G,,/T
vs reciprocal
temperature
of +a0 for the ceramic Cd!3 are almost similar to those reported for thin film CdS [7]. A plot of $uO vs temperature is also indicated in Fig. 7. Since by definition @uO= E,,; - E,, [14], one can see that the variation of +a0 with temperature is largely accounted for by the variation of the bulk Fermi level EFo with temperature (see equation 15(a)) indicating that the gram boundary Fermi level
of ceramic
CdS layer.
E FR is not a strong function of temperature. This result is consistent with the variation of density of trapping states in the grain boundary with temperature as discussed below. Once +a0 is known, the variation of the space charge potential barrier +” at small applied bias voltage (VT 5 q[AJ,/2kT) can be estimated through the eqn (16). Figure 8 shows the variation of +R with
9oc
700
T
500
E
2 C .W
300
100 3
5
4
6
1000/TFig. 6. Variation
of bulk resistivity
with reciprocal
of temperature.
7
1084
H.
SAHAand S. DAS
Table 1. Computation of $I,~,,with temperature
Temp. (“Cl 0
30 ~ 60 - 90 120
Measured capacitance (PF)
Zero-bias capacitance C,, (P F/cm’ )
Zero-b& conductance CG) (mho/cm’ )
Zero-bias potential barrier
Q,,(,(volt\)
1500 950 500 310 280
1.24 1.18 0.62 0.385 0.348
0.030 0.022 0.014 0.010 0.007
0.155 0.140 0.121 0.106 0.0x9
Sample thickness (d) = 0.7 mm, area (A) = 0.3X cm?, average grain size u = I .5 p. and doping density Nd = 1.5 x 10lh cm ’
I-‘) with temperature as a parameter. It is interesting to note that the change in +” with the applied bias voltage is very small and gradual, much less than one would have expected had the applied bias been dropped across the space charge layer only. This implies that most of the applied voltage is dropped across the grain boundary region of width 6 and not across the adjacent space charge layer. It emphasises further the importance of the TFES component of current through the grain boundary scattering barrier in the case of ceramic cadmium sulphide. From Fig. 8, +‘a (= %$,/aV,) at any temperature and voltage can be computed. Once $& is known at zero bias voltages the average one-electron trap density N:( EF) can be estimated in a straightforward
manner through the use of (14). The NT ( E,; ) computed in this fashion for different temperature are shown in Fig. 9. The increase of NT( EF) with decreasing temperature is consistent with the fact that as the temperature is decreased, E,,, moves upwards towards the conduction band edge while E,, remains approximately invariant, thereby filling up a greater number of trapping states within the grain boundary region with the electrons from the bulk of the grain. In other words, as the temperature is decreased c#B”,,is reduced, leading to an increase in N,( EF). A further interesting behaviour of N,( EF) can be inferred by studying its dependence on the bias voltage. The results of such a computation at a
0'02 ! 3
4
5
6
7
1000/T Fig. 7. Variation of zero-bias grain boundaq space charge potential ture.
barrier
with reciprocal
of tempera
Properties
of polycrystalline
ceramic
cadmium
1085
sulphide
160 4 0°C * 1404 -30°C * -6O'C * -90°C
,
-12oOc
80 I 500
0
V, Fig. 8. Variation
of grain boundary
3
I
I 2500
I 2000
I 1500
I 1000
3000
in mA-
space charge potential
barrier
with applied bias voltage.
I
I
I
I
4
5
6
7
1000/T Fig.
9. Variation
of the zero-bias
trapping
density in the grain temperature.
boundary
(@)
with
reciprocal
of
H.
1086
andS.
DAS
600
LOO
200
0
SAHA
800
1000
Vin mV+ Fig. 10
Variation
of the trapping
density
in the gmin boundary
particular temperature (0°C) is shown in Fig. 10. The decrease of NT( E,) with increasing applied bias is consistent with the previous conclusion that most of the applied bias is dropped across the grain boundary region, thereby lowering effectively E,,, and N,( E, ) in turn. 6. CONCLUSION Important
information
about
the
grain
boundary
parameter of ceramic polycrystalline CdS has been obtained for the first time from the simple I- V and C- V measurements summarised as follows: (4 A ceramic CdS layer follows a sine-hyperbolic current-voltage relationship similarly to that followed by polycrystalline silicon. (b) TFE and TFES components of current play major roles in the overall current transport characteristics of the polycrystalline ceramic CdS. Cc) The average one-electron state density (N,( E, )) in the grain boundary region of ceramic CdS is about three orders of magnitude larger than that reported for polysilicon.
(d)
( ST ) v.ith applied hiah \.olt3gc
The nature of variation of zero-bias conductance, zero-bias potential barrier, and the zcrobias trapping state density in the grain boundary of ceramic CdS are almost similar to those reported for polycrystalline silicon.
‘l~,X,1*,,r,le~~rn2~,1rv~~The authors wsh to acknowledge Dr A. I_. Bhattacharya and Sri Narayan of the Department of l’hysich. University of Kalyani for their help in providing cxpcrimental facilities for measurcment~ at lov tempera-
tL,res.
REFERENCES
1. W. E. Taylor. x\;. H. Odell. and N. Y. Fan, r/r, $ /
Properties
of polycrystalline
10. P. Besomi and B. Wessels, J. Appl. Phvs. 51, 4305 (1980). 11. W. P. Bleha, W. H. Hartman, R. L. Jimenez, and R. N. Peacock, J. Vuc. Sci. Technol. 7, 135 (1970). 12. C.-Y. Lu and N. C.-C. Lu, Solid Srure Elecrronics 26, 549 (1983). 13. H. C. Card and E. H. Rhode&k. J. Phys. D. Appl. Phys. 4, 1589 (1971). 14. C. E. Pike and C. H. Seager, J. Appl. Phys. SO, 3414 (1979).
ceramic
cadmium
15. C. E. Pike,
sulphide C. H. Seager,
1087 and
Leamy
(eds.), Grain (1982). SO/U Cell. 4, 135
boundaries in Semiconductors, p. 85. Elsevier
16. K. Mukhopadhyay and H. Saha, (1981). 17. S. Banerjee and H. Saha, J. Phys. D, 16, 185 (1985). 18. N. C.-C. Lu, C.-Y. Lu, M.-K. Lee, and C. Chng, Proc. Internutionul Electron Devices Meeting. Dec. 1982. p. 781. 19. S. Banerjee and H. Saha, Ind. J. Pure Appl. Phys. 21, 205 (1985).