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Electronic properties of the interface between Si and sputter deposited indium-tin oxide
Materials Science and Engineering B 159–160 (2009) 314–317
Contents lists available at ScienceDirect
Materials Science and Engineering B journal homepage: www.elsevier.com/locate/mseb
Electronic properties of the interface between Si and sputter deposited indium-tin oxide E.V. Monakhov a,∗ , R. Balasundaraprabhu a , N. Muthukumarasamy b , B.G. Svensson a a b
Center for Material Science and Nanotechnology, University of Oslo, Saem Selands vei 24, 0316 Oslo, Norway Coimbatore Institute of Technology, Coimbatore, India
a r t i c l e
i n f o
Article history: Received 2 May 2008 Received in revised form 3 November 2008 Accepted 10 November 2008 Keywords: Indium-tin oxide Silicon Interface
a b s t r a c t We have investigated electronic properties of the interface between p-type Si and indium-tin oxide (ITO) films grown by magnetron sputtering. Current–voltage (I–V) and capacitance–voltage (C–V) measurements and deep level transient spectroscopy (DLTS) have been employed. The behaviour of the I–V and C–V characteristics for the ITO/p-Si junctions is correlated to the presence of interfacial states observed by DLTS. Thermal stability of the interfacial states is studied in the temperature range 100–400 ◦ C. For the structures deposited at room temperature, the I–V characteristics show a diode-like behaviour with rectification of about three orders of magnitude. However, the I–V curve cannot be described within the thermionic emission–diffusion approximation. C–V measurements reveal non-linearity in the 1/C2 dependence on V in the near-interface region, indicating the presence of carrier traps. Hole traps have been indeed observed by DLTS and exhibit an activation energy of 0.3 eV with a physical location near the p-Si/ITO interface. Heat treatments in the temperature range 100–400 ◦ C result in annealing of these hole traps and improvement of the I–V and C–V characteristics. The correlation between the electrical properties of the Si/ITO heterojunction and the presence of the electronic states is discussed. © 2008 Elsevier B.V. All rights reserved.
1. Introduction It has long been realized that indium-tin oxide (ITO) can form a rectifying electrical contact with Si resulting in a simple efficient solar cell (see, for instance, [1]). The short wavelength response is observed to be better in ITO/Si heterojunctions (ITO/p-Si or ITO/nSi) than that of a diffused n+ p junction since ITO is transparent to the photons of these short wavelengths and all the light falls directly on the junction where the carriers are generated [2]. Kobayashi et al. [3] have estimated that more than 20% energy conversion efficiency in the ITO/Si junctions can be achieved if the interface is of good quality without generation/recombination centers. However, until now a photoconversion efficiency of only slightly above 10% has been achieved in the junctions formed between ITO and silicon [4]. The interface quality at the ITO/Si junctions is largely influenced by the presence of a thin interfacial oxide layer [2]. Because of the non-stoichiometry of the oxide at or near the Si–SiO2 interface, fixed charges may exist and are expected to increase with the thickness of the interfacial oxide layer. If the interfacial oxide layer is too thick it may impede the tunneling of carriers caus-
∗ Corresponding author. Tel.: +47 22852836; fax: +47 22852836. E-mail address: [email protected] (E.V. Monakhov). 0921-5107/$ – see front matter © 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.mseb.2008.11.023
ing photocurrent suppression. In fact, the variations of the diode ideality are governed by the changes in the interfacial oxide layer thickness and corresponding changes in the interface state density [2]. Shewchun et al. [5] have reported that the interfacial layers can be complex mixtures such as Snx Siy O2 instead of simple SiO2 . Less is known about the electronic properties of the ITO/Si interface. Despite the abundance of data on current–voltage (I–V) and capacitance–voltage (C–V) studies of the ITO/Si heterostructures, the origin and the main properties of the interfacial states are largely unknown. It has been shown that a hole trap located at 0.20 eV above the valence band edge can be detected by deep level transient spectroscopy (DLTS) in p-type Si with the ITO layer deposited by magnetron sputtering [6]. It has also been shown that electron traps are present in sputter deposited ITO/n-Si junctions which are reported to be stable up to 180 ◦ C. To the best of our knowledge, there are no data on thermal stability of such electronic states as well as their correlation with electrical characteristics of ITO/Si junctions, such as I–V and C–V. In the present work, we have studied the ITO/p-Si heterostructures prepared using dc magnetron sputtering. Post-deposition heat treatment is performed in air at temperatures between 100 and 400◦ C and the effect on structural and electrical properties of the films and the electronic properties of the ITO/Si interface is investigated.
E.V. Monakhov et al. / Materials Science and Engineering B 159–160 (2009) 314–317
315
2. Experimental details ITO films were deposited using a dc magnetron sputtering system (CVC type AST-601 system) in a pure argon atmosphere using a 99.98% In2 O3 :SnO2 (90:10), 8 in. target. The system base pressure was 1 × 10−6 Torr. The sample holder is designed to support 4 in. silicon wafers and the rotation of the sample holder is maintained at 6 rpm for all depositions. Cleaned and HF etched Si wafers [(1 0 0), p-type, boron doped, 20 cm] have been used as substrates. Depositions were carried for about 10 min to deposit 300-nm thick ITO layers. An argon partial pressure of 2.5 mTorr and a power density of 2.5 W/cm2 were used during the depositions. The ITO films were then annealed at temperatures of 100–400 ◦ C for 30 min in air. The thickness of the ITO films was measured using a DEKTAK stylus profilometer. The structure of the ITO films was studied using X-ray diffractometer (Siemens D5000 fitted with a Göbel-mirror to obtain a parallel beam of Cu K␣ radiation). The carrier concentration and mobility of the films were measured at room temperature (RT) by Hall effect measurements with a field strength of 5 kG. The sheet resistance and resistivity were measured using a four-point probe setup. Current–voltage (I–V) measurements were performed for ITO/pSi heterostructures at RT using a Keithely 617 electrometer. Capacitance–voltage (C–V) studies were carried out at RT with a Boonton 7200 capacitance meter at a frequency of 1 MHz. DLTS studies were performed in the temperature range 77–300 K using a setup described in details elsewhere [7]. In short, the measured capacitance transients were averaged in intervals of 1 K. The DLTS signal was extracted by using a lock-in type weighting function, and different spectra were obtained corresponding to six rate windows ranging from (20 ms)−1 to (640 ms)−1 .
Fig. 1. X-ray diffractograms of the ITO film grown on p-Si(1 0 0) substrates and annealed at different temperatures in air.
Four-point probe measurements support the results of Hall effect studies. It has been observed that the resistivity decreases with increasing annealing temperature, and reaches a minimum at 300 ◦ C. The resistivity of 2.5 × 10−4 cm of the ITO film annealed at 300 ◦ C is comparable with the best values reported so far in some of the earlier works [11]. Annealing at 400 ◦ C, however, leads to an increase in the resistivity.
3. Results and discussion 3.1. Electrical and structural properties of the films The X-ray diffractograms of the ITO films deposited on Si(1 0 0) and annealed in air in the temperature range 100–400 ◦ C are shown in Fig. 1. The as-deposited films (not shown) and the ones annealed at 100 ◦ C are found to be amorphous in nature. It appears that regardless of the process conditions used, ITO films deposited by dc magnetron sputtering at RT show lack of crystallinity, and give an amorphous feature pattern (see [8] and references therein) with a broad peak between 30◦ and 35◦ of 2. The ITO films annealed in air at 200 ◦ C on Si(1 0 0) show polycrystalline nature revealing a cubic bixbyite structure. The ITO films annealed at 300 ◦ C show polycrystalline nature with well-defined sharp peaks along the crystalline directions (2 1 1), (2 2 2), (4 0 0), (4 4 0) and (6 2 2). From the diffractograms it is seen that the crystallinity improved with annealing temperature. The structure and orientation of the ITO films annealed at 400 ◦ C are almost identical to those annealed at 300 ◦ C exhibiting a dominant (2 2 2) peak orientation. Also, none of the spectra corresponding to higher annealing temperatures reveal any characteristic peaks of Sn, SnO, SnO2 , which indicates that the Sn atoms are probably incorporated substitutionally into the In2 O3 lattice [9,10]. Carrier concentration and mobility determined from Hall effect measurements are shown in Fig. 2 as a function of annealing temperature. Both carrier concentration and carrier mobility increase in the temperature range of room temperature to 300 ◦ C, which is correlated with the structural improvement detected by XRD (Fig. 1). After annealing at 400 ◦ C, however, carrier concentration and mobility decrease, though no change in the crystallinity is observed by XRD.
3.2. I–V measurements Fig. 3 shows the current–voltage characteristics of as-deposited ITO/p-Si junctions and those annealed at different temperatures in the range 100–400 ◦ C. The I–V characteristics show a diode-like behaviour with rectification of about three orders of magnitude. Within the thermionic emission–diffusion approximation, the cur-
Fig. 2. Carrier concentration and mobility of the ITO film versus annealing temperature.
316
E.V. Monakhov et al. / Materials Science and Engineering B 159–160 (2009) 314–317
Fig. 3. I–V characteristics of the ITO/p-Si junctions after the deposition and annealing at different temperatures in air.
rent as a function of applied voltage is expressed by
I = Is exp
qV nkT
−1 ,
(1)
where Is is the reverse saturation current and n is the diode ideality factor. It can be observed that I–V of the as-deposited sample cannot be described by this approximation, indicating poor quality of the ITO/Si interface. It is known for instance that sputter deposition of ITO on Si can create an intermixed damaged layer to a depth of 2–3 nm even at room temperature [12]. Thus, the I–V behaviour of the as-deposited structure can be attributed to the presence of such a damaged layer. Heat treatments at 100 and 200 ◦ C do not lead to considerable changes in the I–V curves. This is in contrast to the XRD data showing improvement of the crystallinity after 200 ◦ C annealing. After the heat treatment at 300 ◦ C, however, a considerable improvement in the diode performance can be seen in the I–V curves. The leakage current decreased significantly, particularly in the range −1 to 0 V. In forward bias, a clear exponential increase of the current can be seen in the voltage range 0–0.25 V. This increase can be described by Eq. (1) with an ideality factor of 1.4. It is interesting to note that the improvement in the I–V behaviour is correlated with a strong increase of the carrier concentration and mobility in Hall measurements (Fig. 2) as well as the crystal structure of the film (Fig. 1). Heat treatment at 400 ◦ C, however does not result in a further improvement of the I–V characteristics but rather a degradation. This degradation is attributed to the enhanced formation of an interfacial oxide layer between ITO and Si at higher temperature. It is interesting to note that the degradation of the interface correlates with degradation of the electrical properties of the film: resistivity, mobility and carrier concentration.
Fig. 4. C–V characteristics of the ITO/p-Si junctions after the deposition and annealing at different temperatures in air.
correlates with the I–V measurements where no improvement is observed after annealing at 100 ◦ C. After the heat treatment at 200 ◦ C, however, one can observe significant changes in the C–V behaviour of the ITO/Si diodes and the 1/C2 versus V dependence becomes linear in the full range of the measurement voltage. The slope of the dependence corresponds to a carrier concentration of 1.5 × 1015 cm−3 in Si. The built-in voltage of the diode is deduced to be 0.25 V. It is interesting to note that this improvement is in contrast to the poor I–V performance of the diode after 200 ◦ C. This can be attributed to different sensitivities of the C–V and I–V measurements to the presence of electrically active centers. Indeed, if the concentration of the centers is significantly lower than the doping, no considerable effect on the C–V characteristics will be observed. At the same time, the amount of the centers can be sufficient to cause significant generation–recombination current influencing the I–V characteristics. It can be concluded that heat treatment at 200 ◦ C results in annealing of a considerable fraction of the interface states, but some residual fraction still remains. Heat treatment at 300 ◦ C anneals apparently the residual interfacial states, which results in the improvement of the I–V characteristics, and 1/C2 demonstrates a good linear dependence on V. The built-in voltage for this diode structure is determined as 0.3 V. No significant change in the C–V behaviour is found after annealing
3.3. C–V measurements The deviation from a linearity in the plot of 1/C2 versus V (Fig. 4) for the as-deposited film indicates the presence of a considerable amount of electronic states. It can be seen that for high voltages, when the depletion region is extended to deeper regions in Si, the dependence of 1/C2 versus V becomes linear. This suggests that the electronic states are localized near the ITO/Si interface. The nonlinearity of the 1/C2 versus V curve correlates with the poor I–V characteristics of the as-deposited sample. Heat treatment at 100 ◦ C does not result in a considerable improvement of the C–V characteristics of the diode: the dependence of 1/C2 on V reveals a non-linear behaviour. This also
Fig. 5. DLTS spectra with a rate window of (640 ms)−1 for the ITO/p-Si junctions before and after annealing at 300 ◦ C.
E.V. Monakhov et al. / Materials Science and Engineering B 159–160 (2009) 314–317
at 400 ◦ C. Taking into account the degradation of the I–V behaviour it can be argued that the heat treatment at 400 ◦ C results in the formation of new interfacial states with a relatively low concentration that escape detection by the C–V measurements. The carrier concentration in Si deduced from the C–V curves is 1.1 × 1015 cm−3 for both 300 and 400 ◦ C annealings. We attribute the deviation in the deduced carrier concentrations in the 200, 300 and 400 ◦ C annealed samples to a deviation in the doping of the Si wafers that are taken from the same batch. 3.4. Electronic traps at the ITO/Si interface Fig. 5 shows DLTS spectra for the as-grown structures and after heat treatment at 300 ◦ C. By applying different bias and filling pulse voltages in different measurements one can change the probing depth region. Two different depth regions have been probed in the present measurements. Firstly, a bias voltage of −5 V with a filling pulse of 3 V (filling voltage −2 V) have been used to probe a depth region from ∼0.5 to ∼1.5 m in the Si sample, labeled as deeper region in Fig. 5. Secondly, in order to probe the interface region, a bias voltage of −2 V and a filling pulse of 4 V (filling voltage 2 V) have been chosen, which correspond to the probing depth region 0–0.5 m. It can be seen that no electron or hole traps are detected by DLTS in the deeper region. In contrast, a pronounced peak, corresponding to a hole trap, is observed in the spectrum for the interface region of the as-grown structure. Analysis of the different DLTS rate windows reveals that this trap has an energy position at 0.3 eV above the valence band edge. Heat treatment at 300 ◦ C results in annealing of the detected hole trap, and no electrically active states are detected in either the deeper region or the interface region. It should be noted that the annealing of the 0.3 eV interfacial state correlates with the improved I–V and C–V characteristics.
317
4. Conclusions We have investigated electronic properties of the ITO/p-Si interface for ITO grown by magnetron sputtering. I–V and C–V characteristics for structures deposited at room temperature show a diode-like behaviour with rectification of about three orders of magnitude. Heat treatment in the temperature range 100–300 ◦ C results in improvement of the I–V and C–V characteristics as well as of the crystal structure and conducting properties of the ITO films. DLTS measurements of the as-grown structure reveal the presence of a hole trap in the interface region with an energy level at 0.3 eV above the valence band edge. Annealing of this hole trap correlates with the improvement in the I–V and C–V characteristics. Acknowledgement This work is supported by Norwegian Research Council via the NANOMAT program. References [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
S. Ashok, S.J. Fonash, R. Singh, P. Wiley, IEEE Electron Device Lett. 2 (1981) 184. A. Subrahmanyam, N. Balasubramanian, Semicond. Sci. Technol. 7 (1992) 324. H. Kobayashi, T. Ishida, Y. Nakato, H. Tsubomura, J. Appl. Phys. 69 (1991) 1736. V. Vasu, A. Subrahmanyam, Appl. Phys. A 80 (2005) 823. J. Shewchun, J. Dubow, A. Myszkowski, R. Singh, J. Appl. Phys. 49 (1978) 855. K. Kuwano, S. Ashok, Appl. Surf. Sci. 629 (1997) 117–118. B.G. Svensson, K.-H. Rydén, B.M.S. Lewerentz, J. Appl. Phys. 66 (1989) 1699. F. Kurdesau, G. Khripunov, A.F. da Cunha, M. Kaelin, A.N Tiwari, J. Non-Cryst. Solids 352 (2006) 1466. H.R. Fallah, M. Ghasemi, A. Hassanzadeh, H. Steki, Mater. Res. Bull. 42 (2007) 487. J. George, C.S. Menon, Surf. Coat. Technol. 132 (2000) 45. J. Pla, M. Tamasi, R. Rizzoli, M. Losurdo, E. Centurioni, C. Summonte, F. Rubinelli, Thin Solid Films 425 (2003) 185. C.W. Ow-Yang, Y. Shigesato, D.C. Paine, J. Appl. Phys. 88 (2000) 3717.
Contents lists available at ScienceDirect
Materials Science and Engineering B journal homepage: www.elsevier.com/locate/mseb
Electronic properties of the interface between Si and sputter deposited indium-tin oxide E.V. Monakhov a,∗ , R. Balasundaraprabhu a , N. Muthukumarasamy b , B.G. Svensson a a b
Center for Material Science and Nanotechnology, University of Oslo, Saem Selands vei 24, 0316 Oslo, Norway Coimbatore Institute of Technology, Coimbatore, India
a r t i c l e
i n f o
Article history: Received 2 May 2008 Received in revised form 3 November 2008 Accepted 10 November 2008 Keywords: Indium-tin oxide Silicon Interface
a b s t r a c t We have investigated electronic properties of the interface between p-type Si and indium-tin oxide (ITO) films grown by magnetron sputtering. Current–voltage (I–V) and capacitance–voltage (C–V) measurements and deep level transient spectroscopy (DLTS) have been employed. The behaviour of the I–V and C–V characteristics for the ITO/p-Si junctions is correlated to the presence of interfacial states observed by DLTS. Thermal stability of the interfacial states is studied in the temperature range 100–400 ◦ C. For the structures deposited at room temperature, the I–V characteristics show a diode-like behaviour with rectification of about three orders of magnitude. However, the I–V curve cannot be described within the thermionic emission–diffusion approximation. C–V measurements reveal non-linearity in the 1/C2 dependence on V in the near-interface region, indicating the presence of carrier traps. Hole traps have been indeed observed by DLTS and exhibit an activation energy of 0.3 eV with a physical location near the p-Si/ITO interface. Heat treatments in the temperature range 100–400 ◦ C result in annealing of these hole traps and improvement of the I–V and C–V characteristics. The correlation between the electrical properties of the Si/ITO heterojunction and the presence of the electronic states is discussed. © 2008 Elsevier B.V. All rights reserved.
1. Introduction It has long been realized that indium-tin oxide (ITO) can form a rectifying electrical contact with Si resulting in a simple efficient solar cell (see, for instance, [1]). The short wavelength response is observed to be better in ITO/Si heterojunctions (ITO/p-Si or ITO/nSi) than that of a diffused n+ p junction since ITO is transparent to the photons of these short wavelengths and all the light falls directly on the junction where the carriers are generated [2]. Kobayashi et al. [3] have estimated that more than 20% energy conversion efficiency in the ITO/Si junctions can be achieved if the interface is of good quality without generation/recombination centers. However, until now a photoconversion efficiency of only slightly above 10% has been achieved in the junctions formed between ITO and silicon [4]. The interface quality at the ITO/Si junctions is largely influenced by the presence of a thin interfacial oxide layer [2]. Because of the non-stoichiometry of the oxide at or near the Si–SiO2 interface, fixed charges may exist and are expected to increase with the thickness of the interfacial oxide layer. If the interfacial oxide layer is too thick it may impede the tunneling of carriers caus-
∗ Corresponding author. Tel.: +47 22852836; fax: +47 22852836. E-mail address: [email protected] (E.V. Monakhov). 0921-5107/$ – see front matter © 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.mseb.2008.11.023
ing photocurrent suppression. In fact, the variations of the diode ideality are governed by the changes in the interfacial oxide layer thickness and corresponding changes in the interface state density [2]. Shewchun et al. [5] have reported that the interfacial layers can be complex mixtures such as Snx Siy O2 instead of simple SiO2 . Less is known about the electronic properties of the ITO/Si interface. Despite the abundance of data on current–voltage (I–V) and capacitance–voltage (C–V) studies of the ITO/Si heterostructures, the origin and the main properties of the interfacial states are largely unknown. It has been shown that a hole trap located at 0.20 eV above the valence band edge can be detected by deep level transient spectroscopy (DLTS) in p-type Si with the ITO layer deposited by magnetron sputtering [6]. It has also been shown that electron traps are present in sputter deposited ITO/n-Si junctions which are reported to be stable up to 180 ◦ C. To the best of our knowledge, there are no data on thermal stability of such electronic states as well as their correlation with electrical characteristics of ITO/Si junctions, such as I–V and C–V. In the present work, we have studied the ITO/p-Si heterostructures prepared using dc magnetron sputtering. Post-deposition heat treatment is performed in air at temperatures between 100 and 400◦ C and the effect on structural and electrical properties of the films and the electronic properties of the ITO/Si interface is investigated.
E.V. Monakhov et al. / Materials Science and Engineering B 159–160 (2009) 314–317
315
2. Experimental details ITO films were deposited using a dc magnetron sputtering system (CVC type AST-601 system) in a pure argon atmosphere using a 99.98% In2 O3 :SnO2 (90:10), 8 in. target. The system base pressure was 1 × 10−6 Torr. The sample holder is designed to support 4 in. silicon wafers and the rotation of the sample holder is maintained at 6 rpm for all depositions. Cleaned and HF etched Si wafers [(1 0 0), p-type, boron doped, 20 cm] have been used as substrates. Depositions were carried for about 10 min to deposit 300-nm thick ITO layers. An argon partial pressure of 2.5 mTorr and a power density of 2.5 W/cm2 were used during the depositions. The ITO films were then annealed at temperatures of 100–400 ◦ C for 30 min in air. The thickness of the ITO films was measured using a DEKTAK stylus profilometer. The structure of the ITO films was studied using X-ray diffractometer (Siemens D5000 fitted with a Göbel-mirror to obtain a parallel beam of Cu K␣ radiation). The carrier concentration and mobility of the films were measured at room temperature (RT) by Hall effect measurements with a field strength of 5 kG. The sheet resistance and resistivity were measured using a four-point probe setup. Current–voltage (I–V) measurements were performed for ITO/pSi heterostructures at RT using a Keithely 617 electrometer. Capacitance–voltage (C–V) studies were carried out at RT with a Boonton 7200 capacitance meter at a frequency of 1 MHz. DLTS studies were performed in the temperature range 77–300 K using a setup described in details elsewhere [7]. In short, the measured capacitance transients were averaged in intervals of 1 K. The DLTS signal was extracted by using a lock-in type weighting function, and different spectra were obtained corresponding to six rate windows ranging from (20 ms)−1 to (640 ms)−1 .
Fig. 1. X-ray diffractograms of the ITO film grown on p-Si(1 0 0) substrates and annealed at different temperatures in air.
Four-point probe measurements support the results of Hall effect studies. It has been observed that the resistivity decreases with increasing annealing temperature, and reaches a minimum at 300 ◦ C. The resistivity of 2.5 × 10−4 cm of the ITO film annealed at 300 ◦ C is comparable with the best values reported so far in some of the earlier works [11]. Annealing at 400 ◦ C, however, leads to an increase in the resistivity.
3. Results and discussion 3.1. Electrical and structural properties of the films The X-ray diffractograms of the ITO films deposited on Si(1 0 0) and annealed in air in the temperature range 100–400 ◦ C are shown in Fig. 1. The as-deposited films (not shown) and the ones annealed at 100 ◦ C are found to be amorphous in nature. It appears that regardless of the process conditions used, ITO films deposited by dc magnetron sputtering at RT show lack of crystallinity, and give an amorphous feature pattern (see [8] and references therein) with a broad peak between 30◦ and 35◦ of 2. The ITO films annealed in air at 200 ◦ C on Si(1 0 0) show polycrystalline nature revealing a cubic bixbyite structure. The ITO films annealed at 300 ◦ C show polycrystalline nature with well-defined sharp peaks along the crystalline directions (2 1 1), (2 2 2), (4 0 0), (4 4 0) and (6 2 2). From the diffractograms it is seen that the crystallinity improved with annealing temperature. The structure and orientation of the ITO films annealed at 400 ◦ C are almost identical to those annealed at 300 ◦ C exhibiting a dominant (2 2 2) peak orientation. Also, none of the spectra corresponding to higher annealing temperatures reveal any characteristic peaks of Sn, SnO, SnO2 , which indicates that the Sn atoms are probably incorporated substitutionally into the In2 O3 lattice [9,10]. Carrier concentration and mobility determined from Hall effect measurements are shown in Fig. 2 as a function of annealing temperature. Both carrier concentration and carrier mobility increase in the temperature range of room temperature to 300 ◦ C, which is correlated with the structural improvement detected by XRD (Fig. 1). After annealing at 400 ◦ C, however, carrier concentration and mobility decrease, though no change in the crystallinity is observed by XRD.
3.2. I–V measurements Fig. 3 shows the current–voltage characteristics of as-deposited ITO/p-Si junctions and those annealed at different temperatures in the range 100–400 ◦ C. The I–V characteristics show a diode-like behaviour with rectification of about three orders of magnitude. Within the thermionic emission–diffusion approximation, the cur-
Fig. 2. Carrier concentration and mobility of the ITO film versus annealing temperature.
316
E.V. Monakhov et al. / Materials Science and Engineering B 159–160 (2009) 314–317
Fig. 3. I–V characteristics of the ITO/p-Si junctions after the deposition and annealing at different temperatures in air.
rent as a function of applied voltage is expressed by
I = Is exp
qV nkT
−1 ,
(1)
where Is is the reverse saturation current and n is the diode ideality factor. It can be observed that I–V of the as-deposited sample cannot be described by this approximation, indicating poor quality of the ITO/Si interface. It is known for instance that sputter deposition of ITO on Si can create an intermixed damaged layer to a depth of 2–3 nm even at room temperature [12]. Thus, the I–V behaviour of the as-deposited structure can be attributed to the presence of such a damaged layer. Heat treatments at 100 and 200 ◦ C do not lead to considerable changes in the I–V curves. This is in contrast to the XRD data showing improvement of the crystallinity after 200 ◦ C annealing. After the heat treatment at 300 ◦ C, however, a considerable improvement in the diode performance can be seen in the I–V curves. The leakage current decreased significantly, particularly in the range −1 to 0 V. In forward bias, a clear exponential increase of the current can be seen in the voltage range 0–0.25 V. This increase can be described by Eq. (1) with an ideality factor of 1.4. It is interesting to note that the improvement in the I–V behaviour is correlated with a strong increase of the carrier concentration and mobility in Hall measurements (Fig. 2) as well as the crystal structure of the film (Fig. 1). Heat treatment at 400 ◦ C, however does not result in a further improvement of the I–V characteristics but rather a degradation. This degradation is attributed to the enhanced formation of an interfacial oxide layer between ITO and Si at higher temperature. It is interesting to note that the degradation of the interface correlates with degradation of the electrical properties of the film: resistivity, mobility and carrier concentration.
Fig. 4. C–V characteristics of the ITO/p-Si junctions after the deposition and annealing at different temperatures in air.
correlates with the I–V measurements where no improvement is observed after annealing at 100 ◦ C. After the heat treatment at 200 ◦ C, however, one can observe significant changes in the C–V behaviour of the ITO/Si diodes and the 1/C2 versus V dependence becomes linear in the full range of the measurement voltage. The slope of the dependence corresponds to a carrier concentration of 1.5 × 1015 cm−3 in Si. The built-in voltage of the diode is deduced to be 0.25 V. It is interesting to note that this improvement is in contrast to the poor I–V performance of the diode after 200 ◦ C. This can be attributed to different sensitivities of the C–V and I–V measurements to the presence of electrically active centers. Indeed, if the concentration of the centers is significantly lower than the doping, no considerable effect on the C–V characteristics will be observed. At the same time, the amount of the centers can be sufficient to cause significant generation–recombination current influencing the I–V characteristics. It can be concluded that heat treatment at 200 ◦ C results in annealing of a considerable fraction of the interface states, but some residual fraction still remains. Heat treatment at 300 ◦ C anneals apparently the residual interfacial states, which results in the improvement of the I–V characteristics, and 1/C2 demonstrates a good linear dependence on V. The built-in voltage for this diode structure is determined as 0.3 V. No significant change in the C–V behaviour is found after annealing
3.3. C–V measurements The deviation from a linearity in the plot of 1/C2 versus V (Fig. 4) for the as-deposited film indicates the presence of a considerable amount of electronic states. It can be seen that for high voltages, when the depletion region is extended to deeper regions in Si, the dependence of 1/C2 versus V becomes linear. This suggests that the electronic states are localized near the ITO/Si interface. The nonlinearity of the 1/C2 versus V curve correlates with the poor I–V characteristics of the as-deposited sample. Heat treatment at 100 ◦ C does not result in a considerable improvement of the C–V characteristics of the diode: the dependence of 1/C2 on V reveals a non-linear behaviour. This also
Fig. 5. DLTS spectra with a rate window of (640 ms)−1 for the ITO/p-Si junctions before and after annealing at 300 ◦ C.
E.V. Monakhov et al. / Materials Science and Engineering B 159–160 (2009) 314–317
at 400 ◦ C. Taking into account the degradation of the I–V behaviour it can be argued that the heat treatment at 400 ◦ C results in the formation of new interfacial states with a relatively low concentration that escape detection by the C–V measurements. The carrier concentration in Si deduced from the C–V curves is 1.1 × 1015 cm−3 for both 300 and 400 ◦ C annealings. We attribute the deviation in the deduced carrier concentrations in the 200, 300 and 400 ◦ C annealed samples to a deviation in the doping of the Si wafers that are taken from the same batch. 3.4. Electronic traps at the ITO/Si interface Fig. 5 shows DLTS spectra for the as-grown structures and after heat treatment at 300 ◦ C. By applying different bias and filling pulse voltages in different measurements one can change the probing depth region. Two different depth regions have been probed in the present measurements. Firstly, a bias voltage of −5 V with a filling pulse of 3 V (filling voltage −2 V) have been used to probe a depth region from ∼0.5 to ∼1.5 m in the Si sample, labeled as deeper region in Fig. 5. Secondly, in order to probe the interface region, a bias voltage of −2 V and a filling pulse of 4 V (filling voltage 2 V) have been chosen, which correspond to the probing depth region 0–0.5 m. It can be seen that no electron or hole traps are detected by DLTS in the deeper region. In contrast, a pronounced peak, corresponding to a hole trap, is observed in the spectrum for the interface region of the as-grown structure. Analysis of the different DLTS rate windows reveals that this trap has an energy position at 0.3 eV above the valence band edge. Heat treatment at 300 ◦ C results in annealing of the detected hole trap, and no electrically active states are detected in either the deeper region or the interface region. It should be noted that the annealing of the 0.3 eV interfacial state correlates with the improved I–V and C–V characteristics.
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4. Conclusions We have investigated electronic properties of the ITO/p-Si interface for ITO grown by magnetron sputtering. I–V and C–V characteristics for structures deposited at room temperature show a diode-like behaviour with rectification of about three orders of magnitude. Heat treatment in the temperature range 100–300 ◦ C results in improvement of the I–V and C–V characteristics as well as of the crystal structure and conducting properties of the ITO films. DLTS measurements of the as-grown structure reveal the presence of a hole trap in the interface region with an energy level at 0.3 eV above the valence band edge. Annealing of this hole trap correlates with the improvement in the I–V and C–V characteristics. Acknowledgement This work is supported by Norwegian Research Council via the NANOMAT program. References [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
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