Electronic Watches and Clocks

ADVANCES IN ELECTRONICS A N D ELECTRON PHYSICS, VOL. 51

Electronic Watches and Clocks A. P. GNADINGER Faselec Corporation Zurich, Swirzerland*

I. Introduction ............................................................

183

G . Future Trends . . . . . . . . . . . . ................................. V. Conclusion ........................................... References . . . .

255

......................... ......................... IV. The Electronic Watch ........ ............................ A. Time Base ..................................................... 11. Some History of Timekeeping 111. Electrical Clocks ............

184 186 186

I. INTRODUCTION Only little more than a decade has passed since the first commercial electronic watch appeared on the market (I). Those early models were manufactured in small quantities and were of no significance compared to the large numbers of mechanical watches then produced annually. Even in the early 1970s, electronic watches were merely considered a technical toy and not taken seriously by traditional watch makers. However, in the last few years, a stormy development in the field of electronic watches has taken place and at present (1979) a substantial fraction of the annual production of clocks and watches is electronic. The reasons for this unusual success of the electronic watch are basically threefold: (1) Using an electronic time base it is easy and therefore inexpensive to achieve accuracies in timekeeping that are far better than what can be realized with mechanical means. *

Present address:

INMOS Corporation, Colorado Springs, Colorado 80906. I83

Copyright 0 1980 by Academic R e r s . Inc All rights of reproduction in any form reserved ISBN 0-12-014651-7

184

A.

P. GNADINGER

(2) Electronic watches are inherently reliable. They have essentially no or very few moving parts that are subject to wear. The integrated circuit, the heart of an electronic watch, has also profited from the vast development effort in applications such as aerospace and computers where high reliability is essential. (3) Electronic watches are versatile. It is easy to include additional functions such as automatic calendar, alarm functions, and stop watch functions, which could only be realized with great difficulties in mechanical watches.

All these advantages are fully exploited in today’s electronic clocks and watches with ever-decreasing costs. Electronic watches follow essentially the trend of semiconductor components, which have always shown a strong decrease in manufacturing costs with maturing of manufacturing technology (2). The industrial realization, however, of electronic watches-particularly filly electronic digital watches-was only feasible with the advent of large-scale integration (LSI) in silicon integrated circuits. A watch circuit requires from several hundred to several thousand components. The restricted volume available in a watch case prohibits the use of discrete elements or small-scale integrated circuits. The impact of the electronic concept on the traditional watch industry that has developed the mechanical watch to perfection over a timespan that has to be measured in centuries was very profound. Even so, this revolution is far from being completed; watch and clock technology has matured substantially, so that this is an appropriate point in time to review the present status of the electronic watch and assess the trend for future developments. N o attempt is made to cover all aspects of electronic watches and clocks in a well-balanced manner. Emphasis is clearly put on the heart of every electronic watch-the integrated electronic circuit. 11. SOMEHISTORYOF TIMEKEEPING Clocks and watches have remained relatively unchanged for many centuries. They have seen, of course, gradual improvements both in style and size and in accuracy and reliability. Until the mid-1960s they were purely mechanical devices. The first mechanical clocks made their appearance in Europe during the eleventh century. They were tower and cathedral clocks of substantial size and weight. Their accuracy was quite poor and they had to be reset daily by sundial or other astronomical observation. The energy for driving these clocks was usually provided by the potential energy of falling

ELECTRONIC WATCHES AND CLOCKS

185

weights. This motion was transmitted to the indicator directly over a gear train. Since there was no means of accurately metering the descent of the falling weight, the indicated time fluctuated widely. A big step in the evolution of mechanical clocks was made with the application of the pendulum, combined with an escapement. This invention is usually credited to Christian Huygens of Holland (1658). Now the descent of the falling weight is used to keep the pendulum in motion, which in turn determines very accurately the motion of the gear train. In other words, the pendulum serves as a time base. The accuracy of such a mechanical clock is further improved by proper design and clever choice of materials to compensate for temperature variation and influence of humidity. The zenith of the development of the mechanical pendulum clock was probably reached in the early twentieth century. The observatory clock built around 1920 by Johann Meindl of Vienna is an outstanding example of the degree of perfection reached in mechanical pendulum clocks: this clock, now at the Antique and Modern Clock Co. of Los Angeles, California, still has an accuracy of one second per month! The evolution of the mechanical wristwatch started when Peter Henlein introduced his egg-shaped version in 151 1. Instead of gravitational energy of falling weights, a spring coil is now used to store potential energy and serves as an energy source to drive the watch. Again early wristwatches did not use a time base to meter the unwinding of the coil and their accuracy was, therefore, quite poor. As a parallel development to the pendulum as a time base for clocks, a torsion pendulum in the form of a balance wheel was introduced in wristwatches. The balance wheel is linked to an escapement that both meters the unwinding of the coil and provides impulses that drive the indicator over an appropriate gear train. Again, the introduction of the balance wheel as a time base proved to be a major improvement in the performance of the mechanical wristwatch. Since then, mechanical clocks and watches have undergone very little change. They have become smaller and more reliable. Their accuracy has improved steadily and manufacturing costs have decreased with the start of industrial production. A modern mechanical watch still consists of the same four basic parts as it did a few centuries ago, as shown in Fig. 1. These parts are an energy source, a time base, counters, and an indicator. The energy source is usually potential energy stored either in falling weights or in a helical coil spring. In later years the self-winding feature has been added to the coil spring. The motion of the bearers arm rewinds the coil continuously and keeps the watch running as long as it is not put to rest for more than approximately 48 hours. The time base is either a pendulum or a balance wheel combined with an escapement mechanism. The counter consists of

186

A. P. GNADINGER TIME EASE

’

COUNTER

(GEAR TRAIN)

’

INDICATOR

FACE AND HANDS

FIG. 1. Block diagram of a mechanical watch.

a mechanical gear train that divides the speed of rotation of the escapement wheel down to the appropriate speed to drive the indicator. The indicator-at last-is in most cases the familiar numbered face with moving hands.

111. ELECTRICAL CLOCKS Electrical clocks do not really satisfy the definition of a clock, since one vary essential component is missing-the time base. As a time base, the frequency of an AC power line is used. This frequency is usually controlled by the power-generating companies to such a degree that a clock deviates only within about + 2 sec from the exact time. Electric clocks consist of a synchronous electric motor, gear train, dial, and hands. The motor runs at a constant speed that is a function of the power line frequency, not its voltage. A second class of electrical clocks and watches uses an electrically driven spring balance movement as a time base. They satisfy the definition of a watch and can be represented by a block diagram similar to the one shown in Fig. 1. The power source is now an electrical battery or power supply. Power is transmitted to the spring balance movement serving as a time base via electric contacts operated by the balance wheel itself. These clocks are employed very often in automobiles. Although electrical clocks and watches are used widely and are still very popular today, they are not treated further here.

IV. THE ELECTRONIC WATCH The block diagram of an electronic watch or clock is given in Fig. 2. Every electronic watch possesses an energy source, a time base, a display and an electronic circuit that connects and controls these parts in a suitable manner.

187

ELECTRONIC WATCHES AND CLOCKS TIME BASE

>

ELECTRONIC CIRCUIT

>

DISPLAY

SOURCE (BATTERY)

FIG.2. Block diagram of an electronic watch or clock.

The different types of electronic clocks and watches, also termed gen-

erations, distinguish themselves through the type of time base used, the

different types of displays, and the complexity of the electronic circuit. So far, four generations of electronic watches have been defined; their main characteristics are summarized in Fig. 3. The first watch generation-introduced in approximately 1964 (/)-uses a conventional mechanical display, that is, hands for hours, minutes, and seconds driven in conventional manner by a gear train. The time base is a synchronized balance wheel. Power is transmitted to the balance wheel electromagnetically. The difference between an electronic watch and electrical watches described in Section I11 can be made clear at this point. In both cases power is transmitted to the balance wheel electromagnetically. However, in an electrical watch the coil is switched via electric contacts operated by the balance wheel itself, whereas in the electronic version these switches are replaced by an electronic switch, usually a transistor. The energy is provided by an electrical battery. The fre-

Time Base

Tuning fork

Ouarlz Resonator

Complexity of the circuit

l-IOTrans1slors

Typical frequency f

300Hz

up lo aboul 500 Transistors

32kHz

2000 - 4000

4MHz

Transtslors

Af I f

lhcorelicai inaccuracy

Watch generation

10 mlnlyear

2

30-90scrlycar

3

01 Ihe walch

1

>.lo5

-6

1-3.10

I0

FIG.3. The four generations of electronic watches and clocks.

188

A. P. GNADINCER

quency of the balance wheel is usually 4 cycles per second with an accuracy Af/f = This frequency variation corresponds to a theoretical accuracy of the watch of 50 min/year. The electronic circuit needed is quite simple, very often only one discrete transistor. For the second watch generation the balance wheel is replaced by a tuning fork as time base (4). The tuning fork oscillates at a frequency of approximately 300 Hz, which is much higher than the balance wheel frequency. The oscillation is transmitted mechanically by means of pawls. Again the energy is provided by a battery and switched with a simple electronic circuit. The stability of the tuning fork movement is better, typically 4 f / f = 2 x lov5,which corresponds to a theoretical accuracy of the watch of 10 min/year. Before the advent of the quartz-crystal-controlled movements this watch generation was quite a success. Now it is largely replaced by watches of the third and fourth generation, mainly because the mechanical coupling of oscillator and divider gear train is quite expensive. The third watch generation still employs an analog display -a face and moving hands-but the rest is electronic. The time base is now a quartz-controlled oscillator with a frequency in the kilohertz to megahertz range. The electronic circuit is much more complex-it contains several hundred components -since the oscillations have to be divided electronically. The second (or minute) hand is driven by a vibrating or stepping motor, which interfaces directly with the electronic circuit. The stability of a quartz-controlled oscillator is much better than that of the time base which correof the two previous generations, typically Af/f = 1 x sponds to a theoretical accuracy of the watch of 30-90 sec/year. With the fourth generation, the last mechanical part-the display -is now replaced by electronic solid-state display. The degree of complexity of the electronic circuit is again considerably higher; it contains about 3000-4000 active components. The typical frequency and the accuracy of a digital watch are identical to those of analog watches of the third generation. The main advantages of electronic over mechanical watches as already mentioned in the introduction become again evident from the representation in Fig. 3: (1) The excellent stability of a quartz-controlled oscillator is the reason for the inherently high accuracy of an electronic watch. (2) The integrated circuit follows the laws of batch processing, as will be explained in Section IV,C, and is therefore inexpensive to produce. (3) Electronic watches are very versatile, since it is not difficult to add some one hundred devices more to a circuit already containing several thousand components and implement in such a way additional functions

ELECTRONIC WATCHES AND CLOCKS

that could only be realized-if ical means.

at all-with

I89

great difficulty with mechan-

The main functional blocks of electronic watches and clocks are covered in detail in the following sections. Emphasis is placed on watches and clocks of the third generation-analog watches-and of the fourth generation-digital watches. A . Time Base The most commonly used timing element in electronic watches and clocks is the quartz crystal. As mentioned in the previous section, time bases employing tuning forks and electronically driven spring balance movements were used in the past for electronic watches of the first and second generation, but are of little importance today. They are not treated any further. As already indicated in Fig. 3, the commonly employed frequencies for a quartz-crystal-controlled oscillator for analog and digital watches of the third and fourth generation are in the range from 32 kHz to 4 MHz. In fact, the frequency of 32 kHz is now generally accepted as a standard, at least for wristwatches. 32 kHz seems to be a good compromise between power consumption, stability of the oscillator, and cost and size of the quartz crystal. The current consumption of an integrated circuit including the quartz oscillator circuit and the subsequent divider chain increases with oscillation frequency, at Ieast for the now commonly employed complementary integrated technologies such as CMOS, as is shown in more detail in Section IV,C. It is therefore desirable to use a rather low frequency in order to minimize power consumption and maximize the battery life. On the other hand, the quartz crystal size and also the manufacturing and packaging costs of the quartz crystals fall and crystal performance increases as frequency increases. it is also more and more difficult to achieve adequate stability of the oscillator and utilize fully the inherent stability of the quartz crystal resonator, if the frequency is decreased. 32 kHz seems now to be a good compromise between these conflicting requirements, at least for wristwatches. For clocks, on the other hand, a frequency of 4 MHz is almost universally accepted as standard. Power consumption requirements of clock circuits are not as stringent as those of wristwatch circuits. Clocks can be driven by much larger batteries so that the lower cost and the lower temperature sensitivity of a 4 MHz quartz is more important than minimum power consumption. There is, however, a tendency to also lower the frequency of clock oscillators to 32 kHz. The costs of 32 kHz quartz crystals have decreased and the technical performance has increased dramatically

I90

A.

P. GNADINGER

during the last few years, because of large volume production of these crystals for wristwatch applications. With only a marginal prize and performance difference between 4 MHz and 32 kHz crystals the lower current consumption of the 32 kHz circuits would therefore also be favorable for clock circuits. The early electronic wristwatches utilizing a quartz-crystal-controlled oscillator were using 8192 Hz as oscillating frequency (56). At that time it was difficult to handle higher frequencies because the current consumption would have been too high since the circuits were realized in a noncomplementary standard bipolar technology and the oscillator designs were not well suited for higher frequencies (3). Although 32 kHz is now generally accepted as a standard for wristwatches, in special cases higher frequencies such as 524 kHz (7), 786 kHz (8),2.4 MHz (9), and even 4.2 MHz (10) are employed. For watches where the main emphasis is placed on accuracy of timekeeping, frequencies higher than 32 kHz are desirable because the better performance of the high frequency quartzes can then be utilized. All these designs have to use much more elaborate circuit techniques in order to keep the current consumption within reasonable bounds. The upper frequency limit is obviously given by the circuit. An overall current drain of 10 pA at 1.4 V and 4.2 MHz has been obtained with a commercially available SOS circuit (10). Similar results were obtained in production with bulk silicon-gate technology, but much more complicated circuit techniques were necessary [6 p A at 1.4 V and 2.4 MHz ( I ] ) ] . A wristwatch introduced on the market in 1974 uses a very stable AT quartz resonator at 2.4 MHz with a guaranteed accuracy of the watch of 1 sec per month (9). This very high timekeeping accuracy, however, can only be achieved at fairly high costs and rather high current consumption. With a quartz crystal as timing element almost any type of oscillator circuit could in principle be used. However, as mentioned before, there are some important restrictions. The current consumption should be as low as possible. Second, the circuit has to be capable of integration. Therefore, circuits using inductances are not suited. Also, due to the volume restrictions in a wristwatch the oscillator should require as few external components as possible. In addition to the quartz crystal, at least one more external component, a trimmer capacitor for the frequency adjustment, is, however, almost always needed. 1. Oscillator Circuits

The most popular quartz oscillator circuit used in electronic wristwatches today is the Pierce oscillator shown in Fig. 4 (3). Figure 4a

ELECTRONIC WATCHES AND CLOCKS

191

p or n c,hannel transistors

+V

Yl1

FIG. 4. (a) Three-point oscillator circuit. (b) Current source implementations. (c) Pierce oscillator circuit.

presents the basic three-point equivalent circuit. The current source can be implemented in several different ways. The choice depends mainly on the technology used to implement the main electronic circuit since it is desirable to integrate the current source together with the oscillator circuit on the same chip. Some possibilities are indicated in Fig. 4b. The most common is the CMOS inverter, which offers a transconductance g, equal to the sum of the transconductances of both transistors. The feedback admittance Y2is basically given by the quartz crystal. As mentioned before, it is undesirable to use inductances in an electronic watch circuit. Therefore, the admittances Yland Y, are best realized by capacitances. For os-

192

A. P. GNADINGER

cillations to take place, Y2 must then be inductive. The equivalent circuit of a quartz crystal can best be represented as shown in Fig. 5a. The reactance X 2of this circuit as a function of frequency is shown in Fig. 5b. The intersection of this curve with the abscissa, where X , ( w ) = 0, are the series and parallel resonant radian frequencies w, and up,respectively. us and wp are given by (12) w, = I/(LC)1’2

w, = w,(l

+ C/C3)1’2

(1)

w,(l

+ C/2C3)

(2)

where L is the inductance of the quartz crystal, C the dynamic, and C 3the shunt capacitance, respectively. If now Yl and Y, in Fig. 4a are susceptances of equal sign (capacitances), Y, (w) must be of opposite sign for oscillations to take place and the oscillation frequency wo has to lie between ws and w,, as indicated in Fig. 5b. In Fig. 4c a practical realization of the Pierce oscillator circuit is represented. The current source is made up of an inverter in CMOS technology. A feedback resistor R, is needed in order to bias the inverter into the linear mode of the transition characteristics so that it can act as a current source. This is shown also in Fig. 6, where the transfer characteristic of a

a)

FIG. 5. (a) Equivalent circuit of a quartz crystal. (b) Reactance of the quartz equivalent circuit as function of frequency.

ELECTRONIC WATCHES AND CLOCKS

193

Vout

'VOO

I

'+l

k I I

i

I

I

I I

I /

1

voo

-Vin

I I

FIG.6. Transfer characteristic and drain current of a CMOS inverter.

CMOS inverter is plotted. At the biasing point Q the current I, in the lower half of the drawing reaches a maximum. This peak current I, is essentially the quiescent current flowing if the quartz crystal is removed and the oscillator is not oscillating. It is to first order linearly dependent on the current consumption of the oscillator in operation as illustrated in Fig. 7, where some experimental data (13)of oscillator current I vs. quiescent inverter current I, are plotted. The slope of this curve depends in a rather complicated way on threshold voltages and gain factors of the oscillator circuit as well as the electrical parameters of the quartz. Quite often-to simplify testing-watch oscillator circuits are tested without quartz resonator and a correlation such as the one shown in Fig. 7 is used to extrapolate to the actual current consumption of the circuit. The biasing resistor R , in Fig. 4c does not influence the current consumption of the circuit as long as its value exceeds a few hundred kiloohms. Its effect on the frequency of the oscillator is also quite small. This resistor is conveniently integrated into the monolithic chip. Because of the high resistance value required, a standard diffused resistor would use up too much silicon area. In nearly all cases it is therefore realized by an active component, preferably a transmission gate as shown in Fig. 8. This complementary pair of transistors is connected in parallel and acts as a

194

A. P. GNADINGER

3

0

I

I

I

I

I

I

1

2

3

4

5

6

-

IQ IPAl

FIG.7. Quiescent current la and corresponding oscillator current I for Pierce oscillator.

high ohmic resistor. The nonlinear characteristic of this element does not pose a disadvantage in this application. Of course, the biasing resistor R , can also be a discrete component bonded externally to the chip. Provision must be made to adjust the oscillator frequency in order to compensate for quartz manufacturing tolerance and aging effects. In the Pierce oscillator configuration of Fig. 4c, the capacitances C , and C, can be combined with C,of the quartz equivalent circuit (Fig. Sa) as a capacitance of value C, in parallel with the quartz. The oscillation radian frequency wo is then given by wo =

w,(l

+ C/2CP)

(3)

where C, is the equivalent value of C1, C,, and C , combined as a capacitance in parallel with the crystal: 9

T9 P FIG.8. Transmission gate.

ELECTRONIC WATCHES AND CLOCKS

c, =

c 3

I95

+ C , C , / ( C , + C2)

(4)

and Eq. (3) reads (wo -

4 / w s

=

c/2cp= c/r2c3 + 2C,C2/(C, + C2)I

(5)

The oscillator frequency can be adjusted by either making the input or output capacitance C , or C2 variable as evident from Eq. ( 5 ) . However, the output capacitance C2 determines the power dissipation and is best integrated into the chip to ensure that it remains at a constant low value. Therefore, the input capacitance C,is usually made variable. The change in oo,Amo, with a variation of C1for maximum and minimum values of C, , C, and Cp is given by

AOO = 0

C 6 7

(l/Cpmin - l/Cpmax)

(6)

This trimming range doo must be wide enough to encompass drifts and manufacturing tolerances but not so wide that the crystal is made to operate outside its stable range. A trimming range of about 70 ppm is easily obtained with a standard 32 kHz quartz with a load capacitance variation of about 6- 14 pF. An actual curve of frequency vs. load capacitance Cpis shown in Fig. 9 (12). Equation ( 5 ) also shows that the frequency of the Pierce circuit is dependent not only on the quartz and its mechanical stability but also on the stability of the relative circuit components C , and C2. Assuming for simplicity that C, = C2,from Eq. ( 5 ) it follows that the expected frequency variation due to circuit capacitance changes is Ao/w

2:

-(C/Ci)(ACi/Ci)

(7)

300

E, n

200

3 . 3 I

a 100

1 I

15 l o a d Capacitance. Cp ( p F ) FIG.

20

9. The frequency variation vs. load capacitance for the type MTQ21 crystal.

I96

A. P. GNADINGER

C may be of the order of 0.003 pF and Cz= 5-40 pF. A frequency stabil-

ity of the order of therefore calls for a capacitor stability of the order of 1%, which can be realized without difficulties in today’s technology. As mentioned in Section IV, the aim should be to design an oscillator with minimum supply current to reach a maximum battery life. The supply current of a standard Pierce oscillator (Fig. 4c), however, is a rather strong function of the supply voltage. Figure 10 shows the typically observed variation of current drain I and output voltage V , of Fig. 4c with supply voltage V ( 1 4 ) .If V is increased, the current I is small and no oscillations take place until a critical value V , is reached. After passing V , the current Z increases sharply and oscillations start with a peak to peak amplitude V , . There is a small built-in hysteresis to the I-V characteristics. By reducing the supply voltage V oscillations can be maintained down to a voltage that is lower than V,, which is mainly determined by the technology used to implement the current source. For a CMOS inverter V , is essentially given by the sum of Lile p and n threshold voltages. V, must be kept below the minimum supply voltage. To allow for manufacturing tolerances a margin of a few tenths of a volt must be provided to ensure the building up of oscillations under worst-case conditions. As evident from Fig. 10 this implies an appreciable increase of nominal current due to the steepness of the I - V characteristics. This rather strong sensitivity of current drain on supply voltage variations is one of the disadvantages of the simple Pierce oscillator.

“2

FIG.10. Typical variations of current drain [and output amplitude V s with supply voltwith permission. age V, observed with a standard oscillator of Fig. 4c. After Vittoz (M),

ELECTRONIC WATCHES AND CLOCKS

I97

A second condition has to be satisfied in order to start and sustain oscillations: The transconductance g, of the current source in Fig. 4a must exceed a certain critical value g,, , which is given by (14)

where Q is the quality factor of the quartz crystal, given by

(9) Inserting Eq. (9) into (8), the critical transconductance can be expressed as a function of the relative frequency pulling range Aw/o:

Q

= I/(osRC)

g m c = 0 s C/QCAW/WO)~

(10)

Equation ( 10) shows that the critical transconductance g,, increases with increasing frequency and decreasing quality factor Q . The relative frequency pulling range A o / o o cannot be changed at will. It is usually limited to 100-200 ppm in order to avoid frequency instabilities due to the variations of capacitances C1, C 2 , and Ct. The drain current necessary to achieve the critical transconductance g,, can be decreased by increasing the amplification factor of the transistors. In CMOS technology this is accomplished by increasing the channel width. There is, however, a minimum value of g, reached if the transistor operates in weak inversion (15). This minimum critical value of g, can be considered as a measure for the minimum current necessary to sustain oscillations. For 32 kHz this minimum current is of the order of 20 nA for standard frequency-pulling ranges. For g , > g,, the osciilations grow up until they are limited by the nonlinearities in the circuit. The main nonlinearity is the sharp increase in the output conductance of the inverter transistors in the peaks of the oscillations if the peak voltage is close to the supply voltage. This variation of the output conductance cannot be well controlled. Therefore, the frequency of the oscillation of the simple Piece oscillator is a rather sensitive function of supply voltage, which is an undesirable feature of a quartzcontrolled oscillator that should be capable of using the high inherent accuracy of the quartz crystal as a timing element. Various additions to the simple Pierce oscillator circuit are possible in order to improve the frequency sensitivity. The simplest solution is adding a series resistor R2 (100-300 kfi) to the output of the inverter (Fig. 4c). A better solution is the addition of two series transistors that are always conducting and operating in the linear mode to the inverter as shown in Fig. 11. This solution is also better suited for integration in actual circuit technologies such as CMOS. The series transistors add a resistance to the inverter circuit that is only weakly dependent on supply voltage and therefore decreases the overall sensitivity of the frequency on the supply voltage.

I98

A. P. GNADINGER

{ P

&P :;

*Out

T"

FIG.11. Inverter oscillator for 32 kHz.

Other improvements of the circuit of Fig. 4c have been proposed (16, 17) with the goal of decreasing the nominal value of the current I and decreasing the sensitivity of this current on supply voltage variations. An alternative realization of the Pierce oscillator of Fig. 4a consists of using a single active transistor driven by a constant-current source as shown in Fig. 12. The current I can be chosen such that the amplitude V , is sufficient to drive the next stage-an inverter, for example. The advantage of this circuit is that the current Z is not influenced by the nonlinearities of the oscillator circuit but is essentially determined by the constant current source. The best results for minimum current consumption of an oscillator cir-

FIG.12. Simple constant-current oscillator circuit.

ELECTRONIC WATCHES AND CLOCKS

I99

cuit are obtained by means of an amplitude feedback scheme that automatically adjusts the current I to the designed value (18).These oscillators are much more complex than the Pierce oscillator. Quite often they consist of up to 40 active elements. A further disadvantage is the fact that the start up of the oscillator is quite slow. It may take up to several seconds-depending on temperature and power supply voltage-to build up the oscillations with the correct amplitude. In large-scale manufacture this may be a prohibitively long time in testing the circuit and may add considerably to the cost of the circuit. Nevertheless, for high-frequency wristwatch oscillators, it is the only reasonable way to keep the current level at an acceptable value. Using this concept, oscillator currents of 1.5 p A at 2.4 MHz have already been achieved in a commercial wristwatch (9) in 1974. An interesting possibility is combining the amplitude feedback scheme with an oscillator circuit where the active transistors operate in weak inversion (15). As mentioned earlier, weak inversion operation can ease the oscillator start up problem by ensuring that g, > g , in Eq. (8) for minimum drain current. The circuit diagram of such an oscillator is shown in Fig. 13. The quartz Q, the transistor T I ,and the two capacitances C3and C4constitute a simple constant-current oscillator as described in Fig. 12 biased by the resistor R, and the current source T z . The DC gain of the closed loop made up of transistors T, , T 3 , T4, and Tz is greater than one. The currents in both branches therefore increase until they are limited by the output characteristics of Tz and T 3 . The drain current ID,of T , is high so that oscillations start to build up. As the amplitude [I,at the gate of T , increases, the average gate voltage V,, of T , must decrease to keep the average current drain of this transistor constant in spite of the nonlinear transfer characteristics. The AC component of the oscillation at VG1is filtered out by the low-pass R z C z . Therefore, the gate voltage VG3of transistor T3 is

1I

"n

-

_

44-7-

FIG. 13. Low-current quartz oscillator using an amplitude feedback scheme. After Vittoz and Fellrath ( 1 9 , reprinted with permission.

200

A.

P. GNADINGER

equal to Vcl . Hence, the drain current of T3decreases as U1increases. As U1 reaches a critical value UlC, the drain current of T4 overcomes that of T3 and the drain voltage of T3jumps to a value close to the supply voltage Vcc . This transition effects a sudden drop of ID,down to a value just necessary to keep the amplitude of oscillation U1 close to the critical value UIC ' For a sinusoidal oscillation signal U, sin wt and for transistors T , and T3 operating in weak inversion with V,, = V,, = 0 (sources connected to a common p well) and v D 3 S UTthe critical value UlCis given by (15) where Z, is the zero order modified Bessel function (Z9),UT = k T / q , and pI-p4 are the gain factors of the transistors T,-T4, respectively. These gain factors are basically given by the geometrical shape factors (effective width and length of the channel) of the transistors. n is the slope factor of the gate transfer characteristics of a transistor operating in weak inversion (20) and is only dependent on technological parameters. The drain current I D , of the transistor T , operating in weak inversion is related to the transconductance g,, by (20) g,, is somewhat larger than the critical transconductance g, necessary for oscillations to be sustained given in Eq. (8). The advantage of using repreweak inversion operation can now clearly be seen. The ratioDI/&,! sents a figure of merit for a watch oscillator circuit indicating minimum power consumption. This value now reaches a maximum in the weak inversion regime. The directly coupled amplifier stage T,-T,, in Fig. 13 is needed to reach the necessary logic swing for driving the following divider chain. The noncritical resistors R, and R , can be implemented in various ways depending on the technology used. A differential resistance of 1-10 GR at zero voltage is quite adequate, so that, for example, polycrystalline diodes (2Z) or high ohmic implanted-polycrystalline resistors (22) can be used if the oscillator circuit is realized in silicon gate technology (23). Fig. 14 shows the experimental results obtained with the circuit of Fig. 13. It is seen that the amplitude of oscillation U , at the gate and the current I are both fairly independent of the supply voltage Vcc in the interesting voltage range of 1-3 V. With typical technological parameters, the current drain is of the order of 30 nA. The total current consumption including the current for the output amplifier T,-T, can easily be kept below 100 nA at 32 kHz, employing a standard quartz resonator. So far, as an example, it was assumed that the oscillator circuits

20 I

ELECTRONIC WATCHES AND CLOCKS I

I

u, [mvl!

J

I

i

1000

I (without quartz)

I I

I

to-’.

(calculated)

00

0

1.0

2:o

FIG. 14. Amplitude of oscillation and total current as a function of supply voltage for the quartz oscillator of Fig. 13. After Vittoz and Fellrath ( I 3 , reprinted with permission.

described in this section were realized in CMOS silicon gate technology. However, the basic three-point oscillator circuit of Fig. 4 can also be implemented using other MOS or bipolar technologies, as described in Section IV,C. For standard bipolar circuits an alternative solution to the Pierce oscillator would be the zero-phase shift circuits as described by Forrer (3).These circuits, which were quite popular in the first electronic wrist watches (5, 6), consume considerably more power and are therefore of no practical use today. For high-frequency applications other possibilities apart from the popular Pierce oscillator have been tried. An interesting example makes use of the Clapp oscillator (24). Again, this circuit cannot easily be implemented in standard IC technology and has therefore no practical use. 2. Digital Tuning Several attempts have been made to eliminate the variable trimmer capacitor that is needed for the frequency adjustments of the oscillator. This trimmer capacitor quite often poses problems because its stability

202

A. P. GNADINGER

might not be high enough to match the inherently good stability of the quartz resonator. It also adds to the manufacturing costs of the watch module. The most promising suggestion in this direction seems to be the digital tuning technique illustrated in Fig. 15 (14,25). The quartz crystal is now used only as a very stable frequency reference whose absolute value has to match the frequency desired only approximately, which means that manufacturing tolerances of the quartz and also of the capacitances C1 and Cz(Fig. 4) can be relaxed. The subsequent divider chain is now made adjustable in such a way that the frequency division ratio matches the quartz frequency. The adjustment is retained in an N-bit alterable memory defining 2N tuning steps. The increment per step is the reverse value of the division ratio, so that a 500,000 ratio is necessary to achieve an accu(0.09 sec/day). There are many advantages to this scheme. racy of Apart from the trimmer capacitor that can be avoided, a better optimization of the oscillator is possible, especially at high frequencies. The tuning range can be widened without degradation of stability and an unadjusted, less-expensive quartz can be used. The adjustable divider can be realized as a preset counter by inhibiting part of the pulses supplied by the oscillator or by adding pulses. The alterable memory should be integrated with the watch circuit in order to take full advantage of the potential simplification of the watch module that can be achieved by avoiding the trimmer capacitor. The number of bits is relatively small and does not consume much area on the silicon chip. Therefore, it can easily be implemented as a static random access memory circuit using standard flip-flops as memory cells. If it is desired to keep the tuning information stored when the battery has to be changed, nonvolatile memories such as FAMOS structures (26) or MNOS (27) techniques have to be applied. These techniques are, however, not fully compatible with standard CMOS processing or will at least add considerably to the manufacturing costs of the integrated circuit. It is also possible to use a second battery for the memory part of the circuit

FIG. IS. Principle of digital tuning. After Vittoz (14), reprinted with permission.

ELECTRONIC WATCHES AND CLOCKS

203

(28).This battery will have a very long lifetime since it has to supply only the leakage current of a few nanoamperes. It adds, however, considerably to the cost of the watch module. Probably the most satisfactory solution is to accept the volatility of the tuning information. This is not a great disadvantage since the time between battery changes approaches 2 to 3 years nowadays. The concept of Fig. 15 can now be extended to an automatic digital tuning scheme as shown in Fig. 16. An acquisition circuit is added to the system that is integrated together with the main watch circuit. This circuit compares the output period of the divider with an external reference and computes the time difference between these two periods. It then transfers this correction to the memory, which in turn adjusts the divider accordingly. The function of the acquisition circuit can even be partly combined with the divider so that the memory circuits are simplified as well. This solution has two major advantages: first, the external equipment necessary to tune the watch is a simple reference generator; second, the information goes unidirectionally into the watch, so that nongalvanic coupling is possible. The concept described has been implemented in a commercial watch module (28). This analog watch with automatic tuning uses a quartz with a nominal frequency at 532 kHz. 14 bits of memory are needed to provide a tuning range of 3% with an accuracy of & The circuit is realized in silicon-gate CMOS technology. The total current drain is less than 4 p,A due to the use of dynamic dividers and the use of amplitude feedback in the oscillator. The tuning of the watch is extremely simple. The watch is placed on top of the reference source and a single button is pushed. This initiates the transmission of a short reference pulse. This pulse is picked

OSCILLATOR

DIVIDER

DISPLAY

Q MEMORY

FIG.

16. Automatic digital tuning. After Vittoz (14), reprinted with permission.

204

A. P. GNADINGER

up by a small coil that is included inside the watch and fed to the acquisition circuit. The inductive coupling even makes it unnecessary to open the watch case. 3. New Time Buse Systems The quartz-stabilized oscillator has found such a wide application in any kind of electronic watch or clock that thoughts and suggestions concerning different time bases have not found much interest so far. The concept of a fully integrated time base avoiding quartz as a resonator seems at first quite intriguing because it would eliminate a bulky, rather expensive, and shock-sensitive mechanical component. However, there is such a wide gap between the stability that can be obtained with the best possible RC oscillator on one hand and with the simplest quartz oscillator on the other hand, that a major advantage of the electronic watchaccuracy-would have to be sacrificed. Furthermore, using such an RC oscillator would run contrary to the general trend mentioned before: decreasing the energy consumption to the lowest possible value in order to extend the battery life, because an RC oscillator would definitely consume more energy than a quartz-stabilized one. Nevertheless, at least one manufacturer (29) has expressed confidence in the feasibility of an oscillator of this kind, but with quite a moderate goal for stability. In addition, an accurately trimmed discrete resistor is needed that would cancel nearly all advantages in cost and volume reduction. Other suggestions such as using a piezoelectric substance that would be deposited onto the silicon wafer during wafer fabrication and would serve as a frequency-controlling element have not proven feasible-at least not until now. Alternatives still using a quartz resonator but assembling it together with the integrated circuit into a common package are, of course, quite attractive in terms of cost and volume reduction. Solutions of this kind are under development at various semiconductor manufacturers and will probably be introduced into commercial watches within the next few years. Time base systems based on radioactive sources have been proposed in the literature (30),but they have not yet been realized. Many problems still have to be solved and with the high development cost and the low prices of quartz resonators, the advantages of such a time base are not obvious at all. 4. Quartz Crystals

The quartz crystal resonators that are now used nearly exclusively in electronic watches and clocks owe their frequency-stabilizing properties

205

ELECTRONIC WATCHES AND CLOCKS

to the piezoelectric effect discovered in 1880 by P. and J. Curie. The theory of piezoelectricity is covered in any elementary physics textbook; it is not treated here. In 1921, W. Cady succeeded in utilizing quartz crystals for the frequency stabilization of a tube oscillator and in the early 1930s, W. A. Marrison and A. Scheibe built the first quartz clocks. The application of quartz crystal resonators in electronic wristwatches had to await the advent of integrated circuits and was only realized in the late 1960s (5, 6). Starting material for any quartz crystal resonator is either natural quartz, mostly found in Brazil, or synthetically grown quartz. The synthetic quartz is particularly suited for industrial applications because of the equal size of the crystals, the absence of cracks and other defects, and in general a much better fabricational yield. The large quartz crystals are cut into small units, where special emphasis has to be placed on accurately controlling the crystalline orientation. This is usually accomplished by X-ray diffraction techniques. There are 12 known crystal cuts differing in the orientation of the crystalline axes. The resulting quartz crystal resonators vary widely in their size and shape and their mechanical and electrical properties. In order to stimulate oscillations, these crystals are covered with electrodes in a suitable manner. Depending on the cut of the crystal and the size and shape of the electrodes, four different modes of oscillations can be induced: flexion, displacement, planar shear, and thickness shear, as illustrated in Fig. 17 (31).These modes do not exist in a pure form. They are, moreover, coupled to each other, the coupling constants being strongly dependent on the geometric dimensions and the ( c ) Planar shear

( a 1 Longitudinal flexure L

_ _ - - - - -_ _ _ _ _

z

t $--------L

Y

4 *

-I +I

A

Z

( b ) Longitudinal displocement

-EX

(d)

Y-

Thickness sheor

-

FIG.17. The various forms of oscillation of quartz crystals. After Glaser (311, reprinted with permission.

206

A.

P. GNADINGER

orientation of the crystal (32). Depending on the crystal cut and the oscillation mode chosen, a frequency range starting at I kHz (xy flexure) up to about 200 MHz (employing the ninth harmonic of an AT-cut crystal in a thickness shear mode) can be covered. The equivalent electrical circuit of a quartz crystal resonator has already been shown in Fig. 5a. The inductance L in Fig. 5a may vary from 300,000 H (xy flexure at 1 kHz) to 5 x H at 200 MHz. For the same frequency range, the dynamical capacitance C varies from 0.05 fF to 0.2 pF, the static or shunt capacitance C3from 1 to 50 pF, and the series resistance R from a few hundred ohms to about 1 M a . This is to illustrate the wide range of the electrical parameters that can be covered. The mechanical properties of a quartz resonator can also vary drastically, depending on the crystal cut and the oscillation mode. The most important mechanical properties are shock resistance, size, temperature dependance, and aging behavior. For 32 kHz wristwatch applications, the crystal type used in the early developments was the xy-flexure mode crystal (X 5” cut) shown in Fig. 18a. This type of crystal, however, is very difficult to mount since any mechanical supports have to be located exactly at the nodes of the mechanical oscillations. The high positioning accuracy required renders this type of quartz shock sensitive and expensive. A big improvement was made with the development of the tuning-fork crystal. The base of the tuning fork provides a rigid body for easy and shockproof mounting. The early versions of tuning-fork crystals, shown in Fig. 18b, were cut out of a flat piece of quartz and covered with electrodes on both sides in a suitable configuration in order to stimulate oscillations in the flexure mode, A much improved version of the tuning-fork crystal, shown in Fig. 18c, has been pioneered by Statek Corp. in recent years (33).These crystals are fabricated many units at the same time, employing an essentially planar technology: First the electrode films are deposited by vacuum evaporation onto one side of a flat quartz plate, then the structure is defined by photolithography, and etched using standard wet chemical or plasma etching methods. Finally, the individual units are separated from each other by etching through the quartz plate with an anisotropic etchant. The direction of the fastest etch rate has to be perpendicular to the quartz plate surface in order to prevent underetching of the masked areas. This requirement necessitated the use of a 2 cut instead of the previously employed NT cut and, as a consequence, a new piezoelectric concept had to be found. With this batch processing scheme, more than 100 units can be produced simultaneously on one quartz plate, resulting in low manufacturing costs. An additional advantage of tuningfork crystal resonators is the fact that their frequency can easily be ad-

+

ELECTRONIC WATCHES AND CLOCKS (0)

207

(b)

Oscillator excitation X Y mode

-I

-A

01

+-

-+

a m +- t

with ‘ flexure

FIG.18. The various types of quartz crystals used in electronic clocks and watches. (a) Quartz crystal oscillating in the flexure mode ( X + Y)-cut. (b) Sawed tuning fork crystal (X + 5”)-cut. (c) Etched tuning fork crystal (x + 5“)-cut.(d) Quartz-crystal oscillating in the thickness shear mode AT-cut. After Glaser (31).reprinted with permission.

justed by laser trimming. Using a semiautomatic adjustment scheme, the mass of the tines and therefore the resonance frequency can be altered by removing a controlled amount of electrode mass provided for this purpose at the end of the tines by laser evaporation. In principle, this can even be done through a clear window after the crystal has been put into a hermetic package. It has also been suggested (34) to use this feature on a finished module, rendering the trimmer capacitor for frequency adjustment obsolete. However, the unavoidable aging of a quartz crystal would probably still make an easy frequency adjustment of a finished watch desirable. For clock applications, where minimum power consumption is not as stringent as for wristwatches, 4 MHz quartz crystals have succeeded as standard as mentioned before. These crystals employ an AT cut and oscillate in the thickness shear mode. They are rather small and quite shock insensitive. The main problem in achieving high accuracy in electronic watches or clocks is the dependence of the quartz crystal frequency on temperature.

208

A. P. GNADINGER

+

This dependency is a quadratic parabola for the (X So)cut and a cubic parabola for the AT cut, as shown in Fig. 19. The turning point or the inflection point, respectively, can be put close to the operating temperature. A proper choice of the cutting angle ensures a rather flat characteristic around these points, as evident from Fig. 19. It can clearly be seen that the AT-cut crystal shows a much better performance over a wide temperature range. This is one of the reasons for choosing this type of crystal in electronic clocks. Especially in automotive applications where an extremely wide temperature range is specified, the tuning-fork NT-cut -20

-40

hflf

=

0

20

40

60

98OoC

k(9--80)2

10-5 6

35O 10'

Af/f

35O 12'

4

35O 14' 35O 16' 350 18' 35O- 20' 35O 22' 35O 24' 35O 26'

2

0 -2 -4

-6 -60

-40 -20 0

20 40 60

80 100'

9O

FIG. 19. Frequency variation as a function of temperature with cutting angle as parameter. (A) CT (X + 5")-, BT-, DT-cut. (b) AT-cut. After Glaser (31), reprinted with permission.

ELECTRONIC WATCHES AND CLOCKS

209

crystal would not qualify because of its inadequate temperature range. For wristwatches, however, the practical temperature range is much narrower due to the temperature-stabilizing effect of the human body. The frequency deviation due to the parabolic characteristic of Fig. 19a is therefore small enough and can in most cases be tolerated. The lower power consumption due to the lower frequency of the NT-cut crystal is, for wristwatches, in most cases more important than the better temperature characteristics of the AT-cut crystal. It seems feasible to compensate for temperature variations by special compensating networks possibly integrated on the main electronic circuit, rendering in such a way the watch or clock more accurate even with nonoptimum quartzes and over a wide temperature range. However, such solutions have not been successful so far, mainly due to the increased complexity of the integrated circuit. Such schemes could have more success with digital tuning as described in Section IV,A,2, but temperature sensors and possibly a microprocessor solution will be necessary. In any case, these inventions would only be used for expensive watches where high precision is wanted. The frequency of a given quartz crystal will also change slightly with time. This aging effect is caused by many factors and is dependent on crystal cut, frequency, manufacturing technology, and mounting and encapsulation methods. All aging factors can be reduced to the following: mass transfer from or to the quartz surface, mass transport along the surface, and structural changes in the electrode films and the mounting structure. These factors have to be minimized, which is usually done by appropriate heat-treatments. First, the crystals are cleaned carefully after cutting and mounting and a first heat-treatment is performed. After cooling down, the crystals are possibly tuned to the proper frequency and hermetically packaged by cold-welding under vacuum. The sealed quartz crystals are now exposed a second time to a high temperature. This way any tension in the electrode films or the mounting structure can be decreased. A typical aging characteristic of a 32 kHz xy' flexure quartz is shown in Fig. 20. Further factors that can influence the frequency of a quartz oscillator are mechanical shocks and vibrations that act upon the quartz crystal. As mentioned before, xy flexure mode crystals as shown in Fig. 18a are the most shock-sensitive units because the wire mounting structure forms an integral part of the resonating system. The shortest possible wire length is h / 4 , i.e., a quarter of the wavelength corresponding to the oscillating frequency. Shorter wire lengths would reduce the Q value to unacceptably low values. This quarter-wavelength restriction actually determines the lowest resonating frequency of the supporting structure. Fortunately, at

210

A.

P. GNADINGER

5 -

I

3

0

6

1

I

9

I 12

Time (months)

' t

I

0

I

1

I

I

1

2

I

3

I

1

4

1

I

5

Time (years)

FIG.20. Aging of quartz watch crystals 32 kHz,XY' flexure mode.

32 kHz this value is high enough (>500 Hz) to be in the nondestructive region. Frequency changes due to mechanical vibrations are usually below 5 ppm for xy flexure mode quartzes. Larger deviations are encountered if a quartz resonator is subjected to a single mechanical shock of, for example, 3000 g , where g is the acceleration factor due to gravity. Here, the maximum frequency deviations can be as large as 20 ppm, which

ELECTRONIC WATCHES AND CLOCKS

21 1

amounts to a time deviation of a 32 kHz watch of 1.73 sec/day. Moreover, it takes approximately 7 days for the quartz to recover (35) due to a memory effect that takes place in the strongly loaded and slightly deformed supporting wire. All these effects are greatly reduced for the tuning-fork crystals (33)because of the rigid base available for mounting purposes. Shock sensitivity also decreases with increasing crystal frequency because the mounting structure no longer influences the resonating system. B. Electronic Watch and Clock Circuits As evident from Fig. 2, the integrated electronic circuit connects and controls the other components of the watch in a suitable manner. Its main functions are (1) to divide the high-frequency output signal of the time base to the low value necessary to drive the display, (2) to feed the energy provided by the battery in a suitable form to the time base, (3) to provide the proper signals for displaying minutes, hours, date, etc., by using various counters, (4) to decode the signals to drive the solid-state display in case of digital watches, and ( 5 ) to drive the stepping motor in case of an analog display.

In additian, there are various auxiliary functions incorporated in the electronic circuit. All these functions are realized by standard digital techniques. The oscillator circuits described in the previous section are actually also part of the integrated circuit of the watch. They are analog circuits. In the early electronic watches they were usually integrated in a separate circuit. In recent years, the manufacturing technologies have been optimized to such a degree that it became feasible to integrate the oscillator circuit on the same chip with the main circuit, so that practically all watch and clock modules nowadays contain only one integrated circuit. Referring again to Fig. 2, the time base and the watch circuit are therefore partly merged. The various functional blocks of the electronic circuit are now described in detail. 1. Frequency Dividers and Counters

One of the main functions of the electronic watch circuit is to reduce the frequency of the output signal of the oscillator in the range from 32

212

A. P. GNADINGER

kHz up to several MHz to a value of the order of a few cycles per second or less, depending on the type of display used. This is accomplished by cascading a number of divider cells where each cell divides the frequency of the signal by a given factor. This factor can be any number from 2 to about 9. The values most often used are 2, 3, and 5 . Keeping in mind that it is highly desirable to keep the number of active components as small as possible in order to minimize power consumption and chip area, employing dynamic logic circuit techniques would be advantageous. However, because of the rather low-frequency operation of most of the divider stages in the chain, dynamic logic can only be employed for the first few stages. The lower-frequency limit is approximately 1-5 kHz, depending on the technology used. It is, however, still worthwhile employing dynamic dividers even for a very small part of the divider chain, since the first few stages will consume most of the power, as is shown later. For high-frequency applications (2-4 MHz) it is even mandatory in order to keep the current consumption within reasonable limits (510 PA). A few examples of divider stages as they are used in actual watch circuits are now given. First, the static version is described and the dynamic version deduced therefrom. A very popular divide-by-2 cell is given in Fig. 21 (36). This combination of inverters and single or two-level gates corresponds to a total number of 22 transistors and realizes the following set of logic equations:

=E,

A

B

=

(I

+ D)A,

D=B,

C = IE

+ AB

(13)

E=C i

I

A A

A

I -

‘-0

I

-

I

I

HE

FIG.21. Basic circuit of scale-of-two CMOS stage. After Vittoz et al. (36), reprinted with permission.

ELECTRONIC WATCHES A N D CLOCKS

213

where 1 is the input signal and each of the variables A , B, C, D, and E can be used as output signal, since they all switch at a frequency half that of the input. This structure has been arrived at by means of a special algorithm based on the standard Huffman (37) method. The complete switching cycle of each variable is given in Table I. In the first state each equation of the set is satisfied. It is thus a stable state, which is preserved as long as I does not change. If Igoes from 0 to 1 (line 2), the equation for B is no longer satisfied. B, therefore, tends to change state, so that the second state is unstable. This leads to another unstable state where the equation for D is no longer satisfied. Transition of D leads to a second stable state (line 4), which will be maintained as long as I is 1. If 1 switches back to 0, the cycle goes on through two more unstable states and then reaches the original state where the cycle had started. It can be seen clearly that this structure is free of any logical hazards: during any of the unstable states only one equation of the set is not satisfied. Hence, a single variable tends to change state and there exist no rating conditions between the variables. This is an important consideration in all divider circuits. In order to ensure proper operation of a divider cell in a real circuit with variation of the technological parameters, racing conditions have to be strictly avoided. A further advantage of the divider cell of Fig. 21 is the use of only the uncomplemented form of the input variable I. This avoids the use of an additional inverter to drive the first stage, which would enhance the power consumption. Another advantage is the possibility of cancelling the dynamic power consumption of the first stage by combining the gate capacitance of the first stage with the functional capacitance Cz of the Pierce oscillator (Fig. 4c). The circuit of Fig. 21 can be simplified by combining some transistors, yielding the 18-transistor circuit of Fig. 22. One transistor has been eliminated by changing the static gate giving C by a dynamic gate (38), where the functions C+ of the block of p-type transistors and C - of the n-type transistors

C + = % i- 2,

C-

=

A B f IE

(14)

have been introduced. It can be shown that node C is floating only during a transient state and the static behavior of the cell is therefore not affected. The dynamic version of the circuit of Fig. 22 can be arrived at by omitting all feedback loops that are required to maintain the stable states. The internal capacitances associated with each node of the circuits will then maintain the state of the divider. This dynamic version is drawn in thick lines in Fig. 22. It is very simple and requires only nine transistors.

214

A. P. GNADINGER TABLE I

SWITCHINGCYCLEOF VARIABLES Type of state

I

A

B

C

D

E

Stable

0

1 I

I I

0 0

0 0

1 1

0

I I

I

O

O

O

I

1

I

0

0

1

I

O

I

O

O

I

I

0

0

1

0

1

I

I

0

0

1

0

1

I

0

1

I

0

1

I

0

1

0

0

1

1

0

1

0

1

1

I

0

1

0

1

1

0

0

0

0

1

1

0

0

0

1

I

1

0

0

0

1

I

0

0

0

0

1

I

0

0

1

Unstable

Path of the switching current"

0

12, 16 0 19

0

5, 9

22 0

2, 4

13 20 0

1

10, 12

21 ~

~

~

~

0 ~~~~

~~~

The last column indicates the transistors through which the current charging or discharging the switching node is flowing. a

Divider stages that divide by a ratio other than 2 are described in the literature (14, 36, 38, 39). An example of a dynamic divide-by-3 cell is shown in Fig. 23 (38, 39). This circuit can be extended to any odd dividing ratio.

ELECTRONIC WATCHES AND CLOCKS

215

E I

FIG.22. Five-gate race free divide-by-2cell. The simplest dynamic divider is drawn in thick lines. After Vittoz (14). reprinted with permission.

The circuits described so far are realized in a complementary technology (CMOS). Some technologies such as 12L provide only single-level gates, that is, NOR or NAND gates, depending on the definition of the logic levels. The most common divide-by-2 cell in this technology is a standard six-gate structure. A simpler circuit using four NOR gates with a single input I is shown in Fig. 24. This circuit is not completely race free. Forbidden transitions have to be suppressed by slowing down the 0 to 1 transitions of variables A and D . This structure has been realized in an actual circuit in Z2L technology with a very small cell size of less than 8000 pm2 (40).

2 . Decoder and Driving Circuits The decoder and driving circuits are the interface between the integrated circuit and the display. There are quite different requirements put on these circuits, depending on the type of display used, the most obvious difference existing between those used in analog clocks and watches and those required to drive a solid-state display. In particular, the maximum current they have to be able to supply can be orders of magnitude apart. Peak current levels for analog watch drivers are in the range of 1 mA, whereas the peak current for LEDs (light emitting diode displays) can be as high as 70 mA. In the case of LCDs (liquid crystal displays), the maximum currents are much lower, mostly around 1 pA, but the complexity of the circuit is far greater since every segment of the display basically needs its own driver stage. The three basic types of decoding and driving circuits used for analog displays, LEDs and LCDs, are now treated in somewhat more detail.

216

A. P. GNADINGER

10-

Fig. 23. Dynamic divide-by-3 cell; it can be extended to any odd dividing ratio. After Vittoz (14). reprinted with permission.

a . Analog Watch Drivers. For analog watches and clocks, no special decoding circuitry is needed since the output signal of the divider chain-usually a short current pulse of 1 Hz-is directly fed to the driver stage, which in turn interfaces with a stepping motor that advances the fastest moving hand of the watch, usually the second hand, in discrete steps. A miniaturized stepping motor is by far the most common device to drive the display of an analog watch. Various designs of those micromotors have been described in the literature ( # 1 , 4 2 ) . They consist basically of a wound coil that is mounted between two permanent magnets. The coil is energized by a short current pulse provided by the drive circuit and moves thus for a predetermined angle. Means are provided so that

A=

B*c

-

B = A*C*D

C= m D

L

D=

FIG.24. Controlled-race divide-by-2 cell using four NOR gates: forbidden transitions (in dashed lines) are avoided by slowing down the 0 to 1 transitions of variables A and D . After Vittoz ( / 4 ) , reprinted with permission.

ELECTRONIC WATCHES A N D CLOCKS

217

this movement is unidirectional. To stop the movement after each pulse, the motor is short-circuited and the resulting magnetic field provides a retarding moment to the coil. Most motors use bipolar pulses; that means that pulses of alternate polarity flow through the motor. However, at least one supplier (42) has specialized in stepping motor designs that employ unipolar current pulses. Figure 25 shows a standard circuit used to drive a bipolar stepping motor M of an analog watch. At each step, the input of one of the two inverters is alternately switched on and current pulses of alternate polarity flow through the motor M. Between pulses, the motor is kept in shortcircuit through the two conducting n-channel transistors. The pulse amplitude is very much dependent on the motor design and is of course kept as low as possible. A minimum peak current of 0.5 mA is typical at the time of this writing. The period of the pulses is usually 1 sec for analog watches with a second hand (in rare cases more than one pulse per second is required, but this is disadvantageous because the current consumption is higher). For watches with only minute and hour hands, the pulse period is longer, 4 , 5 , or 10 sec being typical. It is quite obvious that such a watch has a considerable advantage since the power consumption is reduced in proportion to the pulse period for all parameters (pulse amplitude and width) being equal. For a given peak current, the pulse width is determined by the minimum moment required to drive the second (or minute) hand and the associated gear train. For bipolar motors in wristwatches a pulse width of the

VL (a)

FIG.25. (a) Analog-watch driving circuit. (b) Pulse train of analog-watch driver

218

A. P. GNADINGER

order of 3-30 msec is required. In electronic clocks the driving circuit and the stepping motor are capacitively coupled so that the pulse width is essentially determined by the value of the coupling capacitor and is not fixed by the integrated circuit. The internal resistance of a stepping motor has decreased steadily in the course of time and is at present approximately 1000-2000 fk for bipolar stepping motors and 500- 1000 fk for unipolar motors. In order to be able to supply the maximum required current into such a load, the driver circuit has to have an extremely low internal resistance. The maximum voltage drop in the conducting transistors must be kept below 50- 100 mV to ensure reliable operation from a low-voltage power supply. The channel resistance of an MOS transistor is to first order given by the relation r = L/[pWCo(V - V d l

(15)

where L and W are the length and width of the channel, p the mobility, and Co the oxide capacitance per unit area. V and VT are the supply voltage and the threshold voltage, respectively. For a minimum value of V of 1.1 V and a maximum threshold voltage of 0.7 V (worst-case condition), Co = 530 pF/mm2, p = 200 cm2/V sec, and an effective channel length L of 3.5 pm, the channel width W must be at least 16.5 mm to keep the voltage drop below 50 mV at 1 mA. This extremely wide transistor is realized by a meander-shaped interdigitated structure. The resistances of the source and drain-diffused fingers have to be kept as low as possible, which is usually accomplished by connecting them to a low resistance metal line at as many points as possible. In any case, the driver inverters have to be carefully optimized for minimum size. Even then the total size of the driving circuit very often exceeds 1 mm2 and often covers more than 25% of the total chip area. This can also clearly be seen in Fig. 36, where an example of an actual analog watch circuit is shown. b. LED Decoding and Driving Circuits. The digital watch circuits have to supply decoded signals able to drive a minimum of 34 digits, corresponding to 23 segments plus some special signs such as flashing colon, the AM/PM flag, or the name of the day. LED displays have a big advantage compared to LCDs: they can be multiplexed quite easily. This reduces the complexity of the decoder considerably. A standard multiplexing scheme is shown in Fig. 26 for a display with six digits (14). A single four bits/seven segment decoder is employed sequentially for each digit. The multiplexing switches can best be implemented by means of transmission gates (Fig. 8). A strobing frequency of 64 Hz is used most often. The decoder itself is realized with standard techniques. A compact ratioed CMOS technique has proven

ELECTRONIC WATCHES AND CLOCKS

219

COUNTER

k

FIG.26. Standard counter-multiplexer-decoder circuit as used in watches with LED display. After Vittoz (14), reprinted with permission.

well suited where transistors of one type are used as passive loads switched on simultaneously with the display. The decoded signals are then fed to the segment drivers as shown in Fig. 26. As mentioned earlier, LED drivers have to provide extremely high currents: currents of the order of 10 mA have to be switched by the seven segment drivers and up to 70 mA by the four to eight digit drivers. Therefore, most existing CMOS circuits need external bipolar transistors for the digit drivers or for both digit and segment drivers. There has been one attempt to incorporate all driver circuits onto a single CMOS chip (43),but this solution does not seem to be economical. Too much silicon area is consumed by the CMOS transistors, which have to be laid out so that they can provide the required high currents. Multichip solutions seem therefore to be a better choice; even so, packaging the chips creates additional costs. A manufacturing technology that is ideally suited for LED drivers is the Z2Ltechnology that is covered in more detail in Section IV,C. Being a bipolar technology, it can provide high-current transistors on a rather small area. Yet the multistage amplifiers necessary to scale up the currents from the 10 nA logic level to the 70 mA drive level still need an area of roughly 1-2 mm2 (40). Figure 27 shows a schematic of such an 12L digit driver (40). A low signal at the base of transistor Ql enables QI1to sink the digit drive current of 70 mA. Transistors Ql-Q, are minimum size P L transistors, con-

220

A. P. GNADINGER

stantly drawing 5-10 nA per transistor. With the signal at the base of

Q, going high, the isolated transistors Qs-QI1 are turning off. The digit driver in the off state then draws 50 nA. Transistors Ql-Q3 serve the pur-

pose that any gate signal less than two gate delays long will not turn the stage on. The same configuration is implemented with the segment drivers, preventing the turning on of incorrect segments due to timing errors. Under worst-case conditions, the output transistor has to be designed with a gain factor p > 23 at 70 rnA, which can easily be done on a fairly small chip area. c. LCD Decoders and Drivers. Contrary to LED displays, LCDs cannot be multiplexed easily, as is shown in Section IV,D. The signal for each segment must therefore be decoded separately, unless each output is buffered by a latch circuit that is updated periodically. Each segment of a nonmultiplexed LCD requires a separate driving circuit. Up to 70 external connections between the integrated circuit and the LCD are thus necessary for a complex digital watch. Digital wristwatches are usually operated with a minimum supply voltage of 1.3 V. The LCD, however, requires a voltage of at least 2.5 V, as shown in Section IV,D. It is therefore necessary to use two 1.5 V (1.3 V) batteries in series, or a voltage doubler incorporated into the main circuit. An example of a voltage doubler that is now preferred in wristwatch circuits is described in the next section. It is also mandatory to drive LCDs with alternating voltages. Direct voltage drive would lead to an electrolytic decomposition of the electrodes that would drastically reduce the life expectance of an LCD. If the

ell

ELECTRONIC WATCHES AND CLOCKS

22 I

electrodes of the display were covered with an insulating lacquer to prevent this decomposition, the voltage across the liquid crystal would strongly decrease due to the voltage drop across the double layer formed near the electrodes. An example of a driving and decoding circuit (44) used to drive an LCD in a parallel (nonmultiplexed) fashion is shown in Fig. 28 ( 1 1 ) . A rectangular voltage with 0 and 5 3 V levels is applied to the common back-electrode. In position 2 of the switch, the same voltage is applied to the middle segment of the front electrode, which is considered as an example. In the overlapping region of the two electrodes no voltage drop exists across the liquid crystal and the segment is not excited. If the switch is put in position 1, voltages of opposite polarities are applied to back and front electrode and the segment under consideration is exercised. The segment effectively sees a rectangular alternating voltage of + 3 and -3 V. Standard BCD to segment decoders together with an exclusive OR gate are necessary to drive one digit in the above-mentioned way. The minimum driving frequency of an LCD is given by the sensitivity of the human eye to variations in light intensity. Nonmultiplexed displays LCO P A R A L L E L ORlVE +3v

-3v

v1

nr

A V = V,

'iVN

- Vz

FIG.28. Driving (top) and decoding (bottom) circuit for LCD display in parallel (nonmultiplexed) fashion.

222

A. P. GNADINGER

that are driven by symmetrical rectangular voltage pulses are practically subjected to the same uninterrupted voltage since the electrooptical effect is independent of polarity. The light intensity varies only slightly during a short fraction of time when the capacitances associated with the electrodes are charged and discharged. The human eye can barely see these variations, even at frequencies of around 30 Hz.A convenient frequency that can easily be deduced from the divider chain of the circuit is 32 Hz. This is now usually employed in most circuits. Higher frequencies are not desirable because the current consumption of the display would increase considerably because of the fairly large capacitance of the electrodes. For multiplexed LCDs, the rules are different because a clocked signal is now applied to the display. Figure 29 shows an example of an LCD with N equal digits. In order to allow for XY selection, equal segments are connected together (rows of the matrix). Each digit possesses a separate back electrode (columns of the matrix). The back electrodes are biased in a cyclic fashion independent of the digits to be displayed. For the columns selection, the clock cycle is therefore 1 : N. If the voltage applied to the back electrode is opposite to the voltage at the row electrodes, the desired digit is displayed. The big advantage of multiplexing the LCD is a considerable reduction of the number of external connections. For a multiplexed display this number is given by N + 7, instead of 7N + 1 for a nonmultiplexed version. However, multiplexing a display requires bipolar cyclic pulses with controlled amplitudes because of possible interference with neighboring elements. This leads to a considerable increase in the complexity of the driving and decoding circuitry of LCD displays. Further disLCD Multiplexed Drive

I

I

I I I I

I I I

-1 Segment G +V -v

Digit 1

+2q-L-jj v

I

-2

Digit 2 Digit N

FIG.29. The principle of driving a multiplexed display.

ELECTRONIC WATCHES A N D CLOCKS

223

advantages of multiplexed LCDs more related to the physics of liquid crystals are described in Section IV,D.

3. Auxiliary Circuits Apart from the main functions described so far, each watch and clock circuit contains a variety of auxiliary parts such as logic level shifters, voltage multipliers for LCDs, special circuitry for fast automatic testing, and battery voltage indicators. For multifunctional, digital wristwatches, the additional logic circuitry needed can constitute a major part of the circuit and occupy a considerable chip area. Logic level shifters are required as an interface between the lowvoltage high-frequency part and the high-voltage low-frequency part of a circuit for LED displays. Figure 30 shows an example of such a circuit in CMOS technology (14, 45). Transistors T, and T2 are driven by the low-level signal X and are designed so that they can sink the current provided by the transistors T3 and T4,which are themselves driven by the high-level signal X’.Good pulse shaping and short transit time are given by the inherent regeneration. For LCDs the high voltage is usually supplied by an electronic voltage multiplier allowing the circuit to be operated by a single battery. Modern displays require not more than 2.5-3 V and a voltage doubler can be used. Figure 31 shows an efficient voltage doubler using active switching (46). A first capacitance C, is alternatively connected across the lowvoltage and the low- and high-positive-voltage levels. In the first state it is charged; in the second state it shares its charge with that on capacitance Cz.If C1 and C2 are equal, the voltage on the high positive terminal is

X ’ W 1

C

x 4 L --iL -..

--

Tl

T2

-

224

A. P. GNADINGER

H

FIG.31. Voltage doubler circuit for digital wristwatch with LCD display. Courtesy of Faselec Corp., Zurich, Switzerland.

effectively double the voltage across the low positive terminal and ground. Use is made of the level shifter circuit shown in Fig. 30, which is used to drive the two p-channel switches connected to the high positive terminal. The circuit has to be operated with a certain minimum frequency. A signal of 512 Hz, which can readily be deduced from the divider chain, serves as a clock signal H. Reasonably high values of the capacitances cannot, of course, be integrated into the same chip. They have to be realized by miniaturized discrete components bonded externally to the chip. An important auxiliary circuit that can occupy a considerable amount of chip area is the circuitry needed to set the watch. Most of the timesetting systems use a scheme to accelerate the particular time function to be set or to be corrected. For digital watches at least two push buttons are provided on the watch case that have to be pressed singly or simultaneously in order to enter the so-called set mode, to select the appropriate function (hours, minutes, data, etc.), and to change this function. For analog watches a simpler scheme with a mechanical crown can be employed to set the hours and minute hands as is customarily done with ordinary mechanical watches. To synchronize the second hand to a reference time

225

ELECTRONIC WATCHES AND CLOCKS

signal, a push button may be provided. The circuitry corresponding to these time-setting features is normally implemented in a standard manner employing random-logic gates. A particular example is described in the next section. The push buttons of an electronic wristwatch or of a clock cannot be manufactured with reasonable costs to ensure that no spurious signals enter the circuit. Therefore, antibounce interface circuits must be provided on those input pads of the circuit that are connected to the push buttons. The push buttons are in most cases simple single-pole singlethrow switches without spring-loaded fast-switching action. Upon closing of this switch, in most cases a spurious pulse train is generated that could lead to a malfunctioning of the watch and that has to be suppressed. A circuit employing shift registers could be employed to filter out those unwanted signals. A simpler solution that is well suited for this particular application is shown in Fig. 32. The two transmission gates are clocked with a signal CP of approximately 10 Hz. While closing the push button contact, a logic 1 is generated at the input. This state is stored in the first latch, the master flip-flop, independent of the point of time and the duration of the signal. The information is transferred to the second latch, the slave flip-flop, when the clock pulse is going to 0. To set the circuit back to the initial condition, a 0 has to appear at the input during the negative transition of the clock pulse. In the actual situation a 1 at the input is never considered a disturbance and is therefore transmitted asynchronously. A 0 is only transmitted during the negative transition of the clock signal. A transmission of a disturbance is thereby not totally impossible but highly unlikely. -

CP Push

to main 4circuit

button

CP tranwnissim Qata

FIG.32. Antibounce circuit.

226

A . P. GNADINGER

Testing of an integrated watch circuit can be a time-consuming and expensive operation as mentioned earlier. In order to speed up the testing procedure, special circuitry has to be provided. This is especially true for analog watch circuits, where the output of the driver transistor is in most cases a 1 Hz signal. In order to determine whether a circuit is properly functioning, a measuring time of at least 1 sec is necessary-the time needed so that at least one pulse leaves the output stage. This time is much too long for economic testing. The method ordinarily chosen to shorten testing time is to bridge N stages of the divider chain and increase by this means the output frequency by a factor 2 N .The upper limit of this scheme is reached if transit time effects inherent in the technology used are influencing the pulse shapes and the timing of the circuit to such an extent that distinguishing good and bad circuits cannot be done with a reasonable degree of confidence. To preserve the total number of external connections, this special test pin is quite often combined with some other function of the watch. The selection of the test mode is then accomplished by a special combination of test voltages applied to the bonding pads. An example of such a circuit for accelerated testing is given in the next section. 4. Examples of Actual Clock and Watch Circuits

In Fig. 33, the block diagram of an actual clock circuit, the MB 9B of Faselec Corp., Switzerland, is shown as an example.

I

d p

t-I

Vp or VN

3

""T

M

Alarm out

. I IV.

M

I

I -

I

-

'"lY

-I

I

FIG.33. Block diagram of 4 MHz clock circuit MB 9B. Courtesy of Faselec Corp., Zurich, Switzerland.

ELECTRONIC WATCHES AND CLOCKS

227

Connected to terminals 1 and 2 are the positive and negative terminal of the power supply V, and V, , respectively. The circuit is operated from a single Leclanche-type battery with 1.5 V nominal voltage. External to the circuit and connected to pins 7 and 8 is the quartz crystal with a frequency of 4.19 MHz, which serves as a time base. As mentioned before, this frequency has become a standard for clock operations. The two capacitances Ci, and C,,, are also external to the circuit and connected to pins 7 and 8 in a Pierce configuration. C,,,is a variable trimmer capacitor for accurate frequency adjustment. Integrated on the circuit and connected to pins 7 and 8 as well is the actual oscillator circuit-a simple inverter oscillator with an integrated feedback resistor. The output signal of the oscillator is then divided down to 1 Hz by means of a 23-stage divider circuit as described in Section IV,B,l. The output signal at the end of the divider chain is fed to a bridge-type output driver for a stepping motor requiring alternating drive pulses. This motor is capacitively coupled to the integrated circuit and connected to pins 3 and 5 . At pin 6 an alarm signal of typically 512 Hz is available that can be connected to an alarm transducer. The alarm output contains a very low impedance nchannel driver transistor and a protection diode to short-circuit current spikes from an inductive load so that the alarm transducer can be driven in most cases directly without an external driving transistor. At terminal 4 a push button is connected that is used for accurate time setting and for rapid testing. Left open, it gives the normal running condition. Connected to V,, it interrupts the motor output. This is used for accurate time setting (the first output pulse appears after release of the switch) and to reduce power consumption of the clock during storage. If terminal 4 is connected to a voltage about 1 V higher than the positive supply voltage V , , the test logic is activated, which short-circuits essentially four stages of the divider chain and in that way speeds up the motor and alarm outputs by a factor of 32. Figure 34 shows a photomicrograph of the Faselec circuit MB 9B. The chip measures 1.8 x 2.76 mm and contains approximately 400 active elements. About # of the chip area is occupied by the large output drivers for the motor and the alarm that can clearly be seen at the bottom and the right hand side of the chip. The current consumption of this circuit is typically 30 @, determined largely by the oscillator and the first few divider stages. For clock application, this current consumption is low enough to ensure a battery life of more than a year. For wristwatch applications, the current consumption has to be reduced by more than an order of magnitude to ensure adequate battery life. Figure 35 shows a block diagram of a typical integrated circuit for an analog wristwatch-the MB 4B manufactured by Faselec Corp. The circuit

228

A.

P. GNADINGER

FIG.34. Photomicrograph of the 4 MHz clock circuit MB 9B. Courtesy of Faselec Corp., Zurich, Switzerland.

architecture is similar to that of Fig. 33 but the circuit is now optimized for minimum power consumption. The oscillating frequency of the quartzcrystal-controlled oscillator is 32 kHz. The oscillator is amplitude regulated. This complicates the circuit design considerably but ensures minimum power consumption of the oscillator. One capacitance of the Pierce-type oscillator is integrated on the chip itself; the second one-a variable trimmer capacitor-is connected externally. The current consumption of this circuit is typically 0.6 @, ensuring a battery life of at least two years. A photomicrograph of the circuit MB 4B is shown in Fig. 36. The chip measures 1.7 x 2.0 mm and contains about 400 active elements. As an example of a digital watch circuit, a block diagram of the Faselec circuit MJ l l is shown in Fig. 37. This circuit is a single-chip silicon gate CMOS watch circuit designed to drive a six-digit in-line LCD. It incorporates six functions: hours, minutes, seconds, date, month, and weekdays. The oscillator circuit is basically identical to the concept shown in Fig. 11 with one variable capacitance integrated on the chip itself. The oscillation frequency is 32 kHz. The output signal of the oscillator is fed to a divider chain made up of static cells as described in Section IV,B,1 and di-

ELECTRONIC WATCHES AND CLOCKS

229

FIG.35. Block diagram of 32 kHz watch circuit MB 4B. Courtesy of Faselec C o p . Zurich, Switzerland.

FIG.36. Photomicrograph of the 32 kHz watch circuit MB 4B. Courtesy of Faselec Corp., Zurich, Switzerland.

0sc.h

O~C.OU1

I ATST

DISPLAY MODES

/

\

/Min/Sec/Weekday

--Vp

/M inlDateNVeekday

12 hour or 24 hour display operation

FIG.37. Block diagram of six digit/six function digital watch circuit MJ 1 1 . Courtesy of Faselec Corp., Zurich, Switzerland.

ELECTRONIC WATCHES AND CLOCKS

23 1

vided down t o a 1 Hz signal in a fashion similar to analog watch circuits. The 1 H z signal, however, is now fed to various counters, where the minutes, hours, weekday, date, and month information is generated. The variable length of the months is thereby properly accounted for so that the watch has to be reset only once every four years, during a leap year. The outputs of these various counters are connected to the decoders and driving stages as described in Section IV,B,2, which in turn drive the various segments of the LCD. A bonding option (shown on the right-hand side of Fig. 37) allows the selection of a 12- or 24-hour display mode. The circuit operates with a supply voltage of nominal 1.5 V generated from a battery connected between pins Vp and VL. The LCD requires a higher operating voltage of typically 3 V as described before. This voltage is generated by a voltage doubler (Fig. 31), which needs two external capacitors C2 and C3. The 512 H z input signal of the voltage doubler is deduced from the divider chain. To provide for readability of the watch in the dark, a backlight is provided that is connected to the 1.5 V battery through switch B. The backlight is simply a miniaturized incandescent light bulb mounted at the side of the display. Illumination and operation controls are accomplished by two singlepole single-throw switches A and B. The operation diagram is shown in Fig. 38. Switch A determines what will be displayed, whereas B is used for setting and illumination. If A and B are pressed at the same time, the setting modes are called up. Both inputs have an internal pulldown, which allows these pins to float during normal operation. The watch will start (after power up o r test reset) by displaying hours/minutes/seconds and weekday with the colon continuously on as shown in Fig. 38. Pressing and releasing switch A will change the display to hours/minutes/date and weekday with the colon flashing at a 1 Hz rate. Pressing and releasing switch A again will change the display back to the original information. By pressing switches A and B simultaneously, the circuit enters the set mode. First, minutes and seconds are displayed. If B is pressed, the seconds counter will be reset to zero, the minutes counter will advance by one or will remain unchanged, depending on whether the seconds count was greater or less than 30 sec at the time B was pressed. The seconds counter will immediately resume operation after reset. This feature greatly simplifies accurate setting of the watch for the user, since the timing error will rarely be more than 30 seconds. Pressing and releasing A again will call up the next set mode. The display shows minutes and the colon flashing. Pressing B will advance the minutes at a 2 Hz rate. At the same time, the seconds counter is reset to zero and the watch stops timekeeping operation. This is indicated by the colon being continuously on.

232

A. B Watch starts atter itOD1

P. GNADINGER

4H H . M M S A'I

&r )' ~

I

Display modes

A.B I A and B pressed ar the =me time1

Error mun be less then 2 30 seconds.)

Setmodes

< +

B I S 1weekday1

nB lSet date1

-.("?"I-

B (Set month1

FIG.38. Operation diagram of the six digit/six function digital watch circuit MJ 1 1 . T = Timer reset to display mode 10-20 seconds after the release of switch A or B (only if the watch was not stopped by setting the minutes). Courtesy of Faselec Corp., Zurich, Switzerland.

Pressing and releasing A again will call up the third set mode. The display shows hours and an A or P respectively at the position of unit minutes to indicate AM or PM. The colon is flashing or on, depending on whether the watch was stopped or not in the minutes set mode. B will again advance hours at a 2 Hz rate. In the same manner the weekday, the date, and the month information can be set. In the date-set mode the date counter counts independently of the month information to 3 1. In all set modes, timekeeping is unchanged as long as B is not used. Using B,each counter is set separately and no carry signals from and to other counters are accepted or generated. In all set modes, a timer reset signal is generated 10-20 sec after releasing A or B (unless the watch was stopped in the minutes-set mode), which will automatically return the watch into the display mode hours/minutes/seconds. Referring back to Fig. 37, a test input (TST) is furnished to facilitate high-speed testing of the circuit by short circuiting part of the divider chain in a similar fashion as described for analog watch circuits. A test

ELECTRONIC WATCHES AND CLOCKS

233

FIG. 39. Photomicrograph of the digital watch circuit MJ 11. Courtesy of Faselec Corp., Zurich, Switzerland.

reset input (TR) resets the circuit in a defined state: January 1, 1:OO (AM), 00 sec for the 12-hour operation and 0:OO ( A M ) for the 24-hour operation. Figure 39 shows a photomicrograph of this circuit. The chip measures 3.6 x 3.9 mm and contains roughly 3000 active elements. Because a nonmultiplexed display is used, the total number of bonding pads is fairly large, 58 in this example. Compared to an analog watch circuit as shown in Figs. 34 and 36, the complexity of this circuit is considerably larger. This is mainly due to the increased demand on control circuitry, additional counters, and the considerably more complex decoding and driving circuitry. The total current consumption of the MJ 11 circuit is typically less than 1.5 p4, which guarantees a battery life of at least two years provided the backlight is not operated too often. C . Manufacturing Technologies

The manufacturing technologies chosen to realize the integrated circuits described in the previous chapters have to satisfy certain requirements that are unique for watch and clock circuits. As mentioned earlier, the overriding and most important requirement put on the technology is

234

A.

P. GNADINGER

minimum power consumption, since it determines to a large degree the life expectancy of the battery (at least for analog watches and digital watches with LCDs where the display requires only little power). The second requirement put on a watch circuit technology is low-voltage operation. Watch batteries have typically 1.35 or 1.5 V nominal voltages, so that watch circuits should still operate satisfactorily with minimum voltages of about 1.1 V. Third, a watch circuit technology should be capable of large-scale integration. The most complex circuits such as circuits for digital watches with stop watch and alarm functions contain up to 10,000 individual active components with the corresponding interconnections. Since the major part of such a circuit consists of random logic, the interconnections require a considerable amount of chip area. These circuits can be as large as 20 mm2 or more. Considering these rather severe requirements, only a few of the integrated-circuit technologies developed during the last 10- 15 years qualify for watch circuit applications. In Table I1 some of the technologies are listed that have been developed for these purposes. The first technology in this list is a special bipolar technology optimized for low current consumption (47). This is accomplished by replacing the collector load resistors by current sources implemented as lateral p-n-p transistors. This technology is capable of medium-scale integration (up to a few hundred active components); it can be used for 32 kHz oscillator circuits and it is most suited for watches of the first, second, and third generation (analog display). Its power consumption is rather high, as is typical for any bipolar technology at these low frequencies. With a battery voltage of 1.3 V, the current drawn is approximately 20 nA/kHz for one divider stage. For a typical watch circuit (47) this corresponds to about 10 pA total current consumption. A more recent bipolar technology that is well suited for digital watch circuits intended to drive LED displays is the integrated injection logic ( P L ) technology invented in 1972 (48-50). As already mentioned in Section IV,B, 12Loffers the big advantage that the segment and digit drivers can be integrated on the main integrated circuit. The current consumption, however, is still rather high, typically 15 nA/KHz per divider stage. Recently, an 12L watch circuit with a considerably reduced current consumption has been described (40) where special techniques such as current "starving" have been used to reduce power consumption. With the display off, this circuit draws only an average of 7 pA and will operate correctly to below 5 p A over the temperature range. However, this performance has to be bought by rather tight processing requirements and dense design rules. The more modern technologies that are used for nearly all of the

TABLE I1

INTEGRATED CIRCUITTECHNOLOGIES Degree of integration"

Current consumption for one static fiequency divider stage

Preferred display

Oscillator frequency

Watch generation

Technology

Subgroup

SSI ~400 gates MSI s1OOO gates

=20 nA/kHz

Mechanical

5 3 2 kHz

( I -3)

Bipolar

Standard (micropower) IfL

-25 nA/kHz

LED

5 3 2 kHz

(41

Metal-gate Silicon-gate Silicon on sapphire (SOS)

LSI c5OOO gates MSI 5 IOOO gates

-0.1 nA/kHz -0.4 nA/kHz 4 . 2 nA/kHz

Mechanical LCD

s l MHz 5 4 MHz >4 MHZ

(3.4) (3,4)

CMOS

~~~~

~

~

LSI, Large scale integration; MSI,Medium scale integration; SSI, Small scale integration.

236

A.

P. GNADINGER

present watch and clock circuits are the complementary MOS technologies (CMOS). Of the many subgroups of CMOS technologies, three variations are listed in Table I1 that are most widely used: metal-gate, silicon-gate, and silicon on sapphire (SOS) technology. Before going into a detailed description, some common features of all three variations are described. All three CMOS technologies are well suited for medium- or largescale integration and are therefore applicable for analog and digital watches. They require considerably less power than any of the bipolar technologies. The extraordinary potential of CMOS technology for micropower applications was pointed out as early as 1963 (51). The fundamental difference from bipolar circuits lies in the fact that the current consumption is largely dynamic, being proportional to the number of switching operations, that is, proportional to the operating frequency f. The basic element of any CMOS logic gate is the inverter shown in Fig. 40. Its power consumption consists of three parts: If the inverter rests in one of its logic states, basically no connecting path exists between the positive and negative pole of the power supply and only a very small leakage current ILis flowing through the blocked transistors. If the inverter changes its logic states, the two transistors are both conducting during a short time and a current can flow. This current IT is also dependent on the supply voltage VDDand the shape of the input and output signal. The third contribution to the total current is the current through the output impedance I c . Since MOS circuits have nearly exclusively capacitive loads, it is easy to see that this current I c is proportional to the number of switching operations, that is, the frequency f a n d also to the supply voltage V D D to which the capacitance Cis being charged. This third VDD

P

i FIG.40. CMOS inverter.

ELECTRONIC WATCHES AND CLOCKS

237

component is now by far the dominating contribution provided that the switching time is small compared to the repetition period l/ft so that the power consumption of the inverter in Fig. 40 can be approximated by

P = fCVBI, independently of the transistor device parameters. It has been shown (52) that this remains a good approximation even if the input signal has a finite rise time. The power relation (16) can be extended to a frequency divider stage as described in Section IV,B,l. Assuming a binary divider for simplicity, we obtain a power consumption of wherefis the input frequency and C an appropriately weighted sum of the circuit capacitances. Equation (17) shows that the power consumption of an infinitely long divider chain will at most be twice that of the first stage. This is an important result, indicating that the power consumption of a watch circuit will largely be determined by the first stages of the divider chain (apart from the oscillator). The rest of the circuit that can occupy the major part of an integrated watch circuit in the case of a digital watch will contribute only a small part to the total current consumption since it operates at a very low frequency. This would not be the case in bipolar technologies, where all the gates will contribute about equally to the current consumption. A comparison of the bipolar and CMOS technologies listed in Table I1 is again given in Fig. 41, where the speed power product is plotted as a function of frequency. For the bipolar technologies, the power consumption is nearly constant over a wide range of frequencies. Only at frequencies above a few MHz can the influence of a capacitive current be seen. For the CMOS technologies, the above-mentioned proportional increase of power with frequency can clearly be seen. IzL seems to be more favorable at higher frequencies than CMOS but as mentioned before we have to keep in mind that most of the watch circuit operates at low to very low frequency, where any of the CMOS technologies is far superior. The requirement of low operating voltages (1.1 - 1.5 V) has made the industrial realization of watch and clock circuits in CMOS technology very difficult and delayed the introduction of these technologies considerably. The threshold voltages of the p- as well as the n-channel transistors must obviously be well below the supply voltage. The problems that had to be overcome were therefore the reproducible fabrication of weakly doped ( 1 8 x 1015atoms/cm2) wells in a silicon substrate of opposite conductivity type, the realization of clean gate oxides, the control of the

A.

238

I

10

P. GNADINGER

100

1000

FREQUENCY (kHz1

FIG. 41. Speed-power product as a function of frequency for the five technologies listed in Table 11. '

silicon-oxide interfaces, as well as the stability of the devices. All this had to be realized in a production environment. The first laboratory models of CMOS watch circuits were already made in the early 1960s by the pioneering work of the Centre Electronique Horloget- (6). However, the industrial realization only started some ten years later. It is fair to say that the main obstacle, the realization of controlled weakly doped wells, had to await the introduction of ion implantation techniques (53)into production as replacement for the diffusion technology. This was accomplished in the early 1970s. The three CMOS technologies listed in Table I1 -especially the silicon-gate technology-are now described in somewhat more detail. 1. Silicon-Gate Technology

As mentioned before, the most successful and best suited technology for watch and clock circuit applications is the silicon-gate CMOS technology. Silicon-gate technology was first described by Sarace ct NI. (23) and Faggin and Klein ( 5 4 , 5 5 )for single-channel MOS and combined with the complementary principle in 1971 to form silicon-gate CMOS (56). The first silicon-gate CMOS technology, however, was not suited for watch circuit applications since the threshold voltages were in the range of 1.0-1.5 V, requiring a power supply of more than 3 V.

ELECTRONIC WATCHES AND CLOCKS

239

A silicon-gate CMOS technology suited for watch circuit applications by controlling the threshold voltages to values of approximately 0.5 V was first described in 1972 by Vittoz ef al. (36). In order to describe the silicon-gate CMOS process in detail, a CMOS inverter (Fig. 40)-the basic building block of any watch circuit-is used as an example. Figure 42 (56a) shows a crosssection and Fig. 43 a scanning electron microscope (SEM) photograph of such an inverter. The starting material is a single crystal silicon wafer with (100) orientation and a uniform n-type background doping of about 2 x l O I 5 atoms/cm2. The right-hand part of Fig. 42 and the upper part of Fig. 43c show the p-channel transistor situated in the n-type substrate. It contains the p+-doped source and drain regions forming p+n diodes with a junction depth of typically 1 pm. The gate electrode is made out of polycrystalline silicon, approximately 0.5 pm thick and also doped p+. It is separated from the single-crystal substrate by the gate oxide, which is formed by a thin layer (-700 A) of thermal SiOz. This oxide is an integral part of the active p-channel transistor. By applying a negative voltage of sufficient magnitude (larger than the threshold voltage), the silicon surface between source and drain is inverted and transistor action can take place. The left-hand part of Fig. 42 and the lower part of Fig. 43c show the n-channel transistor situated in a well weakly doped p-type, typically 5-6 pm deep. The source and drain areas are now heavily doped n-type, forming n+pjunctions approximately 1 pm deep. The polycrystalline gate electrode is now n+ doped-the same polarity as source and drain. It is again separated from the channel area by the thin gate oxide. By applying a positive voltage of sufficient magnitude (larger than the threshold voltage), the silicon surface between source and drain is inverted and the

nGHA"EL-TRANSISTOR p-CHANNELTRANSISTOR SOURCE DRAIN

a b c

d

DRAIN

c f

SOURCE

B

FIG.42. Cross section through a CMOS-inverter in silicon-gate technology. a, n substrate; b, p well; c , metal interconnection: d, polysilicon gates; e , field oxide; f, intermediate oxide; g. gate oxide; \ \ \, n-doped; / / /, p-doped silicon. After Liischerera/. (56a) reprinted with permission.

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A. P. GNADINGER

FIG.43. CMOS inverter in silicon-gate technology. (a) Electrical symbol. (b) Electrical . Luscher er a / . (56a), reprinted with circuit diagram. (c) SEM photomicrograph, 6 0 0 ~After permission.

n-channel transistor turns on. The drains of the p- and n-channel transistors are connected with a short metal line. It is necessary to look briefly at the basic equations governing the operation of the MOS transistor in the view of low-voltage operation. The fundamental parameter of the MOS transistor VTn is dependent on the processing parameters as follows (57):

VTn =

4MS

+

2+Fp

-

+

Qss

QB

C O

where 4MS is the polysilicon -semiconductor work function difference, +m the Fermi potential for holes, Q B the bulk charge density, and Qss the charge density at the SiOz-Si interface. C o is the capacitance of the gate oxide per unit area, given by co =

€,/to

(19)

where e0 is the dielectric constant of the gate oxide and c, the oxide thickness. Both #Fp and QBare dependent on the surface concentration of the p well: $FP

= ( k T / q ) In(NA/ni)

(20)

QB

= -[2Es4NA(2&p)]1’2

(21)

ELECTRONIC WATCHES AND CLOCKS

24 1

where N A is the effective surface concentration of the acceptors in the p well, es the dielectric constant of silicon, and q the electronic charge. For the p-channel transistor, the above equations remain essentially the same with the exception of substituting N Aby N D ,the effective donor concentration at the surface of the n substrate, and appropriate changes in signs. To achieve low threshold voltages, it is advantageous to use as thin a gate oxide as possible. Typical values are around 600 A. Qss-the fixed charge at the Si-SiOz interface-has to be kept as low as possible. With (100) orientation of the substrate, Q s s is normally 5 x 1O1O cmb2 with a variation of about _+2 x 1 O l o cm-2. Adjustment of QB is then made to obtain the desired threshold voltage of typically 0.5 5 0.1 V for both types of transistors. It is advantageous to have a p-doped silicon gate for the p-channel and an n-doped silicon gate for the n-channel device. The doping levels required under these circumstances are N D = 1 x 10*scm-2 for the p-channel and N A 2 x 10l8cm-2 for the n-channel device. Early CMOS technologies had severe problems with control of both Qss and QB. Q s s came under control with improvements in processing techniques, clean oxide growth, and control of annealing. The control over the low surface concentration required in the p wells caused severe problems that could only be overcome with the introduction of ion implantation techniques (53). If the polysilicon gates are to be uniformly doped (e.g., n+ type), a special threshold adjust implantation through the gate oxide is necessary in order to compensate €or the 1 V work function difference between n+ poly and n substrate. Such an additional implantation may, however, be justified due to the increase in packing density, since the metal bridge short-circuiting the n+p+ polysilicon diodes can be deleted. These metal bridges can clearly be seen in Fig. 43c. With the use of fairly low-doped material, parasitic threshold voltages in the field oxide regions may become a problem. However, since modern LCDs require only voltages up to 3 V (see Section IV,D), parasitic threshold voltages of 5 V are, in most cases, sufficient. Channel stopper or guard ring diffusions as they are usually applied in standard CMOS technologies for nonwatch applications are therefore not necessary. The major processing steps necessary to fabricate a CMOS silicongate watch circuit are now briefly described. First, the silicon wafer is oxidized and the information regarding the p wells transferred from a photomask to the wafer by standard photolithographic techniques (58). This first window is etched into the oxide and the whole wafer implanted with boron ions, the remaining oxide acting as a mask and preventing implantation outside the p-well regions. The wafer is then subjected to a high-temperature step 1 15OOC) driving the boron to 2 :

(2

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P. GNADINGER

the required depth. After that, the field oxide is formed in a second thermal oxidation step and the active regions of the transistors are etched out of this field oxide requiring a second photolithographic step. The photomask containing the pattern information has to be aligned to the p well very accurately. The gate oxide is then grown and the whole wafer covered with a layer of undoped polycrystalline silicon. The most common method for producing this layer is by a low-pressure chemical vapor deposition (CVD) reaction in a hot-wall furnace tube (59) with SiH4 as a source. The next photolithographic step, again requiring exact alignment of the appropriate photomask, defines the polysilicon runners that serve as gates as well as the first level of interconnections. The gate, source, and drain regions are now doped n+ or p+, separately for the n-channel and p-channel devices, requiring in general one or two additional masking steps. The doping sources can be gaseous, doped oxides, or ion implantation. As a next step, the intermediate oxide is deposited onto the wafer-again employing a chemical vapor deposition-and contact hoies etched through this layer where contacts to source, drain, or gates are intended. The whole wafer is then covered with a metal layer, preferably aluminum. This can be accomplished by evaporation, sputtering, or any other convenient means (60). The next masking step defines the metal interconnections. As a protection against mechanical and chemical attack, the wafer is covered with a layer of silicondioxide or silicon nitride in a low-temperature process and via holes etched to the bonding pads. The wafers are finally subjected to an annealing treatment in hydrogen, which serves to alloy the metal-silicon contacts and reduces the Si-Si02 interface states as well as the radiation damage that may have been introduced during metalization. The finished wafers are then tested, separated from each other, and mounted on suitable substrates. The packaging technology for watch circuits are covered in more detail in a subsequent section.

2 . Silicon-on-Sapphire (SOS) Technology An integrated-circuit technology using monocrystalline silicon films on a sapphire substrate was proposed about ten years ago (61). For some circuit applications, this technique has found industrial applications, especially where high speed and low power are important ( 6 2 , 6 3 ) . At first sight, SOS technology seems very attractive for watch circuit applications as well, particularly if it is combined with complementary MOS technology. SOS would offer a strongly reduced power consumption for a given

ELECTRONIC WATCHES AND CLOCKS

243

frequency or allow higher frequency operation of a watch circuit at given current drain level. This is due to the fact that source and drain regions have very little diffused capacitance associated with them. The silicon islands are grown on the sapphire substrate-an insulator-where no depletion regions can form that would contribute to the capacitance. A second advantage of SOS technology is the absence of parasitic transistor effects, since the silicon islands are separated from each other by an insulator. The performance advantages of combining CMOS transistors with SOS technology were first discussed by BoIeky (64).The original process technology used to fabricate CMOS/SOS circuits involved only one epitaxial silicon layer and contained p-channel deep depletion devices (65)as well as aluminum gates. The resulting threshold voltages were extremely low, making the technology well suited for watch circuit applications. However, a fundamental problem associated with this SOS technology, the inability to control the leakage currents of the p-deep-depletion transistors, made this process impractical. An improvement had been made in this respect by the introduction of the double epitaxial aluminum gate process (64), and the double epitaxial, self-aligned polysilicon gate process (66).These processes, however, are not suited for watch circuit applications because they lead to higher threshold voltages. A controllable process with low enough threshold voltages for watch circuit applications can be accomplished by incorporating n layers and p+-doped polysilicon, as demonstrated by Ipri and Sarace (10).It is supenor to the original technology with deep-depletion p-MOS transistors because only a small fraction of the n-silicon films is electrically conducting and the leakage problem is thereby reduced. Figure 44 shows a cross section through such a CMOS/SOS inverter as described by Ipri and Sarace (10). It combines the simplicity of the deep-depletion approach and the shift in n- and p-channel threshold voltages resulting from an all p+silicon-gate structure. The deep-depletion n-channel device is made from n-epitaxial silicon, source-drain areas are n+ and the gate is p+ polysilicon. The p-channel device is a standard enhancement-type PMOS structure. The processing sequence for the structure shown in Fig. 44 can have several forms. In this particular example, the polysilicon layer is uniformly doped p+ from a boron glass source. After patterning of the polysilicon gates and the interconnections, source and drain areas of the p- and n-channel devices are simultaneously doped from phosphorous (n+) and boron (p+)doped oxides. Care has to be taken that the n+ concentration is low enough to not overcompensate the p+ polysilicon on the n-channel device. By proper choice of the thickness and carrier concentration in the

A. P. GNADINGER

244

Silicon Epitaxy

Masking Oxide

I = j (?-<,

Island Definition

n-

Channel

n-

Oxidation

P+ doped oxide

Poly-Silicon

Gate Definition

x

doped Poly-Si

/ Poly-SI p
k-,

n i d o p e d oxide

Channel Definition

and Source

-

Drain

Diffusions Ahimi nu m

Contact Windows and Metalization

n

-

CHANNEL

TRANSISTOR

p

-

CHANNEL

T R ANSI STO R

FIG. 44. Process sequence of p+-polysilicon-gate, deep-depletion CMOS/SOS process.

ELECTRONIC WATCHES AND CLOCKS

245

n-epitaxial film, threshold voltages for p- and n-channel transistors of 0.3-0.5 V can be achieved. A typical analog watch circuit based on the above technology promises to have a much lower current consumption at a given oscillator frequency compared to the equivalent circuit in bulk silicon-gate CMOS technology. This theoretical expectance has also been indicated in Table 11. However, as reported by Ipri and Sarace (101, the actually measured currents in both technologies are about equal. This rather disappointing result is caused by the residual leakage current problem that still exists in SOS even in its most improved version. Furthermore, due to the special nature of a watch circuit, where most of the gates operate at a very low frequency, these leakage currents can easily ruin the advantage gained in the high-frequency oscillator and divider part of the circuit. It is therefore questionable whether SOS will gain ground as a manufacturing technology for watch circuits. It seems that bulk silicon-gate technology with its much lower cost and about equal technical performance will dominate for a long time to come. However, if SOS became a successful technology for such high-volume parts as memories (62) and microprocessors (63), the price of the substrates would eventually come down and SOS might become cost competitive with bulk CMOS. However, such a development is not in sight at the time of this writing. For some very special applications, such as very high-frequency (>4 MHz) wristwatch applications, where high manufacturing costs are unimportant, CMOS/SOS might even today be a good choice, because in those cases the better high-frequenc y performance of SOS might outweigh the higher cost and the inferior performance of the low-frequency part of the circuit. 3 . Metal-Gate C M O S Technology

The original approach to the monolithic fabrication of CMOS circuits as pioneered by RCA and others (67-69), has been closely related to the standard p-channel technology that was in use at that time. Its main characteristic was the use of a metal gate, mostly aluminum, where source and drain regions were not self-aligned. This technology was, however, not suited for watch circuit application, because the threshold voltages of the p-channel device could not be made low enough to be compatible with the low-voltage requirements in electronic timepiece applications. The desired p-channel threshold voltage of -0.5 V can, in principle, be obtained by employing a metal gate with a more favorable work function difference such as molybdenum (67) or a gate insulator such as

246

A. P. GNADINGER

Si02-A1203(70), which has a favorable insulator-insulator interface barrier (71). The best approach to lower the p-channel threshold voltage, however, and the only approach that has been successful in production, is by way of ion implantation, where a light dose of boron ions is implanted into the channel region after the gate oxide is grown (72). If this implantation is shallow enough, the effect is very nearly just a threshold voltage shift with no change in the effective substrate doping. The ion implantation is then nearly indistinguishable from a negative oxide charge. The n-channel threshold voltage can be adjusted by the doping level in the p well as described in the previous section covering the silicon-gate CMOS technology. Again, to obtain adequate control over the n-channel threshold voltages, ion implantation technology is the only viable production process (53). A metal-gate CMOS process that is optimized for watch circuit application by use of ion implantation technology to set both p- and n-channel threshold voltages has been described by Coppen et al. (73). Figure 45 shows a cross section through a CMOS inverter made in this aluminum gate technology. The use of ion implantation to lower the p-channel threshold voltages has several advantages. First of all, no changes in the conventional AI-Si02 gate structure are necessary. The p-channel threshold voltage adjust implantation can be done most conveniently before the contact window cut by protecting the n-channel side with a photoresist layer and using the reversal of the p-well mask. The complexity added to the process is therefore quite small. Finally, the threshold voltage shift is continuously variable, being about 0.5 V/10l1ions/cm2 and can easily be adjusted to compensate for changes elsewhere in the process, for example,

111 1

'

ELECTRONIC WATCHES AND CLOCKS

247

variations in Q s s . An extensive description of this process is given in Copper et al. (7.3) and is not repeated here. The advantages of the metal-gate CMOS process compared to the silicon-gate and SOS processes described before are its simplicity and its maturity, being just a derivative of the well established general-purpose CMOS process described in White and Cricchi (69), which has been in production for more than 10 years. Its main disadvantage is its higher current consumption due to the larger overlap capacitances of the gate metal over the diffused regions. This last feature goes directly against the general trend toward lower current consumption and increased battery life in an electronic watch. 4. Packaging Technology

After functional testing of the watch circuits in wafer form, the individual circuits are separated from each other by either scribe and brake or by sawing them apart. The individual circuits have then to be put in a suitable package so that they can be mounted in the watch module. Clock circuits are nearly always packaged in a dual in-line package (DIP) with a plastic envelope as shown in Fig. 46a. This form of packaging is standard for many types of integrated circuits. It is inexpensive with proven reliability and can be done in highly mechanized production lines. Its main disadvantage is its large size. For clock applications, this limitation can, however, be tolerated in most cases. For wristwatch circuits, a DIP package would be too bulky. Here, two forms of packaging have become standard in recent years: For analog watch circuits where between 8 and 12 external leads are required, a special miniaturized plastic package has been developed (74) that uses a technology similar to the familiar DIP-package but measures only about 4 x 5 mm for an eight-lead circuit. The watch chip is glued or soldered onto a metallic lead frame, the pads of the circuit are bonded by a thin gold or aluminum wire to the external leads, the circuit is enclosed with a plastic, usually an epoxy resin by an injection molding process, and the outer leads and the individual circuits are separated from each other by a stamping process. An example of a finished SO-8 package is shown in Fig. 46b. For digital watch circuits, where as many as 70 leads have to be bonded, an SO package would become much too bulky and too difficult to manufacture. A new form of packaging digital watch circuits had to be found. The technology that is used most often today is mounting the watch chip directly onto a printed circuit board that serves as a substrate for the whole watch module. The chip is glued onto the printed circuit

248

A. P. GNADINGER

FIG.46. Different forms of packaging watch and clock circuits. (a) Clock circuit packaged in dual in-line package (DIP). (b) Analog wristwatch circuit packaged in miniature package SO-8. (c) Digital wristwatch circuit mounted on printed circuit board.

board, preferably into a recession made by grinding or stamping. The bonding pads of the circuit are connected with the conductor pattern on the PC board by means of ultrasonic bonding employing either a thin gold or aluminum wire. The circuit is then covered by a drop of epoxy resin or by a suitable plastic or metallic cap. This process of mounting the circuit directly onto the printed circuit board is certainly the most popular one today. It is well suited to minimize the required volume. It demands, however, a well-controlled and high-yielding bonding process because of the fairly expensive substrates.

D. Displays An important part of an electronic watch as indicated in Fig. 2-and the most relevant to the user-is the display. It transmits the time information or the additional functions from the watch to the human eye. The analog display with a watch face and moving hands is the one that has dominated for centuries and will certainly coexist with other types of displays in the future. The fastest moving hand-usually the second hand-is driven by a

ELECTRONIC WATCHES AND CLOCKS

249

stepping motor as already described in Section IV,B,2. The minute and hours hand as well as any additional display functions such as the date, are then coupled in turn to the second hand via appropriate mechanical gear trains. Of course, this type of mechanical display can be manufactured in all sizes and shapes. This might be considered one of the main advantages of the old familiar analog watch display: It allows the analog electronic watch to be designed as a jewel piece-much more so than with digital displays. Digital displays used in electronic watches and clocks use seven independent segments per digit which allows any number from 0 to 9 to be formed. Up to 8 digits are common for a watch display. Additional information such as date and day of the week are formed by alphanumeric electrodes on the display, or by annunciators. The first digit may not need all the segments since it may only have to display the numbers 0, 1 or 2. An example of a seven segment display with six digits is shown in Fig. 47. For digital watches-at the time of this writing-two types of displays are the most common: light-emitting diodes (LED) and liquidcrystal displays (LCD). LED displays were predominant in the electronic wristwatches that reached the market in the early 1970s (75, 76). Their color is a bright red or yellow. They turn on and off in tens to hundreds of nanoseconds and exhibit an excellent discrimination ratio, making them easy to multiplex. The interconnect problem is thus reduced considerably. LEDs have reached a high degree of perfection, mostly due to the development effort invested in electronic calculators and instrumentation display. Their big drawback is the fact that they require a very large driving current of the order of milliamperes. No continuous display is possible under thesecircumstances and the electronic watch will show the time only on pressing a push button. The battery life, therefore, depends on how many times the reading push button is pressed. The driving voltage for LED displays is around 3 V. That means that two batteries have to be provided. Voltage doubler circuits as described in Section IV,B,c (Fig. 31) cannot be used with LED displays because of their high internal impedance. The liquid-crystal display (LCD) is now predominant for digital wristwatches. It consumes very little power-of the order of microwatts-

FIG.47. Seven segment display with six digits for digital wristwatch.

250

A.

P. GNADINGER

so that it can be on continuously. Liquid crystal displays are passive displays requiring an external source of illumination, normally the ambient light. To make them also readable in the dark, an internal light source is usually provided, in most cases an incandescent light bulb that is activated on pressing a push button. More recently, light sources that do not drain power from a battery were introduced. These so-called “betalights” are based on the radioactive decay of tritium in combination with a luminescent phosphorus. However, in certain countries the use of this radioactive material is not permitted restricting the application of this power-saving light source considerably. The physics of liquid crystals and liquid-crystal display technology has been covered extensively in the literature (77-79). The LCDs going into electronic watches today are of the twisted, nematic, field effect type. They sandwich the liquid-crystal substance between front and back plates of thin glass, which are sealed together with plastic or glass. On the inner side of the glass plates are transparent conductor patterns, formed by photolithographic techniques into the desired segments and characters to be displayed. The conductor patterns are coated with a special chemical film that aligns the liquid-crystal molecules. Polarizers are laminated to the outside of the glass plates with their polarizing axis perpendicular to each other, so that without the liquid crystal present, light would be blocked. The surface characteristics of the alignment film on the conductor pattern now causes a 90” twist to the liquid crystal molecules and their axes align parallel to the polarizer axes of the front and rear polarizers, respectively, so that the display now passes light. If a voltage is applied to the conductor pattern with respect to the back plane, the liquid-crystal molecules are aligned parallel to themselves making those under the influence of the field perpendicular to the rear polarizer axis. These energized molecules now block the light, causing dark images in the shape of the conductor patterns to appear on a light background. Initially, there were many problems associated with LCDs, such as poor reliability, inadequate contrast ratio and viewing angle, and strong sensitivity to temperature and humidity variations. However, in recent years, considerable improvements have been achieved, so that today’s displays can be considered mature enough for applications in electronic watches. One problem that still awaits a solution is how LCDs can be multiplexed. This question has already been discussed in Section IV,B,b and has been covered in the literature (80-82). Multiplexing would greatly reduce the problems and costs of interconnecting the many pins of the circuit to the conductor pattern on the printed-circuit board. However, it

ELECTRONIC WATCHES AND CLOCKS

25 I

seems that LCDs in a multiplexed mode will always have poorer contrast ratios, smaller viewing angles, and an increase of turn-off time resulting in image smear than nonmultiplex displays, so that there will be a trade-off between cost and performance. Also, such nontechnical considerations as user acceptance of watches with more than six digits will influence the effort in developing multiplexed LCDs. As mentioned before, multiplexing is most important for displays with more than about six digits. For clock applications, displays with large-size characters are desired. Here, standard LCDs are not well suited because of increased difficulties .in manufacture of scaled-up versions and the rather low light intensity available from an LCD. A noteworthy recent development seems very promising for digital clocks-the FLAD, a fluorescent-activated display (83).It has the same low power dissipation as an LCD but a light intensity that is much stronger than that of an LED display. Basically, a FLAD is a liquid-crystal display with a thin plexiglass panel doped with organic fluorescent molecules behind the back plate of the LCD. Ambient light entering the plexiglass panel excites the molecules and the resulting fluorescent light is emitted from the segments of which the display digits consist. The LCD in front of the plexiglass panel acts as a valve and passes or blocks the emitted light, depending on whether a voltage is applied to the segments or not. Newer types of digital displays such as electrochromic (84)or electrophoretic (85) displays are still in the research phase and have not found practical applications in electronic clocks or watches yet.

E. Power Supplies Referring to Fig. 2, where the block diagram of an electronic watch or clock is presented, the last principal part -the energy source-is now treated. It is an extremely vital part of any electronic watch or clock and as mentioned before has probably the most potential of improvement. It is, however, only covered very briefly here. Readers who would like to study this specialized field in more detail should consult the vast literature (86 -88). As mentioned briefly in Section IV,B, the majority of all clocks and watches are driven by primary cells. Rechargeable or secondary batteries have only been used in special cases, most often in conjunction with solar cells. The reason is that their life expectancy is not much larger than that of a primary battery at the present time. For clock applications, volume restrictions are not as severe as for wristwatches. Clocks are therefore operated in most cases by standard

252

A.

P. GNADINGER

dry batteries. Although the Leclanche cell celebrated its one-hundredth anniversary in 1966, it is still the main commercial battery cell and the least expensive of the battery systems. It is primarily a MnO, cell using a starch separator, NH4CI electrolyte, and a zinc can. Newer developments replace the natural MnO, ore by EMD (electrolytic manganese dioxide). These cells have a discharge capacity of two to five times greater than that of the regular cells (89). The starch paste separator is often replaced by a coated separator liner and the electrolyte can also be based on ZnCI, with some NH4CI. All these cells are, of course, not specifically developed for clock applications. They are produced in large quantities for generalpurpose use, representing a worldwide market of roughly 1.4 billion dollars in 1977. For wristwatches, the size of a battery is of primary importance. For this application, a miniaturized construction concept is essential. Most electronic wristwatches produced at this time use a mercury cell as introduced in the 1940s. Of course, many new sizes have since been developed with the emphasis on as small a volume as possible while providing an acceptable capacity. The mercury cell discharges at a nearly constant voltage of 1.35 V. The reaction proceeds through a soluble intermediate (90): HgO

+ HZO

-+

Hg(OH)*

Hg(OH)z + 2e-+ Hg

+ 2(OH)-

For environmental reasons, it is desirable to replace mercury by a less polluting material. Hence, primary cells where Ag,O is used instead of HgO in the cathode have become popular. The cell design is thereby essentially unchanged (88). This cell discharges at a constant 1.65-1.5 V, depending on current drain. The capacity of silver oxide cells can nearly be doubled by employing divalent silver oxide (Ago). However, Ago is metastable and should, thermodynamically, spontaneously decompose with oxygen evolution. Considerable effort has been expended to render Ago stable for use in sealed miniature cells. This effort was consummated in 1976, when divalent silver cells were introduced. Cells being marketed contain both Ago, and Ago and provide about a 20% increase in capacity over monovalent Ag-Zn cells. The goal to achieve long shelf life for primary cells in wristwatches can only marginally be reached by any system that uses a wet electrolyte. The interest in solid electrolytes for batteries to be used in wristwatches is therefore obvious. The best candidates for a solid electrolyte battery are lithium iodide and pAl,O, cell systems (88). They offer a low shelf discharge rate, wide temperature range of operation, absence of leakage, and

ELECTRONIC WATCHES AND CLOCKS

253

ease of miniaturization. Their voltage is higher than that of HgO or Ag,O systems, typically from 1.9 to 3.8 V, depending on the particular combinations. These cells-while being considered very attractive for watch applications-are still in a research or development phase and have not found commercial application yet. An attempt to further increase the ampere-hour capacity of miniature primary cells has been made by Cretzmeyer et al. (91) by reviving the zinc-air cell concept (92). The air access is restricted to the minimum needed to provide the necessary average current of the order of a few microamperes, thereby minimizing the exchange of CO, and water vapor. Air access is limited through the use of very small holes. These cells are claimed to have about twice the ampere-hour capacity of corresponding mercuric oxide-zinc cells, while activated (open) shelf life is quoted to be satisfactory for watch applications.

F. Watch and Clock Modules The components of an electronic watch described in the previous sections are assembled into a so-called watch module. This is the functional block of an electronic watch, which can be mounted into a suitable watch case to form the completed watch. All components except the push buttons needed to set the watch are part of this watch module. Module fabrication is in itself a major part of the watch industry. In fact, most of the watch manufacturers carry out only this operation; they buy the necessary components on the open market-the integrated circuits, for example, from a semiconductor company. Many watch manufacturers, particularly the smaller ones, even buy the completed modules from one of the larger manufacturers and restrict themselves to the assembly of modules into watch cases. Despite the fact that module design and fabrication is a major and important part in the reaIization of electronic clocks and watches, it is covered here only very briefly. Module assembly into finished watches and clocks is not treated at all. The reason is that there is a multitude of constructional aspects of module fabrication, so that a thorough treatment would go far beyond the scope of this chapter, which deals more with the scientific side of the subject. Readers who are particularly interested in the back-end operation of electronic clock and watch manufacture will have to consult the appropriate literature. Modules for analog clocks and wristwatches resemble to a large degree those of mechanical watches, because they still contain the hands and the gear trains. The electronic components-the integrated circuit, the quartz resonator, the trimmer capacitor, and any other external

254

A. P. GNADINGER

capacitors and resistors-are usually mounted on a printed-circuit board as a carrier. This subassembly together with the battery is then combined with the mechanical part, consisting of the stepping motor, the gear train, and the analog display, to form the complete module. Watch modules for digital wristwatches no longer resemble mechanical watch modules, since all moving parts have been eliminated. A printed-circuit board serves as the substrate for all watch components. The integrated-circuit chip is directly mounted onto the board and its connections bonded to the conductors of the board as described in Section IV,C,4. The quartz resonator, the external capacitors, and resistors are soldered to the board as well. The solid-state display is positioned on top of the printed-circuit board and the many connections between the integrated circuit and the display are made by means of the so-called Zebras. This ingenious device consists of an array of conducting and nonconducting elements with a pitch that is equal to or less than the pitch of the conductors either on the printed-circuit board or the display. In this way, connections between display and circuit board can be made regardless of the positional tolerances of the conductors. An exploded view of a digital wristwatch module is shown in Fig. 48, where all essentid components can be seen.

FIG. 48. Exploded view of digital watch module. a, Digital watch circuit on printed-circuit board with quartz and trimmer; b, backplane; c , LCD display; d, module case; e, batteries; f, zebras; g, battery contact.

ELECTRONIC WATCHES AND CLOCKS

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G . Future Trends 1. Autonomy

The dominating trend in the future development of electronic clocks and watches will certainly be toward increased autonomy, since the major drawback of electronic watches with regard to self-winding mechanical watches is the limited life of the battery. One goal that has been set is 10-year autonomy for an electronic wristwatch. This constitutes a goal that should be realizable within a few years with straightforward improvements in circuit design and technology, battery technology, and displays. The most important contribution toward realizing a 10-year watch will probably come from improvements in battery technology. Here, the main efforts will go toward increasing the stored energy density and improving the battery-sealing techniques. HgO batteries will be replaced fairly quickly by Ago or AgzO batteries and newer systems as described in Section IV,E will most likely be introduced soon. There is also quite a good chance that new electrochemical systems that are not obvious at the present time may be discovered and employed in watch batteries. Along with these improvements in battery technology will go further miniaturization that will allow the watch modules to become smaller and more compact and allow the watch designer more freedom in styling. The autonomy of an electronic watch could also be improved by going to secondary batteries that can be recharged by other energy supplies. Watch systems that use solar energy to recharge an accumulator via solar cells have been proposed and have also been developed into commercially available digital watches with LCD displays (93). However, at present, the life of a rechargeable battery is not much longer than that of a primary battery, so that the problem of frequent battery changes remains. It may even be worse because these special cells may not be available as readily as primary batteries. Furthermore, it is well known that the energy available from ambient light may change notably with seasons, latitudes, and dressing habits so that the real autonomy of these watches is questionable. It is the belief of this author that the goal of an autonomy of at least 10 years will be achieved by improving primary batteries rather than by using other forms of power supplies or alternative energy sources. With a given power supply, the autonomy of a watch can also be improved by reducing the power consumption of the other parts of the watch, notably the integrated circuit and the display. Reducing the power consumption of the integrated circuit can either be accomplished by improved circuit techniques or by using more sophisticated manufacturing technologies. It was demonstrated in Section IV,A that more complex os-

256

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cillator designs, particularly with amplitude feedback schemes, can reduce oscillator currents considerably. There is also much room for improvement in developing new frequency divider circuits as described in Section IV,B. On the technological side, the bulk CMOS silicon-gate technology (Section IV,C, I ) will dominate for the foreseeable future. It will certainly be improved by decreasing the dimensions of the elements, which helps to reduce current consumption and also manufacturing costs. An analog watch circuit with a total current consumption of 200 nA has been announced recently (94). This indicates the state of the art at the time of this writing. There is good reason to believe that circuits with even lower current drain can be realized without major changes in the present-day circuit techniques and manufacturing technologies. The type of display used will influence the total current consumption of an electronic watch as well. Watches with LED displays have almost completely disappeared from the market, mainly because of their high power consumption. The LCD watch will certainly dominate the field of digital watches for a long time to come. The main reason, again, is the low current consumption of the display, which can even be further improved by reducing the capacitances of the display electrodes and possibly by replacing the power-consuming backlights with tritium-based lights, which require no external power. Improving the autonomy of a watch, which has been described as a dominating trend, applies particularly to electronic wristwatches, where the battery should be miniaturized as much as possible. For clocks where volume restrictions are not as stringent, the trend toward lower power consumption is also present but it is not dominant. 2. High-Frequency Oscillutors

An oscillating frequency of 32 kHz has become a standard for electronic watches. For some time there was a tendency to go to higher frequencies. This would improve the accuracy of a watch and decrease its temperature sensitivity. However, higher frequency means higher current and this would oppose the trend toward longer battery life. Therefore, it is believed that except for some special applications where high accuracy is required or where power consumption is not so important, the higherfrequency watch will not become very popular. 3. Polyfunctional Instrument

An evolution of the electronic watch toward a polyfunctional wrist instrument was predicted a long time ago (95). Alarm and stopwatch func-

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tions are already standard in LCD watches. These extended timing functions are particularly easy to implement in digital watches. In analog watches with mechanical displays, it is somewhat more difficult. An interesting combination is hybrid watches, where the actual time is shown in an analog fashion and date and stopwatch functions are shown on a digital display. An analog watch has also been announced where the hands of the watch are simulated by a segmented LCD display (96).This approach is very promising since it combines the advantages of the fully electronic solid-state watch without moving parts with the attractiveness of the analog representation. Three main categories of functions may be considered besides the above-mentioned timing functions: data processing, telecommunications, and sensing capabilities. The first category is represented by the watch-calculator combination that was introduced some years ago (97).One may question the real interest in such a combination because the miniaturized keyboard is not easy to work with, while it still yields a fairly bulky and power-hungry watch. A more promising avenue seems to be the processing of time-dependent data in conjunction with the watch. In the field of telecommunication, the most interesting product would be a paging watch. But the bad antenna situation, the poorly controlled environment, and the low power available while still needing to go to high frequencies will render this endeavor very difficult. The sensing function of the watch could incorporate ambient parameters such as temperature and pressure, or physiological parameters such as the body temperature, blood pressure, and heartbeat of the wearer. These many additional functions can in principle easily be implemented in an electronic watch circuit by standard digital techniques employing random-logic circuits. However, the design effort for even a small alteration to an existing circuit is considerable. Generally, it is uneconomical t o custom-design an integrated circuit for small production quantities, so that many of these ideas have not been reduced to practice due to the lack of an adequate market. The reaction of some manufacturers to this problem has been the introduction of microprocessor-like circuit architectures in which the detailed features of the watch are defined by the content of a read-only memory (43,98).The development of new watch functions is then reduced to the elaboration of the new memory content that will be incorporated into the read-only memory. Instead of a completely new mask set, only one new metal mask has to be generated. Attempts have been made to employ technologies with nonvolatile memory capabilities such as FAMOS or MNOS (26, 27), so that even the watch seller could electrically program the finished watch according to the wishes of the watch buyer. Microprocessor-like watch circuits are certainly more

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flexible, and development costs and development times are reduced, but such an all-purpose circuit will certainly occupy more silicon area than a carefully designed and laid out standard circuit, so that production costs will be larger. Even more important, this solution will oppose the dominating trend toward minimal power consumption. A microprocessor-like circuit will need some type of running clock. Since watch circuits operate at low to very low frequencies for the most part, this running clock will contribute considerably to the overall power consumption. Probably some compromise between standard digital logic and microprocessor-like architecture will be the most promising approach. Oscillator, divider chain, and most of the controlling and decoding circuitry will be done with standard logic techniques, where some internal multiplexing will help to reduce the active components needed and information concerning the pin configuration and certain circuit option could be contained in a ROM or PROM. A lot of improvements can certainly be expected in the next few years in packaging technology. There is a definite trend to mechanize and further integrate the various elements needed to complete an electronic watch module. It might become feasible to include the quartz and the integrated circuit in the same package (34) while eliminating the trimmer capacitor completely by employing digital tuning techniques (see Section IV,A,2). New forms of highly mechanized assembly of the few remaining parts (battery, display, and circuit) by use of tape automated bonding (99) or similar techniques can further reduce the manufacturing costs. V. CONCLUSION Electronic clocks and watches have experienced a dramatic development over the last years. From mere technical toys, they have evolved into consumer products with a considerable economic impact. A large fraction of all the watches produced worldwide are now electronic. The dominance of the mechanical watcb industry, notably by the Swiss companies, has been broken, and countries with a strong electronic industry, above all Japan and the United States, have taken over the lead. This'success of electronic watches and clocks had been due to the higher accuracy, high reliability, reduced cost, and ease of implementing additional functions. Electronic clocks and watches have by no means reached a final standard. Improvements have still to be made in battery technology, displays, and overall volume reduction of the watch modules. The functions implemented in a LSI watch circuit may appear trivial when compared to those

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required for other systems such as semiconductor memories and microprocessors. Nevertheless, special requirements such as the low operating voltage and the very low power available as well as the need to combine analog and digital functions on the same chip, ask for careful choices of technologies, circuit techniques, and system organization. Large improvements can still be expected from this side toward lower cost, increased performance, and extended functions. Electronic clocks and watches will certainly remain an important product of daily life. Whether the analog watch with a face and moving hands o r the digital watch with an alphanumeric display will dominate the market in the long range is not known. It seems that user acceptance of the digital watch is not as fast and thorough as anticipated a few years ago. It may well be that the analog watch or some hybrid form will be the winner. Problems such as ease of setting the watch, readability of the display in the dark, information transfer from the display to the eye of the wearer, o r simply tradition might have a decisive influence. A watch is also always a piece ofjewelery and not merely a technical object. It is obviously easier to incorporate an analog display with a round face into a jewlery watch than a digital display. In any case, it is probabIy too early to forecast which type of watch will dominate the market some years from now, but one thing is certain: The electronic clocks and watches will not disappear like some other electronic gadget. They will remain as an important item of daily life.

ACKNOWLEDGMENTS I would like to thank Prof. Dr. Vittoz and his colleagues at the Centre Electronique Horloger, Neuchitel, Switzerland, for helpful discussions and for kindly supplying numerous illustrations. I am also indebted to the management of FaselecCorp., Zurich, Switzerland, who generously supported this work.

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