- Email: [email protected]
ESD sensitivity investigation on a wide range of high density embedded capacitors
Microelectronics Reliability 48 (2008) 1422–1426
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
ESD sensitivity investigation on a wide range of high density embedded capacitors Frederic Barbier a,*, Sebastien Jacqueline b a b
NXP Semiconductors Caen, 2 Esplanade Anton Philips, Colombelles-BP20000, 14906 Caen cedex 9, France NXP Semiconductors Caen, 2 rue de la Girafe, BP 5120, 14079 Caen cedex, France
a r t i c l e Article history: Received 1 July 2008
i n f o
a b s t r a c t This work presents some results from electrical (TDDB, TLP, HBM and MM) measurements and ESD calculations/simulations on passive components such as capacitors. In a SIP context, the ESD sensitivity of innovative 3D capacitors is studied. A method to predict the failure threshold of a wide range of capacitor values under ESD events is presented and validated by measurement on silicon. This method consists of using the basic equation of the charge conservation for capacitors in parallel that is adapted to the model of the ESD event. Ó 2008 Elsevier Ltd. All rights reserved.
1. Introduction For the silicon based system-in-package concept with passive integration, an active die is associated to a passive die [1]. New technologies, such as the assembly of silicon chips onto other silicon chips, also referred to as ‘‘double flip chip” can be used. This is possible thanks to the combination of the most advanced microbumping and die placement techniques. Example is given in Fig. 1 where cross section of product is presented. Filtering, decoupling and other functionalities can be performed thanks to the passive structures with high silicon integration. This approach allows the integrated circuits to tend to a strong miniaturization and also high RF performances. An example of sbSIP (silicon based system-in-package) component is shown in Fig. 2. The active die is directly placed on top of the passive die. Both are then assembled in an appropriate package. With this concept, the active die generally has its own on-chip ESD protections. Unlike the passive technology that has resistors, capacitors and inductors in its portfolio, there is no dedicated ESD protection. This study was driven by the fact that such capacitors are often located directly at the circuit input or output, making them the first components in the ESD transient path. That is why an investigation has to be performed to know the ESD capacitor sensitivity. The goal is to prevent failures during ESD qualification of the IC but also during handling and fabrication. Two models are mainly used to describe ESD pulses: the human body model (HBM), which models handling of an IC by humans, and the machine model (MM), which models handling by machines. Both simulate different ESD events that may occur in the chain of
* Corresponding author. Tel.: +33 (0) 231453934; fax: +33 (0) 231452112. E-mail address: [email protected] (F. Barbier). 0026-2714/$ - see front matter Ó 2008 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2008.07.023
processing and packaging of integrated circuits. In this study we present an ESD investigation performed on the structures that are available in the passive technology focusing on the capacitors. We present a silicon validation of their ESD sensitivity that correlates with the failure prediction obtained by using the law of charge conservation when HBM and MM stresses are applied to capacitors. Two different types of capacitors (two technologies) will be studied. In this paper it will be shown for the first time that using a simple method based on the results of TDDB measurements and on the application of charge conservation or ESD spice-like simulations, it will be possible to predict the failure threshold of capacitors structures under HBM and MM stress. The following sections will describe the TDDB analysis performed on capacitors to obtain their breakdown voltage under ESD zap. TLP characterization will show a good correlation with the previous results. When capacitors are in parallel, like it is during an ESD event (for the HBM/MM circuits), the conservation of the charge will be introduced and used to predict the failure threshold of capacitors. 2. Capacitor description The core of the PICS (passive integration connecting substrate) technology is based on the integration of high density MOS ‘‘trench” capacitors as described in [1]. In the first product generation, these are fabricated in silicon by dry-etching macropores arrays of high aspect ratio up to 20. Capacitors with 30 nm ONO (oxide nitride oxide) dielectric stack and polySi/Al top electrode yield a capacitor density of 25–30 nF/mm2 with low leakage current density (<1 nA/mm2@22 V). In the race of capacitor integration, NXP developed the next generation of PICS technology, offering capacitor density of 80 nF/mm2. This second generation adopts the same concept of
F. Barbier, S. Jacqueline / Microelectronics Reliability 48 (2008) 1422–1426
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capacitor. A metal plate covers the whole body of the capacitor. Then two bonding wires create the connections to two external pins. Several capacitors have been assembled in standard packages to perform the ESD tests. The following section will present some experiments we carried out to study the dielectric reliability of the 3D capacitors under ESD event. In this paper we will use the TDDB data on capacitors to study their ESD sensitivity. Fig. 1. Cross-section of a fully integrated radio module in a molded leadframe.
4. TDDB measurements The constant voltage method, in which the capacitor is stressed at a constant voltage until breakdown occurs, allows characterization of failures due to wear-out, including time-dependent dielectric breakdown (TDDB) lifetime reliability characterization. In a TDDB experiment, the resistance of the capacitors is measured at elevated temperature (100 °C) and electric field. A failure is defined as the time where the resistance of the capacitor has decreased below 1 MX. Typically, the change of resistance at breakdown is very sudden from GX’s to short circuit. The time to breakdown (tbd) is described by an exponential dependence on electric oxide field Eono
tbd ¼ s0 ðTÞ exp½cðTÞEono
Fig. 2. RF transceiver in sbSIP.
capacitors, embedded in highly doped dry etched 3D macro structured silicon, still using ‘‘conventional” dielectric materials, and associated high throughput, low cost and reliable CVD and thermal processing techniques. A scaling of the Si nitride and oxide layers, including the optimization of the films interfaces along deeper macropores arrays, allows to more than tripling the capacitor density. In these two technologies capacitor values from 10 pF up to 10 nF have been tested. 3. Test structures description The designed test structures have been implemented according to Fig. 3. A metal line is used to connect each electrode of the 3D
where s0 and the field acceleration factor (c) are temperature (T) dependant fit parameters [2]. The acceleration factors are used to extrapolate the capacitor lifetime under operating conditions. Based on these data, the reliability for a generic reliability profile [1000 ppm failure rate in 10 year lifetime] can be predicted. The measurements were done at wafer level with a HP5156C (Precision Semiconductor Analyzer) to apply constant voltage stress and record the hard breakdown time. Per stress level, a series of at least 50 samples are tested with an automatic prober, equipped with a heated chuck. The plot of the cumulative number of failures against time-tobreakdown gives the statistical parameters of the Weibull distribution F(t):
m t FðtÞ ¼ 1 exp
g
ð2Þ
where m is the Weibull shape parameter which gives the lifetime spread of the intrinsic breakdown, and g is the time when the reliability becomes 63.2%. Once the distribution parameters are known from the probability plot, the lifetime for a 0.1% failure level can be calculated. TDDB measurements were made applying three constant voltage stresses, within about 5–20% below the intrinsic breakdown voltage (Vbd) of the dielectric nit ox2 V bd ¼ Eox1 bd t ox1 þ Ebd t nit þ Ebd t ox2
Fig. 3. Illustration of a 3D capacitor and its connections to the external pins of the package.
ð1Þ
ð3Þ
where t is the thickness and Ebd is the estimated electric field before breakdown of the 1st oxide, nitride and 2nd oxide layers of the ONO sandwich: 26 V for PICS1 technology and 19 V for PICS2. In this study we will use the long time-scale TDDB data in predicting the voltage breakdown to short time-scale ESD events. For the oxide breakdown, some publications have demonstrated that the dielectric degradation mechanism remains unchanged in the short time scale [3,4]. These TDDB results, extrapolated down to the ESD time domain, show that for the PICS1 technology, the failure voltage of the capacitor for the ESD typical time range is 40 V. For the PICS2 technology, the failure is predicted at 34 V. In the next paragraphs, we will show the relevance of long time-scale TDDB data in predicting the response to short time-scale ESD events.
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5. TLP characterization Transmission line pulse (TLP) testing has been used to study the oxide breakdown voltage under electrostatic discharges. The 2probe TLP system (50 X) applies 100 ns pulses (10 s rise time) to the capacitor under test (CUT), while measuring the voltage across and current through it. Incrementally increasing voltage pulses are applied on the CUT while making DC leakage measurements between pulses. In a TLP system, the voltage and current levels depend on the relative impedance of the transmission line (TL) with respect to the CUT: ICUT = V0/(ZCUT + ZTL) where V0 is the charging voltage of the TL. The capacitor has a resistance well greater than 50X. Then the main resistance is the one from the capacitor and we assume that the TLP stress is similar to a constant voltage stress. Fig. 5 shows the data for two CUTs with similar values in PICS1 and PICS2. The two dielectric failures are observed at 42 V and 34.5 V. In addition we can notice that even if we had higher current capability with higher capacitor values, we always had the same voltage failures for greater capacitor values. Then we compared these values to the voltage acceleration data. By extrapolation to the 100 ns time range of the TDDB data shown in Fig. 4, we can see a good correlation of the results found in the longer time-scale. Capacitor failure voltages measured using both transmission line pulse (TLP) and TDDB test methods are actually related to the intrinsic dielectric breakdown. To confirm this statement, the TLP current/voltage waveforms have been monitored during the two last TLP zaps leading to the failure (CUT 90 pF TLP curve from Fig. 5). We can see in Fig. 6, the resulting current/voltage waveforms obtained at the end of the TLP pulse. The waveforms show that the breakdown process occurs within 10 ns as already studied by Ridley [5]. If a stress which lasts 100 ns is able to produce the same type of failure mechanism as DC stress, the breakdown transient is shorter than 100 ns. This result confirms that the same breakdown process occurs in the DC and the ESD time domain. A similar approach is published by Weir et al. [3]. Using this information, showing a good agreement between the two methods, a failure criterion can be extracted from the voltage acceleration measurement. The predicted failure criteria will be implemented in the study of the conservation of charge when HBM and MM zaps are applied to capacitors. The next paragraph explains how this approach allows us to predict the capacitor failure threshold versus its capacitor value.
Fig. 5. TLP curves obtained with two similar capacitor values in PICS1 and PICS2.
Fig. 6. I/V waveforms for the last two points of the TLP curve (cut 90 pf PICS1) shown in Fig. 5.
6. Conservation of charge (part 1-calculation) An RLC circuit can simulate the electrostatic discharge due to the contact of a charged human body or a charged machine. In this circuit, a capacitor (CHBM = 100 pF or CMM = 200 pF) is used to represent the body or the machine capacitance that is discharged through the device under test [6,7]. If we neglect the resistance (r = 1500X for HBM) and the inductor (l = 7.5 lH for HBM and l = 0.75 lH for MM), we are then in a worst-case representation of the human body model or the machine model discharge. During the discharge, the charged capacitor (CHBM or CMM) is then connected to the uncharged capacitor under test (CUT). Taking into account we have two capacitors in parallel and the charge conservation law, the final voltage (Vf) seen by the CUT is
Vf ¼
Fig. 4. TDDB results on capacitors in PICS1 and PICS2.
C HBM=MM Vi C HBM=MM þ CUT
ð4Þ
The initial voltage (Vi) is the stress voltage applied to the CHBM/MM. This law (Eq. (3)) has been simulated for both ESD models. The capacitor value range was between 1 pF and 10 nF. The simulated voltage stress step for HBM was 10 V and began at 30 V. Above 100 V as voltage stress, the step was 100 V. For
F. Barbier, S. Jacqueline / Microelectronics Reliability 48 (2008) 1422–1426
MM, the voltage step was 10 V and began at 10 V. As failure criteria (Vbreak) we choose the breakdown voltage value extracted from the TDDB curve. We extrapolated down to the nanosecond time frame (at 100 ns, Vbreak = 40 V for the PICS1 process and 34 V for PICS2). With these values as failure criteria for both technologies, the calculation gives the minimum capacitor value needed to keep the final voltage (Vf) below Vbreak. The results are described in Figs. 9 and 10. To give a better confidence in the result obtained we performed some HBM and MM simulations with the Cadence spectre simulator on the studied capacitors. Spectre test benches were designed to simulate HBM and MM stresses. Both were calibrated according to the JEDEC standards [6,7]. Fig. 7 presents the electrical circuits for the human body model (A) and the machine model (B). We performed some
1425
optimizations to obtain the adequate waveforms according to the JEDEC waveforms specifications (current peak, rise time, etc). Fig. 8 presents an illustration for the resulting waveforms across three CUTs under MM zap at 300 V. The chosen simulated CUT values were taken between 100 pF and 10 nF. The applied HBM voltages were 2 kV, 1 kV, 500 V and 200 V. We analyzed the voltage responses across the CUTs and took into account the same failure criteria (Vresponse < Vbreak). As example, under 2 kV HBM, for CUT = 4 nF, the resulting voltage was 42 V. For CUT = 5 nF under 2 kV, the voltage response was 36 V and 31 V for CUT = 6 nF. For a capacitor C = 4 nF, the simulated voltage response is above the failure criteria and this value has been placed in Fig. 9. We used the same process to obtain the other points for both HBM and MM simulations. We can see that the results are very close to those obtained thanks to Eq. (3). This correlation makes us confident in our approach. The following paragraph presents the results for the silicon validation.
Fig. 9. Failure voltage versus capacitor value; measurement/calculation/simulation results for PICS1 capacitors. Fig. 7. HBM (A)/MM (B) test benches used for spice-like simulations.
Fig. 8. Waveforms obtained for MM = 300 V across 3 capacitors under test.
Fig. 10. Failure voltage versus capacitor value; measurement/calculation results for PICS2 capacitors.
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good correlation between measurements and calculations. When the capacitor value increases the resulting failure voltage (ESD voltage) also increases. 8. Physical analysis Physical analysis has been performed on the stressed devices to point out the failure location. We used the OBIRCH method based on two main processes: laser-beam heating and resistance change detection [8]. The resistance change appears as a current or voltage change only when the laser-beam irradiates a line where a current is flowing. This results in imaging current paths. The resistance change caused by laser-beam heating depends on an increase in temperature. When a laser beam is irradiated, the generated heat is transmitted freely across areas that are free of defects however, heat transmission is impeded at defects. This creates a nonuniform temperature increase, which results in imaging defects. In our case the dielectric breakdown creates a resistive current path between the two electrodes. We studied many defective capacitors after HBM/MM stress. As example, two OBIRCH pictures are presented in Fig. 11. The two pictures represent the same defective capacitor structure but coming from two different samples. We can observe two different failure locations (encircled spots). Both capacitors have failed at around 1 kV HBM. Front side and back side views have been tried on many defective capacitors and no reproducible failure locations have been observed. 9. Conclusion
Fig. 11. Front side Obirch pictures for a defective capacitor on two samples; sample 2 (A) and sample 3 (B).
In this study we increased the range of the studied capacitors compared to the literature [9]. For the first time, we present some ESD results on 3D silicon capacitors. We validate a method to predict the ESD sensitivity of a wide range of capacitance value. As expected using larger capacitors increases the capacitor ESD sensitivity. To increase the robustness against ESD stress, an alternative solution would be to use two or three capacitors in series that is equivalent to use a capacitor with double or triple dielectric thickness and it would result in doubling/ tripling of the breakdown voltage. Based on both TDDB results to obtain the breakdown voltage of the capacitors in the typical time domain of ESD and on HBM/MM calculations either with the law of charge conservation or with standard spice-like simulation, a method has been proposed to predict the failure threshold of capacitors under ESD. The proposed method validated by the silicon data enables designers to predict the ESD sensitivity of un-protected capacitors and/or create an ESD protection strategy accordingly.
7. Conservation of charge (part 2-silicon validation)
References
ESD tests were performed to evaluate the 3D capacitor sensitivity. The tests were performed using an MK2 Keytek test system and were based on both human body model and machine model events. An increasing voltage by step of 100 V for HBM and 20 V for MM, was applied to packaged structures comprising capacitors of various sizes until breakdown occurs. Positive and negative zaps have been applied on separate samples. The average of five results for positive zaps and four results for negative zaps are shown in Figs. 9 and 10. We can notice that the minimum HBM voltage applied on CUTs was 100 V. Even if some failures were obtained below this stress value, it can not be seen with data shown in Fig. 9. We can see a
[1] Murray F, et al. Silicon based system-in-package: a new technology platform supported by very high quality passives and system level design tools. Silicon monolithic integrated circuits in RF systems, Topical meeting on 10–12 January; 2007. p. 149–53. [2] JEDEC solid state technology association. Procedure for characterizing timedependent dielectric breakdown of ultra-thin gate dielectrics; August 2003. [3] Weir et al. Gate dielectric breakdown: a focus on ESD protection. In: 42nd annual international reliability physics symposium; 2004. p. 399–403. [4] Wu et al. IEEE Trans Electron Dev 2004;51:1528–31. [8th August]. [5] Ridley BK. J Appl Phys 1975;46:998. [6] JEDEC standard. JESD22-A114D. [7] JEDEC standard. JESD22-A115A. [8] Beaudoin F et al. Current leakage fault localization using backside OBIRCH. IPFA 2001:121–5. [9] Voldman S. RF technology and circuits. Wiley Ed; 2006. p. 129.
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
ESD sensitivity investigation on a wide range of high density embedded capacitors Frederic Barbier a,*, Sebastien Jacqueline b a b
NXP Semiconductors Caen, 2 Esplanade Anton Philips, Colombelles-BP20000, 14906 Caen cedex 9, France NXP Semiconductors Caen, 2 rue de la Girafe, BP 5120, 14079 Caen cedex, France
a r t i c l e Article history: Received 1 July 2008
i n f o
a b s t r a c t This work presents some results from electrical (TDDB, TLP, HBM and MM) measurements and ESD calculations/simulations on passive components such as capacitors. In a SIP context, the ESD sensitivity of innovative 3D capacitors is studied. A method to predict the failure threshold of a wide range of capacitor values under ESD events is presented and validated by measurement on silicon. This method consists of using the basic equation of the charge conservation for capacitors in parallel that is adapted to the model of the ESD event. Ó 2008 Elsevier Ltd. All rights reserved.
1. Introduction For the silicon based system-in-package concept with passive integration, an active die is associated to a passive die [1]. New technologies, such as the assembly of silicon chips onto other silicon chips, also referred to as ‘‘double flip chip” can be used. This is possible thanks to the combination of the most advanced microbumping and die placement techniques. Example is given in Fig. 1 where cross section of product is presented. Filtering, decoupling and other functionalities can be performed thanks to the passive structures with high silicon integration. This approach allows the integrated circuits to tend to a strong miniaturization and also high RF performances. An example of sbSIP (silicon based system-in-package) component is shown in Fig. 2. The active die is directly placed on top of the passive die. Both are then assembled in an appropriate package. With this concept, the active die generally has its own on-chip ESD protections. Unlike the passive technology that has resistors, capacitors and inductors in its portfolio, there is no dedicated ESD protection. This study was driven by the fact that such capacitors are often located directly at the circuit input or output, making them the first components in the ESD transient path. That is why an investigation has to be performed to know the ESD capacitor sensitivity. The goal is to prevent failures during ESD qualification of the IC but also during handling and fabrication. Two models are mainly used to describe ESD pulses: the human body model (HBM), which models handling of an IC by humans, and the machine model (MM), which models handling by machines. Both simulate different ESD events that may occur in the chain of
* Corresponding author. Tel.: +33 (0) 231453934; fax: +33 (0) 231452112. E-mail address: [email protected] (F. Barbier). 0026-2714/$ - see front matter Ó 2008 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2008.07.023
processing and packaging of integrated circuits. In this study we present an ESD investigation performed on the structures that are available in the passive technology focusing on the capacitors. We present a silicon validation of their ESD sensitivity that correlates with the failure prediction obtained by using the law of charge conservation when HBM and MM stresses are applied to capacitors. Two different types of capacitors (two technologies) will be studied. In this paper it will be shown for the first time that using a simple method based on the results of TDDB measurements and on the application of charge conservation or ESD spice-like simulations, it will be possible to predict the failure threshold of capacitors structures under HBM and MM stress. The following sections will describe the TDDB analysis performed on capacitors to obtain their breakdown voltage under ESD zap. TLP characterization will show a good correlation with the previous results. When capacitors are in parallel, like it is during an ESD event (for the HBM/MM circuits), the conservation of the charge will be introduced and used to predict the failure threshold of capacitors. 2. Capacitor description The core of the PICS (passive integration connecting substrate) technology is based on the integration of high density MOS ‘‘trench” capacitors as described in [1]. In the first product generation, these are fabricated in silicon by dry-etching macropores arrays of high aspect ratio up to 20. Capacitors with 30 nm ONO (oxide nitride oxide) dielectric stack and polySi/Al top electrode yield a capacitor density of 25–30 nF/mm2 with low leakage current density (<1 nA/mm2@22 V). In the race of capacitor integration, NXP developed the next generation of PICS technology, offering capacitor density of 80 nF/mm2. This second generation adopts the same concept of
F. Barbier, S. Jacqueline / Microelectronics Reliability 48 (2008) 1422–1426
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capacitor. A metal plate covers the whole body of the capacitor. Then two bonding wires create the connections to two external pins. Several capacitors have been assembled in standard packages to perform the ESD tests. The following section will present some experiments we carried out to study the dielectric reliability of the 3D capacitors under ESD event. In this paper we will use the TDDB data on capacitors to study their ESD sensitivity. Fig. 1. Cross-section of a fully integrated radio module in a molded leadframe.
4. TDDB measurements The constant voltage method, in which the capacitor is stressed at a constant voltage until breakdown occurs, allows characterization of failures due to wear-out, including time-dependent dielectric breakdown (TDDB) lifetime reliability characterization. In a TDDB experiment, the resistance of the capacitors is measured at elevated temperature (100 °C) and electric field. A failure is defined as the time where the resistance of the capacitor has decreased below 1 MX. Typically, the change of resistance at breakdown is very sudden from GX’s to short circuit. The time to breakdown (tbd) is described by an exponential dependence on electric oxide field Eono
tbd ¼ s0 ðTÞ exp½cðTÞEono
Fig. 2. RF transceiver in sbSIP.
capacitors, embedded in highly doped dry etched 3D macro structured silicon, still using ‘‘conventional” dielectric materials, and associated high throughput, low cost and reliable CVD and thermal processing techniques. A scaling of the Si nitride and oxide layers, including the optimization of the films interfaces along deeper macropores arrays, allows to more than tripling the capacitor density. In these two technologies capacitor values from 10 pF up to 10 nF have been tested. 3. Test structures description The designed test structures have been implemented according to Fig. 3. A metal line is used to connect each electrode of the 3D
where s0 and the field acceleration factor (c) are temperature (T) dependant fit parameters [2]. The acceleration factors are used to extrapolate the capacitor lifetime under operating conditions. Based on these data, the reliability for a generic reliability profile [1000 ppm failure rate in 10 year lifetime] can be predicted. The measurements were done at wafer level with a HP5156C (Precision Semiconductor Analyzer) to apply constant voltage stress and record the hard breakdown time. Per stress level, a series of at least 50 samples are tested with an automatic prober, equipped with a heated chuck. The plot of the cumulative number of failures against time-tobreakdown gives the statistical parameters of the Weibull distribution F(t):
m t FðtÞ ¼ 1 exp
g
ð2Þ
where m is the Weibull shape parameter which gives the lifetime spread of the intrinsic breakdown, and g is the time when the reliability becomes 63.2%. Once the distribution parameters are known from the probability plot, the lifetime for a 0.1% failure level can be calculated. TDDB measurements were made applying three constant voltage stresses, within about 5–20% below the intrinsic breakdown voltage (Vbd) of the dielectric nit ox2 V bd ¼ Eox1 bd t ox1 þ Ebd t nit þ Ebd t ox2
Fig. 3. Illustration of a 3D capacitor and its connections to the external pins of the package.
ð1Þ
ð3Þ
where t is the thickness and Ebd is the estimated electric field before breakdown of the 1st oxide, nitride and 2nd oxide layers of the ONO sandwich: 26 V for PICS1 technology and 19 V for PICS2. In this study we will use the long time-scale TDDB data in predicting the voltage breakdown to short time-scale ESD events. For the oxide breakdown, some publications have demonstrated that the dielectric degradation mechanism remains unchanged in the short time scale [3,4]. These TDDB results, extrapolated down to the ESD time domain, show that for the PICS1 technology, the failure voltage of the capacitor for the ESD typical time range is 40 V. For the PICS2 technology, the failure is predicted at 34 V. In the next paragraphs, we will show the relevance of long time-scale TDDB data in predicting the response to short time-scale ESD events.
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5. TLP characterization Transmission line pulse (TLP) testing has been used to study the oxide breakdown voltage under electrostatic discharges. The 2probe TLP system (50 X) applies 100 ns pulses (10 s rise time) to the capacitor under test (CUT), while measuring the voltage across and current through it. Incrementally increasing voltage pulses are applied on the CUT while making DC leakage measurements between pulses. In a TLP system, the voltage and current levels depend on the relative impedance of the transmission line (TL) with respect to the CUT: ICUT = V0/(ZCUT + ZTL) where V0 is the charging voltage of the TL. The capacitor has a resistance well greater than 50X. Then the main resistance is the one from the capacitor and we assume that the TLP stress is similar to a constant voltage stress. Fig. 5 shows the data for two CUTs with similar values in PICS1 and PICS2. The two dielectric failures are observed at 42 V and 34.5 V. In addition we can notice that even if we had higher current capability with higher capacitor values, we always had the same voltage failures for greater capacitor values. Then we compared these values to the voltage acceleration data. By extrapolation to the 100 ns time range of the TDDB data shown in Fig. 4, we can see a good correlation of the results found in the longer time-scale. Capacitor failure voltages measured using both transmission line pulse (TLP) and TDDB test methods are actually related to the intrinsic dielectric breakdown. To confirm this statement, the TLP current/voltage waveforms have been monitored during the two last TLP zaps leading to the failure (CUT 90 pF TLP curve from Fig. 5). We can see in Fig. 6, the resulting current/voltage waveforms obtained at the end of the TLP pulse. The waveforms show that the breakdown process occurs within 10 ns as already studied by Ridley [5]. If a stress which lasts 100 ns is able to produce the same type of failure mechanism as DC stress, the breakdown transient is shorter than 100 ns. This result confirms that the same breakdown process occurs in the DC and the ESD time domain. A similar approach is published by Weir et al. [3]. Using this information, showing a good agreement between the two methods, a failure criterion can be extracted from the voltage acceleration measurement. The predicted failure criteria will be implemented in the study of the conservation of charge when HBM and MM zaps are applied to capacitors. The next paragraph explains how this approach allows us to predict the capacitor failure threshold versus its capacitor value.
Fig. 5. TLP curves obtained with two similar capacitor values in PICS1 and PICS2.
Fig. 6. I/V waveforms for the last two points of the TLP curve (cut 90 pf PICS1) shown in Fig. 5.
6. Conservation of charge (part 1-calculation) An RLC circuit can simulate the electrostatic discharge due to the contact of a charged human body or a charged machine. In this circuit, a capacitor (CHBM = 100 pF or CMM = 200 pF) is used to represent the body or the machine capacitance that is discharged through the device under test [6,7]. If we neglect the resistance (r = 1500X for HBM) and the inductor (l = 7.5 lH for HBM and l = 0.75 lH for MM), we are then in a worst-case representation of the human body model or the machine model discharge. During the discharge, the charged capacitor (CHBM or CMM) is then connected to the uncharged capacitor under test (CUT). Taking into account we have two capacitors in parallel and the charge conservation law, the final voltage (Vf) seen by the CUT is
Vf ¼
Fig. 4. TDDB results on capacitors in PICS1 and PICS2.
C HBM=MM Vi C HBM=MM þ CUT
ð4Þ
The initial voltage (Vi) is the stress voltage applied to the CHBM/MM. This law (Eq. (3)) has been simulated for both ESD models. The capacitor value range was between 1 pF and 10 nF. The simulated voltage stress step for HBM was 10 V and began at 30 V. Above 100 V as voltage stress, the step was 100 V. For
F. Barbier, S. Jacqueline / Microelectronics Reliability 48 (2008) 1422–1426
MM, the voltage step was 10 V and began at 10 V. As failure criteria (Vbreak) we choose the breakdown voltage value extracted from the TDDB curve. We extrapolated down to the nanosecond time frame (at 100 ns, Vbreak = 40 V for the PICS1 process and 34 V for PICS2). With these values as failure criteria for both technologies, the calculation gives the minimum capacitor value needed to keep the final voltage (Vf) below Vbreak. The results are described in Figs. 9 and 10. To give a better confidence in the result obtained we performed some HBM and MM simulations with the Cadence spectre simulator on the studied capacitors. Spectre test benches were designed to simulate HBM and MM stresses. Both were calibrated according to the JEDEC standards [6,7]. Fig. 7 presents the electrical circuits for the human body model (A) and the machine model (B). We performed some
1425
optimizations to obtain the adequate waveforms according to the JEDEC waveforms specifications (current peak, rise time, etc). Fig. 8 presents an illustration for the resulting waveforms across three CUTs under MM zap at 300 V. The chosen simulated CUT values were taken between 100 pF and 10 nF. The applied HBM voltages were 2 kV, 1 kV, 500 V and 200 V. We analyzed the voltage responses across the CUTs and took into account the same failure criteria (Vresponse < Vbreak). As example, under 2 kV HBM, for CUT = 4 nF, the resulting voltage was 42 V. For CUT = 5 nF under 2 kV, the voltage response was 36 V and 31 V for CUT = 6 nF. For a capacitor C = 4 nF, the simulated voltage response is above the failure criteria and this value has been placed in Fig. 9. We used the same process to obtain the other points for both HBM and MM simulations. We can see that the results are very close to those obtained thanks to Eq. (3). This correlation makes us confident in our approach. The following paragraph presents the results for the silicon validation.
Fig. 9. Failure voltage versus capacitor value; measurement/calculation/simulation results for PICS1 capacitors. Fig. 7. HBM (A)/MM (B) test benches used for spice-like simulations.
Fig. 8. Waveforms obtained for MM = 300 V across 3 capacitors under test.
Fig. 10. Failure voltage versus capacitor value; measurement/calculation results for PICS2 capacitors.
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good correlation between measurements and calculations. When the capacitor value increases the resulting failure voltage (ESD voltage) also increases. 8. Physical analysis Physical analysis has been performed on the stressed devices to point out the failure location. We used the OBIRCH method based on two main processes: laser-beam heating and resistance change detection [8]. The resistance change appears as a current or voltage change only when the laser-beam irradiates a line where a current is flowing. This results in imaging current paths. The resistance change caused by laser-beam heating depends on an increase in temperature. When a laser beam is irradiated, the generated heat is transmitted freely across areas that are free of defects however, heat transmission is impeded at defects. This creates a nonuniform temperature increase, which results in imaging defects. In our case the dielectric breakdown creates a resistive current path between the two electrodes. We studied many defective capacitors after HBM/MM stress. As example, two OBIRCH pictures are presented in Fig. 11. The two pictures represent the same defective capacitor structure but coming from two different samples. We can observe two different failure locations (encircled spots). Both capacitors have failed at around 1 kV HBM. Front side and back side views have been tried on many defective capacitors and no reproducible failure locations have been observed. 9. Conclusion
Fig. 11. Front side Obirch pictures for a defective capacitor on two samples; sample 2 (A) and sample 3 (B).
In this study we increased the range of the studied capacitors compared to the literature [9]. For the first time, we present some ESD results on 3D silicon capacitors. We validate a method to predict the ESD sensitivity of a wide range of capacitance value. As expected using larger capacitors increases the capacitor ESD sensitivity. To increase the robustness against ESD stress, an alternative solution would be to use two or three capacitors in series that is equivalent to use a capacitor with double or triple dielectric thickness and it would result in doubling/ tripling of the breakdown voltage. Based on both TDDB results to obtain the breakdown voltage of the capacitors in the typical time domain of ESD and on HBM/MM calculations either with the law of charge conservation or with standard spice-like simulation, a method has been proposed to predict the failure threshold of capacitors under ESD. The proposed method validated by the silicon data enables designers to predict the ESD sensitivity of un-protected capacitors and/or create an ESD protection strategy accordingly.
7. Conservation of charge (part 2-silicon validation)
References
ESD tests were performed to evaluate the 3D capacitor sensitivity. The tests were performed using an MK2 Keytek test system and were based on both human body model and machine model events. An increasing voltage by step of 100 V for HBM and 20 V for MM, was applied to packaged structures comprising capacitors of various sizes until breakdown occurs. Positive and negative zaps have been applied on separate samples. The average of five results for positive zaps and four results for negative zaps are shown in Figs. 9 and 10. We can notice that the minimum HBM voltage applied on CUTs was 100 V. Even if some failures were obtained below this stress value, it can not be seen with data shown in Fig. 9. We can see a
[1] Murray F, et al. Silicon based system-in-package: a new technology platform supported by very high quality passives and system level design tools. Silicon monolithic integrated circuits in RF systems, Topical meeting on 10–12 January; 2007. p. 149–53. [2] JEDEC solid state technology association. Procedure for characterizing timedependent dielectric breakdown of ultra-thin gate dielectrics; August 2003. [3] Weir et al. Gate dielectric breakdown: a focus on ESD protection. In: 42nd annual international reliability physics symposium; 2004. p. 399–403. [4] Wu et al. IEEE Trans Electron Dev 2004;51:1528–31. [8th August]. [5] Ridley BK. J Appl Phys 1975;46:998. [6] JEDEC standard. JESD22-A114D. [7] JEDEC standard. JESD22-A115A. [8] Beaudoin F et al. Current leakage fault localization using backside OBIRCH. IPFA 2001:121–5. [9] Voldman S. RF technology and circuits. Wiley Ed; 2006. p. 129.