- Email: [email protected]
Evaluation of a prototype VLSI tester
275
INTEGRATION Workshop
Evaluation of a prototype VLSI tester Steven E. Butner Department of Electrical & Computer Engineering, University of California, Santa Barbara, CA 93106, U.S.A.
Received 1 May 1986
Abstract. With the advent and ready accessibility of multi-project fabrication for NMOS and
CMOS technologies, creation of custom very large-scale integrated circuits has become commonplace. The functional testing and characterization of the resulting parts requires, in general, an environment that is at least of the same order of complexity as the chip under test. General-purpose test equipment can be found in the industrial marketplace but the cost of such equipment is well into the $500000 range. Most testers cost over a million dollars. Many costly capabilities (such as per-pm electronics for measuring detailed analog properties of signals) are simply not required for functional prototype testing. This paper describes a general-purpose test stand, designed and built at the Santa Barbara campus of the University of California, to support functional testing and characterization of arbitrary NMOS and CMOS VLSI chips packaged with up to 40 pins. A prototype implementation of the tester is discussed; limitations and planned improvements are also presented.
Keywords.
Introduction
Functional testing, VLSI prototype testing.
and problem
statement
The increasing complexity of VLSI devices as well as the emphasis on better overall quality, higher designer productivity, and lower unit costs forces a closer working relationship between the design, engineering, and manufacturing teams engagedin the development of VLSI components. In this chain, testing becomes an increasingly important link. Very large-scale integrated circuits have outgrown traditional general-purpose test systems. In the last ten years, commercial chip complexity has grown from North-Holland INTEGRATION,
the VLSI journal 5 (1987) 275-288
0167-9260/87/$3.50
0 1987, ElsevierSciencePublishersB.V. (North-Holland)
276
S. E. Butner / Evaluation
of a prototype
VLSI tester
2500-gate, 40-pin devices with ~-MHZ clock rates to 200000-gate, 250-pin, 40-MHz devices, making the test engineer’s job an increasingly difficult one. Becauseof this tremendous growth, a significant effort has been made to improve testing techniques and testing equipment. Recently, test equipment producers have revolutionized test equipment architecture, providing all the necessary per-pin hardware as well as significant software aids. Today’s testers are, in effect, collections of highly accurate timing-, voltage-, and current-measuring instruments that are allocated by the test engineer in order to test each chip. The specifications for a modern industrial chip tester will typically include: - 80-MHz test clock rate, - lOO-picosecondoverall timing resolution, - 700-picosecondaccuracy at the test pin, - pin-counts to 256 pins, and - a test vector memory over 1 million elements deep. The price for this test technology is extremely high (e.g. the base price for an 80-pin system as described above is on the order of $1.3 million [l]).
Testing prototype VLSI circuits Testing any logic device involves simulating the voltage, current, and timing environment as would be seen by the chip in a real system. In addition, it is necessaryto sequencethe chip through a series of internal states, checking its actual responsesagainst a set of predicted responses. High volume VLSI chip producers use a variety of testing equipment from the sophisticated testers previously described to optical and scanning electron microscope techniques. The process of testing a VLSI circuit is performed near the end of the development cycle, but the work on test planning must be started much earlier. Designing for testability is an extremely important part of the overall system engineeringjob. At a university the testing problem is significantly different from that of an industrial chip developer. The budget for personnel and equipment to support the activity is severely reduced (from the industrial case).In order to be able to afford fabrication for educational and researchprojects, the cost of mask making and wafer processing is spread across multiple projects. The resulting Steven E. Butner received the B.S. degree in electrical engineering from the University of Kansas in 1969, the MS. (EE) degree from the University of Pennsylvania, and the Ph.D. (EE) degree from Stanford University in 1982. He has industrial experience with General Electric, Honeywell, GTE, and Bell Northern Research. Dr. Butner is currently an associateprofessor of electrical and computer engineering at the Santa Barbara campus of the University of California. His research interests include computer architecture with an emphasis on reliability and VLSI as well as digital system testing. Dr. Butner is a member of ACM and the IEEE.
S.E. Butner / Evaluation
of a prototype
VLSI tester
277
multi-project-chips [2] offer some new test challenges. Some of the problems unique to multi-project-chip testing are: - varying location and number of power and ground pins, - variation of pin direction on a per-pin basis (including bi-directional and/or tri-state behavior changing at full circuit speed), - severalvarieties of clocking (one-phase,two-phase,. . .) with a need for adjustable duty-cycle, non-overlap time, speed,etc. In short, there is an almost total lack of standardization. The ‘design frames’ approach recently introduced within the university community [5] offers a much needed common chip interface for ‘systems’-type designs. If the chip under development does not fit within a bus-organized system context then the design frame technique cannot be used. Significant problems remain in testing and characterizing such prototype custom chips. The facilities needed for functional testing are concerned primarily with flexibility in stimulating and measuring the environment of the unit under test. For chip characterization, however, the interest focusses on speed and the interrelationship of specific signals. The two types of chip evaluation imply somewhat divergent requirements on a test stand. Overview
of the UCSB VLSI
test stand
The VLSI test stand describedin this paper consists of three major subsystems, the microprocessor, the pin electronics, and the clock/controller. A block diagram is given in Fig. 1. This architecture has been designedwith high speed and low-cost testing in mind. The prototype implementation, however, has stressed proof of concept rather than the highest possible speed. Current activities focus on an improved version which is to have a much higher test speed. A microprocessor has been included in the test stand for flexibility and so that the user interface can be made reasonably friendly. The microprocessor does not directly control the stand during testing. Its function is to interact with the user via the RS-232 port to establish parameters, set-up test vectors, and display per-pin electronics. Microprocessor & Memory
. t;
,’
+ I
Master
yz
Vector Memory
2 -= I:-
JAP Bus Clock & i2ontroller
Fig. 1. Block diagram of the VLSI test stand.
S.E. Butner / Evaluation of a prototype VLSI tester
218
Host Computer
File
System
test
Fig. 2. Using the tester with a host computer.
results. Actual testing is performed under the control of the master clock/controller card. This allows use of a low-cost commercial microprocessor (an INTEL 8085) rather than a more complex high performance unit. Note that the maximum speedattainable by this organization is limited by the clock/controller and the pin electronics and not by the microprocessor. The tester may be used in two configurations: attached directly to an RS-232 terminal or attached to a general-purposehost computer (as shown in Fig. 2). All functions of the tester may be invoked in either configuration but the host computer version has significant advantages.The presenceof on-line disk storage allows users to store and retrieve test sets and to generally interact more effectively with the tester. The prototype version of the tester has a 40-pin test capability. There are 40 sets of per-pm electronics, each with a 256-bit shift register test vector memory under control of the master clock/controller card and accessible by the microprocessor. In addition, there are 10 other vector memories. These are similar to the per-pin vector memories with some differences in connectivity. Rather than connecting to a pin of the chip under test, these so-called auxiliary registers are used to control the directionality of bidirectional pins of the chip under test. By this method the direction of any given pin of the test chip can vary from clock to clock at full test speed. Architecture
and prototype
implementation
details
The microcomputer
In the prototype implementation, an INTEL 8085 microprocessor is used as the basis of a simple single-board computer. The system has 2K of random-access memory and 4K of read-only program storage.For easeof design, both memorymapped and direct I/O are used. On the processor board, there are three counter/timers (a single INTEL 8253), a UART (INTEL 8251A) with line
S. E. Butner / Evaluation
of a prototype
VLSI tester
279
Photo 1. VLSI tester (rear view).
driver/receiver, a crystal oscillator time base, as well as the RAM and ROM memories. The test system utilizes a 72-line nonstandard bus which is available to all cards. Photo 1 shows the bus cabinet, including the CPU, 12 pin electronics cards, and the clock/controller card. Both polled and interrupt I/O are used. Interrupts are utilized for asynchronous character I/O via the UART as well as for counter runout and shift register clock event signalling. When the test memories are being circulated at a slow clock rate, individual shift pulses interrupt the microcomputer so that single bit shift register memory transactions may take place. At test speeds, single shift pulses may occur at speeds greater than the microcomputer clock rate. To avoid problems in trying to service interrupts at such an impossible rate, these interrupts are masked during test runs. The clock / controller
This card is the heart of the tester. The master clock/controller unit is a simple Moore-model finite state machine that generates the signals required by the per-pin electronics. During selected states, the state machine waits for an internal clock-speed control counter to overflow (refer to the diagram in Fig. 3). It is via this mechanism that the microcomputer controls the tester clock rate. For example, by loading FFFFl,, into the speed control counter, no delay is incurred (since the counter overflows whenever it gets clocked) and the maximum speed test clock is generated. If the value FFFS,, is loaded, however, an &cycle delay is inserted. Use of a 16-bit counter for clock speed control allows a wide range of clock speed settings (from about 2 KHz to over 4 MHz for a 25 MHz main internal time base). The delay introduced by the clock speed control counter stretches the width of the chip-under-test’s phase 1 and phase 2 clocks as well as tester-internal levels. Single-clock pulses internal to the tester are not stretched. In this way, correct
280
S.E. Butner / Evaluation of a prototype VLSI tester timing
and control
signals
clock mode+
1. t p,reload J delay enable A
JIP bus
Fig. 3. Block diagram of the clock/controller.
timing relationships are automatically maintained. Figure 4 shows the derived control signals. There are many weaknesseswith the existing design. The most severeis that the approach requires too much headroom in frequency. The fact that parts of the clock circuitry must operate an order of magnitude faster than the final clock output limits the top-end testing frequency. A second problem revolves around the use of a counter to delay the user-level clock. While this provides a wide range of delays and is easy to implement, the design is not functionally well-suited at the top end of the frequency range. The insertion of a single delay count halves the clock output frequency, for example. The settings at the high frequency end are much too coarse. Another problem is that the current clock design does not allow adjustment of non-overlap times; both clock phasesare always identical. It is often desireableto be able to set the phase 1 and phase 2 high times as well as
Main Output
Clock Latch
Shift
Phi-l
Shift
Phi-2
Input
Latch
r
r
l-l
l-l 1
-1
r
1
r
1
I
r
UUT Phi-l UUT Phi-2
1 Clk OLatch S-l &2 ILatch Phi-l&2
internal time base (approximately 25MHz) pulse to latch UUT ‘output’ pins 2-phase clock for MOS shift register pulse to latch UUT ‘input’ pins P-phase clock as seen by UUT Fig. 4. Control signal thing diagram.
SE. Butner / Evaluation
Photo 2. Prototype
oj a prototype
VLSI tester
281
VLSI tester (front views).
their non-overlap times independently. The only ‘adjustment’ available in the prototype tester is the clock mode control, a static level (implemented as a toggle switch on the front panel) indicating whether the chip under test uses single-phase or two-phase clocks. The next version of the tester system will contain a clock design with flexibility in adjusting both high time and non-overlap time for the two clock phases independently. The new clock controller also requires significantly less headroom and has more flexible control over top-end frequency. The vector memory and pin electronics This is the ‘business end’ of the tester. The logic and electronics associated with any pin of the UUT (unit under test) is called a ‘pin register’. In the prototype unit, four pin registers are implemented on a printed circuit card (see Photo 1). Each single pin register has a 256-bit dynamic MOS shift register (aAMD2802) to hold test stimuli and responses. The shift register is continuously clocked. There is a multiplexer (controlled by the microcomputer) which steers
282
S.E. Burner / Evaluation of a prototype VLSI tester
Fig. 5. Organization of a pin register unit.
the end bit of the shift register. The block diagram of Fig. 5 illustrates the basic organization. The microcomputer accessesinformation within the shift register by first setting the master clock to a very slow shift rate (in the 4-5 KHz range) and then enabling interrupts for each shift event. When interrupted, the microcomputer can read or write the current bit of any pin register via memory-mapped I/O. The steering multiplexer is used to control accessto the input side of the shift register. Whenever the shift register is required to idle (i.e. to simply retain its contents) the steering multiplexer is set to recirculate the shift register output back to its input. During testing, other settings of the steering mux are used. The exact setting depends on the user-specified direction of the pin under test. Table 1 gives the steering multiplexer details. Now we consider the problem of dealing with bi-directional or tri-state pins. For a portion of the time the tester must drive such pins as if they were inputs and part of the time such pins will drive the tester. There are a couple of ways of handling this type of reversible drive: tri-stateable pin register drivers or ‘fighting’ drivers. The control problems associated with switching pin register drivers on and off are much more complex than the other approach, but this technique is electrically superior. If ‘fighting’ drivers are used, the pin under test must be able to overpower the drive of the test stand (which, of course, is made weaker than it normally would be). In caseswhere the pin under test pulls one direction while
Table 1 Steering multiplexer settings M&X
Selectedinput
00 01 10 11
Test pin value Logic ‘0 Data bus bit Shifter output
Use For output pins To clear register For loading register For input pins or recirculation
S. E. Butner / Evaluation
of a prototype
283
VLSI tester
to/from pin of unit under test
om shift
register
Fig. 6. Directionality control via auxiliary registers.
the test stand goes in another, a voltage divider is established. In order to make minimal assumptions as to the drive capability of units under test, the ‘fighting’ approach was not used in our tester. The current VLSI test stand uses the more complex tri-stateable driver method instead. When the pin under test acts as an output pin, the tester must correctly latch and store the output value. When acting as an input pin, the tester must drive a test datum onto the pin. Role changesbetween input and output behavior can happen at full clock rate and, thus, the microcomputer cannot be involved in the control of directionality. In the prototype tester we use 10 extra pin registers (which we call auxilimy registers) to control the direction of other regular pins. The value at the read-out of any auxiliary register may be used to control the direction of any set of regular pins. This control is achieved via the selection logic shown in Fig. 6. The ten auxiliary registersdrive bus lines AUXOl-AUXlO which are shown as inputs to the direction control multiplexer. This circuit is included for each pin register so that there is independent control of directionality. As is the casefor the steering multiplexer, the latch for the bidirectionality control mux is accessibleto the microprocessor via memory-mapped I/O. Packaging
and fixturing
in the prototype
tester
Issuesrelating to packaging and fixturing are test fixture(s) for interconnecting the unit under test, power/ground switching, signal shielding, and power supply regulation and adjustability. In these areas, the prototype is relatively primitive (refer to Photo 2). There is only a single 40-pin, zero-insertion-force socket for connection to the unit-under-test. This has proven to be adequate since the majority of parts being tested have 40 or fewer pins and are packaged by the fabricator. Power and ground connections are done externally via patch cables. This has also worked adequately, although there is more noise on power and
284
SE. Butner / Evaluation of a prototype VLSI tester
ground leads than we sometimes would like. There is only a single switching-type power supply (+ 5 V, - 5 V, + 12 V, - 12 V) for the entire tester. It supplies all tester logic as well as the electronics of the tester itself. Signal shielding is not needed due to the low frequency of tester operation (below 5 MHz at test pins) and the short distance between the test socket and the pin electronics. Details of the command
interface
The user interface of the VLSI test stand is intended to be simple to learn and use.All commands are indicated by a single character; pin registers are numbered 01-40 (in decimal). The auxiliary registers are numbered 41-50. Registers can be assignedsymbolic names up to 8 charactersin length. Binary test vector information is accepted and displayed in hexadecimal. Any pin register (including the aux registers) can be loaded or read-out via commands received over the .RS-232 port. All data flowing through this port is coded in a printable subset of the ASCII code and is designed to be human-readable. ‘White space’, i.e. spaces,tabs, carriage~returns,and line feeds are ignored by the tester. These characters can be used to make the command stream more readable. Comments can be included in the stream as well. A comment begins with a semicolon ( ; ) and extends through the next carriage return or line feed. An ordinary computer terminal with an RS-232 interface can be plugged directly into the ‘host’ port of the tester (instead of a general-purpose host computer). Table 2 VLSI tester command summary Command
Description
cxxxx Dxx(type)(name).
Set clock speed to xxxxld Define (type) of pm xx,e with symbol (name) as: I...input pin 0.. . output pin 1.. . clock phase 1 2.. . clock phase 2 Byy . . . bidirectional, per aw register yyta. Display and clear error counts Fill pin register (name) with yyld Load pin (name) with bit string (hex) Master reset Toggle ‘quiet’ mode (echo on/off) Read-out pin (name) (as hex string) Read-out all defined pins Begin cyclic test (circular shift, applying all 256 bits repeatedly) Display software version ID Execute one-shot test (apply defined bit strings once) Exit cyclic test (seeT above)
E F(n=@w L(name)xxxx.. . a” R( name) RT V X z
S.E. Butner / Evaluation of a prototype VLSI tester
285
The presence of editors, as well as data storage and analysis tools of a host machine make the host-oriented approach vastly preferred. An internal DIP switch allows specification of the baud rate. The commands available in the prototype VLSI tester are summarized in Table 2. The general sequencefor testing a chip consists of M (master reset), D (define pin types and symbols), L (load input vectors), C (set clock speed), X (execute test), R (read-out result vectors). Host-resident programs are available to display input and output vectors in a logic-analyzer type format as well as to convert test streams to and from CAD databaseformats.
A simplified
example
Consider the test setup for an MS1 parallel-load binary up/down counter, the 74193 [3] which should be familiar to most readers.Our sample test will consist of 20 clocks in up-count mode with an asynchronous clear applied before the first and fourth clocks and a parallel load signal applied after the fifth clock. This is clearly not a comprehensivetest; it is presentedhere merely to illustrate the ease Table 3 User input to test 74193 up/down counter M C FF80 D14i CLR* . DOS UP. D04i DWN. Dlli LD*. D15i IA. DOli IB. DlOi IC. D09i ID. DO30 OA. DO20 OB. DO60 oc. DO70 OD. L UP 55555555550000. L DWN 00000000000000. L CLR* 7DFFFFFFFFFFFF. L LD * FFDFFFFFFFFFFF. L IA 00200000000000. L IB 00200000000000. L IC FFOFFFFFFFFFFFF. L ID FF2FFFFFFFFFFFF. RX R-
;te.st stand master reset ;set test clock rate (FF80 = - 100 kHz) ;declare CLEAR- BAR input pin ;COUNT-UP input pin ;COUNT- DOWN input pm ;LOAD _ BAR input pin ;IA (low-order) ;IB parallel ;IC load data ;ID (high-order) ;OA (low-order) ;OB parallel ;oc output ;OD (high-order) ;COUNT-UP input (20 0- > 1 transitions) ;COUNT- DOWN input ;Clear after 3rd count pulse ;asynch CLEAR- BAR input ;LOAD _ BAR control ;l (parallel ;l load ;0 vector) ;1 ;read-back all loaded registers ;run a single test (length = 56) ;read-back test results
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S.E. Burner / Evaluation
of a prototype
VLSI tester
of use of our tester. In the example, we first reset the tester, then define the pin types. All pin types should be defined before any of the pin registers are loaded. The physical set-up involves turning on the tester, placing the chip under test into the test socket (in this case a special converter socket must be used since the tester has a 40-pin socket), and connecting the +5 V and ground leads to the appropriate pins. In this case + 5 V should be plugged into the jack for pin 16 and ground should be connected to pin 08. The LEDs corresponding to these two pins will immediately indicate their ‘logic’ states. The tester should be connected to a terminal and thus the RS-232 mode switch should be set to ‘TERMINAL’ (rather than ‘HOST’). The user input (with extra comment material added for readability) is given in Table 3. When applied to the tester, the input (Table 3) causesthe following response: - During input, the incoming characters are echoed to the terminal, - When the ‘R-command is executed, the contents of all registers are readback and printed in hexadecimal on the terminal. - The LEDs flash for a brief moment when the 56 test vectors are applied. - The final ‘R’ command requests a snapshot of test vector memory after application of the test. Subsequently, host-resident software can be used to get a logic-analyzer-style plot of the test results. Alternatively, the tester can be placed into cyclic test mode (see description of the ‘T’ command in Table 2) for interactive oscilloscope probing of signals on pins of the unit under test. Improvements
in the tester for increasing
test speed
The existing prototype VLSI tester has been used to functionally test and roughly characterize many student project chips during 1984 and 1985. As a result of our experience with the tester, a new and improved version is currently under development. The improvements focus primarily on increasing top-end test speed. Faster clock/
controller
At the heart of the current speedlimitation is the master clock/controller. This subsystem has been redesigned.The current implementation as a state machine uses too many states per test cycle, thus requiring some parts of the clock generation logic to respond to frequencies 8 to 10 times those seenat the test pin. If we are to achieve our goal ( > 20 MHz clocks at the test pin) this ‘headroom’ factor of ten in frequency clearly cannot continue to exist. The new clock/controller design has an adjustable range from 30 KHz to over 30 MHz with very fine-grain control at the top end. The high-time and non-overlap time of the two clock phases are individually controllable. The circuit is a cross-coupled NOR with a programmable delay inserted in the feedback paths. Reference[6] describesthe new clock/controller in detail.
SE. Butner / Evaluation
Improved
of a prototype
VLSI tester
287
test length counter
Above 2 MHz the Intel 8253 (in the current design) cannot reliably count test events. Since our design goal for the new tester is much faster than 2 MHz, we must redesign and repackage the test length counter. The ultimate solution is a special-purpose VLSI chip integrating several now-separate functions. Integrated
pin register/counter
chip
The first version of a new fully-custom NMOS VLSI chip has been fabricated by MOSIS [4]. The new chip (refer to Fig. 7) houses the electronics for 8 pin registers, each with its own bidirectionality (auxiliary) register. In addition, the chip has a parallel-load down counter for use in accurately controlling test length.
Fig. 7.
288
S.E. Butner / Evaluation
of a prototype
VLSI tester
With 8 VLSI chips, we will have the required electronics can easily be package on a single printed circuit card. Software and microcomputer
for a 64-pin tester. This
changes
No changes to the microcomputer are planned (with the possible exception adding more RAM). The software is, of course, undergoing modifications interface correctly with the new VLSI tester electronics. Bootstrapping
of to
to very high speed
As part of a three-year program to study and develop design principles for Gallium-Arsenide integrated circuits, a very high-speed tester wiIl be required. We plan to rely on the experience with the structures used in the current and second generation VLSI tester to gradually bootstrap ourselves (via succession of increasingly faster versions) into the gigahertz test speeds required for GaAs parts. The ultimate goal is a GaAs test stand which is made primarily from custom GaAs integrated circuits.
We have presented the design of a special-purpose hardware subsystem for functionally testing custom NMOS and CMOS integrated circuits. Experience with a prototype version of the tester has encouraged us to construct a more advanced system with a test speed goal of 20 MHz. The new version utilizes full-custom NMOS VLSI chips to improve the packaging, size, speed, and overall reliability of the test stand. The current and planned tester architectures are being evaluated and modified in order to serve as the basis for much faster test systems.
References [l] Swan, R.,.and C. McMinn, ‘General-purpose tester puts a separate set of resources behind each VLSI-device pin’, Electronics (8 September 1983) 101-106. [2] Mead, C. and L. Conway, Introduction to VLSI Systems (Addison-Wesley, Reading, MA, 1980). [3] Texas Instruments Inc., The TTL Data Bookz, Vol. 1 (1984). [4] “MOSIS, what it is and how to use it”, Information SciencesInstitute, University of Southern California, ISI/TM-84-128, March 1984. [5] BorrieIIo, G., R. Katz, and A. BeII, “The multibus design frame”, EECS Report #UCB/CSD 85/232, University of California, Berkeley, CA, 1985. [6] Akkawi, I., “Design of a high speed test stand for prototype VLSI chips”, MS thesis, Department of Electrical & Computer Engineering, University of California, Santa Barbara, CA, 1985.
INTEGRATION Workshop
Evaluation of a prototype VLSI tester Steven E. Butner Department of Electrical & Computer Engineering, University of California, Santa Barbara, CA 93106, U.S.A.
Received 1 May 1986
Abstract. With the advent and ready accessibility of multi-project fabrication for NMOS and
CMOS technologies, creation of custom very large-scale integrated circuits has become commonplace. The functional testing and characterization of the resulting parts requires, in general, an environment that is at least of the same order of complexity as the chip under test. General-purpose test equipment can be found in the industrial marketplace but the cost of such equipment is well into the $500000 range. Most testers cost over a million dollars. Many costly capabilities (such as per-pm electronics for measuring detailed analog properties of signals) are simply not required for functional prototype testing. This paper describes a general-purpose test stand, designed and built at the Santa Barbara campus of the University of California, to support functional testing and characterization of arbitrary NMOS and CMOS VLSI chips packaged with up to 40 pins. A prototype implementation of the tester is discussed; limitations and planned improvements are also presented.
Keywords.
Introduction
Functional testing, VLSI prototype testing.
and problem
statement
The increasing complexity of VLSI devices as well as the emphasis on better overall quality, higher designer productivity, and lower unit costs forces a closer working relationship between the design, engineering, and manufacturing teams engagedin the development of VLSI components. In this chain, testing becomes an increasingly important link. Very large-scale integrated circuits have outgrown traditional general-purpose test systems. In the last ten years, commercial chip complexity has grown from North-Holland INTEGRATION,
the VLSI journal 5 (1987) 275-288
0167-9260/87/$3.50
0 1987, ElsevierSciencePublishersB.V. (North-Holland)
276
S. E. Butner / Evaluation
of a prototype
VLSI tester
2500-gate, 40-pin devices with ~-MHZ clock rates to 200000-gate, 250-pin, 40-MHz devices, making the test engineer’s job an increasingly difficult one. Becauseof this tremendous growth, a significant effort has been made to improve testing techniques and testing equipment. Recently, test equipment producers have revolutionized test equipment architecture, providing all the necessary per-pin hardware as well as significant software aids. Today’s testers are, in effect, collections of highly accurate timing-, voltage-, and current-measuring instruments that are allocated by the test engineer in order to test each chip. The specifications for a modern industrial chip tester will typically include: - 80-MHz test clock rate, - lOO-picosecondoverall timing resolution, - 700-picosecondaccuracy at the test pin, - pin-counts to 256 pins, and - a test vector memory over 1 million elements deep. The price for this test technology is extremely high (e.g. the base price for an 80-pin system as described above is on the order of $1.3 million [l]).
Testing prototype VLSI circuits Testing any logic device involves simulating the voltage, current, and timing environment as would be seen by the chip in a real system. In addition, it is necessaryto sequencethe chip through a series of internal states, checking its actual responsesagainst a set of predicted responses. High volume VLSI chip producers use a variety of testing equipment from the sophisticated testers previously described to optical and scanning electron microscope techniques. The process of testing a VLSI circuit is performed near the end of the development cycle, but the work on test planning must be started much earlier. Designing for testability is an extremely important part of the overall system engineeringjob. At a university the testing problem is significantly different from that of an industrial chip developer. The budget for personnel and equipment to support the activity is severely reduced (from the industrial case).In order to be able to afford fabrication for educational and researchprojects, the cost of mask making and wafer processing is spread across multiple projects. The resulting Steven E. Butner received the B.S. degree in electrical engineering from the University of Kansas in 1969, the MS. (EE) degree from the University of Pennsylvania, and the Ph.D. (EE) degree from Stanford University in 1982. He has industrial experience with General Electric, Honeywell, GTE, and Bell Northern Research. Dr. Butner is currently an associateprofessor of electrical and computer engineering at the Santa Barbara campus of the University of California. His research interests include computer architecture with an emphasis on reliability and VLSI as well as digital system testing. Dr. Butner is a member of ACM and the IEEE.
S.E. Butner / Evaluation
of a prototype
VLSI tester
277
multi-project-chips [2] offer some new test challenges. Some of the problems unique to multi-project-chip testing are: - varying location and number of power and ground pins, - variation of pin direction on a per-pin basis (including bi-directional and/or tri-state behavior changing at full circuit speed), - severalvarieties of clocking (one-phase,two-phase,. . .) with a need for adjustable duty-cycle, non-overlap time, speed,etc. In short, there is an almost total lack of standardization. The ‘design frames’ approach recently introduced within the university community [5] offers a much needed common chip interface for ‘systems’-type designs. If the chip under development does not fit within a bus-organized system context then the design frame technique cannot be used. Significant problems remain in testing and characterizing such prototype custom chips. The facilities needed for functional testing are concerned primarily with flexibility in stimulating and measuring the environment of the unit under test. For chip characterization, however, the interest focusses on speed and the interrelationship of specific signals. The two types of chip evaluation imply somewhat divergent requirements on a test stand. Overview
of the UCSB VLSI
test stand
The VLSI test stand describedin this paper consists of three major subsystems, the microprocessor, the pin electronics, and the clock/controller. A block diagram is given in Fig. 1. This architecture has been designedwith high speed and low-cost testing in mind. The prototype implementation, however, has stressed proof of concept rather than the highest possible speed. Current activities focus on an improved version which is to have a much higher test speed. A microprocessor has been included in the test stand for flexibility and so that the user interface can be made reasonably friendly. The microprocessor does not directly control the stand during testing. Its function is to interact with the user via the RS-232 port to establish parameters, set-up test vectors, and display per-pin electronics. Microprocessor & Memory
. t;
,’
+ I
Master
yz
Vector Memory
2 -= I:-
JAP Bus Clock & i2ontroller
Fig. 1. Block diagram of the VLSI test stand.
S.E. Butner / Evaluation of a prototype VLSI tester
218
Host Computer
File
System
test
Fig. 2. Using the tester with a host computer.
results. Actual testing is performed under the control of the master clock/controller card. This allows use of a low-cost commercial microprocessor (an INTEL 8085) rather than a more complex high performance unit. Note that the maximum speedattainable by this organization is limited by the clock/controller and the pin electronics and not by the microprocessor. The tester may be used in two configurations: attached directly to an RS-232 terminal or attached to a general-purposehost computer (as shown in Fig. 2). All functions of the tester may be invoked in either configuration but the host computer version has significant advantages.The presenceof on-line disk storage allows users to store and retrieve test sets and to generally interact more effectively with the tester. The prototype version of the tester has a 40-pin test capability. There are 40 sets of per-pm electronics, each with a 256-bit shift register test vector memory under control of the master clock/controller card and accessible by the microprocessor. In addition, there are 10 other vector memories. These are similar to the per-pin vector memories with some differences in connectivity. Rather than connecting to a pin of the chip under test, these so-called auxiliary registers are used to control the directionality of bidirectional pins of the chip under test. By this method the direction of any given pin of the test chip can vary from clock to clock at full test speed. Architecture
and prototype
implementation
details
The microcomputer
In the prototype implementation, an INTEL 8085 microprocessor is used as the basis of a simple single-board computer. The system has 2K of random-access memory and 4K of read-only program storage.For easeof design, both memorymapped and direct I/O are used. On the processor board, there are three counter/timers (a single INTEL 8253), a UART (INTEL 8251A) with line
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Photo 1. VLSI tester (rear view).
driver/receiver, a crystal oscillator time base, as well as the RAM and ROM memories. The test system utilizes a 72-line nonstandard bus which is available to all cards. Photo 1 shows the bus cabinet, including the CPU, 12 pin electronics cards, and the clock/controller card. Both polled and interrupt I/O are used. Interrupts are utilized for asynchronous character I/O via the UART as well as for counter runout and shift register clock event signalling. When the test memories are being circulated at a slow clock rate, individual shift pulses interrupt the microcomputer so that single bit shift register memory transactions may take place. At test speeds, single shift pulses may occur at speeds greater than the microcomputer clock rate. To avoid problems in trying to service interrupts at such an impossible rate, these interrupts are masked during test runs. The clock / controller
This card is the heart of the tester. The master clock/controller unit is a simple Moore-model finite state machine that generates the signals required by the per-pin electronics. During selected states, the state machine waits for an internal clock-speed control counter to overflow (refer to the diagram in Fig. 3). It is via this mechanism that the microcomputer controls the tester clock rate. For example, by loading FFFFl,, into the speed control counter, no delay is incurred (since the counter overflows whenever it gets clocked) and the maximum speed test clock is generated. If the value FFFS,, is loaded, however, an &cycle delay is inserted. Use of a 16-bit counter for clock speed control allows a wide range of clock speed settings (from about 2 KHz to over 4 MHz for a 25 MHz main internal time base). The delay introduced by the clock speed control counter stretches the width of the chip-under-test’s phase 1 and phase 2 clocks as well as tester-internal levels. Single-clock pulses internal to the tester are not stretched. In this way, correct
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S.E. Butner / Evaluation of a prototype VLSI tester timing
and control
signals
clock mode+
1. t p,reload J delay enable A
JIP bus
Fig. 3. Block diagram of the clock/controller.
timing relationships are automatically maintained. Figure 4 shows the derived control signals. There are many weaknesseswith the existing design. The most severeis that the approach requires too much headroom in frequency. The fact that parts of the clock circuitry must operate an order of magnitude faster than the final clock output limits the top-end testing frequency. A second problem revolves around the use of a counter to delay the user-level clock. While this provides a wide range of delays and is easy to implement, the design is not functionally well-suited at the top end of the frequency range. The insertion of a single delay count halves the clock output frequency, for example. The settings at the high frequency end are much too coarse. Another problem is that the current clock design does not allow adjustment of non-overlap times; both clock phasesare always identical. It is often desireableto be able to set the phase 1 and phase 2 high times as well as
Main Output
Clock Latch
Shift
Phi-l
Shift
Phi-2
Input
Latch
r
r
l-l
l-l 1
-1
r
1
r
1
I
r
UUT Phi-l UUT Phi-2
1 Clk OLatch S-l &2 ILatch Phi-l&2
internal time base (approximately 25MHz) pulse to latch UUT ‘output’ pins 2-phase clock for MOS shift register pulse to latch UUT ‘input’ pins P-phase clock as seen by UUT Fig. 4. Control signal thing diagram.
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Photo 2. Prototype
oj a prototype
VLSI tester
281
VLSI tester (front views).
their non-overlap times independently. The only ‘adjustment’ available in the prototype tester is the clock mode control, a static level (implemented as a toggle switch on the front panel) indicating whether the chip under test uses single-phase or two-phase clocks. The next version of the tester system will contain a clock design with flexibility in adjusting both high time and non-overlap time for the two clock phases independently. The new clock controller also requires significantly less headroom and has more flexible control over top-end frequency. The vector memory and pin electronics This is the ‘business end’ of the tester. The logic and electronics associated with any pin of the UUT (unit under test) is called a ‘pin register’. In the prototype unit, four pin registers are implemented on a printed circuit card (see Photo 1). Each single pin register has a 256-bit dynamic MOS shift register (aAMD2802) to hold test stimuli and responses. The shift register is continuously clocked. There is a multiplexer (controlled by the microcomputer) which steers
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Fig. 5. Organization of a pin register unit.
the end bit of the shift register. The block diagram of Fig. 5 illustrates the basic organization. The microcomputer accessesinformation within the shift register by first setting the master clock to a very slow shift rate (in the 4-5 KHz range) and then enabling interrupts for each shift event. When interrupted, the microcomputer can read or write the current bit of any pin register via memory-mapped I/O. The steering multiplexer is used to control accessto the input side of the shift register. Whenever the shift register is required to idle (i.e. to simply retain its contents) the steering multiplexer is set to recirculate the shift register output back to its input. During testing, other settings of the steering mux are used. The exact setting depends on the user-specified direction of the pin under test. Table 1 gives the steering multiplexer details. Now we consider the problem of dealing with bi-directional or tri-state pins. For a portion of the time the tester must drive such pins as if they were inputs and part of the time such pins will drive the tester. There are a couple of ways of handling this type of reversible drive: tri-stateable pin register drivers or ‘fighting’ drivers. The control problems associated with switching pin register drivers on and off are much more complex than the other approach, but this technique is electrically superior. If ‘fighting’ drivers are used, the pin under test must be able to overpower the drive of the test stand (which, of course, is made weaker than it normally would be). In caseswhere the pin under test pulls one direction while
Table 1 Steering multiplexer settings M&X
Selectedinput
00 01 10 11
Test pin value Logic ‘0 Data bus bit Shifter output
Use For output pins To clear register For loading register For input pins or recirculation
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VLSI tester
to/from pin of unit under test
om shift
register
Fig. 6. Directionality control via auxiliary registers.
the test stand goes in another, a voltage divider is established. In order to make minimal assumptions as to the drive capability of units under test, the ‘fighting’ approach was not used in our tester. The current VLSI test stand uses the more complex tri-stateable driver method instead. When the pin under test acts as an output pin, the tester must correctly latch and store the output value. When acting as an input pin, the tester must drive a test datum onto the pin. Role changesbetween input and output behavior can happen at full clock rate and, thus, the microcomputer cannot be involved in the control of directionality. In the prototype tester we use 10 extra pin registers (which we call auxilimy registers) to control the direction of other regular pins. The value at the read-out of any auxiliary register may be used to control the direction of any set of regular pins. This control is achieved via the selection logic shown in Fig. 6. The ten auxiliary registersdrive bus lines AUXOl-AUXlO which are shown as inputs to the direction control multiplexer. This circuit is included for each pin register so that there is independent control of directionality. As is the casefor the steering multiplexer, the latch for the bidirectionality control mux is accessibleto the microprocessor via memory-mapped I/O. Packaging
and fixturing
in the prototype
tester
Issuesrelating to packaging and fixturing are test fixture(s) for interconnecting the unit under test, power/ground switching, signal shielding, and power supply regulation and adjustability. In these areas, the prototype is relatively primitive (refer to Photo 2). There is only a single 40-pin, zero-insertion-force socket for connection to the unit-under-test. This has proven to be adequate since the majority of parts being tested have 40 or fewer pins and are packaged by the fabricator. Power and ground connections are done externally via patch cables. This has also worked adequately, although there is more noise on power and
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ground leads than we sometimes would like. There is only a single switching-type power supply (+ 5 V, - 5 V, + 12 V, - 12 V) for the entire tester. It supplies all tester logic as well as the electronics of the tester itself. Signal shielding is not needed due to the low frequency of tester operation (below 5 MHz at test pins) and the short distance between the test socket and the pin electronics. Details of the command
interface
The user interface of the VLSI test stand is intended to be simple to learn and use.All commands are indicated by a single character; pin registers are numbered 01-40 (in decimal). The auxiliary registers are numbered 41-50. Registers can be assignedsymbolic names up to 8 charactersin length. Binary test vector information is accepted and displayed in hexadecimal. Any pin register (including the aux registers) can be loaded or read-out via commands received over the .RS-232 port. All data flowing through this port is coded in a printable subset of the ASCII code and is designed to be human-readable. ‘White space’, i.e. spaces,tabs, carriage~returns,and line feeds are ignored by the tester. These characters can be used to make the command stream more readable. Comments can be included in the stream as well. A comment begins with a semicolon ( ; ) and extends through the next carriage return or line feed. An ordinary computer terminal with an RS-232 interface can be plugged directly into the ‘host’ port of the tester (instead of a general-purpose host computer). Table 2 VLSI tester command summary Command
Description
cxxxx Dxx(type)(name).
Set clock speed to xxxxld Define (type) of pm xx,e with symbol (name) as: I...input pin 0.. . output pin 1.. . clock phase 1 2.. . clock phase 2 Byy . . . bidirectional, per aw register yyta. Display and clear error counts Fill pin register (name) with yyld Load pin (name) with bit string (hex) Master reset Toggle ‘quiet’ mode (echo on/off) Read-out pin (name) (as hex string) Read-out all defined pins Begin cyclic test (circular shift, applying all 256 bits repeatedly) Display software version ID Execute one-shot test (apply defined bit strings once) Exit cyclic test (seeT above)
E F(n=@w L(name)xxxx.. . a” R( name) RT V X z
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285
The presence of editors, as well as data storage and analysis tools of a host machine make the host-oriented approach vastly preferred. An internal DIP switch allows specification of the baud rate. The commands available in the prototype VLSI tester are summarized in Table 2. The general sequencefor testing a chip consists of M (master reset), D (define pin types and symbols), L (load input vectors), C (set clock speed), X (execute test), R (read-out result vectors). Host-resident programs are available to display input and output vectors in a logic-analyzer type format as well as to convert test streams to and from CAD databaseformats.
A simplified
example
Consider the test setup for an MS1 parallel-load binary up/down counter, the 74193 [3] which should be familiar to most readers.Our sample test will consist of 20 clocks in up-count mode with an asynchronous clear applied before the first and fourth clocks and a parallel load signal applied after the fifth clock. This is clearly not a comprehensivetest; it is presentedhere merely to illustrate the ease Table 3 User input to test 74193 up/down counter M C FF80 D14i CLR* . DOS UP. D04i DWN. Dlli LD*. D15i IA. DOli IB. DlOi IC. D09i ID. DO30 OA. DO20 OB. DO60 oc. DO70 OD. L UP 55555555550000. L DWN 00000000000000. L CLR* 7DFFFFFFFFFFFF. L LD * FFDFFFFFFFFFFF. L IA 00200000000000. L IB 00200000000000. L IC FFOFFFFFFFFFFFF. L ID FF2FFFFFFFFFFFF. RX R-
;te.st stand master reset ;set test clock rate (FF80 = - 100 kHz) ;declare CLEAR- BAR input pin ;COUNT-UP input pin ;COUNT- DOWN input pm ;LOAD _ BAR input pin ;IA (low-order) ;IB parallel ;IC load data ;ID (high-order) ;OA (low-order) ;OB parallel ;oc output ;OD (high-order) ;COUNT-UP input (20 0- > 1 transitions) ;COUNT- DOWN input ;Clear after 3rd count pulse ;asynch CLEAR- BAR input ;LOAD _ BAR control ;l (parallel ;l load ;0 vector) ;1 ;read-back all loaded registers ;run a single test (length = 56) ;read-back test results
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of use of our tester. In the example, we first reset the tester, then define the pin types. All pin types should be defined before any of the pin registers are loaded. The physical set-up involves turning on the tester, placing the chip under test into the test socket (in this case a special converter socket must be used since the tester has a 40-pin socket), and connecting the +5 V and ground leads to the appropriate pins. In this case + 5 V should be plugged into the jack for pin 16 and ground should be connected to pin 08. The LEDs corresponding to these two pins will immediately indicate their ‘logic’ states. The tester should be connected to a terminal and thus the RS-232 mode switch should be set to ‘TERMINAL’ (rather than ‘HOST’). The user input (with extra comment material added for readability) is given in Table 3. When applied to the tester, the input (Table 3) causesthe following response: - During input, the incoming characters are echoed to the terminal, - When the ‘R-command is executed, the contents of all registers are readback and printed in hexadecimal on the terminal. - The LEDs flash for a brief moment when the 56 test vectors are applied. - The final ‘R’ command requests a snapshot of test vector memory after application of the test. Subsequently, host-resident software can be used to get a logic-analyzer-style plot of the test results. Alternatively, the tester can be placed into cyclic test mode (see description of the ‘T’ command in Table 2) for interactive oscilloscope probing of signals on pins of the unit under test. Improvements
in the tester for increasing
test speed
The existing prototype VLSI tester has been used to functionally test and roughly characterize many student project chips during 1984 and 1985. As a result of our experience with the tester, a new and improved version is currently under development. The improvements focus primarily on increasing top-end test speed. Faster clock/
controller
At the heart of the current speedlimitation is the master clock/controller. This subsystem has been redesigned.The current implementation as a state machine uses too many states per test cycle, thus requiring some parts of the clock generation logic to respond to frequencies 8 to 10 times those seenat the test pin. If we are to achieve our goal ( > 20 MHz clocks at the test pin) this ‘headroom’ factor of ten in frequency clearly cannot continue to exist. The new clock/controller design has an adjustable range from 30 KHz to over 30 MHz with very fine-grain control at the top end. The high-time and non-overlap time of the two clock phases are individually controllable. The circuit is a cross-coupled NOR with a programmable delay inserted in the feedback paths. Reference[6] describesthe new clock/controller in detail.
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test length counter
Above 2 MHz the Intel 8253 (in the current design) cannot reliably count test events. Since our design goal for the new tester is much faster than 2 MHz, we must redesign and repackage the test length counter. The ultimate solution is a special-purpose VLSI chip integrating several now-separate functions. Integrated
pin register/counter
chip
The first version of a new fully-custom NMOS VLSI chip has been fabricated by MOSIS [4]. The new chip (refer to Fig. 7) houses the electronics for 8 pin registers, each with its own bidirectionality (auxiliary) register. In addition, the chip has a parallel-load down counter for use in accurately controlling test length.
Fig. 7.
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With 8 VLSI chips, we will have the required electronics can easily be package on a single printed circuit card. Software and microcomputer
for a 64-pin tester. This
changes
No changes to the microcomputer are planned (with the possible exception adding more RAM). The software is, of course, undergoing modifications interface correctly with the new VLSI tester electronics. Bootstrapping
of to
to very high speed
As part of a three-year program to study and develop design principles for Gallium-Arsenide integrated circuits, a very high-speed tester wiIl be required. We plan to rely on the experience with the structures used in the current and second generation VLSI tester to gradually bootstrap ourselves (via succession of increasingly faster versions) into the gigahertz test speeds required for GaAs parts. The ultimate goal is a GaAs test stand which is made primarily from custom GaAs integrated circuits.
We have presented the design of a special-purpose hardware subsystem for functionally testing custom NMOS and CMOS integrated circuits. Experience with a prototype version of the tester has encouraged us to construct a more advanced system with a test speed goal of 20 MHz. The new version utilizes full-custom NMOS VLSI chips to improve the packaging, size, speed, and overall reliability of the test stand. The current and planned tester architectures are being evaluated and modified in order to serve as the basis for much faster test systems.
References [l] Swan, R.,.and C. McMinn, ‘General-purpose tester puts a separate set of resources behind each VLSI-device pin’, Electronics (8 September 1983) 101-106. [2] Mead, C. and L. Conway, Introduction to VLSI Systems (Addison-Wesley, Reading, MA, 1980). [3] Texas Instruments Inc., The TTL Data Bookz, Vol. 1 (1984). [4] “MOSIS, what it is and how to use it”, Information SciencesInstitute, University of Southern California, ISI/TM-84-128, March 1984. [5] BorrieIIo, G., R. Katz, and A. BeII, “The multibus design frame”, EECS Report #UCB/CSD 85/232, University of California, Berkeley, CA, 1985. [6] Akkawi, I., “Design of a high speed test stand for prototype VLSI chips”, MS thesis, Department of Electrical & Computer Engineering, University of California, Santa Barbara, CA, 1985.