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Evaluation of critical surface cleanliness by secondary ion mass spectroscopy
1190
World Abstracts on Microelectronics and Reliability
This paper presents the evaluation results of thermocompression GANG Bonding of gold-plated TAB outer leads to three kinds of metallized ceramic substrates. GoldSelective Plating (GSP) substrates for multi-chip package. Thick Film (TF) substrates for multi-chip package and Single Chip Packages (SCP) which have a trimetal combination of refractory metal (tungsten), Nickel and Gold. The bonding parameters such as the bonding tool (thermode) temperature, pressure, bonding time and preheat temperature were examined on each substrate to get optimum values. As the result, a relation between pull strength and the lead deformation shows that the TAB leads should be bonded with 15-65 percent deformation, the recommended parameters are; the tool temperature of 380-430°C, the bonding pressure ranging from 35 to 45 kg/mm 2, with the preheat temperature of 150°C and the bonding time from 1.0 to 2.5 seconds. The evaluation of initial bondability shows that TAB GANG Bonding has the capability of excellent bonding strength; above 120 grams with standard deviation of less than 20 grams, and the necessity of OLB pads flatness; less than _+12~m for one ounce copper lead. The normal storage of the substrate and the lead does not affect the bondability. And the results of accelerated aging test of 125°C, 150°C and 175°C for more than 8,000 hours show that a lifetime of greater than 70 years at 65°C operating temperature is predicted. The effective activation energy for the pull strength degradation is 0.86-1.05 eV. This is in reasonable agreement with predictions for interdiffusion of Cu-Au. And no significant degradation of the electric resistance was observed on the GSP samples. The feasibility and the high reliability of the GANG Bonding for gold-plated TAB outer leads were confirmed.
Bipolar VLSI builds 16-bit controller handling many fast peripherals at once. SUNIL JOSHI, DEEPAK MITHAN1 and STEVE STEPHANSEN. Electronics, 98 (November 30, 1981). Specialpurpose microprocessor has controller instruction set in microcode, manipulates three operands in one cycle. Optical requirements for projection lithography. W. G. OLDHAM, S. SUnP,AMANIANand A. R. NEUREUTHER.Solid-St. Electron. 24 (10), 975 (1981). An image modulation criterion is proposed as a simple optical performance parameter for lithography using positive photoresist. The modulation, or contrast, is defined in terms of the maximum and minimum intensity in the image of a line/space pattern as (/MAX-IMIN)/(IMAx +IM1N)" For lithography directly on integrated circuit wafers, a contrast in the range of 80-90 % gives acceptable linewidth control. Universal curves are derived showing image contrast for diffraction-limited optical systems with partially coherent illumination and including defocus error. The allowable defocus is derived as a function of the contrast requirement and pattern linewidth. Based on these optical considerations, and the properties of positive photoresists, the useful resolution of state-of-the-art projection systems are shown to be in the neighborhood of 1.25 lam, and progress to a useful resolution of about 0.5/am is forseeable. Evaluation of erilical surface cleanliness by secondary ion mass spectroscopy. R. K. LOWRYand R. G. MASTERS.IEEE/ Proc. 1RPS, 157 (1981). Surfaces of a wide variety of IC materials, from raw silicon wafers to package piece parts, must be ultra-clean prior to key manufacturing steps to assure reliable performance of the finished devices. Knowledge of surface cleanliness is essential for optimum process design. Secondary ion mass spectroscopy (SIMS) is utilized to define levels of impurities on critical surfaces at various stages of device manufacture. Multiware boards complete with microstrip and strip-line packaging. J. PHILIP PLONSKI,TOM BUCK and SAM SMOOKLER. Electronics, 143 (September 8, 1981). Discrete-wired
technique yields controllable impedances of 50-100ohms suitable for high-speed signals.
On-chip stereo filter cuts noise without preprocessing signals. MARTIN GILES. Electronics, 104 (August 11, 1981 ). A pair of dynamically variable low-pass filters reduces noise with no encoding of signal sources. Scaling merged single-device-well MOSFETs for very large scale integration. M. H. El.SAIDand M. I. ELMASRY.Solid-St. Electron. 24 (10), 967 (1981). Single-Device-Well (SDW) MOSFETs are high density MOSFET structures based on merging two MOSFET devices; a surface channel device and a buried channel device sharing the same device well and the same gate. SDWs offer a potential area saving of 50 %. The merits of the merged SDW MOSFETs are further enhanced in a scaled down MOSFET VLSI technology. This is the subject of this paper. Number of vias: a control parameter for global wiring of highdensity chips. D. T. LEE,S. J. HONGand C. K. WONG. IBM JI Res. Dev. 25 (4), 261 (1981). In integrated circuits, components are frequently interconnected by horizontal and vertical wires in respective wiring planes whether on chip, card, or board. The wire changes direction through "'vias" that connect the orthogonal wiring planes. Because of technology constraints, the arrangement of vias must conform with certain neighborhood restrictions. We present results on the guaranteed minimum number and maximum possible number of vias in a given wiring cell for various technology constraints. These numbers provide an early means of control on global wiring routes to further the success of the exact embedding process that follows global wiring. Leadless carriers, components increase board density by 6:1. P. R. JONES.Electronics, 137 (August 25, 1981 ). Vapor-phasesoldered components withstand military environments, decrease assembly costs.
Chip carriers--their application and future direction. J. W. STAFFORD. IEEE Trans. Components Hybrids Mfg Technol. CHMT-4 (2), 195 (1981 ). The need for chip carriers and chipcarrier standards is reviewed. Chip-carrier telecommunications applications as well as thermal characteristics of chip carriers are presented. Impediments to chip-carrier applications as well as future directions are reviewed. Low energy LSI and packaging for system performance. HISAO KANAI. IEEE Trans. Components Hybrids Mfg Technol. CHMT-4 (2), 173 (1981). By defining "power-time products" of digital functional blocks, processor performance can be quantitatively expressed by a parameter which is the product of equivalent energy Us and the thermal resistance Roa. The reduction of Us'RoB through system-oriented large-scale integration (LSI) technology in both chips and packaging is necessary for raising the level of system performance. Using this concept the correlation between gate energy levels for chips, packages, and processors in a hierarchy have been illustrated in four energy levels of gates: microjoule, 100p J, picojoule, and subpicojoule. The low energy current-mode logic (CML) chips and multichip packaging for the NEC ACOS series have been developed to reduce system energy through advanced LSI technology for their high performance. Reliability of TAB products. BILLCHAFFIN.Solid St. Technol., 136 (September 1981). The reliability of products utilizing Tape Automated Bonding (TAB) is discussed. The TAB process is described and the various factors contributing to high product reliability are pointed out. A summary of reliability test data is presented.
World Abstracts on Microelectronics and Reliability
This paper presents the evaluation results of thermocompression GANG Bonding of gold-plated TAB outer leads to three kinds of metallized ceramic substrates. GoldSelective Plating (GSP) substrates for multi-chip package. Thick Film (TF) substrates for multi-chip package and Single Chip Packages (SCP) which have a trimetal combination of refractory metal (tungsten), Nickel and Gold. The bonding parameters such as the bonding tool (thermode) temperature, pressure, bonding time and preheat temperature were examined on each substrate to get optimum values. As the result, a relation between pull strength and the lead deformation shows that the TAB leads should be bonded with 15-65 percent deformation, the recommended parameters are; the tool temperature of 380-430°C, the bonding pressure ranging from 35 to 45 kg/mm 2, with the preheat temperature of 150°C and the bonding time from 1.0 to 2.5 seconds. The evaluation of initial bondability shows that TAB GANG Bonding has the capability of excellent bonding strength; above 120 grams with standard deviation of less than 20 grams, and the necessity of OLB pads flatness; less than _+12~m for one ounce copper lead. The normal storage of the substrate and the lead does not affect the bondability. And the results of accelerated aging test of 125°C, 150°C and 175°C for more than 8,000 hours show that a lifetime of greater than 70 years at 65°C operating temperature is predicted. The effective activation energy for the pull strength degradation is 0.86-1.05 eV. This is in reasonable agreement with predictions for interdiffusion of Cu-Au. And no significant degradation of the electric resistance was observed on the GSP samples. The feasibility and the high reliability of the GANG Bonding for gold-plated TAB outer leads were confirmed.
Bipolar VLSI builds 16-bit controller handling many fast peripherals at once. SUNIL JOSHI, DEEPAK MITHAN1 and STEVE STEPHANSEN. Electronics, 98 (November 30, 1981). Specialpurpose microprocessor has controller instruction set in microcode, manipulates three operands in one cycle. Optical requirements for projection lithography. W. G. OLDHAM, S. SUnP,AMANIANand A. R. NEUREUTHER.Solid-St. Electron. 24 (10), 975 (1981). An image modulation criterion is proposed as a simple optical performance parameter for lithography using positive photoresist. The modulation, or contrast, is defined in terms of the maximum and minimum intensity in the image of a line/space pattern as (/MAX-IMIN)/(IMAx +IM1N)" For lithography directly on integrated circuit wafers, a contrast in the range of 80-90 % gives acceptable linewidth control. Universal curves are derived showing image contrast for diffraction-limited optical systems with partially coherent illumination and including defocus error. The allowable defocus is derived as a function of the contrast requirement and pattern linewidth. Based on these optical considerations, and the properties of positive photoresists, the useful resolution of state-of-the-art projection systems are shown to be in the neighborhood of 1.25 lam, and progress to a useful resolution of about 0.5/am is forseeable. Evaluation of erilical surface cleanliness by secondary ion mass spectroscopy. R. K. LOWRYand R. G. MASTERS.IEEE/ Proc. 1RPS, 157 (1981). Surfaces of a wide variety of IC materials, from raw silicon wafers to package piece parts, must be ultra-clean prior to key manufacturing steps to assure reliable performance of the finished devices. Knowledge of surface cleanliness is essential for optimum process design. Secondary ion mass spectroscopy (SIMS) is utilized to define levels of impurities on critical surfaces at various stages of device manufacture. Multiware boards complete with microstrip and strip-line packaging. J. PHILIP PLONSKI,TOM BUCK and SAM SMOOKLER. Electronics, 143 (September 8, 1981). Discrete-wired
technique yields controllable impedances of 50-100ohms suitable for high-speed signals.
On-chip stereo filter cuts noise without preprocessing signals. MARTIN GILES. Electronics, 104 (August 11, 1981 ). A pair of dynamically variable low-pass filters reduces noise with no encoding of signal sources. Scaling merged single-device-well MOSFETs for very large scale integration. M. H. El.SAIDand M. I. ELMASRY.Solid-St. Electron. 24 (10), 967 (1981). Single-Device-Well (SDW) MOSFETs are high density MOSFET structures based on merging two MOSFET devices; a surface channel device and a buried channel device sharing the same device well and the same gate. SDWs offer a potential area saving of 50 %. The merits of the merged SDW MOSFETs are further enhanced in a scaled down MOSFET VLSI technology. This is the subject of this paper. Number of vias: a control parameter for global wiring of highdensity chips. D. T. LEE,S. J. HONGand C. K. WONG. IBM JI Res. Dev. 25 (4), 261 (1981). In integrated circuits, components are frequently interconnected by horizontal and vertical wires in respective wiring planes whether on chip, card, or board. The wire changes direction through "'vias" that connect the orthogonal wiring planes. Because of technology constraints, the arrangement of vias must conform with certain neighborhood restrictions. We present results on the guaranteed minimum number and maximum possible number of vias in a given wiring cell for various technology constraints. These numbers provide an early means of control on global wiring routes to further the success of the exact embedding process that follows global wiring. Leadless carriers, components increase board density by 6:1. P. R. JONES.Electronics, 137 (August 25, 1981 ). Vapor-phasesoldered components withstand military environments, decrease assembly costs.
Chip carriers--their application and future direction. J. W. STAFFORD. IEEE Trans. Components Hybrids Mfg Technol. CHMT-4 (2), 195 (1981 ). The need for chip carriers and chipcarrier standards is reviewed. Chip-carrier telecommunications applications as well as thermal characteristics of chip carriers are presented. Impediments to chip-carrier applications as well as future directions are reviewed. Low energy LSI and packaging for system performance. HISAO KANAI. IEEE Trans. Components Hybrids Mfg Technol. CHMT-4 (2), 173 (1981). By defining "power-time products" of digital functional blocks, processor performance can be quantitatively expressed by a parameter which is the product of equivalent energy Us and the thermal resistance Roa. The reduction of Us'RoB through system-oriented large-scale integration (LSI) technology in both chips and packaging is necessary for raising the level of system performance. Using this concept the correlation between gate energy levels for chips, packages, and processors in a hierarchy have been illustrated in four energy levels of gates: microjoule, 100p J, picojoule, and subpicojoule. The low energy current-mode logic (CML) chips and multichip packaging for the NEC ACOS series have been developed to reduce system energy through advanced LSI technology for their high performance. Reliability of TAB products. BILLCHAFFIN.Solid St. Technol., 136 (September 1981). The reliability of products utilizing Tape Automated Bonding (TAB) is discussed. The TAB process is described and the various factors contributing to high product reliability are pointed out. A summary of reliability test data is presented.