- Email: [email protected]
Evaluation of double sided, AC-coupled, double metal silicon strip detectors for H1 at HERA
NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH
Nuclear Instruments and Methods in Physics Research A 348 (1994) 454-460 North-Holland
Sect,onA
Evaluation of double sided, AC-coupled, double metal silicon strip detectors for H1 at HERA** D. Pitzl a,*, R. Eichler
a
W. Erdmann
a
K. Gabathuler
b, R.
Horisberger
b
M. Wagener b
a Institut fiir Teilchenphysik, E T H Ziirich, CH-5232 Villigen-PSI, Switzerland b Paul Scherrer Institut, CH-5232 Villigen-PSl, Switzerland
Prototype double sided silicon strip detectors for the H1 vertex detector have been fabricated. The design uses integrated coupling capacitors on both sides and a second metal layer with readout lines on the n-side. Measurements of leakage currents, sheet resistances, metal line quality and contact reliability all show satisfactory results. A multi-guard structure improves the high-voltage and long-term stability of the detectors. The accumulation layer channel resistors on the n-side showed dramatic radiation effects after 6°Co doses of 100 krad and an improved design with a metal gate electrode is demonstrated. Interstrip capacitances have been measured systematically on test structures with various geometries. The capacitance due to the second metal layer on the n-side has been measured for a 2 tzm SiO 2 and a 6 Ixm polyimide dielectric. Up to now, integrated coupling capacitors could not be fabricated with sufficiently low defect rates.
1. Motivation A silicon vertex detector is currently being built for the H1 experiment at HERA [1]. It is designed to tag charm events in order to reduce the light quark background for charm studies. At HERA charm quark pairs are produced in the photon-gluon fusion process which allows a direct measurement of the gluon structure function of the proton. At full luminosity about 108 charmed particles will be produced per year which opens a wide field of topics in rare charm decays. In charm events the most probable track momentum is about l G e V / c and the vertex resolution has a large contribution from multiple scattering. Consequently, the amount of material used in the beam pipe and the support structure for the vertex detector must be kept at a minimum. A second constraint derives from the extended interaction region at HERA, which has a length of about 20 cm FWHM when the 208 MHz RF system for the proton beam is used. The proposed vertex detector consists of two layers of double sided silicon strip detectors around a new carbon fiber beam pipe of 90 mm diameter. The active detector length is 35.4 cm, covered by six silicon detectors in a row with preamplifiers at both ends. The effective strip length is limited by the interstrip capacitance loading the preamplifiers and the desired signal-to-noise ratio. We
* Corresponding author. ** Work supported in part by the Swiss National Science Foundation.
have developed an amplifier and pipeline chip that achieves a ratio of 15 : 1 at a load of 30 pF [2]. Double sided silicon strip detectors offer an efficient way of obtaining two-dimensional position information by collecting the induced signals from drifting electrons and holes on segmented anodes and cathodes, called n-side and p-side, respectively. The strips on the two sides are orthogonal in order to achieve comparable position resolutions in both projections. The strips on the p-side are running along the beam direction for a measurement of the q~-coordinate and are directly bonded to the preamplifiers, while the n-side strips, measuring the z-coordinate, require special readout lines. One option is to use a separate fanout print on a Kapton or glass substrate [3,4]. However, it is difficult to achieve the necessary density of readout lines on these substrates and the assembly of the vertex detector becomes more complicated. Historically, the development of silicon strip detectors was driven by the application of planar IC technology to wafer-scale devices on high resistivity silicon. Today, double metal CMOS processes are widely available and can be adapted to provide integrated readout lines for the n-side strips. The critical aspect is the intermetal dielectric which should be as thick as possible to reduce the stray capacitance while maintaining highly reliable contacts between the metal layers. Here we report on two prototypes using 2 txm SiO 2 and 6 txm polyimide as the intermetal dielectric. Coupling capacitors are used to prevent the strip leakage current from entering the preamplifiers, which is then absorbed by bias resistors integrated on the detector. The coupling capacitance should be at least ten times larger
0168-9002/94/$07.00 © 1994 - Elsevier Science B.V. All rights reserved SSDI 0 1 6 8 - 9 0 0 2 ( 9 4 ) 0 0 3 9 2 - K
D. Pitzl et aL / Nucl. Instr. and Meth. in Phys. Res. A 348 (1994) 454-460
than the interstrip capacitance to avoid signal spreading, which requires values of 15-20 p F / c m . This is achieved by an SiO 2 layer of 200 nm thickness between the strip implant and the metallisation. On double sided detectors, the n-side strips are usually raised to the bias voltage while the p-side is held at ground potential. The coupling capacitors may then be used to separate the DC-levels and operate the n-side preamplifiers at ground potential, making the design of the readout hybrid less demanding. However, if one coupling capacitor breaks, the preamplifier channel immediately saturates and neighbouring channels may be affected as well. On the detector the electric field is disturbed over a region of about 600 Ixm. As a precaution, it is therefore foreseen to operate the front-end electronics for the n-side at the bias voltage, in which case a defect capacitor causes a shift in the DC operating point of just one preamplifier channel. The rate of defect coupling capacitors should be less than 1% on each detector side. A further motivation for using integrated coupling capacitors on the n-side is to provide n-strip isolation by the field plate effect, where the metal is made wider than the strip implant and biased as to interrupt the electron accumulation channel at the substrate surface. However, in our design the n-strip isolation is achieved by an intermediate p-blocking implant. It is not yet established which technology is to be favoured in terms of interstrip capacitance. The radiation dose in the H1 vertex detector from scattered synchrotron radiation and proton beam background during stable operation at the design luminosity is expected to be about 1 krad per year. A much higher dose will be accumulated during injection, beam tuning and accidental beam losses. Prototypes of our front end chip showed tolerable performance degradation for doses up to 100 krad. The silicon detectors have been irradiated to the same dose.
455
on the substrate. The boron implant for the p-side strips has a sheet resistance of 280 1 2 / [ ] and a lateral diffusion of 0.5 Ixm on each side, as determined from 4-point resistors of varying width. The implanted strip pitch on the p-side is 25 Ixm. Every second strip is metallised and read out while the intermediate strips induce signals on their neighbours by capacitive charge division. A metal line thickness of 0.9 ixm was determined from the measured resistance, and the drawn line width is reduced by,2 ixm during etching, The active strip length is 57.6 mm and the width of the active detector area is 32 mm, covered by 640 readout strips. The full size of one detector ai~ter cutting is 59 mm × 34 mm, such that two detectors fit on one wafer. The p-strips are biased from a common guard ring by the punch-through effect across a 5 Ixm gap. The phosphor doping for the n-side strips has a sheet resistance of 13 1 2 / O . The strip length is 32 mm and the pitch was chosen to be 44 ixm, again with every second strip metallised and read out. The first metal layer has a thickness of 0.4 mxm. A second metal layer contains 640 readout lines at 50 Ixm pitch, each connected to one metallised n-strip, (see Fig. 1). A layer of 2 Ixm SiO 2 was used for the intermetal dielectric in our series while 6 Ixm polyimide was used in a second series fabricated for the DELPHI collaboration [7]. The metal-2 lines have a thickness of 0.9 Ixm and the line width is reduced by about 0.5 ixm during etching. The ohmic separation of the n-strips is achieved by an intermediate p-blocking implant which has a sheet resistance of 2600 1 2 / O , corresponding to a surface doping of 5 X 1012/cm 2, assuming. 100% activation. The n-strips are biased from a common guard ring through accumulation channel resistors, which are defined by the p-blocking implant (Fig. 1). Integrated coupling capacitors on both sides are formed by an SiO 2 layer with a thickness of 200 nm between the strip implant and a polysilicon layer, which is in contact with the metal line. The field oxide, which covers the
2. Design and technology Prototype detectors and test structures were fabricated on high resistivity n-type wafers of 100 mm diameter and 300 txm thickness from Wacker Chemitronic. The resistivity, as determined from diode C - V curves, varied between 9 k O cm and 24 k12 cm for the wafers in this batch. On a single wafer resistivity variations of 10% from the center towards the edge were found using the n-side strip isolation to determine the depletion voltage locally. The corresponding drift field deformations are not yet large enough to deteriorate the position resolution. The processing was performed at CSEM [5] based on the technology developed for the ALEPH silicon vertex detector [6]. The mask design is supplied by the customer with design rules corresponding to a 3 Ixm CMOS process. The process has two implants on each side of the wafer, which are precisely aligned with the help of marks etched
Fig. 1. Details of the CAD design for the n-side. Metal-1 and metal-2 are shown in black,' n+-implant is dark grey and the p-blocking implant is light grey, leaving accumulation channel resistors in white. Contacts between metal-1 and metal-2 are running diagonally across the detector. III. SEMICONDUCTOR DETECTORS
456
D. Pitzl et al. /NucL Instr. and Meth. in Phys. Res. A 348 (1994) 454-460
substrate between the strips, has a thickness of 0.9 p~m on both sides. The wafers are passivated by a layer of SiO 2 on both sides with etched contacts for the bond pads. Bond pads on the n-side are formed on the first metal layer and increased in thickness by metal-2 deposition. Bond pads must not be produced on metal-2 alone, since bonding may introduce mechanical stresses when SiO 2 is used for the intermetal dielectric, while polyimide is rather soft and may be difficult to bond on.
Fig. 2. The floating guard ring potentials were measured with the high impedance source and monitor units of an HP4145B Semiconductor Parameter Analyser. The detectors can be biased up to 200 V without breakdown. We conclude, that multi-guard structures, although not mandatory for the successful operation of silicon detectors, offer increased high-voltage and possibly also long-term stability and can be included in many designs without extra processing steps and without increasing the non-sensitive detector area. 3.3. Punchthrough biasing
3. Results 3.1. Leakage currents
The total leakage current for the strip detectors after wafer cutting was between 50 n A / c m z and 100 n A / c m 2, measured at room temperature and 10 V above full depletion. These values are satisfactory, given the complexity of the process. Strip leakage currents of 50 nA (corresponding to 1500 n A / c m 2 in this case) start to contribute to the noise of our preamplifier. One test structure was placed at a distance of only 5 mm from the flattened edge of the wafer and showed leakage currents between 200 n A / c m 2 and 3000 n A / c m e. We conclude that the safe region for good detectors has a diameter of at most 90 mm on a 4 in. wafer. The leakage current of one detector was monitored for six months under permanent bias and did not increase over this period. 3.2. Multi-guard structure
All silicon detectors have a guard ring implant that surrounds the active area on the p-side and collects the leakage current generated at the detector edges. For stable operation it has to be placed at a distance equivalent to about two wafer thicknesses inside the scribe line, such that the depletion region does not reach the edges. In the CSEM process the scribe line region on the p-side receives an n-type implant to avoid surface inversion and depletion, which can be caused by negative charges that may accumulate on the passivation oxide. Positive charges in the oxide, on the other hand, lead to an accumulation layer at the substrate surface which reduces the width of the depletion region and consequently increases the electric field strength. Surface avalanche breakdown is then considered the most common breakdown mechanism on silicon detectors. The high-voltage stability can be improved by adding a multi-guard structure between the first guard ring and the scribe line implant [8]. Our design consists of five floating guard ring implants with a width of 25 Ixm and separated by 50 Ixm gaps, as shown in the insert of Fig. 2. The gaps are covered by floating metal gates on a thin oxide. This structure spreads the bias voltage drop at the surface over a distance of 300 p~m and several p - n junctions, as shown in
The strips on the p-side are biased from the innermost guard ring by the punchthrough effect across a short gap [9]. This p - n - p structure has an exponential I - V characteristic once the potential difference between the strip and the guard ring exceeds a certain threshold voltage. In our application it is more appropriate to regard the strip leakage current as the independent variable which then determines the strip potential. With the guard ring held at ground potential, the strip potential becomes positive after punchthrough, thus reducing the effective bias voltage between p-side and n-side. This is shown in Fig. 3 for strip leakage currents from 1 nA to 1 p,A. Due to the exponential I - V characteristic the strip potential changes by just 1 V over this range. The dynamic resistance of the punchthrough structure is roughly proportional to 1 / I , reaching 3 MI~ at a strip leakage current of 50 nA. For smaller resistance values the bias resistor starts to contribute to the preamplifier noise. Measurements taken after a 6°Co irradiation of 100 krad are also shown in Fig. 3. The punchthrough threshold voltage increased by 1 V while the dynamic resistance did not change. The punchthrough structure can be refined to a MOSFET device by adding a gate electrode on the oxide covering the punchthrough gap [10]. This FOXFET is operated in the subthreshold region to achieve a large
200
.
.
.
.
I
,
,
,
•
i
.
.
.
.
i
.
.
.
.
0V vdng V ~ --X Y ~ -~-'=_/--/-acive Inner area
~
4
3
2
~
gua~
dng 0 / /
/%
1 0 rHlCdoeline rlngm
70O I~rn
2
n-n
>
100
50
0
.
.
.
.
i
50
.
.
.
.
i
.
.
100
.
.
i
150
.
.
.
.
200
Vb,,,' [ V ]
Fig. 2. Floating guard ring potential for the multi-guard structure. The insert shows a vertical section of the detector.
D. Pitzl et al. /Nucl. Instr. and Meth. in Phys. Res. A 348 (1994) 454-460 5
. . . . . . . .
i
. . . . . . . .
i
i
......
..:10
8
. . . .
1000000
i
. . . .
Wdrav~ = 8
4.
.
.
.
.
i 1
457 . . . .
i
.
~ i
1
,
I
,
,
,
,
2
". . . . . . . . . . . . . . . . . . .
100 krlld 3'
~
107
~
100000~
W d ~ ~ = 8 ~ITI 10
2.
10000-
10 8
1-
010.0
........
, 10 "s
........
, 10-7
.
.
.
.
.
.
.
I000
I0 s 10"6
....
Fig. 3. Punchthrough voltage and dynamic resistance for a 5 txm gap and a strip implant width of 12 /xm at 60 V bias before and after 100 krad 6°Co irradiation.
dynamic resistance and the gate potential is used to control the strip potential. We do not see a compelling reason to add this extra electrode, which has to be supplied from the front-end hybrid. The value of the punchthrough voltage can be optimised at the design stage by choosing the gap length. In Fig. 4 we show the punchthrough voltage obtained for test structures with various gap lengths and strip implant widths. A gap length of 4 txm is minimal in the CSEM process, due to the lateral diffusion of the p implants, and we chose a value of 5 Ixm for the detectors. The uniformity of the punchthrough voltage has been measured on several detectors. The maximum variation over 640 strips was 1.2 V, while the local variations between neighbouring strips were always below 0.2 V. The resulting distortions in the drift field are negligible.
35
,
=
30-
• •
25-
•
J
,
l
l
=
,
,
l
,
w. 6pro w~ 8pm w ~ 101xm w= 12wn
l
l
l
_e •
>
] i
20-
|
lO
! |
. . . .
;
1'o . . . .
2'o . . . . Vb=,o
I trl p [ A ]
. . . .
1'o . . . .
15
[~tm]
Fig. 4. Punchthrough voltages at 1 nA strip leakage current and 60 V detector bias for test structures with various gap lengths and strip widths. Values are the drawn dimensions.
3'0 . . . .
;0 . . . .
co
[V ]
Fig. 5. Accumulation channel resistance normalized by the channel length and the effective width just above full depletion for nominal channel widths of 8, 10, 12 and 20 txm before and after • . . 100 krad 6 0 Co irradiation.
3.4. Accumulation channel resistors Accumulation channel resistors for strip biasing on the n-side are a standard feature of the CSEM process. They are formed by the p-blocking implant between the end of the n-strips and the n-side guard ring. The conduction mechanism is due to an electron accumulation layer at the substrate surface caused by positive charges trapped in the field oxide. Once the detector is fully depleted to suppress any conduction through the substrate the resistance is given by the usual relation p R~----
L
d ( w - ~)'
where L and W are the drawn length and width of the channel, p / d is the sheet resistance and W - E the effective width. However, it was found that the resistor value increases with bias voltage even above full depletion, as shown in Fig. 5. By using test structures with varying width it could be established that the sheet resistance remains constant at 18.5 1 2 / [ ] while the effective channel width is being reduced at higher bias voltage. Radiation effects have been studied with a 6°Co source for doses up to 100 krad. The fixed oxide charge increased by a factor of four from an initial value of 2 × 1011/cm2 in both the field oxide and the thinner coupling oxide, as determined from MOS-capacitor C - V curves. The accumulation channel resistance did not decrease, as expected, but increased dramatically and became more strongly bias voltage dependent (see Fig. 5). The sheet resistance increased to about 100 k 1 2 / [ ] which may be caused by a reduction of the surface mobility for the electrons due to the creation of traps at the S i - S i O 2 interface. At higher bias voltages the channel width decreases to a point where IIl. SEMICONDUCTOR DETECTORS
458
D. Pitzl et al. /Nucl. Instr. and Meth. in Phys. Res. A 348 (1994) 454-460
it pinches off completely and the n-strip becomes disconnected from the guard ring. The increased resistance and the pinch-off behaviour are not fully understood at the moment. However, we had some test structures where the accumulation channel resistor is covered by a 200 nm oxide and a metal gate (see the insert in Fig. 6). The gate electrode, which is common for all strips, can be used to control the channel resistance, as shown in Fig. 6 for one channel and after a dose of 100 krad. Positive gate voltages drive the substrate surface into stronger accumulation. The gated channel resistors do not show a pinch-off behaviour up to this dose. We conclude, that gated accumulation channel resistors offer additional control and increased radiation stability when compared to plain accumulation channel resistors. In order to avoid an additional supply voltage on the hybrid it appears feasible to operate on the uppermost curve in Fig. 6 and simply bond the common gate to the n-side guard ring.
3.0
~
2.5
~ w
2.0.
~
1.5.
o.
1.0.
--
0.5.
'
'
'
'
'
'
'
'
i
.
i
i
•
i 20
-
i
.
i
.
,
.
i
.
,
;:,,:,c.o,,pF,oI
•
0.0
.
i
•
i
'
i
'
40
strip pitch
'
i
60 [ ~n
i
,
i
80
'
i
' 100
]
Fig. 7. Interstrip capacitance on the p-side for one strip with respect to its first and second neighbours on the left and the right. The strip implant drawn width is 8 txm and there are no intermediate strips. The line fit uses a phenomenological parameterisation.
3.5. Interstrip capacitance on the p-side
Special test structures were designed to measure the interstrip capacitance for various geometries. The first and second neighbours to the left and the right of a central strip were connected by a metal line such that the capacitance between the central strip and its four neighbours could be measured with just two probe contacts. The adjacent group of strips on both sides and the common guard ring were tied to the shield ground of the HP4284 Precision LCR Meter. The bias voltage was supplied to the n-side from a Keithley 617 Electrometer. The measured capacitance was independent of the measuring frequency in the range from 1 kHz to 1 MHz and the Q-value of the equivalent circuit was high (100-1000), indicating a purely capacitive circuit. Results are shown in Fig. 7 for strip pitches between 20 ~ m and 100 p,m. The strip implants were drawn with a
100000
. . . .
i
. . . .
,
. . . .
,
,
~/~
.
,
. . . .
V g a t e - Vbi ~ = o v -
¢
86000-
60000.
~
width of 8 txm and the structures did not contain intermediate strips. The results may be summarized by a phenomenological parameterisation: Ci L
49 F / c m pitch [Ixm] + 0.32 p F / c m ,
(1)
where L is the strip length. This formula does not include the capacitance through the substrate to the n-side of the detector, which may be calculated from Cb - - = 0.0035 p F / c m × pitch [ F m ] L
(2)
for a wafer thickness of 300 txm. For the case of 50 txm pitch a special structure allowed us to measure separately the interstrip capacitance to first, second and third neighbours, which is shared as 7 0 : 2 5 : 5 . The 5% effect for third neighbours is not included in formula (1). At 50 ~ m pitch the total strip capacitance is 1.5 p F / c m , or 27 pF for an effective strip length of 18 cm, which is the value used in the design of the H1 vertex detector. 3.6. Interstrip capacitance on the n-side
1 f
8=
J
'~ ~
40000
~
2
~
-
20000-
0
~
. . . .
110 . . . .
~
2;
8
. . . . Vbi..
310 . . . .
410 . . . .
75
50
[ V ]
Fig. 6. Gated accumulation channel resistor with 8 Ixm channel width after 100 krad 6°Co irradiation for several gate voltages. The insert shows the mask design.
The test structures for the n-side all had a fixed pitch of 88 ~ m and did not include a second metal layer. For bias voltages above full depletion the measured capacitances were independent of the measurement frequency above 10 kHz. The capacitance between one strip and its two left and right neighbours is shown in Fig. 8 for a strip width of 12 p,m and varying the width of the p-blocking implant. A shallow minimum appears for rather wide p-blocking implants, which is probably best described by quoting a gap of about 10 p,m between the n- and p-implants. Using formula (1) we observe that n-side strips have about twice
D. Pitzl et aL / Nucl. Instr. and Meth. in Phys. Res. A 348 (1994) 454-460 2.5
i ....
i ....
i ....
al°
i ....
,
i ....
i ....
i ....
i ....
2og~ot~],o I
~
i ....
i ....
i
o
---
'
I
I . . . .
~ . . . .
2,o
i
~
1.0-
~ 0.5-
0.0
' ' ' i
. . . .
I . . . .
20
I . . . .
I . . . .
I . . . .
40
width of p-blocking
I
60 Implant
80 [ ~.m
....
I''' I O0
]
Fig. 8. Interstrip capacitance on the n-side for a strip pitch of 88 ~m on a test structure without second metal layer. The second scale indicates the gap between n- and p-implants.
459
was reached. However, some capacitors showed leakage currents above 1 txA, always in conjunction with reduced breakdown voltages. The critical field strength for SiO 2 is 8 M V / c m , corresponding to 160 V across 200 nm. The measured breakdown voltages ranged from 0 V for pinholes, intermediate values between 20 V and 120 V, and up to a maximum of 164 V. The rate of strips with pinhole defects was found to be between 1% and 2% on each detector and on each side, Setting a threshold at 50 V, which corresponds to a typical bias voltage appearing across the-capacitors on the n-side, the total rate of defect strips was between 2% and 30%. Some defects could be attributed to scratches visible on the wafer which were probably created during double sided polishing. Other defects were attributed to an over-etching of contacts during the processing. The second prototype series included samples with capacitors formed by 150 nm Si3N 4 on top of 200 nm SiO 2. Silicon nitride has a dielectric constant Er 7.5, as compared to 3.9 for SiO 2, which helps to maintain a large value for the coupling capacitance. The critical field strengths are equal for both materials and the layer of silicon nitride is expected to cover the pinholes in the underlying SiO 2. Furthermore, the manufacturer modified the etching procedure which resulted in a considerable improvement for the coupling capacitors on the p-side where defect rates of 1% and less were observed. However, the n-side capacitors still had defect rates around 20%. It could be established that most of these defects are created during the processing of the polyimide and second metal layer and further improvements of the processing are being pursued. Alternatively, separate coupling capacitor chips can be used which are mounted between the detectors and the preamplifiers and are formed by 50 nm SiO 2 to reduce their size. These smaller capacitor chips are far less expensive than double sided detectors such that a low yield is less critical. The bias resistors are still integrated on the detectors, which greatly improves their testability compared to " p u r e " DC coupled detectors. One probe contact on each side is sufficient for a leakage current measurement at full depletion. :
the interstrip capacitance than p-side strips of the same pitch. 3.7. Second metal layer capacitance The second metal layer adds stray capacitance between neighbouring metal traces and by coupling to the n-strips underneath. A reliable measurement requires that all but one metal-2 lines are bonded to a common metal plate. The n-side guard ring was connected to the same plate and a negative bias voltage was applied to the p-side. On a full-size detector and for the version with 2 Ixm SiO 2 as the intermetal dielectric we measured a capacitance of 21 pF between one strip and the rest of the detector. The n-strip alone contributes about 6 pF, as determined from the test structures, which leaves 15 pF due to the second metal layer. For the prototypes with 6 txm polyimide and a very similar geometry [7] we obtained a value of 10.5 pF, which is consistent with a reduction by a factor of three for the capacitance added by the second metal layer. A 6 Ixm dielectric allows three detectors to be daisy-chained to one readout chip with acceptable signal-to-noise ratio. The quality of the contacts between metal-1 and metal-2 is very good in both versions. The prototypes with 2 txm SiO 2 included contact chain test structures and no defect was found in 104 contacts tested. The contacts through the 6 txm polyimide layer required special processing steps for the manufacturer and a defect rate of less than 0.003 was achieved. 3.8. Integrated coupling capacitors The breakdown voltage of the integrated coupling capacitors was determined by applying a slowly ramping voltage between the strip implant and the metallisation while monitoring the capacitor leakage current. Leakage currents were usually a few n A until abrupt breakdown
4. Summary Prototype double sided, AC-coupled, double metal silicon strip detectors from CSEM have been evaluated. All detector parameters were satisfactory, except for the integrated coupling capacitors which could not be produced with sufficiently low defect rates so far. The second metal layer was fabricated on 2 p,m SiO 2 and on 6 p,m polyimide, with excellent contact quality in both cases. Accumulation layer resistors on the n-side showed an increased sheet resistance and bias voltage dependence after irradiation. A modified design which includes a metal gate on the resistor eliminates this problem for doses up to 100 krad. III. SEMICONDUCTOR DETECTORS
460
D. Pitzl et al. /Nucl. Instr. and Meth. in Phys. Res. A 348 (1994) 454-460
A multi-guard structure is useful to increase the high-voltage and long-term stability o f the detectors. Interstrip capacitances have been measured for various strip geometries and can be used as references for future detector designs.
References [1] J. Biirger et al., Technical proposal to build silicon tracking detectors for HI, H1 internal report 226 (1992) and DESY PRC 92/01. [2] R. Horisberger and D. Pitzl, Nucl. Instr. and Meth. A 326 (1993) 92.
[3] G. Ambrosi, presented at this Conference (3rd London Conf. on Position Sensitive Detectors, London, UK, 1993). [4] A. Honma, these Proceedings (3rd London Conf. on Position Sensitive Detectors, London, UK, 1993) Nucl. Instr. and Meth. A 348 (1994) 409. [5] A. Perret and P. Weiss, Centre Suisse d'Electronique et de Microtechnique (CSEM), Rue Jaquet-Droz 7, CH-2007 Neuchatel, Switzerland. [6] G. Batignani et al., Nucl. Instr. and Meth. A 310 (1991) 160. [7] We thank W. Dulinski, LEPSI, Strasbourg, and P. Weilhammer, CERN, for providing us with detectors from their prototype series. [8] L. Evensen et al., Nucl. Instr. and Meth. A 326 (1993) 135. [9] J. Ellison et al., IEEE Trans. Nucl. Sci. NS-36 (1989) 267. [10] P.P. Allport et al., Nucl. Instr. and Meth. A 310 (1991) 155.
Nuclear Instruments and Methods in Physics Research A 348 (1994) 454-460 North-Holland
Sect,onA
Evaluation of double sided, AC-coupled, double metal silicon strip detectors for H1 at HERA** D. Pitzl a,*, R. Eichler
a
W. Erdmann
a
K. Gabathuler
b, R.
Horisberger
b
M. Wagener b
a Institut fiir Teilchenphysik, E T H Ziirich, CH-5232 Villigen-PSI, Switzerland b Paul Scherrer Institut, CH-5232 Villigen-PSl, Switzerland
Prototype double sided silicon strip detectors for the H1 vertex detector have been fabricated. The design uses integrated coupling capacitors on both sides and a second metal layer with readout lines on the n-side. Measurements of leakage currents, sheet resistances, metal line quality and contact reliability all show satisfactory results. A multi-guard structure improves the high-voltage and long-term stability of the detectors. The accumulation layer channel resistors on the n-side showed dramatic radiation effects after 6°Co doses of 100 krad and an improved design with a metal gate electrode is demonstrated. Interstrip capacitances have been measured systematically on test structures with various geometries. The capacitance due to the second metal layer on the n-side has been measured for a 2 tzm SiO 2 and a 6 Ixm polyimide dielectric. Up to now, integrated coupling capacitors could not be fabricated with sufficiently low defect rates.
1. Motivation A silicon vertex detector is currently being built for the H1 experiment at HERA [1]. It is designed to tag charm events in order to reduce the light quark background for charm studies. At HERA charm quark pairs are produced in the photon-gluon fusion process which allows a direct measurement of the gluon structure function of the proton. At full luminosity about 108 charmed particles will be produced per year which opens a wide field of topics in rare charm decays. In charm events the most probable track momentum is about l G e V / c and the vertex resolution has a large contribution from multiple scattering. Consequently, the amount of material used in the beam pipe and the support structure for the vertex detector must be kept at a minimum. A second constraint derives from the extended interaction region at HERA, which has a length of about 20 cm FWHM when the 208 MHz RF system for the proton beam is used. The proposed vertex detector consists of two layers of double sided silicon strip detectors around a new carbon fiber beam pipe of 90 mm diameter. The active detector length is 35.4 cm, covered by six silicon detectors in a row with preamplifiers at both ends. The effective strip length is limited by the interstrip capacitance loading the preamplifiers and the desired signal-to-noise ratio. We
* Corresponding author. ** Work supported in part by the Swiss National Science Foundation.
have developed an amplifier and pipeline chip that achieves a ratio of 15 : 1 at a load of 30 pF [2]. Double sided silicon strip detectors offer an efficient way of obtaining two-dimensional position information by collecting the induced signals from drifting electrons and holes on segmented anodes and cathodes, called n-side and p-side, respectively. The strips on the two sides are orthogonal in order to achieve comparable position resolutions in both projections. The strips on the p-side are running along the beam direction for a measurement of the q~-coordinate and are directly bonded to the preamplifiers, while the n-side strips, measuring the z-coordinate, require special readout lines. One option is to use a separate fanout print on a Kapton or glass substrate [3,4]. However, it is difficult to achieve the necessary density of readout lines on these substrates and the assembly of the vertex detector becomes more complicated. Historically, the development of silicon strip detectors was driven by the application of planar IC technology to wafer-scale devices on high resistivity silicon. Today, double metal CMOS processes are widely available and can be adapted to provide integrated readout lines for the n-side strips. The critical aspect is the intermetal dielectric which should be as thick as possible to reduce the stray capacitance while maintaining highly reliable contacts between the metal layers. Here we report on two prototypes using 2 txm SiO 2 and 6 txm polyimide as the intermetal dielectric. Coupling capacitors are used to prevent the strip leakage current from entering the preamplifiers, which is then absorbed by bias resistors integrated on the detector. The coupling capacitance should be at least ten times larger
0168-9002/94/$07.00 © 1994 - Elsevier Science B.V. All rights reserved SSDI 0 1 6 8 - 9 0 0 2 ( 9 4 ) 0 0 3 9 2 - K
D. Pitzl et aL / Nucl. Instr. and Meth. in Phys. Res. A 348 (1994) 454-460
than the interstrip capacitance to avoid signal spreading, which requires values of 15-20 p F / c m . This is achieved by an SiO 2 layer of 200 nm thickness between the strip implant and the metallisation. On double sided detectors, the n-side strips are usually raised to the bias voltage while the p-side is held at ground potential. The coupling capacitors may then be used to separate the DC-levels and operate the n-side preamplifiers at ground potential, making the design of the readout hybrid less demanding. However, if one coupling capacitor breaks, the preamplifier channel immediately saturates and neighbouring channels may be affected as well. On the detector the electric field is disturbed over a region of about 600 Ixm. As a precaution, it is therefore foreseen to operate the front-end electronics for the n-side at the bias voltage, in which case a defect capacitor causes a shift in the DC operating point of just one preamplifier channel. The rate of defect coupling capacitors should be less than 1% on each detector side. A further motivation for using integrated coupling capacitors on the n-side is to provide n-strip isolation by the field plate effect, where the metal is made wider than the strip implant and biased as to interrupt the electron accumulation channel at the substrate surface. However, in our design the n-strip isolation is achieved by an intermediate p-blocking implant. It is not yet established which technology is to be favoured in terms of interstrip capacitance. The radiation dose in the H1 vertex detector from scattered synchrotron radiation and proton beam background during stable operation at the design luminosity is expected to be about 1 krad per year. A much higher dose will be accumulated during injection, beam tuning and accidental beam losses. Prototypes of our front end chip showed tolerable performance degradation for doses up to 100 krad. The silicon detectors have been irradiated to the same dose.
455
on the substrate. The boron implant for the p-side strips has a sheet resistance of 280 1 2 / [ ] and a lateral diffusion of 0.5 Ixm on each side, as determined from 4-point resistors of varying width. The implanted strip pitch on the p-side is 25 Ixm. Every second strip is metallised and read out while the intermediate strips induce signals on their neighbours by capacitive charge division. A metal line thickness of 0.9 ixm was determined from the measured resistance, and the drawn line width is reduced by,2 ixm during etching, The active strip length is 57.6 mm and the width of the active detector area is 32 mm, covered by 640 readout strips. The full size of one detector ai~ter cutting is 59 mm × 34 mm, such that two detectors fit on one wafer. The p-strips are biased from a common guard ring by the punch-through effect across a 5 Ixm gap. The phosphor doping for the n-side strips has a sheet resistance of 13 1 2 / O . The strip length is 32 mm and the pitch was chosen to be 44 ixm, again with every second strip metallised and read out. The first metal layer has a thickness of 0.4 mxm. A second metal layer contains 640 readout lines at 50 Ixm pitch, each connected to one metallised n-strip, (see Fig. 1). A layer of 2 Ixm SiO 2 was used for the intermetal dielectric in our series while 6 Ixm polyimide was used in a second series fabricated for the DELPHI collaboration [7]. The metal-2 lines have a thickness of 0.9 Ixm and the line width is reduced by about 0.5 ixm during etching. The ohmic separation of the n-strips is achieved by an intermediate p-blocking implant which has a sheet resistance of 2600 1 2 / O , corresponding to a surface doping of 5 X 1012/cm 2, assuming. 100% activation. The n-strips are biased from a common guard ring through accumulation channel resistors, which are defined by the p-blocking implant (Fig. 1). Integrated coupling capacitors on both sides are formed by an SiO 2 layer with a thickness of 200 nm between the strip implant and a polysilicon layer, which is in contact with the metal line. The field oxide, which covers the
2. Design and technology Prototype detectors and test structures were fabricated on high resistivity n-type wafers of 100 mm diameter and 300 txm thickness from Wacker Chemitronic. The resistivity, as determined from diode C - V curves, varied between 9 k O cm and 24 k12 cm for the wafers in this batch. On a single wafer resistivity variations of 10% from the center towards the edge were found using the n-side strip isolation to determine the depletion voltage locally. The corresponding drift field deformations are not yet large enough to deteriorate the position resolution. The processing was performed at CSEM [5] based on the technology developed for the ALEPH silicon vertex detector [6]. The mask design is supplied by the customer with design rules corresponding to a 3 Ixm CMOS process. The process has two implants on each side of the wafer, which are precisely aligned with the help of marks etched
Fig. 1. Details of the CAD design for the n-side. Metal-1 and metal-2 are shown in black,' n+-implant is dark grey and the p-blocking implant is light grey, leaving accumulation channel resistors in white. Contacts between metal-1 and metal-2 are running diagonally across the detector. III. SEMICONDUCTOR DETECTORS
456
D. Pitzl et al. /NucL Instr. and Meth. in Phys. Res. A 348 (1994) 454-460
substrate between the strips, has a thickness of 0.9 p~m on both sides. The wafers are passivated by a layer of SiO 2 on both sides with etched contacts for the bond pads. Bond pads on the n-side are formed on the first metal layer and increased in thickness by metal-2 deposition. Bond pads must not be produced on metal-2 alone, since bonding may introduce mechanical stresses when SiO 2 is used for the intermetal dielectric, while polyimide is rather soft and may be difficult to bond on.
Fig. 2. The floating guard ring potentials were measured with the high impedance source and monitor units of an HP4145B Semiconductor Parameter Analyser. The detectors can be biased up to 200 V without breakdown. We conclude, that multi-guard structures, although not mandatory for the successful operation of silicon detectors, offer increased high-voltage and possibly also long-term stability and can be included in many designs without extra processing steps and without increasing the non-sensitive detector area. 3.3. Punchthrough biasing
3. Results 3.1. Leakage currents
The total leakage current for the strip detectors after wafer cutting was between 50 n A / c m z and 100 n A / c m 2, measured at room temperature and 10 V above full depletion. These values are satisfactory, given the complexity of the process. Strip leakage currents of 50 nA (corresponding to 1500 n A / c m 2 in this case) start to contribute to the noise of our preamplifier. One test structure was placed at a distance of only 5 mm from the flattened edge of the wafer and showed leakage currents between 200 n A / c m 2 and 3000 n A / c m e. We conclude that the safe region for good detectors has a diameter of at most 90 mm on a 4 in. wafer. The leakage current of one detector was monitored for six months under permanent bias and did not increase over this period. 3.2. Multi-guard structure
All silicon detectors have a guard ring implant that surrounds the active area on the p-side and collects the leakage current generated at the detector edges. For stable operation it has to be placed at a distance equivalent to about two wafer thicknesses inside the scribe line, such that the depletion region does not reach the edges. In the CSEM process the scribe line region on the p-side receives an n-type implant to avoid surface inversion and depletion, which can be caused by negative charges that may accumulate on the passivation oxide. Positive charges in the oxide, on the other hand, lead to an accumulation layer at the substrate surface which reduces the width of the depletion region and consequently increases the electric field strength. Surface avalanche breakdown is then considered the most common breakdown mechanism on silicon detectors. The high-voltage stability can be improved by adding a multi-guard structure between the first guard ring and the scribe line implant [8]. Our design consists of five floating guard ring implants with a width of 25 Ixm and separated by 50 Ixm gaps, as shown in the insert of Fig. 2. The gaps are covered by floating metal gates on a thin oxide. This structure spreads the bias voltage drop at the surface over a distance of 300 p~m and several p - n junctions, as shown in
The strips on the p-side are biased from the innermost guard ring by the punchthrough effect across a short gap [9]. This p - n - p structure has an exponential I - V characteristic once the potential difference between the strip and the guard ring exceeds a certain threshold voltage. In our application it is more appropriate to regard the strip leakage current as the independent variable which then determines the strip potential. With the guard ring held at ground potential, the strip potential becomes positive after punchthrough, thus reducing the effective bias voltage between p-side and n-side. This is shown in Fig. 3 for strip leakage currents from 1 nA to 1 p,A. Due to the exponential I - V characteristic the strip potential changes by just 1 V over this range. The dynamic resistance of the punchthrough structure is roughly proportional to 1 / I , reaching 3 MI~ at a strip leakage current of 50 nA. For smaller resistance values the bias resistor starts to contribute to the preamplifier noise. Measurements taken after a 6°Co irradiation of 100 krad are also shown in Fig. 3. The punchthrough threshold voltage increased by 1 V while the dynamic resistance did not change. The punchthrough structure can be refined to a MOSFET device by adding a gate electrode on the oxide covering the punchthrough gap [10]. This FOXFET is operated in the subthreshold region to achieve a large
200
.
.
.
.
I
,
,
,
•
i
.
.
.
.
i
.
.
.
.
0V vdng V ~ --X Y ~ -~-'=_/--/-acive Inner area
~
4
3
2
~
gua~
dng 0 / /
/%
1 0 rHlCdoeline rlngm
70O I~rn
2
n-n
>
100
50
0
.
.
.
.
i
50
.
.
.
.
i
.
.
100
.
.
i
150
.
.
.
.
200
Vb,,,' [ V ]
Fig. 2. Floating guard ring potential for the multi-guard structure. The insert shows a vertical section of the detector.
D. Pitzl et al. /Nucl. Instr. and Meth. in Phys. Res. A 348 (1994) 454-460 5
. . . . . . . .
i
. . . . . . . .
i
i
......
..:10
8
. . . .
1000000
i
. . . .
Wdrav~ = 8
4.
.
.
.
.
i 1
457 . . . .
i
.
~ i
1
,
I
,
,
,
,
2
". . . . . . . . . . . . . . . . . . .
100 krlld 3'
~
107
~
100000~
W d ~ ~ = 8 ~ITI 10
2.
10000-
10 8
1-
010.0
........
, 10 "s
........
, 10-7
.
.
.
.
.
.
.
I000
I0 s 10"6
....
Fig. 3. Punchthrough voltage and dynamic resistance for a 5 txm gap and a strip implant width of 12 /xm at 60 V bias before and after 100 krad 6°Co irradiation.
dynamic resistance and the gate potential is used to control the strip potential. We do not see a compelling reason to add this extra electrode, which has to be supplied from the front-end hybrid. The value of the punchthrough voltage can be optimised at the design stage by choosing the gap length. In Fig. 4 we show the punchthrough voltage obtained for test structures with various gap lengths and strip implant widths. A gap length of 4 txm is minimal in the CSEM process, due to the lateral diffusion of the p implants, and we chose a value of 5 Ixm for the detectors. The uniformity of the punchthrough voltage has been measured on several detectors. The maximum variation over 640 strips was 1.2 V, while the local variations between neighbouring strips were always below 0.2 V. The resulting distortions in the drift field are negligible.
35
,
=
30-
• •
25-
•
J
,
l
l
=
,
,
l
,
w. 6pro w~ 8pm w ~ 101xm w= 12wn
l
l
l
_e •
>
] i
20-
|
lO
! |
. . . .
;
1'o . . . .
2'o . . . . Vb=,o
I trl p [ A ]
. . . .
1'o . . . .
15
[~tm]
Fig. 4. Punchthrough voltages at 1 nA strip leakage current and 60 V detector bias for test structures with various gap lengths and strip widths. Values are the drawn dimensions.
3'0 . . . .
;0 . . . .
co
[V ]
Fig. 5. Accumulation channel resistance normalized by the channel length and the effective width just above full depletion for nominal channel widths of 8, 10, 12 and 20 txm before and after • . . 100 krad 6 0 Co irradiation.
3.4. Accumulation channel resistors Accumulation channel resistors for strip biasing on the n-side are a standard feature of the CSEM process. They are formed by the p-blocking implant between the end of the n-strips and the n-side guard ring. The conduction mechanism is due to an electron accumulation layer at the substrate surface caused by positive charges trapped in the field oxide. Once the detector is fully depleted to suppress any conduction through the substrate the resistance is given by the usual relation p R~----
L
d ( w - ~)'
where L and W are the drawn length and width of the channel, p / d is the sheet resistance and W - E the effective width. However, it was found that the resistor value increases with bias voltage even above full depletion, as shown in Fig. 5. By using test structures with varying width it could be established that the sheet resistance remains constant at 18.5 1 2 / [ ] while the effective channel width is being reduced at higher bias voltage. Radiation effects have been studied with a 6°Co source for doses up to 100 krad. The fixed oxide charge increased by a factor of four from an initial value of 2 × 1011/cm2 in both the field oxide and the thinner coupling oxide, as determined from MOS-capacitor C - V curves. The accumulation channel resistance did not decrease, as expected, but increased dramatically and became more strongly bias voltage dependent (see Fig. 5). The sheet resistance increased to about 100 k 1 2 / [ ] which may be caused by a reduction of the surface mobility for the electrons due to the creation of traps at the S i - S i O 2 interface. At higher bias voltages the channel width decreases to a point where IIl. SEMICONDUCTOR DETECTORS
458
D. Pitzl et al. /Nucl. Instr. and Meth. in Phys. Res. A 348 (1994) 454-460
it pinches off completely and the n-strip becomes disconnected from the guard ring. The increased resistance and the pinch-off behaviour are not fully understood at the moment. However, we had some test structures where the accumulation channel resistor is covered by a 200 nm oxide and a metal gate (see the insert in Fig. 6). The gate electrode, which is common for all strips, can be used to control the channel resistance, as shown in Fig. 6 for one channel and after a dose of 100 krad. Positive gate voltages drive the substrate surface into stronger accumulation. The gated channel resistors do not show a pinch-off behaviour up to this dose. We conclude, that gated accumulation channel resistors offer additional control and increased radiation stability when compared to plain accumulation channel resistors. In order to avoid an additional supply voltage on the hybrid it appears feasible to operate on the uppermost curve in Fig. 6 and simply bond the common gate to the n-side guard ring.
3.0
~
2.5
~ w
2.0.
~
1.5.
o.
1.0.
--
0.5.
'
'
'
'
'
'
'
'
i
.
i
i
•
i 20
-
i
.
i
.
,
.
i
.
,
;:,,:,c.o,,pF,oI
•
0.0
.
i
•
i
'
i
'
40
strip pitch
'
i
60 [ ~n
i
,
i
80
'
i
' 100
]
Fig. 7. Interstrip capacitance on the p-side for one strip with respect to its first and second neighbours on the left and the right. The strip implant drawn width is 8 txm and there are no intermediate strips. The line fit uses a phenomenological parameterisation.
3.5. Interstrip capacitance on the p-side
Special test structures were designed to measure the interstrip capacitance for various geometries. The first and second neighbours to the left and the right of a central strip were connected by a metal line such that the capacitance between the central strip and its four neighbours could be measured with just two probe contacts. The adjacent group of strips on both sides and the common guard ring were tied to the shield ground of the HP4284 Precision LCR Meter. The bias voltage was supplied to the n-side from a Keithley 617 Electrometer. The measured capacitance was independent of the measuring frequency in the range from 1 kHz to 1 MHz and the Q-value of the equivalent circuit was high (100-1000), indicating a purely capacitive circuit. Results are shown in Fig. 7 for strip pitches between 20 ~ m and 100 p,m. The strip implants were drawn with a
100000
. . . .
i
. . . .
,
. . . .
,
,
~/~
.
,
. . . .
V g a t e - Vbi ~ = o v -
¢
86000-
60000.
~
width of 8 txm and the structures did not contain intermediate strips. The results may be summarized by a phenomenological parameterisation: Ci L
49 F / c m pitch [Ixm] + 0.32 p F / c m ,
(1)
where L is the strip length. This formula does not include the capacitance through the substrate to the n-side of the detector, which may be calculated from Cb - - = 0.0035 p F / c m × pitch [ F m ] L
(2)
for a wafer thickness of 300 txm. For the case of 50 txm pitch a special structure allowed us to measure separately the interstrip capacitance to first, second and third neighbours, which is shared as 7 0 : 2 5 : 5 . The 5% effect for third neighbours is not included in formula (1). At 50 ~ m pitch the total strip capacitance is 1.5 p F / c m , or 27 pF for an effective strip length of 18 cm, which is the value used in the design of the H1 vertex detector. 3.6. Interstrip capacitance on the n-side
1 f
8=
J
'~ ~
40000
~
2
~
-
20000-
0
~
. . . .
110 . . . .
~
2;
8
. . . . Vbi..
310 . . . .
410 . . . .
75
50
[ V ]
Fig. 6. Gated accumulation channel resistor with 8 Ixm channel width after 100 krad 6°Co irradiation for several gate voltages. The insert shows the mask design.
The test structures for the n-side all had a fixed pitch of 88 ~ m and did not include a second metal layer. For bias voltages above full depletion the measured capacitances were independent of the measurement frequency above 10 kHz. The capacitance between one strip and its two left and right neighbours is shown in Fig. 8 for a strip width of 12 p,m and varying the width of the p-blocking implant. A shallow minimum appears for rather wide p-blocking implants, which is probably best described by quoting a gap of about 10 p,m between the n- and p-implants. Using formula (1) we observe that n-side strips have about twice
D. Pitzl et aL / Nucl. Instr. and Meth. in Phys. Res. A 348 (1994) 454-460 2.5
i ....
i ....
i ....
al°
i ....
,
i ....
i ....
i ....
i ....
2og~ot~],o I
~
i ....
i ....
i
o
---
'
I
I . . . .
~ . . . .
2,o
i
~
1.0-
~ 0.5-
0.0
' ' ' i
. . . .
I . . . .
20
I . . . .
I . . . .
I . . . .
40
width of p-blocking
I
60 Implant
80 [ ~.m
....
I''' I O0
]
Fig. 8. Interstrip capacitance on the n-side for a strip pitch of 88 ~m on a test structure without second metal layer. The second scale indicates the gap between n- and p-implants.
459
was reached. However, some capacitors showed leakage currents above 1 txA, always in conjunction with reduced breakdown voltages. The critical field strength for SiO 2 is 8 M V / c m , corresponding to 160 V across 200 nm. The measured breakdown voltages ranged from 0 V for pinholes, intermediate values between 20 V and 120 V, and up to a maximum of 164 V. The rate of strips with pinhole defects was found to be between 1% and 2% on each detector and on each side, Setting a threshold at 50 V, which corresponds to a typical bias voltage appearing across the-capacitors on the n-side, the total rate of defect strips was between 2% and 30%. Some defects could be attributed to scratches visible on the wafer which were probably created during double sided polishing. Other defects were attributed to an over-etching of contacts during the processing. The second prototype series included samples with capacitors formed by 150 nm Si3N 4 on top of 200 nm SiO 2. Silicon nitride has a dielectric constant Er 7.5, as compared to 3.9 for SiO 2, which helps to maintain a large value for the coupling capacitance. The critical field strengths are equal for both materials and the layer of silicon nitride is expected to cover the pinholes in the underlying SiO 2. Furthermore, the manufacturer modified the etching procedure which resulted in a considerable improvement for the coupling capacitors on the p-side where defect rates of 1% and less were observed. However, the n-side capacitors still had defect rates around 20%. It could be established that most of these defects are created during the processing of the polyimide and second metal layer and further improvements of the processing are being pursued. Alternatively, separate coupling capacitor chips can be used which are mounted between the detectors and the preamplifiers and are formed by 50 nm SiO 2 to reduce their size. These smaller capacitor chips are far less expensive than double sided detectors such that a low yield is less critical. The bias resistors are still integrated on the detectors, which greatly improves their testability compared to " p u r e " DC coupled detectors. One probe contact on each side is sufficient for a leakage current measurement at full depletion. :
the interstrip capacitance than p-side strips of the same pitch. 3.7. Second metal layer capacitance The second metal layer adds stray capacitance between neighbouring metal traces and by coupling to the n-strips underneath. A reliable measurement requires that all but one metal-2 lines are bonded to a common metal plate. The n-side guard ring was connected to the same plate and a negative bias voltage was applied to the p-side. On a full-size detector and for the version with 2 Ixm SiO 2 as the intermetal dielectric we measured a capacitance of 21 pF between one strip and the rest of the detector. The n-strip alone contributes about 6 pF, as determined from the test structures, which leaves 15 pF due to the second metal layer. For the prototypes with 6 txm polyimide and a very similar geometry [7] we obtained a value of 10.5 pF, which is consistent with a reduction by a factor of three for the capacitance added by the second metal layer. A 6 Ixm dielectric allows three detectors to be daisy-chained to one readout chip with acceptable signal-to-noise ratio. The quality of the contacts between metal-1 and metal-2 is very good in both versions. The prototypes with 2 txm SiO 2 included contact chain test structures and no defect was found in 104 contacts tested. The contacts through the 6 txm polyimide layer required special processing steps for the manufacturer and a defect rate of less than 0.003 was achieved. 3.8. Integrated coupling capacitors The breakdown voltage of the integrated coupling capacitors was determined by applying a slowly ramping voltage between the strip implant and the metallisation while monitoring the capacitor leakage current. Leakage currents were usually a few n A until abrupt breakdown
4. Summary Prototype double sided, AC-coupled, double metal silicon strip detectors from CSEM have been evaluated. All detector parameters were satisfactory, except for the integrated coupling capacitors which could not be produced with sufficiently low defect rates so far. The second metal layer was fabricated on 2 p,m SiO 2 and on 6 p,m polyimide, with excellent contact quality in both cases. Accumulation layer resistors on the n-side showed an increased sheet resistance and bias voltage dependence after irradiation. A modified design which includes a metal gate on the resistor eliminates this problem for doses up to 100 krad. III. SEMICONDUCTOR DETECTORS
460
D. Pitzl et al. /Nucl. Instr. and Meth. in Phys. Res. A 348 (1994) 454-460
A multi-guard structure is useful to increase the high-voltage and long-term stability o f the detectors. Interstrip capacitances have been measured for various strip geometries and can be used as references for future detector designs.
References [1] J. Biirger et al., Technical proposal to build silicon tracking detectors for HI, H1 internal report 226 (1992) and DESY PRC 92/01. [2] R. Horisberger and D. Pitzl, Nucl. Instr. and Meth. A 326 (1993) 92.
[3] G. Ambrosi, presented at this Conference (3rd London Conf. on Position Sensitive Detectors, London, UK, 1993). [4] A. Honma, these Proceedings (3rd London Conf. on Position Sensitive Detectors, London, UK, 1993) Nucl. Instr. and Meth. A 348 (1994) 409. [5] A. Perret and P. Weiss, Centre Suisse d'Electronique et de Microtechnique (CSEM), Rue Jaquet-Droz 7, CH-2007 Neuchatel, Switzerland. [6] G. Batignani et al., Nucl. Instr. and Meth. A 310 (1991) 160. [7] We thank W. Dulinski, LEPSI, Strasbourg, and P. Weilhammer, CERN, for providing us with detectors from their prototype series. [8] L. Evensen et al., Nucl. Instr. and Meth. A 326 (1993) 135. [9] J. Ellison et al., IEEE Trans. Nucl. Sci. NS-36 (1989) 267. [10] P.P. Allport et al., Nucl. Instr. and Meth. A 310 (1991) 155.