NM B
Nuclear Instruments and Methods in Physics Research B77 (1993) 239-242 North-Holland
Beam Interactions with Materials 8 Atoms
Evaluation of single-event immunity in micron-size device area using single-ion microprobe technique Takashi Matsukawa, Katsunori Noritake, Meishoku Koh, Ken-ichi Hara, Makoto Goto and Iwao Ohdomari School of Science and Engineering,
Waseda University, 3-4-l Ohkubo Shinjuku-ku,
Tokyo 169, Japan
A novel technique which enables us to hit a micron-size device area with a single ion has been established. Evaluation of single event immunity at particular device sites has become possible using this technique. Latchup immunity of a CMOS IC has been evaluated by measuring dependence.
ion-induced
charges
which
trigger
latchup.
1. Introduction VLSIs have been applied widely to artificial satellites in order to achieve advanced performance. Since VLSIs used in the space environment are bombarded with cosmic rays incessantly, they often suffer from single-event phenomena (SEP) which are induced by collision of a single energetic ion with integrated circuits. Typical examples of SEP are soft errors in memory devices [l] and latchups in CMOS ICs 121. Among these the latchup is more serious in the sense that it often results in burnout of devices. The single-event immunity of VLSIs decreases with scaling down of device feature size. Thus increasing immunity is essential to achieve both high performance and high reliability of the satellites. So far radiation hardening of VLSIs has been conducted by modifying device structures based on the data such as SEP cross sections which are obtained by randomly irradiating a whole device chip and by processing the data statistically [3,4]. These conventional tests are indirect in the sense that identification of error sites in the device is not possible. In the course of our work for wider application of ion microprobes, we have developed a direct method to test the single-event immunity which enables to hit micron-size area with single ions. So far a trial has been done to manipulate single ions using an extremely diluted beam of lo3 particles/s by Fischer [5]. By changing successively the relative location of ion beam and target, they eventually achieved the single ion incidence per site. However, in order to hit a particular site in a device with single ions at any time, extraction of single ions from an ion beam and aiming a particular incident site is inevitable. In our case, a beam chopper for extracting single ions has been added to a conventional ion micro0168-583X/93/$06.00
0 1993 - Elsevier
Science Publishers
The
amount
of charges
has been
found
to have
a site
probe. For aiming a scanning electron microscope (SEM) has been installed to the target chamber of our microprobe system. We have applied these technique to investigate the site dependence of single-event immunity in VLSIs for the first time. In this work, we evaluate single-event immunity at various sites of a CMOS IC using the single-ion microprobe technique. CMOS integrated circuits have inherently parasitic thyristors as shown in fig. 1. The wellsubstrate junction is normally biased reversely and the parasitic thyristor is usually off. When a single ion strikes the well-substrate junction, transient leakage current flows across the junction. If the current amplitude exceeds a critical value, the current triggers the parasitic thyristor to the breakover and latchup occurs. As an indicator to evaluate latch up immunity at various incident sites of ions, we have measured the integrated charges due to leakage current. The immunity has been found to have a site dependence.
2. Experimental Throughout the experiments, single helium ions of 3 and 4.5 MeV have been provided from the single-ion microprobe at Waseda University, the details of which will be described elsewhere [7]. A CMOS IC (Motorola MC14049) with six inverter circuits was selected as a test device. The IC chip was exposed by removing plastic package with a heated fuming acid. Exposure of chips is essential for directly observing the feature of commercially available devices and for precise positioning of the incident sites with single ions. The device was mounted on a sample stage in the target chamber side by side with a copper mesh which is used as a dummy target for aiming.
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V. TOMOGRAPHY
/ SINGLE
EVENT
T. Matsukawa et al. / Evaluation of single-event immunity
240
Incident ion
,
V
n-substrate
0
Fig. 1. A schematic view of CMOS inverter showing leakage current induced by ion incidence.
Aiming of the target with single ions was performed by following the way we developed previously [S]. Firstly, features of the test chip and the dummy target were observed with the SEM. After measuring the relative location of the test chip and the dummy target using SEM images as shown in fig. 2, we obtained a
(4
2,,v
Fig. 2. SEM microphotograph of sample device and copper mesh.
Charge Sensitive Pre-Amp.
Target Chamber
vertical: 2OmV/div holizontal: O.Sms/div Fig. 3. (a) A circuit for measuring collected charge. (b) Output waveform of a charge-sensitive preamplifier.
: p-well region : protection
200,um Fig. 4. Layout
of the MC14049
CMOS IC.
circu
241
T. Matsukawa et al. / Evaluation of single-event immunity secondary electron image of the dummy target by scanning the focused ion beam. This means that we can identify a particular incident site of the ion beam by the SEM image. The image was utilized also for optimizing the focusing condition. Hitting a particular device site in the test chip was achieved by moving the sample holder by the relative distance obtained beforehand so that a desired site came to the beam site. During the transportation, the ion beam was cut temporarily. Fig. 3a is a schematic view of a circuit for measuring
collected charges. V,, bias was applied to the test CMOS IC in the target chamber through a charge sensitive preamplifier (Tennelec TC170). All the input terminals of the test IC were grounded. The leakage current induced by ion incidence was integrated and amplified by the preamplifier. The output waveforms were observed using a digital storage oscilloscope (IWATSU DS-6612). An output waveform of the preamplifier is shown in fig. 3b. The abrupt change in voltage waveform (AV) is due to charge collection upon ion incidence. The amount of charge can be
o
: O
0
: 3O
0
: cii
x lull (a) 3MeV-He+
x (h)
run1
4.5McV-He’+
Fig. 5. Charge collected upon incidence of single helium ions with an energy of (a) 3 and (b) 4.5 MeV. V. TOMOGRAPHY
/ SINGLE
EVENT
242
T. Matsukawa et al. / Evaluation of single-event immunity
obtained from the product of voltage change Av the feedback capacitance C, in the preamplifier. got a map of the induced charges by measuring charge at each site in the test IC for every 100 interval.
and We the pm
3. Results and discussions Fig. 4 shows a microphotograph and a layout of the test IC. There are six n-channel MOSFETs in the shaded area from the center to the left and six p-channel MOSFETs in the right hand side. The shaded area corresponds to the p-well, which is reversely biased against n-type substrate. There also exist protection circuits composed of pn junction diodes in the area indicated by the dotted lines. Fig. 5 shows the results of mapping. The amount of charges collected at each site upon single-ion incidence is indicated quantitatively by the size of circles. Figs. 5a and 5b are the results for 3.0 MeV and 4.5 MeV helium ions, respectively. Both figures show the large amount of charge observed in the region corresponding to the p-type well. Since the amount of charge due to the leakage current can be regarded as a trigger for the latchup, these maps can be a certain scale for latchup susceptibility of the test IC. The charge collected at the sites around the well would be from the protection circuits which are composed of pn junction diodes or other component, although the detail of the device structure is not known. It is not clear at present whether or not the charge collection in these area can trigger the latchup.
4. Conclusions The amount of charge induced by single-ion incidence was measured using a single-ion microprobe
technique at various target sites in a test CMOS IC. Since the leakage current across the well-substrate junction can trigger latchup, the charge observed at the various sites indicates a certain scale of latchup susceptibility. The amount of charge has been found to have a site dependence. We identify the area in which a large amount of charge was observed as the p-well region.
Acknowledgements This work was supported in part by a Grant-in-Aid for Developmental Scientific Research, the Ministry of Education, Science and Culture of Japan, and also by a Waseda University Grant for Special Research Projects.
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