- Email: [email protected]
Experience with ESOP, a fast microprogrammable trigger processor
Computer Physics Communications 26 (1982) 69—77 North-Holland Publishing Company
69
EXPERIENCE WITH ESOP, A FAST MICROPROGRAMMABLE TRIGGER PROCESSOR D.A. JACOBS CERN Geneva, Switzerland
ESOP is a fast processor designed to front-end the data-acquisition computer in high energy physics experiments and perform second level trigger calculations. It is in use in five experiments at CERN and Saclay. It will be shown how ESOP realises its high performance and how such a machine may he supported in an experiment. For trigger calculations the efficiency of the connection to the detector read-out system is extremely important and the ways in which this is done in practice with ESOP will be discussed. An outline of some existing trigger algorithms will be given and some conclusions drawn on desirable features of a second-generation processor based on experience with ESOP.
1. Introduction This paper describes a fast, modular, microprogrammable processor ESOP and the ways in which it is being put to use for second level trigger and other fast calculations in a number of high-energy physics experiments. In doing this, it draws on the work of many people who have contributed to the development, not only from DD division CERN where the processor was designed [I], but also from the various experimental teams. In recent years the complexity of logic used for triggering high-energy physics experiments has increased considerably. In part this is due to the increased complexity and fine structure of the detectors themselves, covering ever larger solid angles with higher precision. In addition, however, there is a tendency to use more selective triggers in order to obtain larger samples of interesting events in the time available. This is because the data accumulation rate of an experiment is often now limited either by the read-out time of the detectors or by the off-line processing power available. It is thus important not to waste any of this capacity by carrying through data which are finally rejected. The quantities of data stored for each event and the corresponding read-out time continue to grow, and sizes in excess of 20 Kbytes with upwards on 20 ms read-out time are not uncommon, How then are such selective triggers con001 O-4655/82/0000--0000/$02.75
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structed? There is always a relatively simple first level which must be very fast (< 1 ms) and which is used to freeze the data in the detector read-out systems. For this, hardwired high-speed logic is the only possibility. After the data are frozen, the experiment is dead until either the data are read out to the on-line computer or the read-out systems are cleared and reset. Some experiments are only practical if the decision to clear or to read out can be made in a few microseconds. In such cases hardwired logic is often also used for this second level of triggering. If, however, much data is needed for the trigger decision, as when a large solid angle is covered, the logic and cabling become very complex, inflexible and expensive. In less critical situations, or as a third level, when decision times upwards from a few tens of microseconds are acceptable, a fast programmed processor often offers a more economic and flexible solution. The fact that such processors read the detector data over the normal bus structures makes for relatively simple installation and the programmability allows scope for easy refinement of the trigger algorithm during the life of the experiment. ESOP belongs to this category and has been built with the aim of producing as fast a processor as possible with reasonably simple hardware. It runs as a slave of the normal data acquisition computer, controlled via CAMAC interfaces. The detector data which it reads is normally also available to the host corn-
1982 North-Holland
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D.A. Jacobs
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provision was made for unsigned 16 bit arithmetic as well as the more usual 2s complement representation. Floating-point was not considered necessary for the applications envisaged. The CPU cycle
ESOP CONFIGURATIONS
_______
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ROMULUS I -_[ROUTING_~
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-
IREADOUTI
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11
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—-
I>-I ~ l=I~I ~‘
~ ~j~j
ESOP BUS
m
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time was brought as low as possible with available
FLAGS PULSES IN ~~~LEVELS
ESOP CRATE
——
Arithmetic Logic Unit (ALU) and circuits ns. Memories although available, capable of nothandling cheap, this ratetarget the are125easily was
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Experience with ESOP
0
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I
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set to do all normal processing and memory opera-
tions in one cycle, only exception being X 16 bit multiply level of processor which the required performance two which cycles. could The16actual then
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-
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Fig. I. The modules constituting an ESOP configuration.
puter via bus branching logic or from the memory of ESOP. For this reason, it can also be used as an intelligent read-out controller, doing data cornpression or improving the data structure. Exampies of these uses will be given later.
which be reached could depended be carriedonout theinnumber parallel.ofSeparate actions ALUs were thus provided for data processing, data address calculation and instruction address calculation. Unless the required operations are highly ordered, however, it is difficult to make full use of such parallelism without allowing the programmer full control over it. The processor was thus made microprogrammable at the user level with 48 bit wide instruction words built out of fields controlling the various gating and processing functions. Having the data and instruction memones separate has the additional advantage of allowing simultaneous access to both. With this basic layout in mind, the processor was built up around four buses: instruction (48 bits), instruction address (12 bits), data (16 bits) and data address (16 bits). The arithmetic unit has a file of
2. The processor design The processor is built with Schottky-TTL technology in CIM mechanics. Its modular layout has allowed the design to evolve over a number of years as new circuits became available and new needs arose. Fig. I shows a block diagram of the modules available and the way in which they may be configured together, although it is unlikely that any one application would need all the options shown, The word length for data in memory and for arithmetic calculations was chosen as 16 bits, which is sufficient for most detector read-out systems and directly compatible with typical on-line minicomputers. Detector data are normally positive integers and to make full use of the word length,
Table I Instruction sequence for synchronisation with external trigger signals Instr. no.
4
Set up break logic to skip + I on occurrence of trigger signal and ±2 on abort signal Change instruction ALU op-code from A + I (normal sequence) to A + B, processor will loop on next instruction until a non-zero value (I or 2) is placed in B by the break logic Enable break, processor loops here waiting for break condition Come here if trigger received
5
Come here if abort signal recieved
2
3
D.A. Jacobs
LOOP
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Experience with ESOP
CONTROL
a)
Table 2
Instruction sequence for loop to search a memory block for a word of a particular value
N:rrnoh A±I
~AI~UIM
Load loop counter with block size, set break logic to
ALU 2 bI
71
LOOSE
COMPARE
B
-
I
A
A— B
3
Read first word to data bus, present data memory with incremented address, transfer value for comparison to ALU B register, set instruction memory ALU to loop next instruction as in table I, instruction 2
4
Enable break, transfer word from data bus to ALU A register, compare it with B, read next word from data memory to data bus, present data memory with following incremented address, (processor loops on
~
OP~A-B OP A-B~O:E-)A-BI-I A - B < 0: E CIA-B)- I
SIGN
skip + I on loop counter =0 and +2 on arithmetic Get address of first word, present it to the data memory, set the data memory ALU to auto-merementit
this instruction until break condition occurs) c)
BIT
5 6
SEARCH
DATA WORD
10)0 1101010 0101 I IS
12
LBSR
9
13 -
7
I~ 10~0~0 )I
6
10101
3
LOAD & FIND
0
~
BIT
BIT
CBSB
CAD.
<0
NO MORE
Come here if block scanned without match Come here if match found
BITT
Fig. 2. Special features of ESOP anthmetic power.
eight 16 bit registers with simultaneous read/write access for local data storage. In the instruction memory unit, instructions are prefetched. Its built-in ALU is used to generate normal instruction sequencing, jumps and subroutine calls. Multiway conditional skips and branches are generated by deriving address modifiers from the arithmetic condition codes. Since the processor is thought to be dedicated to a particular task, a true interrupt system is not required, but synchronisation with outside events is obtained by a “break” logic which generates multiway branches in a similar way to branch-oncondition. This is illustrated by the logic sequence shown in table 1. The data memory control unit has a file of eight registers for address storage, and, with its own ALU, can carry out normal, base and indexed
addressing with autoincrement or decrement in any steps. It provides access from ESOP to the data memory which is built in 4 or 8 Kword modules up to a maximum of 64 Kwords. Sets of memory modules are grouped under the control of up to eight four-port controllers. One port is dedicated to ESOP via the data memory controller, while the other three are Direct Memory Access (DMA) ports equipped with all the necessary control logic, memory address and word count registers. This will be explained further in discussing processor interfacing. Apart from the parallelism, another route has been taken to improve processor performance, namely the introduction of processor functions specially adapted to the proposed applications. Trigger software makes heavy use of loops with conditional termination, and to minimise thr loop overheads, a presettable loop counter is included which may be counted down for each loop execution (fig. 2a). The ‘loop counter = 0’ state is available along with the normal arithmetic conditions for use in a multiway branch at the end of the loop. This is illustrated in table 2 for the special case of a memory search using a single instruction. A very common operation in trigger calcula-
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1).A. Jacobs
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Experience with ESOP
tions is that of ‘loose-comparison’, i.e. A B
ESOP memory and that of the host computer. The transfer rate is that of the CAMAC system. since the ESOP side is very much faster. A transportable cross-assembler has been written to implement the assembly language described above and ESOP code is typically developed with
value tested.
the editor and file system of the host computer.
Lastly, a module operating in parallel with the normal arithmetic unit is provided for bit operations. Shifts of any kind and length can be made in one cycle. The bit numbers of bits set in a word can be found as shown in fig. 2c at the rate of one bit per cycle. This is useful for decoding pattern unit contents for instance, Programming the processor by setting the individual bits of instruction words would be obvi-
The cross-assembler is able to check the syntax of the source code as well as detect clashes of op-codes and straight-forward clashes of bus use. For the down-line loading and control of ESOP. two situations can be distinguished: program development and integration in the production dataacquisition software. For the former, there is a complete interactive FORTRAN program with commands to load and dump instruction and data
ously very tedious. For this reason a kind of assembler language was developed in which each
memory, to access and modify individual words and to start and stop ESOP. With the help of some
field is represented by an operation mnemonic, sometimes with parameters. For tnstance, ALO APB sets the arithmetic unit ALU code to A + B while LDA loads the ALU A register from the data bus. In as far as the fields do not clash with one another, such micro-operations may be freely logically ORed together to make up an instruction word. Thus the programming of ESOP is not difficult for anyone with assembler language programming experience. The challenge of exploiting the parallelism to the full may be taken up at a second phase.
standard ESOP routines which may be placed in an unused part of memory, it is also possible to examine the address and data register files. Using this package and the hardware break-point logic, fully interactive debugging of software is possible. For incorporating ESOP in a data-acquisition systern, there is a library of routines for loading and control. The direct access to ESOP memory allows the use of playback of previously recorded data for the tuning of trigger algorithms. To the cross-assembler has been added a logical simulator of the processor hardware. All aspects of ESOP software run on the simulator with the exception of external breaks and DMA transfers. The object code is transfered from the assembler
—
3. Connection to the host computer and supporting software As already mentioned, ESOP operates as a slave of the data acquisition computer to whose CAMAC system it is connected by two single-width interface modules. One is used for instruction memory access and processor control, while the other is connected directly to the data memory modules via the second ports of the four-port DMA controllers. The registers in these controllers may be set either from ESOP or by CAMAC. Thus with the added help of a CAMAC DMA controller, direct block transfers can be made between the
to the simulator and the ‘data memory’ of the simulator may be preloaded, either by hand or from files in the same format as for the actual machine. In this way, the simulator can be run with ‘real’ data. The simulator is a very considerable aid to the development of ESOP programs. It allows the testing of algorithms in the early planfling stages of experiments before the hardware is
built and has added features such as tracing execution time, multiple break pointing and nondestructive examination of full processor states between instructions, which greatly eases the debugging process.
D.A. Jacobs
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Experience with ESOP
4. Connection of ESOP to the detectors of experiments 4.1. CAMAC The most generally used read-out system for detectors is a set of CAMAC branches, and by means of an Auxiliary Branch Controller (ABC) module [2], ESOP as well as the main data acquisition system may control such a branch. ESOP drives the ABC via an I/O module with sets of latches which can be connected to the data bus [3]. CAMAC transactions are thus program controlled, but due to the speed of ESOP, may proceed at the maximum rate for the branch. The time taken to read in the detector data is of course a critical parameter for the overall performance of the trigger calculation and in this respect CAMAC is disproportionately slow if more than a few words have to be read. For this reason, considerable effort has been put into providing other, faster methods. These use DMA transfer into the data memory. Each four port controller provides two such channels for external devices, multiplexed with each other. Since each of the possible eight controllers can handle data at 8 Mbyte/s, a total sustained rate of 64 Mbyte/s can be achieved, Interfaces to several popular systems have been built. 4.2. RMH [4] This is a high speed MWPC read-out system in ECL logic, which is now being extended for use with other detectors. Transfers are possible at about 12 Mbyte/s, and this is the fastest read-out system currently being used with ESOP. The basic RMH system allows for the use of local intelligence by providing a data fan-out module and non-destructive read-out. The ESOP interface [5] allows autonomous start of transfer after a strobe and provides a read-out busy signal for use as a veto. The end of transfer condition is coupled to the ESOP break logic. 4.3. ROMULUS [6] Access to a ROMULUS vertical bus is by a three way routing unit [7]. This allows transfers
fl
from branch to ROBD, from branch to ESOP or from ESOP to ROBD. The routing unit is coupled to ESOP memory by an adaptor module B24. The data-flow switching of the routing unit and B24 are controlled by ESOP’s I/O module. 4.4. DTRC [8] This is a buffered version of the DTR/DEC system for drift chamber digitizing with a vertical bus operating at 300—500 ns per word. The branch driver module includes a two-way bus switch (from branch to CAMAC or ESOP or both) and interface to ESOP data memory. Other special interfaces have been constructed for particular detectors. These will be described below in the context of the experiments in which they are used.
5. Present uses of ESOPs in experiments A total of 9 ESOPs are currently in use for five experiments. A short look at these applications will give an introduction to the practical application of the processor. The experiments are all very different from each other, the only common point being the desire to improve performance with an intelligent trigger calculation in a few hundred microseconds. MWPCs read with the RMH systern are seen to be the most popular detecors for the triggers, and there isoperation, no doubt non-destructive that its combination of dead-timeless fast read-out and fast clear makes the RMH systern very attractive for this purpose. 5.1. European Hybrid Spectrometer (EHS) [9] This comprehensive spectrometer for hadron physics at the CERN SPS incudes, as a vertex detector for some experiments, a Rapid Cycling Bubble Chamber (RCBC) of 80 cm diameter operating at 30 Hz. A primary trigger from scintillator hodoscopes is supposed to indicate that an event occurred in the chamber and thus to enable the taking of a picture. However, only events in the central region of the chamber can be analysed and the ratio of useful/unwanted target material is
74
D.A. Jacobs
EHS
/
position of the beam track in Dl to about 1 mm. The effect of the magnetic field is handled by a look-up table. Having done this, ESOP waits until the data from the diode arrays has arrived (read-out
OFVT RCBC
takes 200~i).If no hit in Dl is found near enough the expected position (remember IA— BI<~, the event occurred upstream of Dl and can be rejected.
D D~
D
2
~
—
Reject
—
Accept
______________
ESOP CODE
_____________
READ ii,
—
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au3
PC~ED~T I~ApA.
FOUND
NO
VETO
YES FINE PREDIC ON
D2
FOUND IN D~ NO
YES
NO I~~UALT
Experience with ESOP
Otherwise the hit on Dl is used to make a refined prediction on D2 to about 400 p.m. If no hit occurred there, the event is taken to have occurred in the useful volume and is accepted. If a hit is found, a zone a few millimeters wide around this point is searched for other hits, which, if found, would indicate that what is being seen is the foward jet of a good event. If there is just a single hit, the event probably occurred down-stream and is rejected. Monte Carlo calculations indicate an efficiency of above 90% for this trigger. A second ESOP is used at EHS to handle data from the large-volume drift chamber ISIS [11]. Using four DMA controllers in parallel, 16 Kwords of data are read from this detector in 2—3 ms, before charge leakage from its capacitor memories has time to spoil its iontzation measuring accuracy. ESOP compacts this data to about 2/3 of its original size in 5—7 ms by removing unused chan.
VET
YES
OK
Fig. 3. The principle of the optical fiducial volume ingger for EHS.
such that only about 1/3 of the primary triggers represent good events. Since the cameras are only capable of 15—20 Hz, expensive dead time can be reduced by making a more selective trigger decision in time to inhibit the picture taking. An ESOP is being programmed for this task using the principle shown in fig. 3. The detectors are MWPCs (Ul and U3) and two novel diode arrays Dl and D2 [10] looking into the bubble chamber and imaging tracks with a secondary flash some 600 p. before the normal picture taking. They can be thought of as acting like MWPCs with single planes of horizontal wires. They give a spatial resolution of about 180 p.m and are read out to ESOP via a special interface at 100 ns/word. With a simple calculation based on one plane in Ul and 4 planes in U3, ESOP can predict the
nels. 5.2. NAil [12] This experiment at CERN is an example of the use of a more specialised trigger to select interactions of a particular kind. The parts of the apparatus contributing to the trigger are shown in simplified form in fig. 4. The experiment aims to study charm particles and uses as trigger the appearance of a single electron from the decay of such a particle. The primary trigger is generated by the Cerenkov and the electron calorimeter, but is heavily contaminated with unwanted triggers due to high momentum hadrons and electron pairs. The total read-out time for an event is several milliseconds and a significant increase in sensitivity is got by using an intelligent trigger to abort the read-out in such cases. Two ESOPs are used for this purpose. One reads data via the RMH system from 4 planes of MWPCs Wl and W2 and from a scintillator hodo-
D.A. Jacobs
/
Experience with ESOP
K, ~r strangeness exchange reactions. Time-of-flight and liquid hydrogen ~erenkovs will be used to distinguish these reactions from passing ir, ir and K, K so forming the primary trigger, but this
NA II
I
75
Target In magnetic field
I
HErøn
WI
W
2
Calorimeter
Fig. 4. Apparatus used in the trigger of experiment NAI I.
would still result intarget a 2000: 1 background level. of ESOP and and will behind read the data from MWPC calculate planes the in front reaction angle so reject the to small angle region contaming most of the background. 5.4. INFN Trieste
scope. It searches for the trigger particle and measures its momentum from the deflection it has undergone in the field of the magnet. This is done simply by looking at the miss distance from the measured trajectory to the target position. Meanwhile the second ESOP has been reading data from the electron calorimeter over a normal CAMAC branch and the ABC. It calculates the energy deposited by the trigger particle and, on receiving its momentum from the first ESOP, has the necessary information to recognise a high momentum hadron. If the event survives this check, the first ESOP goes on to look for a possible second electron of a pair, using coplanarity, The ESOPs veto about 75% of the primary triggers and have an 80% efficiency for accepting good events. The resultant decrease in dead time has increased the sensitivity of the experiment by a factor of about 2. In addition, there are 2/3 fewer events to be handled off-line to obtain a given number of good ones.
5.3.This S166 CERN PS experiment, east area (see currently fig. 5),being is another set upexample in the of the MWPC—RMH—ESOP combination for tnggering. E hyperon states are being studied by the S166
This group is setting up an experiment at Saclay and also will use ESOP with MWPCs and RMH in a similar geometrical lay-out to S 166, but in this case the selection criteria are reversed and ESOP will be used to select very small angle scattering. 5.5. R807 [13] This experiment at the CERN ISR represents a sophisticated use of ESOP. It aims to study high transverse-momentum events, triggering on the emergence of a single high momentum particle from the interaction zone, This has to be done over a solid angle of about 1 sr, which consider-
R 807
irical drift chambers PC 2
Drift
chamber
sector pair)
~I J J J~ ~JL..I._~_f_ J ~
MWPCs
~Tar~et
MWPCs
Fig. 5. The concept of the trigger of experiment S 166.
fig. 6. Apparatus used in the trigger of experiment R807.
76
D.A. Jacobs
/ Experience
ably complicates the trigger. The R807 team has attacked this problem with a multilevel trigger, The parts of the apparatus used for triggering are shown in simplified cross-section in fig. 6. A hardwired pretrigger using hodoscopes and bands in the MWPCs PC1 and PC2 makes an initial selection of tracks coming almost straight from the interaction region, but after this the background contamination still exceeds 100: 1. The task of the ESOP is to refine the trigger by finding and measuring the momentum of the candidate trigger particle, which it does using data from the set of cyclindrical drift chambers in the axial magnetic field. An interesting point of the application is that the pretrigger is used to select which zones or sectors of the drift chambers should be read out to ESOP. This procedure considerably speeds read-out and the trigger calculation, The drift chamber data is digitised in a DTR system modified for selective read-out [14]. The data is transferred to ESOP by the ROMULUS bus router and B24 module mentioned earlier. Normally, for each canditate particle four samples of data from each of two sectors (see fig. 6b) are read to ESOP. The software in the processor is capable of finding the candidate track in the presence of background and measures its momentum by the sagitta of its curvature in the magnetic field, The efficiency of the trigger is about 60% at twice the cut-off momentum and. the background is reduced by a factor of between 200 and 750 depending on the cut-off criteria chosen, The read-out time for a whole event is of the order of 30 ms, while the time for ESOP to reject a trigger is about 120 p.s. In view of the high available primary trigger rate, the sensitivity of the experiment is increased by about the same factor as that by which the background is reduced,
6. Experience and future plans The experience gained with the experiments mentioned above allows some conclusions to be drawn about the problems of supporting trigger processors such as ESOP in general use. For physicists with some previous assembler language programming experience and a grasp of the trigger
with ESOP
hardware, the development of algorithms in ESOP is not a problem. For this the cross-assembler and simulator are of great use. Naturally, however, each group would like to run the software on its own computer. Even with nominally transportable programs as in the case of ESOP, the support effort needed for installation on a new computer type and for maintenance of distributed software is fairly considerable. For the hardware, the cornbination of first level trigger logic, detector readout systems and processor forms a rather complex, closely coupled installation. Support personnel with detailed knowledge of one part are unlikely to be equally expert in the others. The resultant splits in responsibility can give rise to difficulties which are not unlike those associated with a computer centre configuration with equipment from various vendors. For smooth operation, it has proved essential for some member of the experimental team to become closely acquainted with the whole installation and the ESOP hardware in particular. The latter is usually achieved by having him participate in the testing of the processor for his experiment. With, in addition, a knowledge of his trigger and read-out systems, he is then in a good position to efficiently isolate problems. It is of course important that such expertise remain available throughout the life of the experiment. The design of ESOP is by now fairly mature and from its present applications it is possible to single out some aspects whose improvement would bring most returns in a second generation design. The superposition on the microcoded machine of a higher level instruction set borrowed from an existing mincomputer would be attractive in that it would then allow programming in all the languages supported on that mini. This would, however, imply a 1oss of access to the parallelism of the machine, and the indications are that most trigger code consists of time-critical loops. It would thus not be possible to write any significant part of the software in such a manner without an appreciable loss in performance. It does not seem likely that a very large factor can be gained in cycle time, bearing in mind that the techniques which allow supercomputers to achieve 20—30 ns cycle times are likely to remain inaccessible to constructors of small specialised machines such as
D.A. Jacobs
/
Experience with ESOP
ESOP for some time. On the other hand, gains can be made by extending the parallelism of the machine and subdividing the clock period to allow phased execution of more linked functions within a cycle. Performance would be increased and programming simplified by having a duplicate data bus and symmetrical access from the ALU to the buses and register files. A wider instruction word would be needed for the extra operations, but this would also simplify programming by eliminating clashes between fields. In view of the importance of 1oop performance, the loop counter logic should be extended to multiple levels. Few detector read-out systems organise their data for ease of access according to the physical structure of the detectors. For example, the RMH system merely outputs a list of channels hit in order of increasing channel number, Thus the first part of many trigger algorithms involves a time wasting search for data from particular wire planes, etc. In some special cases this problem has been attacked with additional read-out hardware, but it would be attractive in a future machine to have dedicated general purpose I/O processors able to spy on the incoming data streams and, for exampIe, build up pointer tables to wire planes in real time. In the future it seems likely that Fastbus will provide a good system for use with trigger processors, incorporating as it does, high speed with the possibility of easy multicrate access. Thus any new machine should be able to address Fastbus in an efficient way. Implementing these improvements with modern technology, it should be possible to produce an easily maintainable machine with several times the processing power of the present ESOP.
Acknowledgement
77
various times, but the main thanks are due to T. Lingjaerde, D. Marland and A. Fucci who designed and built the hardware and to D. Myers and W. Jank who wrote the assembler and simulator. The support and help of the interested experimental teams was extremely important for improving the design and constructing the necessary interfaces and they continue to give valuable guidance for future improvements. In this area, particular mention must be made of D. Giddings, B. Heck, J. Hooper, G. Lutjens and S.O. Nielsen,
References [1] T. Lingjaerde, CERN - Data Handling Division, DD/75/17 (May 1975). T. Lingjaerde, CERN — Data Handling Division, DD/76/9 (May 1976). T. Lingjaerde and D. Marland, CERN — Data Handling Division, DD/77/8 (June 1977). D. Marland, CERN — Data Handling Division, DD/78/l3 (August 1978). D. Jacobs, CERN — Data Handling Division, DD/80/22 (October 1980). [2] J.-P. Vanuxem, EP-Electronics Note 80-06 (September 1980). [3] T. Lingjaerde, ESOP application note no. 1, CERN — Data Handling Division (January 1979). [4] Lindsay et al., NucI. Instr. and Meth. 156 (1978) 329. [5] J.-P. Melot, private communication (1978). [61P.J. Ponting, EP-Electronics Note 80-01 (February 1980). [7] S. Cairanti and B. Heck, CERN/EF/R807-ESOP, 80-1 (July 1980). [8] C. Ljuslin, private communication (1979). [9] W.W.M. Allison et al., CERN SPSC/75-l5/P-42 (1975). [101 H. Anders, CERN/EP/EHS/PH 80-2, 103-114 (March 1980). [11] W.W.M. Allison et al., Nuci. Instr. and Meth. 119 (1974) [12] C. Damerell et a!., Comput. Phys. Commun. 22 (1981) 349. [13] B. Heck et al., Presented at the Europhysics Conf. on Computing in high energy and nuclear physics, Bologna, Italy (9—12 September 1980).
As mentioned in the introduction, many people have contributed to the development of ESOP at
[14] S. Cairanti, G. Di Tore and B. Heck, CERN/EF/R807ESOP, 80-2 (July 1980).
69
EXPERIENCE WITH ESOP, A FAST MICROPROGRAMMABLE TRIGGER PROCESSOR D.A. JACOBS CERN Geneva, Switzerland
ESOP is a fast processor designed to front-end the data-acquisition computer in high energy physics experiments and perform second level trigger calculations. It is in use in five experiments at CERN and Saclay. It will be shown how ESOP realises its high performance and how such a machine may he supported in an experiment. For trigger calculations the efficiency of the connection to the detector read-out system is extremely important and the ways in which this is done in practice with ESOP will be discussed. An outline of some existing trigger algorithms will be given and some conclusions drawn on desirable features of a second-generation processor based on experience with ESOP.
1. Introduction This paper describes a fast, modular, microprogrammable processor ESOP and the ways in which it is being put to use for second level trigger and other fast calculations in a number of high-energy physics experiments. In doing this, it draws on the work of many people who have contributed to the development, not only from DD division CERN where the processor was designed [I], but also from the various experimental teams. In recent years the complexity of logic used for triggering high-energy physics experiments has increased considerably. In part this is due to the increased complexity and fine structure of the detectors themselves, covering ever larger solid angles with higher precision. In addition, however, there is a tendency to use more selective triggers in order to obtain larger samples of interesting events in the time available. This is because the data accumulation rate of an experiment is often now limited either by the read-out time of the detectors or by the off-line processing power available. It is thus important not to waste any of this capacity by carrying through data which are finally rejected. The quantities of data stored for each event and the corresponding read-out time continue to grow, and sizes in excess of 20 Kbytes with upwards on 20 ms read-out time are not uncommon, How then are such selective triggers con001 O-4655/82/0000--0000/$02.75
©
structed? There is always a relatively simple first level which must be very fast (< 1 ms) and which is used to freeze the data in the detector read-out systems. For this, hardwired high-speed logic is the only possibility. After the data are frozen, the experiment is dead until either the data are read out to the on-line computer or the read-out systems are cleared and reset. Some experiments are only practical if the decision to clear or to read out can be made in a few microseconds. In such cases hardwired logic is often also used for this second level of triggering. If, however, much data is needed for the trigger decision, as when a large solid angle is covered, the logic and cabling become very complex, inflexible and expensive. In less critical situations, or as a third level, when decision times upwards from a few tens of microseconds are acceptable, a fast programmed processor often offers a more economic and flexible solution. The fact that such processors read the detector data over the normal bus structures makes for relatively simple installation and the programmability allows scope for easy refinement of the trigger algorithm during the life of the experiment. ESOP belongs to this category and has been built with the aim of producing as fast a processor as possible with reasonably simple hardware. It runs as a slave of the normal data acquisition computer, controlled via CAMAC interfaces. The detector data which it reads is normally also available to the host corn-
1982 North-Holland
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D.A. Jacobs
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provision was made for unsigned 16 bit arithmetic as well as the more usual 2s complement representation. Floating-point was not considered necessary for the applications envisaged. The CPU cycle
ESOP CONFIGURATIONS
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Experience with ESOP
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set to do all normal processing and memory opera-
tions in one cycle, only exception being X 16 bit multiply level of processor which the required performance two which cycles. could The16actual then
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Fig. I. The modules constituting an ESOP configuration.
puter via bus branching logic or from the memory of ESOP. For this reason, it can also be used as an intelligent read-out controller, doing data cornpression or improving the data structure. Exampies of these uses will be given later.
which be reached could depended be carriedonout theinnumber parallel.ofSeparate actions ALUs were thus provided for data processing, data address calculation and instruction address calculation. Unless the required operations are highly ordered, however, it is difficult to make full use of such parallelism without allowing the programmer full control over it. The processor was thus made microprogrammable at the user level with 48 bit wide instruction words built out of fields controlling the various gating and processing functions. Having the data and instruction memones separate has the additional advantage of allowing simultaneous access to both. With this basic layout in mind, the processor was built up around four buses: instruction (48 bits), instruction address (12 bits), data (16 bits) and data address (16 bits). The arithmetic unit has a file of
2. The processor design The processor is built with Schottky-TTL technology in CIM mechanics. Its modular layout has allowed the design to evolve over a number of years as new circuits became available and new needs arose. Fig. I shows a block diagram of the modules available and the way in which they may be configured together, although it is unlikely that any one application would need all the options shown, The word length for data in memory and for arithmetic calculations was chosen as 16 bits, which is sufficient for most detector read-out systems and directly compatible with typical on-line minicomputers. Detector data are normally positive integers and to make full use of the word length,
Table I Instruction sequence for synchronisation with external trigger signals Instr. no.
4
Set up break logic to skip + I on occurrence of trigger signal and ±2 on abort signal Change instruction ALU op-code from A + I (normal sequence) to A + B, processor will loop on next instruction until a non-zero value (I or 2) is placed in B by the break logic Enable break, processor loops here waiting for break condition Come here if trigger received
5
Come here if abort signal recieved
2
3
D.A. Jacobs
LOOP
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Experience with ESOP
CONTROL
a)
Table 2
Instruction sequence for loop to search a memory block for a word of a particular value
N:rrnoh A±I
~AI~UIM
Load loop counter with block size, set break logic to
ALU 2 bI
71
LOOSE
COMPARE
B
-
I
A
A— B
3
Read first word to data bus, present data memory with incremented address, transfer value for comparison to ALU B register, set instruction memory ALU to loop next instruction as in table I, instruction 2
4
Enable break, transfer word from data bus to ALU A register, compare it with B, read next word from data memory to data bus, present data memory with following incremented address, (processor loops on
~
OP~A-B OP A-B~O:E-)A-BI-I A - B < 0: E CIA-B)- I
SIGN
skip + I on loop counter =0 and +2 on arithmetic Get address of first word, present it to the data memory, set the data memory ALU to auto-merementit
this instruction until break condition occurs) c)
BIT
5 6
SEARCH
DATA WORD
10)0 1101010 0101 I IS
12
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7
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Come here if block scanned without match Come here if match found
BITT
Fig. 2. Special features of ESOP anthmetic power.
eight 16 bit registers with simultaneous read/write access for local data storage. In the instruction memory unit, instructions are prefetched. Its built-in ALU is used to generate normal instruction sequencing, jumps and subroutine calls. Multiway conditional skips and branches are generated by deriving address modifiers from the arithmetic condition codes. Since the processor is thought to be dedicated to a particular task, a true interrupt system is not required, but synchronisation with outside events is obtained by a “break” logic which generates multiway branches in a similar way to branch-oncondition. This is illustrated by the logic sequence shown in table 1. The data memory control unit has a file of eight registers for address storage, and, with its own ALU, can carry out normal, base and indexed
addressing with autoincrement or decrement in any steps. It provides access from ESOP to the data memory which is built in 4 or 8 Kword modules up to a maximum of 64 Kwords. Sets of memory modules are grouped under the control of up to eight four-port controllers. One port is dedicated to ESOP via the data memory controller, while the other three are Direct Memory Access (DMA) ports equipped with all the necessary control logic, memory address and word count registers. This will be explained further in discussing processor interfacing. Apart from the parallelism, another route has been taken to improve processor performance, namely the introduction of processor functions specially adapted to the proposed applications. Trigger software makes heavy use of loops with conditional termination, and to minimise thr loop overheads, a presettable loop counter is included which may be counted down for each loop execution (fig. 2a). The ‘loop counter = 0’ state is available along with the normal arithmetic conditions for use in a multiway branch at the end of the loop. This is illustrated in table 2 for the special case of a memory search using a single instruction. A very common operation in trigger calcula-
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tions is that of ‘loose-comparison’, i.e. A B
ESOP memory and that of the host computer. The transfer rate is that of the CAMAC system. since the ESOP side is very much faster. A transportable cross-assembler has been written to implement the assembly language described above and ESOP code is typically developed with
value tested.
the editor and file system of the host computer.
Lastly, a module operating in parallel with the normal arithmetic unit is provided for bit operations. Shifts of any kind and length can be made in one cycle. The bit numbers of bits set in a word can be found as shown in fig. 2c at the rate of one bit per cycle. This is useful for decoding pattern unit contents for instance, Programming the processor by setting the individual bits of instruction words would be obvi-
The cross-assembler is able to check the syntax of the source code as well as detect clashes of op-codes and straight-forward clashes of bus use. For the down-line loading and control of ESOP. two situations can be distinguished: program development and integration in the production dataacquisition software. For the former, there is a complete interactive FORTRAN program with commands to load and dump instruction and data
ously very tedious. For this reason a kind of assembler language was developed in which each
memory, to access and modify individual words and to start and stop ESOP. With the help of some
field is represented by an operation mnemonic, sometimes with parameters. For tnstance, ALO APB sets the arithmetic unit ALU code to A + B while LDA loads the ALU A register from the data bus. In as far as the fields do not clash with one another, such micro-operations may be freely logically ORed together to make up an instruction word. Thus the programming of ESOP is not difficult for anyone with assembler language programming experience. The challenge of exploiting the parallelism to the full may be taken up at a second phase.
standard ESOP routines which may be placed in an unused part of memory, it is also possible to examine the address and data register files. Using this package and the hardware break-point logic, fully interactive debugging of software is possible. For incorporating ESOP in a data-acquisition systern, there is a library of routines for loading and control. The direct access to ESOP memory allows the use of playback of previously recorded data for the tuning of trigger algorithms. To the cross-assembler has been added a logical simulator of the processor hardware. All aspects of ESOP software run on the simulator with the exception of external breaks and DMA transfers. The object code is transfered from the assembler
—
3. Connection to the host computer and supporting software As already mentioned, ESOP operates as a slave of the data acquisition computer to whose CAMAC system it is connected by two single-width interface modules. One is used for instruction memory access and processor control, while the other is connected directly to the data memory modules via the second ports of the four-port DMA controllers. The registers in these controllers may be set either from ESOP or by CAMAC. Thus with the added help of a CAMAC DMA controller, direct block transfers can be made between the
to the simulator and the ‘data memory’ of the simulator may be preloaded, either by hand or from files in the same format as for the actual machine. In this way, the simulator can be run with ‘real’ data. The simulator is a very considerable aid to the development of ESOP programs. It allows the testing of algorithms in the early planfling stages of experiments before the hardware is
built and has added features such as tracing execution time, multiple break pointing and nondestructive examination of full processor states between instructions, which greatly eases the debugging process.
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Experience with ESOP
4. Connection of ESOP to the detectors of experiments 4.1. CAMAC The most generally used read-out system for detectors is a set of CAMAC branches, and by means of an Auxiliary Branch Controller (ABC) module [2], ESOP as well as the main data acquisition system may control such a branch. ESOP drives the ABC via an I/O module with sets of latches which can be connected to the data bus [3]. CAMAC transactions are thus program controlled, but due to the speed of ESOP, may proceed at the maximum rate for the branch. The time taken to read in the detector data is of course a critical parameter for the overall performance of the trigger calculation and in this respect CAMAC is disproportionately slow if more than a few words have to be read. For this reason, considerable effort has been put into providing other, faster methods. These use DMA transfer into the data memory. Each four port controller provides two such channels for external devices, multiplexed with each other. Since each of the possible eight controllers can handle data at 8 Mbyte/s, a total sustained rate of 64 Mbyte/s can be achieved, Interfaces to several popular systems have been built. 4.2. RMH [4] This is a high speed MWPC read-out system in ECL logic, which is now being extended for use with other detectors. Transfers are possible at about 12 Mbyte/s, and this is the fastest read-out system currently being used with ESOP. The basic RMH system allows for the use of local intelligence by providing a data fan-out module and non-destructive read-out. The ESOP interface [5] allows autonomous start of transfer after a strobe and provides a read-out busy signal for use as a veto. The end of transfer condition is coupled to the ESOP break logic. 4.3. ROMULUS [6] Access to a ROMULUS vertical bus is by a three way routing unit [7]. This allows transfers
fl
from branch to ROBD, from branch to ESOP or from ESOP to ROBD. The routing unit is coupled to ESOP memory by an adaptor module B24. The data-flow switching of the routing unit and B24 are controlled by ESOP’s I/O module. 4.4. DTRC [8] This is a buffered version of the DTR/DEC system for drift chamber digitizing with a vertical bus operating at 300—500 ns per word. The branch driver module includes a two-way bus switch (from branch to CAMAC or ESOP or both) and interface to ESOP data memory. Other special interfaces have been constructed for particular detectors. These will be described below in the context of the experiments in which they are used.
5. Present uses of ESOPs in experiments A total of 9 ESOPs are currently in use for five experiments. A short look at these applications will give an introduction to the practical application of the processor. The experiments are all very different from each other, the only common point being the desire to improve performance with an intelligent trigger calculation in a few hundred microseconds. MWPCs read with the RMH systern are seen to be the most popular detecors for the triggers, and there isoperation, no doubt non-destructive that its combination of dead-timeless fast read-out and fast clear makes the RMH systern very attractive for this purpose. 5.1. European Hybrid Spectrometer (EHS) [9] This comprehensive spectrometer for hadron physics at the CERN SPS incudes, as a vertex detector for some experiments, a Rapid Cycling Bubble Chamber (RCBC) of 80 cm diameter operating at 30 Hz. A primary trigger from scintillator hodoscopes is supposed to indicate that an event occurred in the chamber and thus to enable the taking of a picture. However, only events in the central region of the chamber can be analysed and the ratio of useful/unwanted target material is
74
D.A. Jacobs
EHS
/
position of the beam track in Dl to about 1 mm. The effect of the magnetic field is handled by a look-up table. Having done this, ESOP waits until the data from the diode arrays has arrived (read-out
OFVT RCBC
takes 200~i).If no hit in Dl is found near enough the expected position (remember IA— BI<~, the event occurred upstream of Dl and can be rejected.
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2
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—
Accept
______________
ESOP CODE
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—
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FOUND
NO
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YES FINE PREDIC ON
D2
FOUND IN D~ NO
YES
NO I~~UALT
Experience with ESOP
Otherwise the hit on Dl is used to make a refined prediction on D2 to about 400 p.m. If no hit occurred there, the event is taken to have occurred in the useful volume and is accepted. If a hit is found, a zone a few millimeters wide around this point is searched for other hits, which, if found, would indicate that what is being seen is the foward jet of a good event. If there is just a single hit, the event probably occurred down-stream and is rejected. Monte Carlo calculations indicate an efficiency of above 90% for this trigger. A second ESOP is used at EHS to handle data from the large-volume drift chamber ISIS [11]. Using four DMA controllers in parallel, 16 Kwords of data are read from this detector in 2—3 ms, before charge leakage from its capacitor memories has time to spoil its iontzation measuring accuracy. ESOP compacts this data to about 2/3 of its original size in 5—7 ms by removing unused chan.
VET
YES
OK
Fig. 3. The principle of the optical fiducial volume ingger for EHS.
such that only about 1/3 of the primary triggers represent good events. Since the cameras are only capable of 15—20 Hz, expensive dead time can be reduced by making a more selective trigger decision in time to inhibit the picture taking. An ESOP is being programmed for this task using the principle shown in fig. 3. The detectors are MWPCs (Ul and U3) and two novel diode arrays Dl and D2 [10] looking into the bubble chamber and imaging tracks with a secondary flash some 600 p. before the normal picture taking. They can be thought of as acting like MWPCs with single planes of horizontal wires. They give a spatial resolution of about 180 p.m and are read out to ESOP via a special interface at 100 ns/word. With a simple calculation based on one plane in Ul and 4 planes in U3, ESOP can predict the
nels. 5.2. NAil [12] This experiment at CERN is an example of the use of a more specialised trigger to select interactions of a particular kind. The parts of the apparatus contributing to the trigger are shown in simplified form in fig. 4. The experiment aims to study charm particles and uses as trigger the appearance of a single electron from the decay of such a particle. The primary trigger is generated by the Cerenkov and the electron calorimeter, but is heavily contaminated with unwanted triggers due to high momentum hadrons and electron pairs. The total read-out time for an event is several milliseconds and a significant increase in sensitivity is got by using an intelligent trigger to abort the read-out in such cases. Two ESOPs are used for this purpose. One reads data via the RMH system from 4 planes of MWPCs Wl and W2 and from a scintillator hodo-
D.A. Jacobs
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Experience with ESOP
K, ~r strangeness exchange reactions. Time-of-flight and liquid hydrogen ~erenkovs will be used to distinguish these reactions from passing ir, ir and K, K so forming the primary trigger, but this
NA II
I
75
Target In magnetic field
I
HErøn
WI
W
2
Calorimeter
Fig. 4. Apparatus used in the trigger of experiment NAI I.
would still result intarget a 2000: 1 background level. of ESOP and and will behind read the data from MWPC calculate planes the in front reaction angle so reject the to small angle region contaming most of the background. 5.4. INFN Trieste
scope. It searches for the trigger particle and measures its momentum from the deflection it has undergone in the field of the magnet. This is done simply by looking at the miss distance from the measured trajectory to the target position. Meanwhile the second ESOP has been reading data from the electron calorimeter over a normal CAMAC branch and the ABC. It calculates the energy deposited by the trigger particle and, on receiving its momentum from the first ESOP, has the necessary information to recognise a high momentum hadron. If the event survives this check, the first ESOP goes on to look for a possible second electron of a pair, using coplanarity, The ESOPs veto about 75% of the primary triggers and have an 80% efficiency for accepting good events. The resultant decrease in dead time has increased the sensitivity of the experiment by a factor of about 2. In addition, there are 2/3 fewer events to be handled off-line to obtain a given number of good ones.
5.3.This S166 CERN PS experiment, east area (see currently fig. 5),being is another set upexample in the of the MWPC—RMH—ESOP combination for tnggering. E hyperon states are being studied by the S166
This group is setting up an experiment at Saclay and also will use ESOP with MWPCs and RMH in a similar geometrical lay-out to S 166, but in this case the selection criteria are reversed and ESOP will be used to select very small angle scattering. 5.5. R807 [13] This experiment at the CERN ISR represents a sophisticated use of ESOP. It aims to study high transverse-momentum events, triggering on the emergence of a single high momentum particle from the interaction zone, This has to be done over a solid angle of about 1 sr, which consider-
R 807
irical drift chambers PC 2
Drift
chamber
sector pair)
~I J J J~ ~JL..I._~_f_ J ~
MWPCs
~Tar~et
MWPCs
Fig. 5. The concept of the trigger of experiment S 166.
fig. 6. Apparatus used in the trigger of experiment R807.
76
D.A. Jacobs
/ Experience
ably complicates the trigger. The R807 team has attacked this problem with a multilevel trigger, The parts of the apparatus used for triggering are shown in simplified cross-section in fig. 6. A hardwired pretrigger using hodoscopes and bands in the MWPCs PC1 and PC2 makes an initial selection of tracks coming almost straight from the interaction region, but after this the background contamination still exceeds 100: 1. The task of the ESOP is to refine the trigger by finding and measuring the momentum of the candidate trigger particle, which it does using data from the set of cyclindrical drift chambers in the axial magnetic field. An interesting point of the application is that the pretrigger is used to select which zones or sectors of the drift chambers should be read out to ESOP. This procedure considerably speeds read-out and the trigger calculation, The drift chamber data is digitised in a DTR system modified for selective read-out [14]. The data is transferred to ESOP by the ROMULUS bus router and B24 module mentioned earlier. Normally, for each canditate particle four samples of data from each of two sectors (see fig. 6b) are read to ESOP. The software in the processor is capable of finding the candidate track in the presence of background and measures its momentum by the sagitta of its curvature in the magnetic field, The efficiency of the trigger is about 60% at twice the cut-off momentum and. the background is reduced by a factor of between 200 and 750 depending on the cut-off criteria chosen, The read-out time for a whole event is of the order of 30 ms, while the time for ESOP to reject a trigger is about 120 p.s. In view of the high available primary trigger rate, the sensitivity of the experiment is increased by about the same factor as that by which the background is reduced,
6. Experience and future plans The experience gained with the experiments mentioned above allows some conclusions to be drawn about the problems of supporting trigger processors such as ESOP in general use. For physicists with some previous assembler language programming experience and a grasp of the trigger
with ESOP
hardware, the development of algorithms in ESOP is not a problem. For this the cross-assembler and simulator are of great use. Naturally, however, each group would like to run the software on its own computer. Even with nominally transportable programs as in the case of ESOP, the support effort needed for installation on a new computer type and for maintenance of distributed software is fairly considerable. For the hardware, the cornbination of first level trigger logic, detector readout systems and processor forms a rather complex, closely coupled installation. Support personnel with detailed knowledge of one part are unlikely to be equally expert in the others. The resultant splits in responsibility can give rise to difficulties which are not unlike those associated with a computer centre configuration with equipment from various vendors. For smooth operation, it has proved essential for some member of the experimental team to become closely acquainted with the whole installation and the ESOP hardware in particular. The latter is usually achieved by having him participate in the testing of the processor for his experiment. With, in addition, a knowledge of his trigger and read-out systems, he is then in a good position to efficiently isolate problems. It is of course important that such expertise remain available throughout the life of the experiment. The design of ESOP is by now fairly mature and from its present applications it is possible to single out some aspects whose improvement would bring most returns in a second generation design. The superposition on the microcoded machine of a higher level instruction set borrowed from an existing mincomputer would be attractive in that it would then allow programming in all the languages supported on that mini. This would, however, imply a 1oss of access to the parallelism of the machine, and the indications are that most trigger code consists of time-critical loops. It would thus not be possible to write any significant part of the software in such a manner without an appreciable loss in performance. It does not seem likely that a very large factor can be gained in cycle time, bearing in mind that the techniques which allow supercomputers to achieve 20—30 ns cycle times are likely to remain inaccessible to constructors of small specialised machines such as
D.A. Jacobs
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Experience with ESOP
ESOP for some time. On the other hand, gains can be made by extending the parallelism of the machine and subdividing the clock period to allow phased execution of more linked functions within a cycle. Performance would be increased and programming simplified by having a duplicate data bus and symmetrical access from the ALU to the buses and register files. A wider instruction word would be needed for the extra operations, but this would also simplify programming by eliminating clashes between fields. In view of the importance of 1oop performance, the loop counter logic should be extended to multiple levels. Few detector read-out systems organise their data for ease of access according to the physical structure of the detectors. For example, the RMH system merely outputs a list of channels hit in order of increasing channel number, Thus the first part of many trigger algorithms involves a time wasting search for data from particular wire planes, etc. In some special cases this problem has been attacked with additional read-out hardware, but it would be attractive in a future machine to have dedicated general purpose I/O processors able to spy on the incoming data streams and, for exampIe, build up pointer tables to wire planes in real time. In the future it seems likely that Fastbus will provide a good system for use with trigger processors, incorporating as it does, high speed with the possibility of easy multicrate access. Thus any new machine should be able to address Fastbus in an efficient way. Implementing these improvements with modern technology, it should be possible to produce an easily maintainable machine with several times the processing power of the present ESOP.
Acknowledgement
77
various times, but the main thanks are due to T. Lingjaerde, D. Marland and A. Fucci who designed and built the hardware and to D. Myers and W. Jank who wrote the assembler and simulator. The support and help of the interested experimental teams was extremely important for improving the design and constructing the necessary interfaces and they continue to give valuable guidance for future improvements. In this area, particular mention must be made of D. Giddings, B. Heck, J. Hooper, G. Lutjens and S.O. Nielsen,
References [1] T. Lingjaerde, CERN - Data Handling Division, DD/75/17 (May 1975). T. Lingjaerde, CERN — Data Handling Division, DD/76/9 (May 1976). T. Lingjaerde and D. Marland, CERN — Data Handling Division, DD/77/8 (June 1977). D. Marland, CERN — Data Handling Division, DD/78/l3 (August 1978). D. Jacobs, CERN — Data Handling Division, DD/80/22 (October 1980). [2] J.-P. Vanuxem, EP-Electronics Note 80-06 (September 1980). [3] T. Lingjaerde, ESOP application note no. 1, CERN — Data Handling Division (January 1979). [4] Lindsay et al., NucI. Instr. and Meth. 156 (1978) 329. [5] J.-P. Melot, private communication (1978). [61P.J. Ponting, EP-Electronics Note 80-01 (February 1980). [7] S. Cairanti and B. Heck, CERN/EF/R807-ESOP, 80-1 (July 1980). [8] C. Ljuslin, private communication (1979). [9] W.W.M. Allison et al., CERN SPSC/75-l5/P-42 (1975). [101 H. Anders, CERN/EP/EHS/PH 80-2, 103-114 (March 1980). [11] W.W.M. Allison et al., Nuci. Instr. and Meth. 119 (1974) [12] C. Damerell et a!., Comput. Phys. Commun. 22 (1981) 349. [13] B. Heck et al., Presented at the Europhysics Conf. on Computing in high energy and nuclear physics, Bologna, Italy (9—12 September 1980).
As mentioned in the introduction, many people have contributed to the development of ESOP at
[14] S. Cairanti, G. Di Tore and B. Heck, CERN/EF/R807ESOP, 80-2 (July 1980).