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Experimental and analytical study on chip hot spot temperature
International Journal of Heat and Mass Transfer 54 (2011) 2066–2072
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International Journal of Heat and Mass Transfer journal homepage: www.elsevier.com/locate/ijhmt
Experimental and analytical study on chip hot spot temperature Chan Byon, Kyosung Choo, Sung Jin Kim ⇑ School of Mechanical, Aerospace and Systems Engineering, Korea Advanced Institute of Science and Technology, Daejeon 305-701, Republic of Korea
a r t i c l e
i n f o
Article history: Received 8 July 2010 Received in revised form 3 December 2010 Accepted 3 December 2010 Available online 1 February 2011 Keywords: Hot spot temperature Spreading resistance
a b s t r a c t In this study, the effects of various chip thicknesses on the chip hot spot temperature are investigated using both experimental and analytical methods. The temperature distribution in the chip is measured under the various chip thicknesses (21.5–400 lm) and various heater power conditions (0.2–0.5 W). In order to support the experimental data and gain a physical insight, closed-form analytic expressions are suggested. Based on the suggested analytic expressions, the effects of the nondimensional contact radius, nondimensional substrate thickness, and the Biot number are investigated. Ó 2010 Elsevier Ltd. All rights reserved.
1. Introduction Microelectronic components have become the heart of many modern electronic products from home/office PC systems to advanced military/defense electronic systems. However, microelectronic devices require power, and the conversion of electrical energy to thermal energy is an unavoidable byproduct of the normal operation of any electronic device. This leads to higher microprocessor temperature that, if not properly managed, will significantly affect the performance, power leakage, and reliability of microelectronic chips, assemblies, and products. Today’s semiconductor technology trend is heading towards thinner and smaller packages [1,2]. There are many advantages in using thin chips, including reduced space which allows more functionality per unit volume in a 3D package [3]. However, miniaturization and design complexity are causing highly non-uniform power distribution on the microprocessors, producing ‘‘high-flux hot spots’’. As the chip thickness and die size decrease, the chip temperature and the hot spot temperature in a chip increase [4,5]. This is due to the fact that the thermal spreading resistance (spreading resistance hereafter) increases with decreasing chip thickness and die size [6,7]. The spreading resistance refers to the thermal resistance that occurs when heat flows out of a narrow region into a larger region. If the heat dissipated from the component does not spread out efficiently, the hot spot temperature may reach an unacceptable level causing damage. To reduce the hot-spot-induced thermal damage in chips, it is important to predict the hot spot temperature. Many researchers tried to predict the hot spot temperature. Akiyama et al. [8] and Lin et al. [9] performed numerical simula⇑ Corresponding author. Tel.: +82 42 350 3043; fax: +82 42 350 8207. E-mail address: [email protected] (S.J. Kim). 0017-9310/$ - see front matter Ó 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.ijheatmasstransfer.2010.12.022
tions to predict the hot spot temperature. Chiu et al. [10] used infrared microscopy to measure the temperature of a solder joint. However, they did not measure the hot spot temperature directly because the hot spot is not exposed to the ambient. Wang and Bar-Cohen [11] developed a numerical model for predicting the hot spot temperature and included TEC in their numerical model to reduce the hot spot temperature. Even though plenty of researchers have tried to predict the hot spot temperature, the hot spot temperature and the temperature distribution on a semiconductor chip could not be directly measured because there were no high resolution micro-sensors. In this study, the hot spot temperature and temperature distribution in the chip are measured utilizing the diode temperature sensor array (DTSA) previously developed by Han and Kim [12]. In their research, the experiments were performed with fixed chip thickness. In contrast, the purpose of the present experimental study is to find the effect of the various chip thicknesses on the hot spot temperature. The experimental parameters include the various chip thicknesses (21.5, 31, 42, 100, 200, and 400 lm) and various heater power conditions (0.2, 0.3, 0.4, and 0.5 W). Another purpose of the present study is to suggest an analytic expression for predicting the spreading resistance. The spreading resistance is a key parameter used in predicting the hot spot temperature and, accordingly, many studies were devoted to developing analytic expressions for spreading resistance [13–17]. Understanding of spreading resistance allows us to gain a physical insight, and helps in determining the physical reasonableness of experimental hot spot temperature data. In this study, closed-form analytic expressions for spreading resistance are suggested and compared with measured hot spot temperature. Based on the suggested analytic expressions, the effects of the nondimensional contact radius, nondimensional substrate thickness, and the Biot number are considered.
C. Byon et al. / International Journal of Heat and Mass Transfer 54 (2011) 2066–2072
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Nomenclature Bi h H k qw r,z r1 r2 T
Biot number () heat transfer coefficient (W/m2K) substrate thickness (m) thermal conductivity of the substrate (W/mK) heat flux at the source surface (W/m2) cylindrical coordinate (m) source radius (m) substrate radius (m) temperature (K)
Fig. 1. Circuit configuration of a DTSA system.
2. Experiment In order to measure the hot spot temperature and the temperature distribution, a diode temperature sensor array (DTSA) developed by Han and Kim [12] is used. The DTSA is innovative temperature sensor arrays which can measure the temperatures of 1024 points in the area of 8 8 mm. Diodes are arranged in 32 32 array in the DTSA. Eight poly-silicon heaters of 1 kX are embedded onto a silicon wafer for heating the specific area of the DTSA chip. The DTSA chip is mounted on the PCB by using a flip-chip packaging method. The size of the designed PCB is 50 50 mm. Solder balls of 300 lm in diameter is used for interconnecting the PCB pads and the DTSA chip pads. The thermal conductivities of the components are summarized in Table 1. A DTSA signal board was also developed for scanning the diode and conditioning the diode signals of the DTSA. It consisted of a FPGA (field programmable gate array), an amplifier, a power driver, an analog MUX (multiplexer), a constant current source, and a data acquisition board, as shown in Fig. 1. The FPGA was used for selecting which diode would be measured among the 32 32 diodes. A Verilog program was used to operate the FPGA chip. The 1024 measured voltage drops were multiplexed into one signal through the analog MUX. These signals were amplified by the amplifier circuits. The data acquisition board (PCI-6052E, National Instruments) was used for A/D conversion of the signals and for sending control sig-
Greek symbols nondimensional contact radius () nondimensional substrate thickness () W nondimensional spreading resistance ()
e s
Subscripts 1 ambient () conv convection ()
nals to the power driver for heating the surface of the DTSA. In operation, the FPGA (EPM3064) receives a synchronized clock signal generated in the data acquisition board. The FPGA then counts the synchronizing clock and sends the control signals to the row and column analog MUX for diode selection. Constant current (10 lA) then flows into the chosen diode. Finally, the forward voltage drop is measured through the amplifier. The diode sensors need to be calibrated in order to accurately measure temperature with the DTSA. For this we experimentally determined the relations between temperature and forward voltage drops of each DTSA diode. The DTSA (the 32 32 diode array) was connected to the circuits and tested in a temperature controlled chamber. The diode voltage drops were measured by varying the temperature within the temperature controlled chamber. In order to illustrate the relationship between forward voltage drops and temperatures, the results from four sample diodes are plotted in Fig. 2. As expected, they exhibit strong linear relations. However, each diode produces a different offset voltage drop because of its position in the wafer and impurities. Therefore, the calibration of each diode signal in the DTSA required two variables (a slope and an intercept) to describe the linear relationships between the diode signal and temperature. We used the least squares fit method for finding the slopes and intercepts of each diode. In this experiment, the temperature signals of the DTSA have ±0.5 °C accuracy in the 0–100 °C range. We waited until the variation of the temperature difference between the chips and ambient was within 0.2 °C for 10 min. The maximum heat loss from the top surface of the heated chip to the ambient is estimated to be about 3% of the total imposed heat. The chemical-mechanical planarization (CMP) method is used for reducing the thickness of the DTSA chip. The flip-chip package
Table 1 Description of DTSA.
Die Underfill Solder ball PCB
Geometry
Materials
12 12 mm 12 12 0.3 mm 0.3 mm diameter 50 50 2 mm
Silicon Silica 30 wt% Pb/Sn FR-4
Fig. 2. Calibration results of four diodes among 1024 diodes in the DTSA.
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firmly attaches the DTSA chip to the PCB to each other. The back of the DTSA chip can then be safely peeled off by the CMP process. Using the CMP process, DTSA chips with the thicknesses of 21.5, 31, 42, 100, 200, and 400 lm are fabricated. The heat is generated by one heater among 8 heaters. The heater (size 1 1 mm) is in the center of DTSA chip and various power conditions are tested (0.2, 0.3, 0.4, and 0.5 W). Fig. 3 shows the temperature distributions on the DTSA surface when 0.3 W is applied at an ambient temperature of 25 °C. As shown in Fig. 3(a), the temperature profile is nearly flat and the hot spot is hardly observable for a wafer of 400 lm in thickness. However, as the chip thickness decreases, the hot spot temperature increases abruptly. This is due to the fact that the heat generated within the chip cannot effectively spreads in the lateral direction as the chip becomes thinner. The hot spot temperature on the DTSA chip increases to 100 °C for a wafer with a thickness of 21.5 lm. It is worth noting that the chips manufactured for industrial uses often have a higher power generation than the DTSA chips. Therefore, we deduce from this experiment that thermal problems can become more serious in industry as the thickness of the chip decreases smaller than several tens of microns. Fig. 4 schematically illustrates VLSI chip package structure and heat transfer paths of chips that are widely used in microelectronic devices. Two common packaging techniques are flip chip packaging and wire bonding packaging. As shown in Fig. 4, there are three heat transfer paths in the VLSI chips. Path 1 can be the dominant path among the three paths since the heat generated in the wafer can be readily dissipated through solder balls and gold wires which have 100 times higher thermal conductivity than the adhesive and epoxy molding compound. On the other hand, Path 2 provides a much larger cross sectional area than Path 1 for the heat transfer. Therefore, both the sides and the bottom of the chip should be taken into account to estimate the spreading resistance accurately.
Path 2 Adhesive material
Epoxy molding compound Copper line Connector
Chip
Solder
PCB
Path 3
Path 1
(a)
Path 2 Gold wire
Adhesive material
Chip
Epoxy molding compound Copper line Connector
PCB
Path 3 (b)
Path 1
Fig. 4. Heat transfer paths of VLSI chips structure: (a) Flip-chip package model, (b) Wire bonding package model.
3. Analysis 3.1. Exact solution In order to validate the experimental results and evaluate the heat transfer characteristics of the DTSA, an analytic model is used [16]. The problems of the previous research generally concerns ther-
Fig. 3. Three-dimensional views of the temperature distributions for various chip thicknesses.
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mal conduction in a cylindrical substrate, as shown in Fig. 5(a). A circular heater of radius r1 is mounted on top of a substrate of radius r2 and thickness H. Even though many semiconductor devices are square or rectangular, the temperature distribution with them can be determined by considering the axi-symmetric problem depicted in Fig. 5(a), provided that the square root of the area is used as the characteristic length, and the same area ratio is used [17]. The two-dimensional conduction equation (Eq. (1)) can be solved to yield the temperature distribution in the substrate. Uniform heat flux condition is applied at the heater and the thermal insulation condition is applied at the top surface except for the heater area:
1 o oT o2 T r þ 2 ¼ 0; r or or oz oT ¼ 0; at r ¼ 0; or oT ¼ h1 ðT T 1 Þ; at r ¼ r 2 ; k or oT at z ¼ 0; k ¼ h2 ðT T 1 Þ; oz qw 0 < r < r 1 ; oT ¼ at z ¼ H; oz 0r 1 < r < r 2 :
ð1Þ ð2Þ ð3Þ ð4Þ ð5Þ
The solutions can be obtained for three cases: heat transfer through both the bottom and side surfaces (Case 1: Fig. 5(b)), heat transfer through the side surface only (Case 2: Fig. 5(c)), and heat
transfer through the bottom surface only (Case 3: [15]). The boundary conditions (2)–(5) are for the Case 1. Upon using the method of separation of variables, the series solution for the temperature distribution for Case 1 is presented in nondimensional form [16]:
T case 1
h i X 2eJ 1 ðkn eÞJ 0 ðkn r Þ Bikn2 cosh ðkn z Þ þ sinh ðkn z Þ h ih 2 i; ¼ kn 2 2 n¼1 kn J 0 ðkn Þ þ J 1 ðkn Þ Bi sinh ðkn sÞ þ kn cosh ðkn sÞ 2
ð6Þ
where J0 and J1 are Bessel functions of the first kind of order 0 and 1, respectively. The eigenvalue kn is the n-th positive root of the following transcendental equation, knJ1(kn )/J0(kn) = Bi1 for both Cases 1 and 2. The nondimensional variables are given as the following:
hi r 2 r ; r ¼ ; r2 k kðT T 1 Þ T ¼ ; qw r 2
Bii ¼
z ¼
z ; r2
e¼
r1 ; r2
s¼
H ; r2 ð7Þ
where T1 is the ambient temperature, k is the thermal conductivity, qw is the heat flux, e is the nondimensional contact radius, and s is the nondimensional substrate thickness. Bi is the Biot number, which provides a measure of the temperature drop in the solid relative to the temperature difference between the surface and the fluid. The Bi1 and Bi2 are calculated from h1 and h2, respectively, where the heat transfer coefficient h1 and h2 are the heat transfer coefficients at the side surface and at the bottom surface, respectively. When Bi2 approaches zero, the solution for Case 1 (Eq. (6)) reduces to the solution for Case 2 (Eq. (8)) in which the bottom surface is insulated. Therefore, the solution for Case 2 can be obtained as:
T case
2
¼ 2e
X
J 1 ðkn eÞJ 0 ðkn r Þ cosh ðkn z Þ h i: sinh ðkn sÞ J 20 ðkn Þ þ J 21 ðkn Þ
2 n¼1 kn
ð8Þ
This result can also be obtained by solving Eq. (1) under the boundary condition of Eq. (2), (3), (5), (9):
at z ¼ 0;
oT ¼ 0: oz
ð9Þ
For Case 3, the solution has been presented in Ref. [15]. For From the obtained solution for nondimensional temperature, the nondimensional expression for the thermal resistance is developed as:
Wcase
1
Wcase
2
h i 9 8 = 2J 1 ðkn eÞ Bikn2 þ tanh ðkn sÞ 1
ð10Þ
ð11Þ
By using the maximum temperature of the substrate, the nondimensional thermal resistance is defined as the following:
1
Wcase 1 ¼ pffiffiffiffiffiffi T max ;
pe
Fig. 5. Schematics of the problem and the corresponding coordinate system.
ð12Þ
The total thermal resistance is equal to the sum of the convection resistance, axial conduction resistance, and spreading resistance. In Case 2, there is no axial conduction path. Therefore, both the convection resistance and axial conduction resistance should be subtracted for Case 1 to estimate the spreading resistance. In contrast to Case 1, only the convection resistance should be subtracted for Case 2 to estimate the spreading resistance. In the flip chip packages shown in Fig. 4, the heat flows out through the solder balls, rather than flowing directly to the ambient. Therefore, the heat transfer coefficients, h1 and h2 in Eq. (3), (4) are the overall heat transfer coefficient that should be estimated upon considering the thermal
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conductivity of solder and copper line, as well as the convective heat transfer coefficient. To estimate h1 and h 2, the thermal resistances of the components along the heat flow path (as shown in Fig. 4) are combined mathematically, as recommended in [18].
2.5
ð13Þ
3.2. Closed-form analytic expressions
2.0
1.5
As mentioned in Section 3.1, the analytic solutions developed by previous researchers [15,16] are in the form of an infinite series with special functions. It takes a long time to obtain the solution, because hundreds of terms need to be computed. Therefore, in the present study, closed-form analytic expressions are developed using the analytical solutions. The developed closed-form analytic expressions are given as:
1.0
0.5 0.0
0.1
0.2
0.3
0.4
0.5
r* Fig. 6. Comparative plots of the temperature distributions: the experimental, 1Þ analytic, and numerical results r rr2 ; T ¼ kðTT : qw r 2
(1) Case 1:
1
Wcase 1 ffi pffiffiffiffi PUc ;
ð14Þ
þ tanhðkc sÞ ; 1 þ Bikc2 tanhðkc sÞ 8 1 < k ¼ p Bipffiffip ; c 1 when Bi1 0:86 p1ffiffi : P ¼ 0:97 þ 0:35e Bi1 p ; ( pffiffiffiffi kc ¼ p Bi1 þ 1e ; when Bi1 > 0:86 P ¼ 0:97 0:35e: kc Bi2
(2) Case 2: (i) when Bi1 6 0.86, 0:54
1 0:97 þ 0:38 Bi1 tanhðkc sÞ p
Wcase 2 ffi pffiffiffiffi
0:698
0:296
where kc ¼ 12:6 Bi1 ð1 3:06 Bi1 (ii) when Bi1 > 0.86,
e
;
ð15Þ
eÞ.
1 0:97 þ 1:1e ; p tanhðkc sÞ
Wcase 2 ffi pffiffiffiffi
ð16Þ
where kc ¼ 8. These closed-form analytic expressions are explicit and simple to use. The comparison with the series solution shows a close agreement within 15% when 0.2 < e < 0.9, 0.2 < s, 105 < Bi1, Bi2 < 103. It is recommended that Eq. (14) be used when the Bi1 and Bi2 are comparable. When Bi1 is much larger than Bi2, Eqs. (15) or (16) should be used. When Bi2 is dominant, the approximate correlation of Ref. [15] should be used. 4. Results 4.1. Experimental results and verification Fig. 6 shows comparative plots of the analytically and experimentally obtained nondimensional temperature versus nondimensional coordinate, which are defined in Eq. (7). Included is a plot representing the numerical results obtained by ICEPAK 4.4.8, provided by FLUENT, Inc. ICEPAK is known to produce an accurate solution when a simple geometry is considered [19]. The numerical model, as illustrated in Fig. 4, is described as follows: dimensions of the system: 50 50 2.7 mm; thickness of the PCB: 2 mm; thickness of the underfill: 0.3 mm; thicknesses of the chip: 21.5,
31, 42, 100, 200, and 400 lm; solder balls: 0.3 mm 80 ea; size of the heater: 1 1 mm; and dimensions of the copper line: 0.1 15 mm. The solder balls were designed as a hexahedron block to simplify the numerical model. Eighty copper lines were designed in four directions, each of which had 20 lines. The thermal conductivity of the chip was defined as a function of temperature [18]. The thermal conductivity values of the silicon, underfill, solders, copper line, and PCB are the same as the values used in [6]. As shown in Fig. 6, the numerical and experimental results agree well, with a maximum error of 7%. The analytic results from the closed-form expressions also match the experimental result well. In particular, the hot spot temperatures are well predicted by the analytic results within the error of 6%. For plots of both the analytic results and experimental data, the inflection point is observable at the location of heater boundary. In the outer region where heat is not applied, relatively large discrepancies are observed between the analytic and experimental results. This is due to the fact that the heat flows out through the solder balls which are attached below around the perimeter of the chip (Fig. 4) while the heat transfer through the side surface is assumed in the analysis. The discrepancy is also attributable to that the convective heat transfer through the top surface is neglected in the analysis. In Fig. 7, the hot spot temperature variations for various heating powers and chip thicknesses are plotted. As shown in Fig. 7, the hot spot tem-
180
Experiment 0.2 W 0.3 W 0.4 W 0.5 W Analysis [16] 0.2 W 0.3 W 0.4 W 0.5 W
160
o
where
Maximum temperature [ C]
p
Uc ¼
Experiment 21.5 μm 42 μm 100 μm 400 μm Analysis [16] 21.5 μm 42 μm 100 μm 400 μm Simulation 21.5 μm 42 μm 100 μm 400 μm
3.0
T*
1 1 Lsolder Lcopper þ þ : ¼ hoverall A hconv Aconv ksolder Asolder kcopper Acopper
3.5
140 120 100 80 60 40 20 0
50
100
150
200
250
300
350
400
450
Thickness [μm] Fig. 7. The maximum temperature variation of the DTSA chips versus thickness.
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perature increases abruptly as the chip thickness decreases. When the designed chip thickness decreases far less than several tens of micrometers, the hot spot temperature rises drastically, causing a thermal runaway of the chips of flip-chip package methods as shown in Fig. 7. We must therefore design chip thickness carefully for avoiding hot spot-induced thermal problems.
6
Ψ case 1
5
Yovanovich [16] (Case 1) Present (Case 2) Lee et al. [15] (Case 3)
4 3 2 1 0 0.2
τ
0.4
(a) Bi2 /Bi1 = 0.01 2.4 2.2 2.0
Yovanovich [16] (Case 1) Present (Case 2) Lee et al. [15] (Case 3)
1.8
Ψcase 1
The nondimensional thermal resistance of Eq. (14)–(16) is obtained as a function of nondimensional contact radius e, nondimensional substrate thickness s, and the Biot number Bi. The Biot number provides a measure of the temperature drop in the solid relative to the temperature difference between the surface and the fluid. The nondimensional contact radius refers to the relative size of heated area compared with the substrate area. The nondimensional substrate thickness is the relative thickness of the substrate compared with the substrate radius. Based on the analytic expressions, we explore the effect of the nondimensional parameters on the spreading resistance. The nondimensional thermal resistance of Eq. (14) is plotted in Fig. 8. The expressions for the three cases (Cases 1–3) are plotted in Fig. 8 for various nondimensional substrate thicknesses. At a smallest value of Bi2/Bi1 (=0.01) as shown in Fig. 8(a), there is a large discrepancy between the curve for Case 3 [15] and those of Cases 1 and 2. This means that the heat flows through the side surface is dominant at the small value of Bi2/Bi1. At a moderate value of Bi2/Bi1 (=0.1) as shown in Fig. 8(b), the curve for Case 1 approaches that of Case 3 [15] as the substrate thickness decreases, while it approaches the curve for Case 2 asymptotically as the thickness increases. At a largest value of Bi2/Bi1 (=1) as shown in Fig. 8(c), there is a large discrepancy between the curve for Case 2 and others. This means that the heat flows through the bottom surface is dominant at the large value of Bi2/Bi1. In addition, as shown in this figure, the result of Case 3 [15] is relatively insensitive to the change of the substrate thickness, while Wcase 2 has a strong dependence on the substrate thickness. From these results, it can be concluded that we should make the thickness as large as possible especially when the heat transfer through the bottom surface is not facilitated. The maximum nondimensional spreading resistance calculated by Eq. (14) is plotted in Fig. 9 for various substrate thicknesses and Biot numbers. In this figure, the Biot number, Bi represents both Bi1 and Bi2 because these two Biot numbers were set to be identical. The effect of various parameters on the heat transfer characteristics is displayed in Fig. 9. First, for fixed e and s, it can be expected that the minimum spreading resistance occurs when the Biot number approaches infinity. In this limit, the surface in contact with the air becomes isothermal. A solution for this isothermal case presented in Ref. [20] is also plotted in Fig. 9 and an excellent agreement was observed. Second, the nondimensional spreading resistance decreases with increasing nondimensional substrate thickness. This observation is consistent with the present experimental results. Also, the nondimensional spreading resistance decreases as the Biot number increases. Third, when the nondimensional substrate thickness is larger than 1, the nondimensional spreading resistance is found to be relatively insensitive to the changes in either the substrate thickness or the Biot number, while it becomes primarily a function of a nondimensional contact radius. It is because the pattern of heat flow near the source region is hardly affected by the changes in conditions far away from the source [15]. Fourth, as shown in Fig. 9(a) and (b), the nondimensional spreading resistance increases as the nondimensional contact radius, e increases. It is due to the fact that the total amount of heat increases with increasing contact area which is proportional to the square of e by definition of e.
7
1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2
τ
0.4
(b) Bii2 /Bi1 = 0.1 2.4 2.2 2.0
Yovanovich [16] (Case 1) Present (Case 2) Lee et al. [15] (Case 3)
1.8
Ψ case 1
4.2. Characteristics of the spreading resistance
8
1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2
τ
0.4
(c) Bi2 /Bi1 = 1 Fig. 8. Nondimensional spreading resistances for various Biot number ratios and nondimensional substrate thicknesses: e = 0.1.
5. Conclusion In this study, the hot spot temperature and temperature distribution in the flip-chip package were estimated using both experimental and analytical methods. The effects of various chip thicknesses (21.5, 31, 42, 100, 200, and 400 lm) and various heater power conditions (0.2, 0.3, 0.4, and 0.5 W) on the hot spot temperature were considered. In order to support the experimental data and gain a physical insight, closed-form analytic expressions were
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gram funded by the Ministry of Science and Technology (No. M1060000022406J000022410) and the Korea Research Foundation Grant funded by the Korean Government (MOEHRD, Basic Research Promotion Fund) (KRF-2008-314-D00045).
Bi = 0.1 Bi = 1 Bi = 10 Isothermal [20]
10
Ψ case 1
References
1
0.01
0.1
τ (a) = 0.1
1
Bi = 0.1 Bi = 1 Bi = 10 Isothermal [20]
100
Ψ case 1
10
10
1
0.01
0.1
τ
1
10
(b) = 0.5 Fig. 9. The effect of the parameters on the nondimensional spreading resistance.
suggested. The suggested analytic expression agrees well with the experimental data, within 6%. Based on the suggested analytic expressions, the effects of the nondimensional contact radius, nondimensional substrate thickness, and the Biot number were considered. Acknowledgement This work was supported by the Korea Science and Engineering Foundation (KOSEF) through the National Research Laboratory Pro-
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Contents lists available at ScienceDirect
International Journal of Heat and Mass Transfer journal homepage: www.elsevier.com/locate/ijhmt
Experimental and analytical study on chip hot spot temperature Chan Byon, Kyosung Choo, Sung Jin Kim ⇑ School of Mechanical, Aerospace and Systems Engineering, Korea Advanced Institute of Science and Technology, Daejeon 305-701, Republic of Korea
a r t i c l e
i n f o
Article history: Received 8 July 2010 Received in revised form 3 December 2010 Accepted 3 December 2010 Available online 1 February 2011 Keywords: Hot spot temperature Spreading resistance
a b s t r a c t In this study, the effects of various chip thicknesses on the chip hot spot temperature are investigated using both experimental and analytical methods. The temperature distribution in the chip is measured under the various chip thicknesses (21.5–400 lm) and various heater power conditions (0.2–0.5 W). In order to support the experimental data and gain a physical insight, closed-form analytic expressions are suggested. Based on the suggested analytic expressions, the effects of the nondimensional contact radius, nondimensional substrate thickness, and the Biot number are investigated. Ó 2010 Elsevier Ltd. All rights reserved.
1. Introduction Microelectronic components have become the heart of many modern electronic products from home/office PC systems to advanced military/defense electronic systems. However, microelectronic devices require power, and the conversion of electrical energy to thermal energy is an unavoidable byproduct of the normal operation of any electronic device. This leads to higher microprocessor temperature that, if not properly managed, will significantly affect the performance, power leakage, and reliability of microelectronic chips, assemblies, and products. Today’s semiconductor technology trend is heading towards thinner and smaller packages [1,2]. There are many advantages in using thin chips, including reduced space which allows more functionality per unit volume in a 3D package [3]. However, miniaturization and design complexity are causing highly non-uniform power distribution on the microprocessors, producing ‘‘high-flux hot spots’’. As the chip thickness and die size decrease, the chip temperature and the hot spot temperature in a chip increase [4,5]. This is due to the fact that the thermal spreading resistance (spreading resistance hereafter) increases with decreasing chip thickness and die size [6,7]. The spreading resistance refers to the thermal resistance that occurs when heat flows out of a narrow region into a larger region. If the heat dissipated from the component does not spread out efficiently, the hot spot temperature may reach an unacceptable level causing damage. To reduce the hot-spot-induced thermal damage in chips, it is important to predict the hot spot temperature. Many researchers tried to predict the hot spot temperature. Akiyama et al. [8] and Lin et al. [9] performed numerical simula⇑ Corresponding author. Tel.: +82 42 350 3043; fax: +82 42 350 8207. E-mail address: [email protected] (S.J. Kim). 0017-9310/$ - see front matter Ó 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.ijheatmasstransfer.2010.12.022
tions to predict the hot spot temperature. Chiu et al. [10] used infrared microscopy to measure the temperature of a solder joint. However, they did not measure the hot spot temperature directly because the hot spot is not exposed to the ambient. Wang and Bar-Cohen [11] developed a numerical model for predicting the hot spot temperature and included TEC in their numerical model to reduce the hot spot temperature. Even though plenty of researchers have tried to predict the hot spot temperature, the hot spot temperature and the temperature distribution on a semiconductor chip could not be directly measured because there were no high resolution micro-sensors. In this study, the hot spot temperature and temperature distribution in the chip are measured utilizing the diode temperature sensor array (DTSA) previously developed by Han and Kim [12]. In their research, the experiments were performed with fixed chip thickness. In contrast, the purpose of the present experimental study is to find the effect of the various chip thicknesses on the hot spot temperature. The experimental parameters include the various chip thicknesses (21.5, 31, 42, 100, 200, and 400 lm) and various heater power conditions (0.2, 0.3, 0.4, and 0.5 W). Another purpose of the present study is to suggest an analytic expression for predicting the spreading resistance. The spreading resistance is a key parameter used in predicting the hot spot temperature and, accordingly, many studies were devoted to developing analytic expressions for spreading resistance [13–17]. Understanding of spreading resistance allows us to gain a physical insight, and helps in determining the physical reasonableness of experimental hot spot temperature data. In this study, closed-form analytic expressions for spreading resistance are suggested and compared with measured hot spot temperature. Based on the suggested analytic expressions, the effects of the nondimensional contact radius, nondimensional substrate thickness, and the Biot number are considered.
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Nomenclature Bi h H k qw r,z r1 r2 T
Biot number () heat transfer coefficient (W/m2K) substrate thickness (m) thermal conductivity of the substrate (W/mK) heat flux at the source surface (W/m2) cylindrical coordinate (m) source radius (m) substrate radius (m) temperature (K)
Fig. 1. Circuit configuration of a DTSA system.
2. Experiment In order to measure the hot spot temperature and the temperature distribution, a diode temperature sensor array (DTSA) developed by Han and Kim [12] is used. The DTSA is innovative temperature sensor arrays which can measure the temperatures of 1024 points in the area of 8 8 mm. Diodes are arranged in 32 32 array in the DTSA. Eight poly-silicon heaters of 1 kX are embedded onto a silicon wafer for heating the specific area of the DTSA chip. The DTSA chip is mounted on the PCB by using a flip-chip packaging method. The size of the designed PCB is 50 50 mm. Solder balls of 300 lm in diameter is used for interconnecting the PCB pads and the DTSA chip pads. The thermal conductivities of the components are summarized in Table 1. A DTSA signal board was also developed for scanning the diode and conditioning the diode signals of the DTSA. It consisted of a FPGA (field programmable gate array), an amplifier, a power driver, an analog MUX (multiplexer), a constant current source, and a data acquisition board, as shown in Fig. 1. The FPGA was used for selecting which diode would be measured among the 32 32 diodes. A Verilog program was used to operate the FPGA chip. The 1024 measured voltage drops were multiplexed into one signal through the analog MUX. These signals were amplified by the amplifier circuits. The data acquisition board (PCI-6052E, National Instruments) was used for A/D conversion of the signals and for sending control sig-
Greek symbols nondimensional contact radius () nondimensional substrate thickness () W nondimensional spreading resistance ()
e s
Subscripts 1 ambient () conv convection ()
nals to the power driver for heating the surface of the DTSA. In operation, the FPGA (EPM3064) receives a synchronized clock signal generated in the data acquisition board. The FPGA then counts the synchronizing clock and sends the control signals to the row and column analog MUX for diode selection. Constant current (10 lA) then flows into the chosen diode. Finally, the forward voltage drop is measured through the amplifier. The diode sensors need to be calibrated in order to accurately measure temperature with the DTSA. For this we experimentally determined the relations between temperature and forward voltage drops of each DTSA diode. The DTSA (the 32 32 diode array) was connected to the circuits and tested in a temperature controlled chamber. The diode voltage drops were measured by varying the temperature within the temperature controlled chamber. In order to illustrate the relationship between forward voltage drops and temperatures, the results from four sample diodes are plotted in Fig. 2. As expected, they exhibit strong linear relations. However, each diode produces a different offset voltage drop because of its position in the wafer and impurities. Therefore, the calibration of each diode signal in the DTSA required two variables (a slope and an intercept) to describe the linear relationships between the diode signal and temperature. We used the least squares fit method for finding the slopes and intercepts of each diode. In this experiment, the temperature signals of the DTSA have ±0.5 °C accuracy in the 0–100 °C range. We waited until the variation of the temperature difference between the chips and ambient was within 0.2 °C for 10 min. The maximum heat loss from the top surface of the heated chip to the ambient is estimated to be about 3% of the total imposed heat. The chemical-mechanical planarization (CMP) method is used for reducing the thickness of the DTSA chip. The flip-chip package
Table 1 Description of DTSA.
Die Underfill Solder ball PCB
Geometry
Materials
12 12 mm 12 12 0.3 mm 0.3 mm diameter 50 50 2 mm
Silicon Silica 30 wt% Pb/Sn FR-4
Fig. 2. Calibration results of four diodes among 1024 diodes in the DTSA.
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firmly attaches the DTSA chip to the PCB to each other. The back of the DTSA chip can then be safely peeled off by the CMP process. Using the CMP process, DTSA chips with the thicknesses of 21.5, 31, 42, 100, 200, and 400 lm are fabricated. The heat is generated by one heater among 8 heaters. The heater (size 1 1 mm) is in the center of DTSA chip and various power conditions are tested (0.2, 0.3, 0.4, and 0.5 W). Fig. 3 shows the temperature distributions on the DTSA surface when 0.3 W is applied at an ambient temperature of 25 °C. As shown in Fig. 3(a), the temperature profile is nearly flat and the hot spot is hardly observable for a wafer of 400 lm in thickness. However, as the chip thickness decreases, the hot spot temperature increases abruptly. This is due to the fact that the heat generated within the chip cannot effectively spreads in the lateral direction as the chip becomes thinner. The hot spot temperature on the DTSA chip increases to 100 °C for a wafer with a thickness of 21.5 lm. It is worth noting that the chips manufactured for industrial uses often have a higher power generation than the DTSA chips. Therefore, we deduce from this experiment that thermal problems can become more serious in industry as the thickness of the chip decreases smaller than several tens of microns. Fig. 4 schematically illustrates VLSI chip package structure and heat transfer paths of chips that are widely used in microelectronic devices. Two common packaging techniques are flip chip packaging and wire bonding packaging. As shown in Fig. 4, there are three heat transfer paths in the VLSI chips. Path 1 can be the dominant path among the three paths since the heat generated in the wafer can be readily dissipated through solder balls and gold wires which have 100 times higher thermal conductivity than the adhesive and epoxy molding compound. On the other hand, Path 2 provides a much larger cross sectional area than Path 1 for the heat transfer. Therefore, both the sides and the bottom of the chip should be taken into account to estimate the spreading resistance accurately.
Path 2 Adhesive material
Epoxy molding compound Copper line Connector
Chip
Solder
PCB
Path 3
Path 1
(a)
Path 2 Gold wire
Adhesive material
Chip
Epoxy molding compound Copper line Connector
PCB
Path 3 (b)
Path 1
Fig. 4. Heat transfer paths of VLSI chips structure: (a) Flip-chip package model, (b) Wire bonding package model.
3. Analysis 3.1. Exact solution In order to validate the experimental results and evaluate the heat transfer characteristics of the DTSA, an analytic model is used [16]. The problems of the previous research generally concerns ther-
Fig. 3. Three-dimensional views of the temperature distributions for various chip thicknesses.
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mal conduction in a cylindrical substrate, as shown in Fig. 5(a). A circular heater of radius r1 is mounted on top of a substrate of radius r2 and thickness H. Even though many semiconductor devices are square or rectangular, the temperature distribution with them can be determined by considering the axi-symmetric problem depicted in Fig. 5(a), provided that the square root of the area is used as the characteristic length, and the same area ratio is used [17]. The two-dimensional conduction equation (Eq. (1)) can be solved to yield the temperature distribution in the substrate. Uniform heat flux condition is applied at the heater and the thermal insulation condition is applied at the top surface except for the heater area:
1 o oT o2 T r þ 2 ¼ 0; r or or oz oT ¼ 0; at r ¼ 0; or oT ¼ h1 ðT T 1 Þ; at r ¼ r 2 ; k or oT at z ¼ 0; k ¼ h2 ðT T 1 Þ; oz qw 0 < r < r 1 ; oT ¼ at z ¼ H; oz 0r 1 < r < r 2 :
ð1Þ ð2Þ ð3Þ ð4Þ ð5Þ
The solutions can be obtained for three cases: heat transfer through both the bottom and side surfaces (Case 1: Fig. 5(b)), heat transfer through the side surface only (Case 2: Fig. 5(c)), and heat
transfer through the bottom surface only (Case 3: [15]). The boundary conditions (2)–(5) are for the Case 1. Upon using the method of separation of variables, the series solution for the temperature distribution for Case 1 is presented in nondimensional form [16]:
T case 1
h i X 2eJ 1 ðkn eÞJ 0 ðkn r Þ Bikn2 cosh ðkn z Þ þ sinh ðkn z Þ h ih 2 i; ¼ kn 2 2 n¼1 kn J 0 ðkn Þ þ J 1 ðkn Þ Bi sinh ðkn sÞ þ kn cosh ðkn sÞ 2
ð6Þ
where J0 and J1 are Bessel functions of the first kind of order 0 and 1, respectively. The eigenvalue kn is the n-th positive root of the following transcendental equation, knJ1(kn )/J0(kn) = Bi1 for both Cases 1 and 2. The nondimensional variables are given as the following:
hi r 2 r ; r ¼ ; r2 k kðT T 1 Þ T ¼ ; qw r 2
Bii ¼
z ¼
z ; r2
e¼
r1 ; r2
s¼
H ; r2 ð7Þ
where T1 is the ambient temperature, k is the thermal conductivity, qw is the heat flux, e is the nondimensional contact radius, and s is the nondimensional substrate thickness. Bi is the Biot number, which provides a measure of the temperature drop in the solid relative to the temperature difference between the surface and the fluid. The Bi1 and Bi2 are calculated from h1 and h2, respectively, where the heat transfer coefficient h1 and h2 are the heat transfer coefficients at the side surface and at the bottom surface, respectively. When Bi2 approaches zero, the solution for Case 1 (Eq. (6)) reduces to the solution for Case 2 (Eq. (8)) in which the bottom surface is insulated. Therefore, the solution for Case 2 can be obtained as:
T case
2
¼ 2e
X
J 1 ðkn eÞJ 0 ðkn r Þ cosh ðkn z Þ h i: sinh ðkn sÞ J 20 ðkn Þ þ J 21 ðkn Þ
2 n¼1 kn
ð8Þ
This result can also be obtained by solving Eq. (1) under the boundary condition of Eq. (2), (3), (5), (9):
at z ¼ 0;
oT ¼ 0: oz
ð9Þ
For Case 3, the solution has been presented in Ref. [15]. For From the obtained solution for nondimensional temperature, the nondimensional expression for the thermal resistance is developed as:
Wcase
1
Wcase
2
h i 9 8 = 2J 1 ðkn eÞ Bikn2 þ tanh ðkn sÞ 1
ð10Þ
ð11Þ
By using the maximum temperature of the substrate, the nondimensional thermal resistance is defined as the following:
1
Wcase 1 ¼ pffiffiffiffiffiffi T max ;
pe
Fig. 5. Schematics of the problem and the corresponding coordinate system.
ð12Þ
The total thermal resistance is equal to the sum of the convection resistance, axial conduction resistance, and spreading resistance. In Case 2, there is no axial conduction path. Therefore, both the convection resistance and axial conduction resistance should be subtracted for Case 1 to estimate the spreading resistance. In contrast to Case 1, only the convection resistance should be subtracted for Case 2 to estimate the spreading resistance. In the flip chip packages shown in Fig. 4, the heat flows out through the solder balls, rather than flowing directly to the ambient. Therefore, the heat transfer coefficients, h1 and h2 in Eq. (3), (4) are the overall heat transfer coefficient that should be estimated upon considering the thermal
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conductivity of solder and copper line, as well as the convective heat transfer coefficient. To estimate h1 and h 2, the thermal resistances of the components along the heat flow path (as shown in Fig. 4) are combined mathematically, as recommended in [18].
2.5
ð13Þ
3.2. Closed-form analytic expressions
2.0
1.5
As mentioned in Section 3.1, the analytic solutions developed by previous researchers [15,16] are in the form of an infinite series with special functions. It takes a long time to obtain the solution, because hundreds of terms need to be computed. Therefore, in the present study, closed-form analytic expressions are developed using the analytical solutions. The developed closed-form analytic expressions are given as:
1.0
0.5 0.0
0.1
0.2
0.3
0.4
0.5
r* Fig. 6. Comparative plots of the temperature distributions: the experimental, 1Þ analytic, and numerical results r rr2 ; T ¼ kðTT : qw r 2
(1) Case 1:
1
Wcase 1 ffi pffiffiffiffi PUc ;
ð14Þ
þ tanhðkc sÞ ; 1 þ Bikc2 tanhðkc sÞ 8 1 < k ¼ p Bipffiffip ; c 1 when Bi1 0:86 p1ffiffi : P ¼ 0:97 þ 0:35e Bi1 p ; ( pffiffiffiffi kc ¼ p Bi1 þ 1e ; when Bi1 > 0:86 P ¼ 0:97 0:35e: kc Bi2
(2) Case 2: (i) when Bi1 6 0.86, 0:54
1 0:97 þ 0:38 Bi1 tanhðkc sÞ p
Wcase 2 ffi pffiffiffiffi
0:698
0:296
where kc ¼ 12:6 Bi1 ð1 3:06 Bi1 (ii) when Bi1 > 0.86,
e
;
ð15Þ
eÞ.
1 0:97 þ 1:1e ; p tanhðkc sÞ
Wcase 2 ffi pffiffiffiffi
ð16Þ
where kc ¼ 8. These closed-form analytic expressions are explicit and simple to use. The comparison with the series solution shows a close agreement within 15% when 0.2 < e < 0.9, 0.2 < s, 105 < Bi1, Bi2 < 103. It is recommended that Eq. (14) be used when the Bi1 and Bi2 are comparable. When Bi1 is much larger than Bi2, Eqs. (15) or (16) should be used. When Bi2 is dominant, the approximate correlation of Ref. [15] should be used. 4. Results 4.1. Experimental results and verification Fig. 6 shows comparative plots of the analytically and experimentally obtained nondimensional temperature versus nondimensional coordinate, which are defined in Eq. (7). Included is a plot representing the numerical results obtained by ICEPAK 4.4.8, provided by FLUENT, Inc. ICEPAK is known to produce an accurate solution when a simple geometry is considered [19]. The numerical model, as illustrated in Fig. 4, is described as follows: dimensions of the system: 50 50 2.7 mm; thickness of the PCB: 2 mm; thickness of the underfill: 0.3 mm; thicknesses of the chip: 21.5,
31, 42, 100, 200, and 400 lm; solder balls: 0.3 mm 80 ea; size of the heater: 1 1 mm; and dimensions of the copper line: 0.1 15 mm. The solder balls were designed as a hexahedron block to simplify the numerical model. Eighty copper lines were designed in four directions, each of which had 20 lines. The thermal conductivity of the chip was defined as a function of temperature [18]. The thermal conductivity values of the silicon, underfill, solders, copper line, and PCB are the same as the values used in [6]. As shown in Fig. 6, the numerical and experimental results agree well, with a maximum error of 7%. The analytic results from the closed-form expressions also match the experimental result well. In particular, the hot spot temperatures are well predicted by the analytic results within the error of 6%. For plots of both the analytic results and experimental data, the inflection point is observable at the location of heater boundary. In the outer region where heat is not applied, relatively large discrepancies are observed between the analytic and experimental results. This is due to the fact that the heat flows out through the solder balls which are attached below around the perimeter of the chip (Fig. 4) while the heat transfer through the side surface is assumed in the analysis. The discrepancy is also attributable to that the convective heat transfer through the top surface is neglected in the analysis. In Fig. 7, the hot spot temperature variations for various heating powers and chip thicknesses are plotted. As shown in Fig. 7, the hot spot tem-
180
Experiment 0.2 W 0.3 W 0.4 W 0.5 W Analysis [16] 0.2 W 0.3 W 0.4 W 0.5 W
160
o
where
Maximum temperature [ C]
p
Uc ¼
Experiment 21.5 μm 42 μm 100 μm 400 μm Analysis [16] 21.5 μm 42 μm 100 μm 400 μm Simulation 21.5 μm 42 μm 100 μm 400 μm
3.0
T*
1 1 Lsolder Lcopper þ þ : ¼ hoverall A hconv Aconv ksolder Asolder kcopper Acopper
3.5
140 120 100 80 60 40 20 0
50
100
150
200
250
300
350
400
450
Thickness [μm] Fig. 7. The maximum temperature variation of the DTSA chips versus thickness.
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perature increases abruptly as the chip thickness decreases. When the designed chip thickness decreases far less than several tens of micrometers, the hot spot temperature rises drastically, causing a thermal runaway of the chips of flip-chip package methods as shown in Fig. 7. We must therefore design chip thickness carefully for avoiding hot spot-induced thermal problems.
6
Ψ case 1
5
Yovanovich [16] (Case 1) Present (Case 2) Lee et al. [15] (Case 3)
4 3 2 1 0 0.2
τ
0.4
(a) Bi2 /Bi1 = 0.01 2.4 2.2 2.0
Yovanovich [16] (Case 1) Present (Case 2) Lee et al. [15] (Case 3)
1.8
Ψcase 1
The nondimensional thermal resistance of Eq. (14)–(16) is obtained as a function of nondimensional contact radius e, nondimensional substrate thickness s, and the Biot number Bi. The Biot number provides a measure of the temperature drop in the solid relative to the temperature difference between the surface and the fluid. The nondimensional contact radius refers to the relative size of heated area compared with the substrate area. The nondimensional substrate thickness is the relative thickness of the substrate compared with the substrate radius. Based on the analytic expressions, we explore the effect of the nondimensional parameters on the spreading resistance. The nondimensional thermal resistance of Eq. (14) is plotted in Fig. 8. The expressions for the three cases (Cases 1–3) are plotted in Fig. 8 for various nondimensional substrate thicknesses. At a smallest value of Bi2/Bi1 (=0.01) as shown in Fig. 8(a), there is a large discrepancy between the curve for Case 3 [15] and those of Cases 1 and 2. This means that the heat flows through the side surface is dominant at the small value of Bi2/Bi1. At a moderate value of Bi2/Bi1 (=0.1) as shown in Fig. 8(b), the curve for Case 1 approaches that of Case 3 [15] as the substrate thickness decreases, while it approaches the curve for Case 2 asymptotically as the thickness increases. At a largest value of Bi2/Bi1 (=1) as shown in Fig. 8(c), there is a large discrepancy between the curve for Case 2 and others. This means that the heat flows through the bottom surface is dominant at the large value of Bi2/Bi1. In addition, as shown in this figure, the result of Case 3 [15] is relatively insensitive to the change of the substrate thickness, while Wcase 2 has a strong dependence on the substrate thickness. From these results, it can be concluded that we should make the thickness as large as possible especially when the heat transfer through the bottom surface is not facilitated. The maximum nondimensional spreading resistance calculated by Eq. (14) is plotted in Fig. 9 for various substrate thicknesses and Biot numbers. In this figure, the Biot number, Bi represents both Bi1 and Bi2 because these two Biot numbers were set to be identical. The effect of various parameters on the heat transfer characteristics is displayed in Fig. 9. First, for fixed e and s, it can be expected that the minimum spreading resistance occurs when the Biot number approaches infinity. In this limit, the surface in contact with the air becomes isothermal. A solution for this isothermal case presented in Ref. [20] is also plotted in Fig. 9 and an excellent agreement was observed. Second, the nondimensional spreading resistance decreases with increasing nondimensional substrate thickness. This observation is consistent with the present experimental results. Also, the nondimensional spreading resistance decreases as the Biot number increases. Third, when the nondimensional substrate thickness is larger than 1, the nondimensional spreading resistance is found to be relatively insensitive to the changes in either the substrate thickness or the Biot number, while it becomes primarily a function of a nondimensional contact radius. It is because the pattern of heat flow near the source region is hardly affected by the changes in conditions far away from the source [15]. Fourth, as shown in Fig. 9(a) and (b), the nondimensional spreading resistance increases as the nondimensional contact radius, e increases. It is due to the fact that the total amount of heat increases with increasing contact area which is proportional to the square of e by definition of e.
7
1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2
τ
0.4
(b) Bii2 /Bi1 = 0.1 2.4 2.2 2.0
Yovanovich [16] (Case 1) Present (Case 2) Lee et al. [15] (Case 3)
1.8
Ψ case 1
4.2. Characteristics of the spreading resistance
8
1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2
τ
0.4
(c) Bi2 /Bi1 = 1 Fig. 8. Nondimensional spreading resistances for various Biot number ratios and nondimensional substrate thicknesses: e = 0.1.
5. Conclusion In this study, the hot spot temperature and temperature distribution in the flip-chip package were estimated using both experimental and analytical methods. The effects of various chip thicknesses (21.5, 31, 42, 100, 200, and 400 lm) and various heater power conditions (0.2, 0.3, 0.4, and 0.5 W) on the hot spot temperature were considered. In order to support the experimental data and gain a physical insight, closed-form analytic expressions were
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gram funded by the Ministry of Science and Technology (No. M1060000022406J000022410) and the Korea Research Foundation Grant funded by the Korean Government (MOEHRD, Basic Research Promotion Fund) (KRF-2008-314-D00045).
Bi = 0.1 Bi = 1 Bi = 10 Isothermal [20]
10
Ψ case 1
References
1
0.01
0.1
τ (a) = 0.1
1
Bi = 0.1 Bi = 1 Bi = 10 Isothermal [20]
100
Ψ case 1
10
10
1
0.01
0.1
τ
1
10
(b) = 0.5 Fig. 9. The effect of the parameters on the nondimensional spreading resistance.
suggested. The suggested analytic expression agrees well with the experimental data, within 6%. Based on the suggested analytic expressions, the effects of the nondimensional contact radius, nondimensional substrate thickness, and the Biot number were considered. Acknowledgement This work was supported by the Korea Science and Engineering Foundation (KOSEF) through the National Research Laboratory Pro-
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