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EXPERIMENTAL CONTROL OF CHAOTIC BEHAVIOUR IN DC-DC CONVERTERS
IFAC MCPL 2007 The 4th International Federation of Automatic Control Conference on Management and Control of Production and Logistics September 27-30, Sibiu - Romania
EXPERIMENTAL CONTROL OF CHAOTIC BEHAVIOUR IN DC-DC CONVERTERS Florin Dragan, Daniel Curiac, Emil Voisan, Adrian Motantau Department of Automatical Control,University “Politehnica” from Timisoara, Bv. V. Parvan, 1900 Timisoara, Romania [email protected]
Abstract: Power electronic systems are an important class of systems that operate by a variable structure control. Chaotic behaviour of some dc-dc converters were demonstrated by computer simulations. The paper approaches three experimental control methods for this kind of systems grouped in a single software package. As development board we used a board with a microcontroller and as interface a panel PC. Copyright © 2007 IFAC Keywords: chaotic behaviour, control, computer interface, converter, power systems.
1. INTRODUCTION Nonlinear dynamics is an older and broader field than power electronics. High efficiency solid state power conversion has become possible through the continuing development of high power semiconductor devices. The operation of these devices as switches, which is necessary for high efficiency, means that power electronic circuits are essentially nonlinear time varying dynamical systems. The conventional approach ignores nonlinear effects and could design a circuit with a normal behaviour but in practice it has a chaotic behaviour (2003). In recent years, the possibility of controlling nonlinear chaotic dynamical systems has been the subject of extensive investigation. Following the pioneering work , much research efforts has focused on the possibility of solving the problem of suppressing chaotic regimes in systems with this behaviour .
Fig. 1. The buck dc-dc converter The values for the circuit elements are R=15[Ω]; L=12[mH]; C=20[μF]; Vin=5[V]. The functionality of the circuit can be described by the following dynamical system with variable structure (1998b) (1996a): (1 − d ) 1 ⎧ ⎪ x&1 = − L x 2 + L Vin ⎨ 1 1 ⎪ x& 2 = x1 − x2 C RC ⎩
(1)
1.1 Actual systems behaviour The converters studied was a dc-dc buck and a dc-dc current mode controlled boost. The buck dc-dc converter is in fact a chopper that converts a dc input to a dc output at a lower value. Figure 1 shows the circuit (2001) (1998b). Fig. 2. The current mode controlled boost conveter
427
where d=0 means the switch S on and 1 means the switch is off (1996b) (1997). The second circuit shown in figure 2 is a dc-dc current mode controlled boost converter and could be described by the following dynamical system: . ⎧ A1 x + B 1V i for t cl , n < t < t op ,n
x = ⎨ ⎩ A 2 x + B 2V i
The principle of the OGY controller is very simple. For systems with chaotic behavior you can assume that the system will evolve close enough to a stable orbit on which you want to stabilize it. In order to keep the system on that orbit, you have to add small perturbations to a parameter. The dynamics of the system can be represented as arising from an n-dimensional nonlinear discrete-time function of the following form: x k +1 = P (x k , p ) (3) where p is an accessible system parameter. In the case of continuous-time systems this map is given via some form of sampling(1990). There is a maximum small perturbation Δp* in the parameter p by which it is acceptable to vary p from the nominal value p*. For the value of p* there is a chaotic attractor of the underlying system which contains a specific periodic trajectory around which one wishes to stabilize the dynamics. The position of this periodic trajectory is a function of p, but the local dynamics do not vary much with the allowed small changes in parameter p. While the dynamics is assumed to arise from a map, one needs no model for the global dynamics. These assumptions would seem to allow for the control of any chaotic system for which a faithful map can be constructed, e.g., from experimental data. For simplicity the presentation is restricted to a twodimensional map P. An equilibrium point xF(p) of the map (3) of the system is defined by: x F ( p ) = P(x F ( p ), p ) (4) therefore it moves with the parameter p by:
for t op , n ≤ t < t cl , n +1
{top ,n } = {t | i (t ) = I ref } {tcl ,n } ⊂ {kT , k ∈ Ζ} ⎡− 1 / RC 0⎤ ⎡ 0 ⎤ (2) A1 = ⎢ , B1 = ⎢ ⎥ ⎥ 0⎦ ⎣ 0 ⎣1 / L ⎦ where x=[v i]T represent the state vector of the boost converter and depends on the state of the circuit: The circuit consists from a controlled switch S, a diode D, an inductor, a capacitor and a load resistor characterized by inductance L, resistance R and capacity C. The control for the switch is assured by a flip-flop and a comparator circuit. The values are R=10[Ω], L=1.5[mH], C=10[μF] (1992). The bifurcation diagrams (2000a,b) for the circuits is shown in figure 3 for buck and 4 for boost. It can be observed that the circuit has a chaotic behavior.
dx F ( p ) ∂P dx ( p ) ∂P ⋅ F + = (5) dp dp ∂p x ( p ), p ∂x x ( p ), p F F Let x*(p*) denote the unstable equilibrium point of the map P existing for the parameter value p* and corresponding to that periodic trajectory on the attractor which one wants to stabilize. From (5) results: dx dx ∂P ∂P (6) = F − ⋅ F ∂p x* , p* dp p* ∂x x* , p* dp p*
Fig. 3 The bifurcation diagram for the buck converter
or
b = (I − A ) ⋅ g
where g = dx F dp
, A= p
*
(7) ∂P ∂x
x* , p *
, b=
∂P ∂p
(8) x* , p*
In the close neighborhood of the desired equilibrium point x*(p*) we can assume with good accuracy that the dynamics of map P is linear and can be expressed by the first-order approximation of (1990): ∂P ∂P Δx k +1 = ⋅ Δx k + ⋅ Δp k = ∂x x* , p* ∂p x* , p* (9)
Fig. 4 The bifurcation diagram for the boost converter
= A ⋅ Δx k + b ⋅ Δp k
Substituting (7) in (9): (10) Δxk +1 = A ⋅ Δxk + (I − A) ⋅ g ⋅ Δpk There is a practical method for determining the amplitude of the perturbation. You have to simulate the system without perturbation, find the peak value of the current(voltage) for the desired orbit. Write
The diagram shows the period doubling and after that, chaos. It could be observed the intermittencies zones. 2. OGY CONTROL METHOD
428
down that value, together with a few more values for the following iterations. Then apply a small perturbation, find again the peak value of the current(voltage) and see how much it varied. Now you have to see how much you have to vary the perturbation according to the difference between the values for the next iterations and the desired orbit. After you have the amount, all you have to do is to find out when the system gets close enough to the desired orbit in order to apply the perturbation.
DMA channels on the Advanced Highperformance Bus (AHB) take full advantage of the separate data path provided by the Harvard architecture, moving data rapidly and largely independent of the instruction path. There are two DMA units, one is dedicated to move data between the Ethernet interface and SRAM, the other DMA unit has eight programmable channels with 16 request signals to service other peripherals and interfaces (USB, SSP, I2C, UART, Timers, EMI, and external request pins). There are two independent 32-bit wide Burst Flash memories enabling true read-while-write operation. The Flash memories are single-voltage erase/program with 20 year minimum data retention and 100K minimum erase cycles. The primary Flash memory is much larger than the secondary Flash. There are 32 bytes of OTP memory ideally suited for serial numbers, security keys, factory calibration constants, or other permanent data constants. These OTP data bytes can be programmed only one time through either the JTAG interface or by the CPU, and these bytes can never be altered afterwards. Interrupt management in the STR91xF is implemented from daisy-chaining two standard ARM VIC units. This combined VIC has 32 prioritized interrupt request channels and generates two interrupt output signals to the CPU. The output signals are FIQ and IRQ, with FIQ having higher priority. The STR91xF offers configurable and flexible power management control that allows the user to choose the best power option to fit the application. Power consumption can be dynamically managed by firmware and hardware to match the system’s requirements. Power management is provided via clock control to the CPU and individual peripherals.
3. HARDWARE INSTRUMENTS Hardware board, developed by HITEX, is based on ARM 9 processor. Main characteristics are: controller STR912FW44X: ARM 966 32 bit / 96 MHz, 512kB + 32 kB flash memory, 96kB SRAM, Ethernet 10/100, USB 2.0, CAN 2.0, timers and other periferics, 2 LED 7- segment LED display, JTAG interface, IMC(Inductive Motor Controller) conector. The STR91xF is a SiP device, comprised of two stacked die. One die is the ARM966E-S CPU with peripheral interfaces and analog functions, and the other die is the burst Flash. The two die are connected to each other by a custom high-speed 32bit burst memory interface and a serial JTAG test/programming interface. The ARM966E-S core inherently has separate instruction and data memory interfaces (Harvard architecture), allowing the CPU to simultaneously fetch an instruction, and read or write a data item through two Tightly-Coupled Memory (TCM) interfaces. The result is streamlined CPU Load and Store operations and a significant reduction in cycle count per instruction. In addition to this, a 5-stage pipeline is used to increase the amount of operational parallelism, giving the most performance out of each clock cycle. A 32-bit wide SRAM resides on the CPU’s Data TCM (D-TCM) interface, providing single-cycle data accesses. The D-TCM shares SRAM access with the Advanced High-performance Bus (AHB). Sharing is controlled by simple arbitration logic to allow the DMA unit on the AHB to also access to the SRAM.
4. EXPERIMENTAL CONTROL Using the development kit and the panel PC presented above we made a control application for this kind of converters with chaotic behaviours. In figure 6 is shown the software interface for this application.
Fig. 6 Experimental control interface The interface is organised in 2 zones: one for results visualisation and the second for choosing the parameters for the converters and control. In the top part of the first zone are shown the waveforms for current or voltage for the circuits, depends on what is selected at the corresponding control. The bifurcation
Fig. 5 Panel-PC interface The panel PC (figure 5) main characteristics are: touchScreen(15”) – rezistiv, processor Celeron M(400FSB), memory 512M, video Extreme Graphics 2.
429
REFERENCES
diagram is shown in the bottom part. The bifurcation diagram values are loaded in memory to avoid wasting time with the calculus. In the second zone, the setup, it could be selected what converter we want for control (from the converters presented in 1), some parameters for the converter and the control parameters. The interface controls was chosen for a good communication between user and the panel PC touch screen. The results for the voltage is presented in figure 7 for boost converter and in figure 8 for the buck converter.
Banerjee S., Verghese S., (2001) (edited), “Nonlinear phenomena in power electronics: attractor, chaos, bifurcation and nonlinear control”, IEEE Press USA, Banerjee S., Chakrabarty K., (1998b) „Nonlinear modelling and bifurcations in the boost converter”, IEEE Trans. on Power Electronics, vol. 13, no. 2, pp. 252-260 Banersjee S., Karthic M. S., Yuan G. H., Yorke J. H.,(2000a), „Bifurcations in one-dimensional piecewise soomth maps- theory and applications in switching circuits”, IEEE Trans. on Circuits and Systems-I, vol 47, no.3. Banerjee S., Ranja P., Grebogi C.,(2000b) „Bifurcations in two-dimensional piecewise smooth maps-theory and applications in switching circuits”, IEEE Trans. on Circuits and Systems-I, vol. 47, no. 5, Chakrabarty K., Podder G., Banerjee S., (1996b), „Bifurcation behavior of buck converter”, IEEE Trans. on Power Electronics, vol. 11, no. 3, pp. 439-447 Chan W.C.Y. and Tse C. K., (1997), „Study of bifurcations in current programmed dc/dc boost converters: from quasiperiodicity to period doubling”, IEEE Trans. on Circuits and SystemsI, vol. 44, no.12, pp. 1129-1142 Deane J. H., (1992), „Chaos in a current-mode controlled boost dc-dc converter”, IEEE Trans. on Circuits and Systems-I, vol. 39, pp. 680-683, August 1992 Di Bernardo M., Garofalo F., Glielmo L., Vasca F., (1998b), „Switchings, bifurcations and chaos in DC-DC converters”, IEEE Trans. on Circuits and Systems-I, vol. 45, no. 2, pp. 133-141, Fossas E., Olivar G., (1996a) „Study of chaos in the buck converter”, IEEE Transactions on Circuits and Systems-I, vol. 43, no. 1, pp. 13-25 Ott E., Grebogi C. and Yorke J. A., (1990), „Controlling chaos”, Phvsical Review Letters, vol. 64. no. 11, pp. 1196-1199, Tse C. K., (2003) “Complex Behavior of Switching Power Converters”, Boca Raton, USA: CRC Press,
Fig. 7 Output voltage for OGY control applied to boost converter after 0.02 sec
Fig. 8 Output voltage for OGY control applied to buck converter after 0.02 sec We developed the software for data acquisition and control in C++ using libraries dedicated for our board. CONCLUSION Ott-Grebogi-Yorke method as a chaotic behaviour control had good results in simulations studies. But in practice is hard to obtain a chaotic behaviour for a circuit because of noise or other neglected components in theoretical and simulation studies. Our application approaches form the experimental point of view the OGY control method for 2 kind of converters, with very good results. On the other hand the interface is user-friendly and very easy to communicate with the user. The results confirm the simulation studies in both cases.
430
EXPERIMENTAL CONTROL OF CHAOTIC BEHAVIOUR IN DC-DC CONVERTERS Florin Dragan, Daniel Curiac, Emil Voisan, Adrian Motantau Department of Automatical Control,University “Politehnica” from Timisoara, Bv. V. Parvan, 1900 Timisoara, Romania [email protected]
Abstract: Power electronic systems are an important class of systems that operate by a variable structure control. Chaotic behaviour of some dc-dc converters were demonstrated by computer simulations. The paper approaches three experimental control methods for this kind of systems grouped in a single software package. As development board we used a board with a microcontroller and as interface a panel PC. Copyright © 2007 IFAC Keywords: chaotic behaviour, control, computer interface, converter, power systems.
1. INTRODUCTION Nonlinear dynamics is an older and broader field than power electronics. High efficiency solid state power conversion has become possible through the continuing development of high power semiconductor devices. The operation of these devices as switches, which is necessary for high efficiency, means that power electronic circuits are essentially nonlinear time varying dynamical systems. The conventional approach ignores nonlinear effects and could design a circuit with a normal behaviour but in practice it has a chaotic behaviour (2003). In recent years, the possibility of controlling nonlinear chaotic dynamical systems has been the subject of extensive investigation. Following the pioneering work , much research efforts has focused on the possibility of solving the problem of suppressing chaotic regimes in systems with this behaviour .
Fig. 1. The buck dc-dc converter The values for the circuit elements are R=15[Ω]; L=12[mH]; C=20[μF]; Vin=5[V]. The functionality of the circuit can be described by the following dynamical system with variable structure (1998b) (1996a): (1 − d ) 1 ⎧ ⎪ x&1 = − L x 2 + L Vin ⎨ 1 1 ⎪ x& 2 = x1 − x2 C RC ⎩
(1)
1.1 Actual systems behaviour The converters studied was a dc-dc buck and a dc-dc current mode controlled boost. The buck dc-dc converter is in fact a chopper that converts a dc input to a dc output at a lower value. Figure 1 shows the circuit (2001) (1998b). Fig. 2. The current mode controlled boost conveter
427
where d=0 means the switch S on and 1 means the switch is off (1996b) (1997). The second circuit shown in figure 2 is a dc-dc current mode controlled boost converter and could be described by the following dynamical system: . ⎧ A1 x + B 1V i for t cl , n < t < t op ,n
x = ⎨ ⎩ A 2 x + B 2V i
The principle of the OGY controller is very simple. For systems with chaotic behavior you can assume that the system will evolve close enough to a stable orbit on which you want to stabilize it. In order to keep the system on that orbit, you have to add small perturbations to a parameter. The dynamics of the system can be represented as arising from an n-dimensional nonlinear discrete-time function of the following form: x k +1 = P (x k , p ) (3) where p is an accessible system parameter. In the case of continuous-time systems this map is given via some form of sampling(1990). There is a maximum small perturbation Δp* in the parameter p by which it is acceptable to vary p from the nominal value p*. For the value of p* there is a chaotic attractor of the underlying system which contains a specific periodic trajectory around which one wishes to stabilize the dynamics. The position of this periodic trajectory is a function of p, but the local dynamics do not vary much with the allowed small changes in parameter p. While the dynamics is assumed to arise from a map, one needs no model for the global dynamics. These assumptions would seem to allow for the control of any chaotic system for which a faithful map can be constructed, e.g., from experimental data. For simplicity the presentation is restricted to a twodimensional map P. An equilibrium point xF(p) of the map (3) of the system is defined by: x F ( p ) = P(x F ( p ), p ) (4) therefore it moves with the parameter p by:
for t op , n ≤ t < t cl , n +1
{top ,n } = {t | i (t ) = I ref } {tcl ,n } ⊂ {kT , k ∈ Ζ} ⎡− 1 / RC 0⎤ ⎡ 0 ⎤ (2) A1 = ⎢ , B1 = ⎢ ⎥ ⎥ 0⎦ ⎣ 0 ⎣1 / L ⎦ where x=[v i]T represent the state vector of the boost converter and depends on the state of the circuit: The circuit consists from a controlled switch S, a diode D, an inductor, a capacitor and a load resistor characterized by inductance L, resistance R and capacity C. The control for the switch is assured by a flip-flop and a comparator circuit. The values are R=10[Ω], L=1.5[mH], C=10[μF] (1992). The bifurcation diagrams (2000a,b) for the circuits is shown in figure 3 for buck and 4 for boost. It can be observed that the circuit has a chaotic behavior.
dx F ( p ) ∂P dx ( p ) ∂P ⋅ F + = (5) dp dp ∂p x ( p ), p ∂x x ( p ), p F F Let x*(p*) denote the unstable equilibrium point of the map P existing for the parameter value p* and corresponding to that periodic trajectory on the attractor which one wants to stabilize. From (5) results: dx dx ∂P ∂P (6) = F − ⋅ F ∂p x* , p* dp p* ∂x x* , p* dp p*
Fig. 3 The bifurcation diagram for the buck converter
or
b = (I − A ) ⋅ g
where g = dx F dp
, A= p
*
(7) ∂P ∂x
x* , p *
, b=
∂P ∂p
(8) x* , p*
In the close neighborhood of the desired equilibrium point x*(p*) we can assume with good accuracy that the dynamics of map P is linear and can be expressed by the first-order approximation of (1990): ∂P ∂P Δx k +1 = ⋅ Δx k + ⋅ Δp k = ∂x x* , p* ∂p x* , p* (9)
Fig. 4 The bifurcation diagram for the boost converter
= A ⋅ Δx k + b ⋅ Δp k
Substituting (7) in (9): (10) Δxk +1 = A ⋅ Δxk + (I − A) ⋅ g ⋅ Δpk There is a practical method for determining the amplitude of the perturbation. You have to simulate the system without perturbation, find the peak value of the current(voltage) for the desired orbit. Write
The diagram shows the period doubling and after that, chaos. It could be observed the intermittencies zones. 2. OGY CONTROL METHOD
428
down that value, together with a few more values for the following iterations. Then apply a small perturbation, find again the peak value of the current(voltage) and see how much it varied. Now you have to see how much you have to vary the perturbation according to the difference between the values for the next iterations and the desired orbit. After you have the amount, all you have to do is to find out when the system gets close enough to the desired orbit in order to apply the perturbation.
DMA channels on the Advanced Highperformance Bus (AHB) take full advantage of the separate data path provided by the Harvard architecture, moving data rapidly and largely independent of the instruction path. There are two DMA units, one is dedicated to move data between the Ethernet interface and SRAM, the other DMA unit has eight programmable channels with 16 request signals to service other peripherals and interfaces (USB, SSP, I2C, UART, Timers, EMI, and external request pins). There are two independent 32-bit wide Burst Flash memories enabling true read-while-write operation. The Flash memories are single-voltage erase/program with 20 year minimum data retention and 100K minimum erase cycles. The primary Flash memory is much larger than the secondary Flash. There are 32 bytes of OTP memory ideally suited for serial numbers, security keys, factory calibration constants, or other permanent data constants. These OTP data bytes can be programmed only one time through either the JTAG interface or by the CPU, and these bytes can never be altered afterwards. Interrupt management in the STR91xF is implemented from daisy-chaining two standard ARM VIC units. This combined VIC has 32 prioritized interrupt request channels and generates two interrupt output signals to the CPU. The output signals are FIQ and IRQ, with FIQ having higher priority. The STR91xF offers configurable and flexible power management control that allows the user to choose the best power option to fit the application. Power consumption can be dynamically managed by firmware and hardware to match the system’s requirements. Power management is provided via clock control to the CPU and individual peripherals.
3. HARDWARE INSTRUMENTS Hardware board, developed by HITEX, is based on ARM 9 processor. Main characteristics are: controller STR912FW44X: ARM 966 32 bit / 96 MHz, 512kB + 32 kB flash memory, 96kB SRAM, Ethernet 10/100, USB 2.0, CAN 2.0, timers and other periferics, 2 LED 7- segment LED display, JTAG interface, IMC(Inductive Motor Controller) conector. The STR91xF is a SiP device, comprised of two stacked die. One die is the ARM966E-S CPU with peripheral interfaces and analog functions, and the other die is the burst Flash. The two die are connected to each other by a custom high-speed 32bit burst memory interface and a serial JTAG test/programming interface. The ARM966E-S core inherently has separate instruction and data memory interfaces (Harvard architecture), allowing the CPU to simultaneously fetch an instruction, and read or write a data item through two Tightly-Coupled Memory (TCM) interfaces. The result is streamlined CPU Load and Store operations and a significant reduction in cycle count per instruction. In addition to this, a 5-stage pipeline is used to increase the amount of operational parallelism, giving the most performance out of each clock cycle. A 32-bit wide SRAM resides on the CPU’s Data TCM (D-TCM) interface, providing single-cycle data accesses. The D-TCM shares SRAM access with the Advanced High-performance Bus (AHB). Sharing is controlled by simple arbitration logic to allow the DMA unit on the AHB to also access to the SRAM.
4. EXPERIMENTAL CONTROL Using the development kit and the panel PC presented above we made a control application for this kind of converters with chaotic behaviours. In figure 6 is shown the software interface for this application.
Fig. 6 Experimental control interface The interface is organised in 2 zones: one for results visualisation and the second for choosing the parameters for the converters and control. In the top part of the first zone are shown the waveforms for current or voltage for the circuits, depends on what is selected at the corresponding control. The bifurcation
Fig. 5 Panel-PC interface The panel PC (figure 5) main characteristics are: touchScreen(15”) – rezistiv, processor Celeron M(400FSB), memory 512M, video Extreme Graphics 2.
429
REFERENCES
diagram is shown in the bottom part. The bifurcation diagram values are loaded in memory to avoid wasting time with the calculus. In the second zone, the setup, it could be selected what converter we want for control (from the converters presented in 1), some parameters for the converter and the control parameters. The interface controls was chosen for a good communication between user and the panel PC touch screen. The results for the voltage is presented in figure 7 for boost converter and in figure 8 for the buck converter.
Banerjee S., Verghese S., (2001) (edited), “Nonlinear phenomena in power electronics: attractor, chaos, bifurcation and nonlinear control”, IEEE Press USA, Banerjee S., Chakrabarty K., (1998b) „Nonlinear modelling and bifurcations in the boost converter”, IEEE Trans. on Power Electronics, vol. 13, no. 2, pp. 252-260 Banersjee S., Karthic M. S., Yuan G. H., Yorke J. H.,(2000a), „Bifurcations in one-dimensional piecewise soomth maps- theory and applications in switching circuits”, IEEE Trans. on Circuits and Systems-I, vol 47, no.3. Banerjee S., Ranja P., Grebogi C.,(2000b) „Bifurcations in two-dimensional piecewise smooth maps-theory and applications in switching circuits”, IEEE Trans. on Circuits and Systems-I, vol. 47, no. 5, Chakrabarty K., Podder G., Banerjee S., (1996b), „Bifurcation behavior of buck converter”, IEEE Trans. on Power Electronics, vol. 11, no. 3, pp. 439-447 Chan W.C.Y. and Tse C. K., (1997), „Study of bifurcations in current programmed dc/dc boost converters: from quasiperiodicity to period doubling”, IEEE Trans. on Circuits and SystemsI, vol. 44, no.12, pp. 1129-1142 Deane J. H., (1992), „Chaos in a current-mode controlled boost dc-dc converter”, IEEE Trans. on Circuits and Systems-I, vol. 39, pp. 680-683, August 1992 Di Bernardo M., Garofalo F., Glielmo L., Vasca F., (1998b), „Switchings, bifurcations and chaos in DC-DC converters”, IEEE Trans. on Circuits and Systems-I, vol. 45, no. 2, pp. 133-141, Fossas E., Olivar G., (1996a) „Study of chaos in the buck converter”, IEEE Transactions on Circuits and Systems-I, vol. 43, no. 1, pp. 13-25 Ott E., Grebogi C. and Yorke J. A., (1990), „Controlling chaos”, Phvsical Review Letters, vol. 64. no. 11, pp. 1196-1199, Tse C. K., (2003) “Complex Behavior of Switching Power Converters”, Boca Raton, USA: CRC Press,
Fig. 7 Output voltage for OGY control applied to boost converter after 0.02 sec
Fig. 8 Output voltage for OGY control applied to buck converter after 0.02 sec We developed the software for data acquisition and control in C++ using libraries dedicated for our board. CONCLUSION Ott-Grebogi-Yorke method as a chaotic behaviour control had good results in simulations studies. But in practice is hard to obtain a chaotic behaviour for a circuit because of noise or other neglected components in theoretical and simulation studies. Our application approaches form the experimental point of view the OGY control method for 2 kind of converters, with very good results. On the other hand the interface is user-friendly and very easy to communicate with the user. The results confirm the simulation studies in both cases.
430