- Email: [email protected]
decade CMOS devices
Current Applied Physics 15 (2015) 352e355
Contents lists available at ScienceDirect
Current Applied Physics journal homepage: www.elsevier.com/locate/cap
Experimental observation of voltage amplification using negative capacitance for sub-60 mV/decade CMOS devices Jaesung Jo, Changhwan Shin* School of Electrical and Computer Engineering, University of Seoul, Seoul 130-743, South Korea
a r t i c l e i n f o
a b s t r a c t
Article history: Received 2 October 2014 Received in revised form 4 December 2014 Accepted 30 December 2014 Available online 14 January 2015
In this study, an experimental study of negative capacitance is performed in order to overcome the physical limit of subthreshold slope (SS), SS 60 mV/decade at 300 K, which is originated from (i) using the thermionic emission process in complementary metal-oxide-semiconductor (CMOS) technology and (ii) non-scalability of the thermal voltage kBT/q (i.e., in order to realize SS lower than 60 mV/decade at 300 K). To make the surface potential higher than the gate voltage, a step-up voltage amplifier is included in the CMOS gate stack using a ferroelectric capacitor implemented with ferroelectric material. The measured SS in long-channel CMOS transistors is 13 mV per decade at 300 K. A simple connection of the ferroelectric capacitor to a complementary metal oxide semiconductor (CMOS) gate electrode would provide a new evolutionary pathway for future CMOS scaling. © 2015 Elsevier B.V. All rights reserved.
Keywords: Negative capacitance MOSFET CMOS
1. Introduction Next-generation complementary metal oxide semiconductor (CMOS) devices are increasingly being required to have low power consumption and high performance. To satisfy these requirements, a steep switching characteristic (i.e., having a subthreshold slope (SS) less than 60-mV/decade at 300 K) is required, especially for low power supply voltages of 0.5 V or less. However, silicon-based CMOS devices cannot overcome the physical limitation of SS because of the thermionic emission process (i.e. the thermal voltage is not scaled), and therefore the power supply voltage (VDD) for 22/ 20-nm and 16/14-nm CMOS technology is tied up to 0.7 Ve0.9 V. In fact, the power density in state-of-the-art CMOS technology has been soared up to the power density of a nuclear reactor because VDD has not decreased as rapidly as the scaling of device size. To address this technical challenge, the concept of negative capacitance was suggested [1,2] and experimental [3e6] and theoretical [9,11e15] works were previously performed for low-power CMOS devices. The main advantage to be realized by using negative capacitance is that the steep switching feature (i.e., sub-60-mV/ decade SS, resulting in lower VDD) can be implemented without device performance degradation. It is noteworthy that another steep switching device, known as Tunnel FET (TFETs), can do
* Corresponding author. E-mail address: [email protected] (C. Shin). http://dx.doi.org/10.1016/j.cap.2014.12.029 1567-1739/© 2015 Elsevier B.V. All rights reserved.
achieve sub-60-mV/decade SS but its performance is severely degraded because of the band-to-band tunneling mechanism. In order to experimentally demonstrate the negative capacitance of the ferroelectric capacitor, P(VDF0.75-TrFE0.25) has received attention as one of the ferroelectric materials: its effects were discussed in previous research works [3,4]. However, the ferroelectric insulation layer in the previous studies was too thick to be inserted into the gate stack of the state-of-the-art CMOS device. To tackle this technical issue, a ferroelectric capacitor is separately fabricated and then connected in series to CMOS devices in frontend-of-line (FEOL) process. This work demonstrated that a ferroelectric capacitor using P(VDF0.75-TrFE0.25) can be successfully fabricated and then connected in series to CMOS device. This provides an evolutionary pathway for future CMOS device scaling because it is compatible with previously commercialized techniques such as stress engineering, HK/MG gate stacks, and threedimensional FinFET device structure. For this reason, the ferroelectric capacitor consisted of P(VDF0.75-TrFE0.25) is connected to a commercialized CMOS device in series to confirm the CMOS-compatibility and its potential as ultra-low power CMOS technology. Moreover, the step-up voltage amplification realized by the ferroelectric capacitor is observed and experimentally measured. And it is discussed with the measured capacitanceevoltage curves and measured input transfer characteristic curves with sub-60-mV/decade steep-switching features in CMOS devices.
J. Jo, C. Shin / Current Applied Physics 15 (2015) 352e355
353
2. Fabrication of a ferroelectric capacitor To fabricate a negative capacitor, an 80-nm-thick TiN metal layer was first deposited on a bulk silicon substrate by DC magnetron sputtering. Then, a poly(vinylidenefluoride-trifluoroethylene) [P(VDF0.75-TrFE0.25)] powder was fully dissolved in methyl-ethylketone (MEK) solvent, to prepare a 1 wt% (weight percent) P(VDF0.75eTrFE0.25) solution. The solution was deposited on top of the TiN metal layer by spin coating at 1500 rpm for 30 s, so that a ferroelectric-insulation layer was created. This was followed by an annealing process at ~140 C for ~1 h. Finally, a 100-nm thick gold electrode patterned as a circular shape with a diameter of 0.2 mm was deposited by thermal evaporation. 3. Results and discussion Generally, the capacitance of ferroelectric capacitor is quantitatively expressed [1] as the following Equation (1).
CFE ¼
d2 U dP 2
1 ¼
1 2a þ 12bP 2 þ 30gP 4
(1)
where U ( ¼ aP2 þ bP4 þ gP6 þ EextP) is the Gibb's free energy, P is polarization, and a, b, g are the constant values of ferroelectric material. The material constants in the Equation (1) are as follows: a ¼ 1/2ε > 0, b ¼ 0, g ¼ 0 for dielectric material such as SiO2, HfO2. Hence, the energy of the dielectric capacitor using SiO2 and/or HfO2 cannot become negative. However, if ferroelectric material is used as an insulation layer of capacitor, its material constants are as follows: a < 0, b < 0, g > 0, especially for P(VDF0.75-TrFE0.25) material [7]. Therefore, the energy of the ferroelectric capacitor can become negative in a certain region of polarization. As shown in Fig. 1, the energy can be negative in a certain region where the molecular chain of the P(VDF0.75-TrFE0.25) material is rotated by 180 [8] (i.e., the phase transition of the ferroelectric material). Because of the relationship between CFE and U of the ferroelectric capacitor [see Equation (1)], the ferroelectric capacitor can have a negative capacitance value while the phase of the ferroelectric material is transited. In order to “stably” use the negative capacitance effect of the ferroelectric capacitor in CMOS devices, the total capacitance seen from the CMOS gate stack must be positive (even though the ferroelectric capacitor's capacitance is negative). Hence, when a dielectric layer is connected to a ferroelectric capacitor in series, the total capacitance can be positive with the voltage
Fig. 1. Gibb's free energy versus polarization of ferroelectric capacitor. It is extracted from the equation U ¼aP2 þ bP4 þ gP6 þ EextP, where a ¼ a0(T Tc), a0 ¼ 1.75 107 Jm/ C2K, b ¼ 0.375 1012 Jm5/C4, and g ¼ 0.316 1014 Jm9/C6 for P(VDF-TrFE) [7], and the external voltage can be neglected in steady state. The dotted rectangular region in the figure indicates the negative capacitance region.
Fig. 2. Three-dimensional (3-D) illustration showing the series connection between a ferroelectric capacitor and a long-channel commercialized MOSFET (i.e., 2N7000 NChannel Enhancement Mode Field Effect Transistor of Fairchild Semiconductor).
amplification in CMOS devices (as discussed in [1,9]). To experimentally verify the effect of internal voltage (VInt) amplification on CMOS device performance (i.e., SS less than 60 mV/decade), the FCG structure (i.e., the ferroelectric capacitor and transistor gate connection structure [10]) is developed, as shown in Fig. 2. Fig. 3a shows the measured capacitance vs. gate voltage of a long-channel MOSFET only, and Fig. 3b shows the measured capacitance vs. gate voltage of a ferroelectric capacitor only. As a general rule, the total capacitance is lower than the minimal capacitance of two capacitors when they are connected in series. However, this is not the case, if a negative capacitor is included in the configuration of the series-connected capacitors (see Fig. 3c). As predicted in [11], a single-valued and peaked CeV characteristic is experimentally observed, which implies the sign of operation in the NC region. Because of the existence of a step-up
Fig. 3. Measured capacitance (vs. gate voltage) of (a) the long-channel MOSFET only and (b) the ferroelectric capacitor only. (c) Measured total capacitance (vs. gate voltage) of the long-channel MOSFET connected with the ferroelectric capacitor (orange-colored line), and the estimated capacitance (vs. gate voltage) of the ferroelectric capacitor when it is connected with the MOSFET (red-colored line). The following equation is used to quantitatively estimate CFE ¼ [CMOS CTOTAL/(CMOS CTOTAL)]. Note that the applied voltage is swept from 5.0 V to þ5.0 V, then back to e5.0 V with a 1 MHz frequency and 30 mV AC voltage. For the measurements, the semiconductor characterization system (Keithley 4200-SCS) was used. (For interpretation of the references to color in this figure legend, the reader is referred to the web version of this article.)
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J. Jo, C. Shin / Current Applied Physics 15 (2015) 352e355
voltage transformer implemented by the negative capacitance, the total capacitance (e.g., ~40 pF marked by the dotted circle in Fig. 3c) is higher than the minimum capacitance (e.g., ~15 pF in Fig. 3a) of the two series-connected capacitors (CFE and CMOS). Therefore, if a ferroelectric capacitor is connected to the top of the gate oxide insulator in the CMOS gate stack, the total gate oxide capacitance seen from the gate electrode can be increased. The amplified capacitance was only observed for a limited range of gate voltages (i.e., phase transition region of the ferroelectric material); note that the SS < 60 mV/decade region in the transistor input transfer characteristic curve is the interpretation of the internal voltage gain >1. This experimental observation is related to previous simulation works [11e13]. To experimentally observe the internal voltage (VInt) amplified by a ferroelectric capacitor, VInt is measured as a function of the gate voltage (Fig. 4a). As shown in Fig. 4b, the internal voltage gain is higher than 1 (i.e., dVInt/dVG > 1), and thereby it can lead to the increased surface potential in CMOS devices (i.e., 4S > VG). Moreover, the internal voltage, which was significantly amplified by the ferroelectric capacitor (i.e., dVInt/dVG ¼ 8.5), was explicitly measured. This experimental observation of voltage amplification by a ferroelectric capacitor is consistent with the previously published work [3e6]. In general, the surface potential is a fraction of the gate voltage in a CMOS system, resulting in the minimum SS value of 60-mV/ decade [see Equation (2)]. However, the SS can be made lower than 60-mV/decade only when the surface potential is higher than the gate voltage (i.e., if the internal voltage is amplified by the ferroelectric capacitor).
SS ¼
vVG vfS vV ¼ 60mV=dec G v4S vðlog10 ID Þ v4S
(2)
Fig. 5. Measured drain current (ID) versus gate voltage (VG) of the long-channel NMOS transistor without the ferroelectric capacitor (see blue-colored line) or with the ferroelectric capacitor (see green-colored line). A significant improvement in subthreshold slope (SS) is experimentally observed (i.e., from 150 mV/dec to 13 mV/dec in the forward voltage sweep) at 300 K. Note that the applied gate voltage is swept from 5.0 V to þ5.0 V, then back to e 5.0 V, and the drain voltage is þ5.0 V. (For interpretation of the references to color in this figure legend, the reader is referred to the web version of this article.)
The aforementioned expectation is verified in Fig. 5. When the fabricated ferroelectric capacitor is connected to the gate electrode of the long-channel MOS transistor, SS is dramatically lowered to 13 mV/decade at 300 K. This steep switching region is closely associated with the internal voltage amplification (i.e., the steep switching occurs when the internal voltage is amplified). It is believed that the observed steep switching may result from a breakdown of the ferroelectric insulator. To determine whether or not it was caused by the large gate leakage current, the gate leakage current is measured. As shown in Fig. 6, the gate leakage current is ~10 pA when there is voltage amplification. This explicitly indicates that the steep switching characteristic (i.e., SS ~ 13 mV/decade at 300 K) was not obtained because of ferroelectric insulator breakdown. 4. Conclusion Because of the non-scalable thermal voltage and/or the physical limitation of the SS (¼60-mV/decade at 300 K), power supply voltages (VDD) have not been decreased as rapidly as the aggressive scaling of CMOS device sizes, so the power density in CMOS devices has constantly increased. To overcome this technical challenge, an experimental study of the negative capacitance is performed. The steps carried out were as follows. (i) it is introduced the fabrication
Fig. 4. (a) Measured internal voltage (VInt) vs. gate voltage (VG), (b) measured internal voltage gain (VInt/VG) vs. gate voltage (VG). The dotted line indicates the unity gain (i.e., VInt/VG ¼ 1) of the step-up voltage amplifier. Note that the applied voltage is swept from 5.0 V to þ5.0 V, then back to e5.0 V.
Fig. 6. Measured gate leakage current (IG) vs. gate voltage (VG). The gate leakage current is in the range of l pA ~0.5 nA. Note that the applied voltage is swept from 5.0 V to þ5.0 V, then back to e5.0 V.
J. Jo, C. Shin / Current Applied Physics 15 (2015) 352e355
steps for a ferroelectric capacitor using ferroelectric material, and the negative capacitance is then experimentally extracted from the measured CeV curves. (ii) Using the ferroelectric capacitor, the step-up voltage amplification in the CMOS system is experimentally observed (i.e., dVInt/dVG > 1). (iii) Finally, an SS of 13 mV/ decade is experimentally shown in a MOS transistor with the ferroelectric capacitor. Acknowledgment This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (No. 2014R1A2A1A11050637).
[6]
[7]
[8]
[9]
[10]
[11]
References [1] S. Salahuddin, S. Datta, Use of negative capacitance to provide voltage amplification for low power nanoscale devices, Nano Lett. 8 (2008) 405. [2] V.V. Zhirnov, R.K. Cavin, Negative capacitance to the rescue? Nat. Nanotechnol. 3 (2008) 77. [3] G.A. Salvatore, D. Bouvet, A.M. Ionescu, Demonstration of subthreshold swing smaller than 60 mV/decade in Fe-FET with P(VDF-TrFE)/SiO2 gate stack, in: IEEE IEDM. Proc, 2008, p. 1. [4] R. Alexandru, G.A. Salvatore, D. Jimenez, A.M. Ionescu, Metal-ferroelectricmetal-oxide-semiconductor field effect transistor with sub-60mV/decade subthreshold swing and internal voltage amplification, in: IEEE IEDM. Proc, 2010, 16.3.1. [5] D.J.R. Appleby, N.K. Ponon, K.S.K. Kwa, B. Zou, P.K. Petrov, T. Wang,
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N.M. Alford, A. O'Neil, Experimental observation of negative capacitance in ferroelectrics at room temperature, Nano Lett. 14 (2014) 3864. A.I. Khan, D. Bhowmik, P. Yu, S.J. Kim, X. Pan, R. Ramesh, S. Salahuddin, Experimental evidence of ferroelectric negative capacitance in nanoscale heterostructures, Appl. Phys. Lett. 99 (2011), 113501e1. G. Bai, R. Li, Z.G. Liu, Y.D. Xia, J. Yin, Tuned dielectric, pyroelectric and piezoelectric properties of ferroelectric P(VDF-TrFE) thin films by using mechanical loads, J. Appl. Phys. 111 (2012) 044102e044111. W.J. Hu, D.M. Juo, L. You, J. Wang, Y.C. Chen, Y.H. Chu, T. Wu, Universal ferroelectric switching dynamics of vinylidene fluoride-trifluoroethylene copolymer films, Sci. Rep. 4 (2014) 4772. A. Jain, M.A. Alam, Stability constraints define the minimum subthreshold swing of a negative capacitance field-effect transistor, IEEE Trans. Electron Dev. 61 (2014) 2235. Y. Katoh, S. Fujieda, Y. Hayashi, T. Kunio, Non-volatile FCG (FerroelectricCapacitor and Transistor-Gate Connection) memory cell with non-destructive read-out operation, in: Symp. on VLSI Tech. Proc, 1996, p. 56. D. Jimenez, E. Miranda, A. Godoy, Analytic model for the surface potential and drain current in negative capacitance field effect transistor, IEEE Trans. Electron Dev. 57 (2010) 2405. Y.G. Xiao, Z.J. Chen, M.H. Tang, Z.H. Tang, S.A. Yan, J.C. Li, X.C. Gu, T.C. Zhou, X.P. Ouyang, Simulation of electrical characteristics in negative capacitance surrounding-gate ferroelectric field-effect transistors, Appl. Phys. Lett. 101 (2012), 253511e1. A.I. Khan, C.W. Yeung, C. Hu, S. Salahuddin, Ferroelectric negative capacitance MOSFET: capacitance tuning & antiferroelectric operation, in: IEEE IEDM. Proc, 2011, 11.3.1. A. Cano, D. Jimenez, Multidomain ferroelectricity as a limiting factor for voltage amplification in ferroelectric field-effect transistors, Appl. Phys. Lett. 97 (2010) 133509e133511. A. Jain, M.A. Alam, Prospects of hysteresis-free abrupt switching (0 mV/ decade) in landau switches, IEEE Trans. Electron Dev. 60 (2013) 4269.
Contents lists available at ScienceDirect
Current Applied Physics journal homepage: www.elsevier.com/locate/cap
Experimental observation of voltage amplification using negative capacitance for sub-60 mV/decade CMOS devices Jaesung Jo, Changhwan Shin* School of Electrical and Computer Engineering, University of Seoul, Seoul 130-743, South Korea
a r t i c l e i n f o
a b s t r a c t
Article history: Received 2 October 2014 Received in revised form 4 December 2014 Accepted 30 December 2014 Available online 14 January 2015
In this study, an experimental study of negative capacitance is performed in order to overcome the physical limit of subthreshold slope (SS), SS 60 mV/decade at 300 K, which is originated from (i) using the thermionic emission process in complementary metal-oxide-semiconductor (CMOS) technology and (ii) non-scalability of the thermal voltage kBT/q (i.e., in order to realize SS lower than 60 mV/decade at 300 K). To make the surface potential higher than the gate voltage, a step-up voltage amplifier is included in the CMOS gate stack using a ferroelectric capacitor implemented with ferroelectric material. The measured SS in long-channel CMOS transistors is 13 mV per decade at 300 K. A simple connection of the ferroelectric capacitor to a complementary metal oxide semiconductor (CMOS) gate electrode would provide a new evolutionary pathway for future CMOS scaling. © 2015 Elsevier B.V. All rights reserved.
Keywords: Negative capacitance MOSFET CMOS
1. Introduction Next-generation complementary metal oxide semiconductor (CMOS) devices are increasingly being required to have low power consumption and high performance. To satisfy these requirements, a steep switching characteristic (i.e., having a subthreshold slope (SS) less than 60-mV/decade at 300 K) is required, especially for low power supply voltages of 0.5 V or less. However, silicon-based CMOS devices cannot overcome the physical limitation of SS because of the thermionic emission process (i.e. the thermal voltage is not scaled), and therefore the power supply voltage (VDD) for 22/ 20-nm and 16/14-nm CMOS technology is tied up to 0.7 Ve0.9 V. In fact, the power density in state-of-the-art CMOS technology has been soared up to the power density of a nuclear reactor because VDD has not decreased as rapidly as the scaling of device size. To address this technical challenge, the concept of negative capacitance was suggested [1,2] and experimental [3e6] and theoretical [9,11e15] works were previously performed for low-power CMOS devices. The main advantage to be realized by using negative capacitance is that the steep switching feature (i.e., sub-60-mV/ decade SS, resulting in lower VDD) can be implemented without device performance degradation. It is noteworthy that another steep switching device, known as Tunnel FET (TFETs), can do
* Corresponding author. E-mail address: [email protected] (C. Shin). http://dx.doi.org/10.1016/j.cap.2014.12.029 1567-1739/© 2015 Elsevier B.V. All rights reserved.
achieve sub-60-mV/decade SS but its performance is severely degraded because of the band-to-band tunneling mechanism. In order to experimentally demonstrate the negative capacitance of the ferroelectric capacitor, P(VDF0.75-TrFE0.25) has received attention as one of the ferroelectric materials: its effects were discussed in previous research works [3,4]. However, the ferroelectric insulation layer in the previous studies was too thick to be inserted into the gate stack of the state-of-the-art CMOS device. To tackle this technical issue, a ferroelectric capacitor is separately fabricated and then connected in series to CMOS devices in frontend-of-line (FEOL) process. This work demonstrated that a ferroelectric capacitor using P(VDF0.75-TrFE0.25) can be successfully fabricated and then connected in series to CMOS device. This provides an evolutionary pathway for future CMOS device scaling because it is compatible with previously commercialized techniques such as stress engineering, HK/MG gate stacks, and threedimensional FinFET device structure. For this reason, the ferroelectric capacitor consisted of P(VDF0.75-TrFE0.25) is connected to a commercialized CMOS device in series to confirm the CMOS-compatibility and its potential as ultra-low power CMOS technology. Moreover, the step-up voltage amplification realized by the ferroelectric capacitor is observed and experimentally measured. And it is discussed with the measured capacitanceevoltage curves and measured input transfer characteristic curves with sub-60-mV/decade steep-switching features in CMOS devices.
J. Jo, C. Shin / Current Applied Physics 15 (2015) 352e355
353
2. Fabrication of a ferroelectric capacitor To fabricate a negative capacitor, an 80-nm-thick TiN metal layer was first deposited on a bulk silicon substrate by DC magnetron sputtering. Then, a poly(vinylidenefluoride-trifluoroethylene) [P(VDF0.75-TrFE0.25)] powder was fully dissolved in methyl-ethylketone (MEK) solvent, to prepare a 1 wt% (weight percent) P(VDF0.75eTrFE0.25) solution. The solution was deposited on top of the TiN metal layer by spin coating at 1500 rpm for 30 s, so that a ferroelectric-insulation layer was created. This was followed by an annealing process at ~140 C for ~1 h. Finally, a 100-nm thick gold electrode patterned as a circular shape with a diameter of 0.2 mm was deposited by thermal evaporation. 3. Results and discussion Generally, the capacitance of ferroelectric capacitor is quantitatively expressed [1] as the following Equation (1).
CFE ¼
d2 U dP 2
1 ¼
1 2a þ 12bP 2 þ 30gP 4
(1)
where U ( ¼ aP2 þ bP4 þ gP6 þ EextP) is the Gibb's free energy, P is polarization, and a, b, g are the constant values of ferroelectric material. The material constants in the Equation (1) are as follows: a ¼ 1/2ε > 0, b ¼ 0, g ¼ 0 for dielectric material such as SiO2, HfO2. Hence, the energy of the dielectric capacitor using SiO2 and/or HfO2 cannot become negative. However, if ferroelectric material is used as an insulation layer of capacitor, its material constants are as follows: a < 0, b < 0, g > 0, especially for P(VDF0.75-TrFE0.25) material [7]. Therefore, the energy of the ferroelectric capacitor can become negative in a certain region of polarization. As shown in Fig. 1, the energy can be negative in a certain region where the molecular chain of the P(VDF0.75-TrFE0.25) material is rotated by 180 [8] (i.e., the phase transition of the ferroelectric material). Because of the relationship between CFE and U of the ferroelectric capacitor [see Equation (1)], the ferroelectric capacitor can have a negative capacitance value while the phase of the ferroelectric material is transited. In order to “stably” use the negative capacitance effect of the ferroelectric capacitor in CMOS devices, the total capacitance seen from the CMOS gate stack must be positive (even though the ferroelectric capacitor's capacitance is negative). Hence, when a dielectric layer is connected to a ferroelectric capacitor in series, the total capacitance can be positive with the voltage
Fig. 1. Gibb's free energy versus polarization of ferroelectric capacitor. It is extracted from the equation U ¼aP2 þ bP4 þ gP6 þ EextP, where a ¼ a0(T Tc), a0 ¼ 1.75 107 Jm/ C2K, b ¼ 0.375 1012 Jm5/C4, and g ¼ 0.316 1014 Jm9/C6 for P(VDF-TrFE) [7], and the external voltage can be neglected in steady state. The dotted rectangular region in the figure indicates the negative capacitance region.
Fig. 2. Three-dimensional (3-D) illustration showing the series connection between a ferroelectric capacitor and a long-channel commercialized MOSFET (i.e., 2N7000 NChannel Enhancement Mode Field Effect Transistor of Fairchild Semiconductor).
amplification in CMOS devices (as discussed in [1,9]). To experimentally verify the effect of internal voltage (VInt) amplification on CMOS device performance (i.e., SS less than 60 mV/decade), the FCG structure (i.e., the ferroelectric capacitor and transistor gate connection structure [10]) is developed, as shown in Fig. 2. Fig. 3a shows the measured capacitance vs. gate voltage of a long-channel MOSFET only, and Fig. 3b shows the measured capacitance vs. gate voltage of a ferroelectric capacitor only. As a general rule, the total capacitance is lower than the minimal capacitance of two capacitors when they are connected in series. However, this is not the case, if a negative capacitor is included in the configuration of the series-connected capacitors (see Fig. 3c). As predicted in [11], a single-valued and peaked CeV characteristic is experimentally observed, which implies the sign of operation in the NC region. Because of the existence of a step-up
Fig. 3. Measured capacitance (vs. gate voltage) of (a) the long-channel MOSFET only and (b) the ferroelectric capacitor only. (c) Measured total capacitance (vs. gate voltage) of the long-channel MOSFET connected with the ferroelectric capacitor (orange-colored line), and the estimated capacitance (vs. gate voltage) of the ferroelectric capacitor when it is connected with the MOSFET (red-colored line). The following equation is used to quantitatively estimate CFE ¼ [CMOS CTOTAL/(CMOS CTOTAL)]. Note that the applied voltage is swept from 5.0 V to þ5.0 V, then back to e5.0 V with a 1 MHz frequency and 30 mV AC voltage. For the measurements, the semiconductor characterization system (Keithley 4200-SCS) was used. (For interpretation of the references to color in this figure legend, the reader is referred to the web version of this article.)
354
J. Jo, C. Shin / Current Applied Physics 15 (2015) 352e355
voltage transformer implemented by the negative capacitance, the total capacitance (e.g., ~40 pF marked by the dotted circle in Fig. 3c) is higher than the minimum capacitance (e.g., ~15 pF in Fig. 3a) of the two series-connected capacitors (CFE and CMOS). Therefore, if a ferroelectric capacitor is connected to the top of the gate oxide insulator in the CMOS gate stack, the total gate oxide capacitance seen from the gate electrode can be increased. The amplified capacitance was only observed for a limited range of gate voltages (i.e., phase transition region of the ferroelectric material); note that the SS < 60 mV/decade region in the transistor input transfer characteristic curve is the interpretation of the internal voltage gain >1. This experimental observation is related to previous simulation works [11e13]. To experimentally observe the internal voltage (VInt) amplified by a ferroelectric capacitor, VInt is measured as a function of the gate voltage (Fig. 4a). As shown in Fig. 4b, the internal voltage gain is higher than 1 (i.e., dVInt/dVG > 1), and thereby it can lead to the increased surface potential in CMOS devices (i.e., 4S > VG). Moreover, the internal voltage, which was significantly amplified by the ferroelectric capacitor (i.e., dVInt/dVG ¼ 8.5), was explicitly measured. This experimental observation of voltage amplification by a ferroelectric capacitor is consistent with the previously published work [3e6]. In general, the surface potential is a fraction of the gate voltage in a CMOS system, resulting in the minimum SS value of 60-mV/ decade [see Equation (2)]. However, the SS can be made lower than 60-mV/decade only when the surface potential is higher than the gate voltage (i.e., if the internal voltage is amplified by the ferroelectric capacitor).
SS ¼
vVG vfS vV ¼ 60mV=dec G v4S vðlog10 ID Þ v4S
(2)
Fig. 5. Measured drain current (ID) versus gate voltage (VG) of the long-channel NMOS transistor without the ferroelectric capacitor (see blue-colored line) or with the ferroelectric capacitor (see green-colored line). A significant improvement in subthreshold slope (SS) is experimentally observed (i.e., from 150 mV/dec to 13 mV/dec in the forward voltage sweep) at 300 K. Note that the applied gate voltage is swept from 5.0 V to þ5.0 V, then back to e 5.0 V, and the drain voltage is þ5.0 V. (For interpretation of the references to color in this figure legend, the reader is referred to the web version of this article.)
The aforementioned expectation is verified in Fig. 5. When the fabricated ferroelectric capacitor is connected to the gate electrode of the long-channel MOS transistor, SS is dramatically lowered to 13 mV/decade at 300 K. This steep switching region is closely associated with the internal voltage amplification (i.e., the steep switching occurs when the internal voltage is amplified). It is believed that the observed steep switching may result from a breakdown of the ferroelectric insulator. To determine whether or not it was caused by the large gate leakage current, the gate leakage current is measured. As shown in Fig. 6, the gate leakage current is ~10 pA when there is voltage amplification. This explicitly indicates that the steep switching characteristic (i.e., SS ~ 13 mV/decade at 300 K) was not obtained because of ferroelectric insulator breakdown. 4. Conclusion Because of the non-scalable thermal voltage and/or the physical limitation of the SS (¼60-mV/decade at 300 K), power supply voltages (VDD) have not been decreased as rapidly as the aggressive scaling of CMOS device sizes, so the power density in CMOS devices has constantly increased. To overcome this technical challenge, an experimental study of the negative capacitance is performed. The steps carried out were as follows. (i) it is introduced the fabrication
Fig. 4. (a) Measured internal voltage (VInt) vs. gate voltage (VG), (b) measured internal voltage gain (VInt/VG) vs. gate voltage (VG). The dotted line indicates the unity gain (i.e., VInt/VG ¼ 1) of the step-up voltage amplifier. Note that the applied voltage is swept from 5.0 V to þ5.0 V, then back to e5.0 V.
Fig. 6. Measured gate leakage current (IG) vs. gate voltage (VG). The gate leakage current is in the range of l pA ~0.5 nA. Note that the applied voltage is swept from 5.0 V to þ5.0 V, then back to e5.0 V.
J. Jo, C. Shin / Current Applied Physics 15 (2015) 352e355
steps for a ferroelectric capacitor using ferroelectric material, and the negative capacitance is then experimentally extracted from the measured CeV curves. (ii) Using the ferroelectric capacitor, the step-up voltage amplification in the CMOS system is experimentally observed (i.e., dVInt/dVG > 1). (iii) Finally, an SS of 13 mV/ decade is experimentally shown in a MOS transistor with the ferroelectric capacitor. Acknowledgment This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (No. 2014R1A2A1A11050637).
[6]
[7]
[8]
[9]
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