- Email: [email protected]
Si heterostructures grown by mesotaxy
Nuclear Instruments and Methods in Physics Research B59/60
(1991) 693-697
693
North-Holland
Exploiting Si/CoSi JSi heterostructures
grown by mesotaxy
Alice E. White, K.T. Short, Karen Maex ‘, R. Hull, Yong-Fen Hsieh, S.A. Audet, K.W. Goossen, D.C. Jacobson and J.M. Poate AT&T Bell Laboratories,
600 Mountain Avenue, Murray Hill, NJ 07974, USA
Buried single-crystal silicide layers in silicon formed by ion implantation and annealing have many potential applications (some more practical than others!) including metal base transistors (operating at 77 K), buried collector contacts for bipolar transistors, and buried groundplanes for ultrahigh-speed electronics. Fabrication of prototype devices is complicated by the presence of defects in the overlayer silicon, but preliminary results are reported.
1. Introduction Devices incorporating buried metal layers as active or passive elements were proposed over 30 years ago, but materials-related difficulties hampered their development. Now, the ability to grow high-quality (lOO)-oriented Si/metal-silicide/Si heterostructures using ion implantation (mesotaxy [l-5]) means that some of these concepts can be revisited. In particular, we have been investigating three potential applications for these structures: metal base transistors, buried collector contacts for bipolar transistors, and buried groundplanes for microstrip transmission lines. A metal base transistor requires base thicknesses that are less than the electron mean free path for ballistic operation. To make the silicide layers as thin as possible, it is necessary to reduce the straggle of the implant profile as well as the dose. This has been accomplished by reducing the implant energy, but the concomitant reduction in implantation range leaves only a thin Si overlayer. Recently, we demonstrated that an additional overlayer of crystalline Si can be grown on these structures by chemical vapor deposition. Then by carefully choosing a set of implantation parameters for a small extra dose of Si, we can selectively amorphize the Si surrounding the CoSi, allowing a reduction of the defect density in the Si by solid phase epitaxy while retaining the original crystalline quality of the silicide layer. Schottky diodes fabricated on such structures show good characteristics for the back CoSi,/Si interface but not yet for the front. Similar Si/CoSi,/Si structures, which cannot yet be grown by other techniques, may find several uses in integrated electronics. For example, using such a layer
’ Permanent address: IMEC, Leuven, Belgium. O168-583X/91/%03.50
as a buried collector contact for a bipolar transistor should lower the collector series resistance, thereby increasing both the cutoff frequency and the maximum frequency that a bipolar can achieve. In addition, calculations have shown that if such a layer is used as a groundplane in a microstrip configuration, ultrahighspeed signals (100 GHz) can be propagated with far less dispersion than on a standard microstrip. Details of the layer formation have been reported previously [l, and references therein]. Briefly, a high dose of Co+ ions (- 1 X 1017/cm2) is implanted into a silicon wafer that is held at 350 o C to promote dynamic annealing. The energy of the ions determines the depth and the dose determines the thickness of the final layer. After a two-step anneal to 1OOO’C in vacuum the Co coalesces to form a well defined layer of stoichiometric CoSi, buried beneath the surface of the wafer. The Si/CoSi, interfaces are surprisingly abrupt as seen in high resolution transmission electron microscope (TEM) observation and the appearance of a double period reconstruction (first observed in a mesotaxy layer) is evidence for interface quality [6]. The structural integrity of these layers is confirmed by the electrical properties. In particular, the residual resistivity is as low as 2 $4 cm at 7! K, implying an electron mean free path (X) of - 500 A. This suggests the possibility of ballistic transport across the CoSi, layer if it can be made thin enough.
2. Metal base transistor If coherent ballistic transmission of electrons across the metal base of a transistor could be achieved, the device would have the possibility for very-high speed operation. First, however, three conditions must be met [7]: (1) The metal/silicide interfaces must be smooth
0 1991 - Elsevier Science Publishers B.V. (North-Holland)
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A. E. White et al. / Si / CoSi, / Si heterostructures
and parallel to conserve k and obtain high transmission. (2) The Bloch states in the metal and the silicon must line up. (3) The electron mean free path in the metal must be greater than the base thickness at the temperature of operation. Previous work on MBE-grown Si/CoSi z/Si heterostructures in (1 11)-oriented silicon [8] satisfied conditions (1) and (3) but not (2). Calculations have shown that condition (2) is satisfied in (lOO)-oriented heterostructures [9], however. Since (100) structures are difficult to grow by MBE, we thought that this device was an excellent candidate for mesotaxy. The effort has proceeded along two fronts: making thinner CoSi, layers and characterizing the Schottky barrier heights at the Si/CoSi, interfaces. The thickness of the silicide layers can be reduced by lowering the Co dose during the implantation, but there is a threshold peak concentration of Co (- 18 at.%) below which the layer does not coalesce during annealing [l]. This threshold translates into a condition on the “connectedness” of the CoSi, precipitates that are present already in the as-implanted sample [lo]. If these precipitates are touching before the anneals, they fill in to form a well defined layer. If they are isolated, they grow primarily along (111) facets, forming large octahedral precipitates. This transition from layer formation to isolated precipitates occurs over a very narrow dose range, - 10% at 200 keV. To overcome this limitation, the implant energy can be lowered, but eventually the Si surface gets in the way. Nonetheless, layers as thin as 400 A have been created by the mesotaxy technique and there is enough surface Si (300 A) to serve as a seed for epitaxial growth of additional Si. This has been successfully accomplished by conventional chemical vapor deposition (CVD) [ll] as well as by rapid thermal CVD and low-pressure vapor phase epitaxy (LPVPE) [12]. The implantation damage causes defects in the Si above the CoSi, layer and in the substrate directly below the layer that will degrade the performance of devices fabricated in these structures. A technique that has been used to improve the quality of Si on sapphire [13] and Si on buried SiO, layers [14] can also be used in this situation. Implantation conditions for a low dose of Si can be chosen so that the Si directly above and below the CoSi, layer is amorphized, but the crystallinity of the CoSi, layer and of a thin Si surface layer are retained. When the structure is regrown using the Si surface layer and the substrate as a seed, significantly lower defect densities are achieved [15]. To characterize the Schottky barriers, mesa-transistors (- 10e2 cm2) were fabricated in Si/CoSi,/Si heterostructures using standard photolithographic techniques and a combination of reactive ion and wet chemical etching. The emitter contact was produced by a low energy Sb + implant and the backside collector contact was formed by deposition of Sb and laser
V (mv) Fig. 1. I-Vcharacteristic
for a typical collector-base
CoSi,/Si junction. The somewhat noisier trace is the ideality (referenced to the right-hand scale). The Schottky barrier height determined from this measurement was 0.64 eV.
annealing. Emitter-base junctions were non-ideal with a high reverse leakage (7 X 10e4 A) and a Schottky barrier height (determined from a Norde plot) of 0.57 eV. Presumably this low value is due to defects in the overgrown Si. Collector-base junctions had idealities that were about 1.1, lower reverse leakage currents (10m5 to lop6 A), a long linear region in the forward-biased curve, and Schottky barrier heights (determined from the extrapolation of the linear region to zero bias) of 0.64 eV. An Z-V characteristic (with the ideality, n) from a typical junction is shown in fig. 1. The amorphization and regrowth technique was applied to the back interface of a sample which had no Si overgrowth. Compared to a control, the diodes had lower leakage currents (by a factor of 5) and idealities that were either unchanged or closer to 1; however, there were sample-to-sample variations in these quantities as well. So, at the very least, the process did not degrade the diodes. Work on the front interface where the room for improvement is much greater is underway. In summary, CoSi, layers as thin as 400 A can be created in a (lOO)-oriented Si wafer by implantation and annealing as long as the threshold peak concentration for layer formation is exceeded. Vertical transport measurements on mesa-transistor structures give good Z-I’ characteristics for the collector-base junction, but the emitter-base junctions have degraded characteristics, presumably due to the defects in the Si overlayer. An amorphization and regrowth process which retains the crystallinity in the CoSi, layer shows promise for improved electrical performance. Recently the group from Jiilich [12] has reported the first demonstration of a permeable base transistor with a buried CoSi, gate formed by ion implantation in (lOO)-oriented Si. The grating was fabricated by implanting Co through an oxide mask followed by rapid
A. E. White et al. / Si / CoSi, / Si heterostructures
thermal annealing (750°C for 30 s and 1150°C for 10 s). The thick (8200 A) overlayer was grown by LPVPE. Using the back-contact as the source, the transistor characteristics were encouraging, with a breakdown voltage of 8 V. With the back contact as the drain, the breakdown voltage was lower and the range of gate voltages was smaller, but the transconductance was higher, 11 mS/mm. Now that they have demonstrated the feasibility of using a mesotaxy silicide layer in a permeable base transistor, they are working on performing high-frequency measurements and optimizing the device parameters. 3. Buried collector contacts Figures of merit for high-speed bipolar transistors include jr, the cutoff frequency (where the current gain, the maximum oscillation 8, equals I) and f,,,, frequency, (where the unilateral gain equals 1) [16]. These two quantities are related by f,,,, af:/2.The cutoff frequency depends, among other things, on the collector series resistance-capacitance product. The traditional approach to lowering the collector series resistance has been to fabricate the transistor on an epi wafer. This has several disadvantages: it n/n+ results in larger transistor sizes, the lateral diffusion of the n+ layer degrades performance, and autodoping from the n+ layer during Si epi overgrowth limits the minimum epilayer thickness. Using a mesotaxy silicide layer as a buried collector contact should lower the collector series resistance (the CoSi, has a room temperature resistivity of < 20 p0 cm). Furthermore, the stability of the CoSi, means that there will be no lateral diffusion or autodoping problems. Results from a sample device are shown in fig. 2. The 3 in. (100) Si substrate was processed in a standard 500
,
I
I
8
,
I
Fig. 2. Common emitter output characteristics of a bipolar transistor with a buried collector contact made using mesotaxy. The base current is varied from 0 to 60 pA in 20 CA steps. Breakdown occurs at 8 V and fi is 7.5.
695
manufacturing line except for the Co+ implantation and annealing (which was performed in a research laboratory). The definition of the contact area and the formation of the buried silicide layer were done first. Then the contacts were patterned, implanted and diffused to form the bipolar transistor in the standard way. The output characteristics were obtained in the common emitter configuration. The breakdown voltage is 7-8 V and the transistor has a current gain, B, of - 7.5 that is constant with base current. This is a factor of 10 lower than the /3 values for the transistors from a control wafer. Also, these transistors are too leaky to perform high frequency measurements. Both the low gain and the excess leakage are probably due to threading dislocations in the top Si. Although the transistor performance is degraded, the test run provided a demonstration that the mesotaxy silicide layers are stable to processing. Moreover, if there were excess Co in the overlayer Si (in precipitates decorating the dislocations, for example), the devices would not have worked at all.
4. Interconnects for ultrahigh-speed ICs As the switching times of electronic devices become shorter than 10 ps, the role of the interconnect in ultrahigh-speed integrated circuits becomes extremely important. Dispersion occuring along the interconnect can negate the performance of high speed devices after propagation of only a few hundred micrometers. A microstrip is the simplest high-speed interconnect used in integrated circuits, but dispersion of the fundamental mode occurs at 46 GHz. Dispersion could be pushed to higher frequencies by making the substrate thinner, but this results in increased breakage and reduced heat sinking. Calculations predict enhanced performance if the center conductor-groundplane spacing, h, can be reduced, so we have proposed using a buried silicide layer as a ground plane. Dispersion in the transmission line is caused by a change in the phase velocity in the guide with frequency, the effective index of the where ncff, “phase = c/n,,, guide, is midway between the substrate and air at zero frequency and is determined by the number of field lines of the fundamental mode in either at higher frequencies. As the frequency increases, more of the field lines get concentrated in the substrate until, at high frequencies, the index of the guide is equal to the index of the substrate. As a result, a pulse, which consists of a broad spectrum of frequencies, undergoes dispersion. The effective index as a function of frequency for a 10 pm center conductor with three different values of h is plotted in fig. 3. For the standard Si wafer with an Al backplane (h = 500 pm), the change in index from the static value to that of the substrate occurs over 2 decades in frequency, resulting in large dispersion. ReVI. HIGH-E/-DOSE
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100
10’s
10”
4 10’2
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Fig. 3. The effective index of microstrip with a 10 pm wide Al center conductor for three different center conductorgroundplane spacings (h) as a function of frequency.
ducing h pushes the dispersion to higher frequencies and reduces the total dispersion. The higher resistivity of the silicide layer compared to Al means that signals on the buried groundplane microstrip will suffer more loss, but a complete time domain analysis shows that this loss is not severe. This is shown in fig. 4, where a 10 ps signal with a 2.3 ps rise time is sampled after traveling 2 mm along both a standard microstrip and a buried groundplane microstrip. It is clear that the signal on the buried groundplane microstrip has suffered much less dispersion. Although the losses are higher, they are not severe. In contrast, the rise time of the signal on the standard microstrip has increased to 6.6 ps and the signal is highly distorted. The fabrication requirements for the buried groundplane are severe, but we have created several substrates using high energy, high dose implantation of Co+ to make the 3000 A thick layers that are necessary. A cross-sectional TEM view of such a substrate is shown in fig. 5. The implantation was done at 1.5 MeV
0
10
ED
so
1
40
TIME DELAY (DW)
Fig. 4. Results of a calculation for propagation of a 100 GHz pulse 2 mm along a standard microstrip and a buriedgroundplane microstrip.
to a dose of 8.5 x 1017 Co+/cm’. After annealing to llOO°C for 1 h, the Co had coalesced to form a 3000 .& layer of CoSi, buried under 8600 A of crystalline Si. This should serve as an excellent foundation for testing the concept.
5. Summary
The ability to fabricate buried crystalline CoSi, layers in (lOO)-oriented silicon with the mesotaxy technique offers the potential for several novel devices. Although the defect density in the Si overlayer is still a major problem, the feasibility of using these layers has been demonstrated in some preliminary experiments on prototype devices. Mesa-transistors fabricated on thin (700 A) silicide layers have good collector-base junctions but the emitter-base junction is leaky. A bipolar transistor with an implanted silicide layer as a buried
Fig. 5. Cross-sectional TEM micrograph of a buried CoSi, layer fabricated by implanting 8.5 X 10” Coc/cm2 at 1.5 MeV into a (lOO)-oriented Si wafer held at 350°C. The surface of the wafer is indicated by arrows. Similar layers are being used as substrates for microstrip to test the predictions for high-speed transmission.
A. E. White et al. / Si / Co%, / Si heterostructures
collector contact was processed in a standard manufacturing line and had a reasonable breakdown voltage albeit reduced gain. Schuppen et al. [12] have demonstrated a permeable base transistor with a transconductance as high as 11 mS/mm. Calculations show that using a mesotaxy silicide as a buried groundplane for microstrip may reduce dispersion of high-speed electronic signals. As a first step toward demonstration of this design, we have fabricated 3000 A thick silicide layers buried under almost a micrometer of crystalline Si using high-energy implantation.
Acknowledgements Work on the buried collector contacts was performed in collaboration with J.O. Osenbach and H. Praefcke. We have benefitted greatly from technical discussions with R. Tung, M. Green, R.C. Dynes, and W.F. Brinkman.
References [l] A.E. White, K.T. Short, R.C. Dynes,
R. Hull and J.M. Vandenberg, Nucl. Instr. and Meth. B39 (1989) 253. [2] A.H. van Ommen, J.J.M. Ottenheim. A.M.L. Theunissen and A.G. Maiwan, Appl. Phys. Lett. 53 (1988) 669. [3] J.C. Barbour, ST. Picraux and B.L. Doyle, Mater. Res. Sot. Symp. Proc. 107 (1988) 269.
691
[4] K. Kohlhof, S. Mantl, B. Stritzker and W. Jager, Nucl. Instr. and Meth. B39 (1989) 276. [5] H. Vanderstraeten, Y. Bruynseraede, M.F. Wu, A. Vantomme, G. Langouche and J.M. Phillips, Appl. Phys. Lett. 57 (1990) 135. 161 D. Loretto. J.M. Gibson and S.M. Yalisove, Phys. Rev. Lett. 63 (1989) 298. [7] J.C. Hensel, A.F.J. Levi, R.T. Tung and J.M. Gibson, Appl. Phys. Lett. 47 (1985) 151. [8] E. Rosencher. P.A. Badoz, J.C. Pfister, F. Arnaud d’Avitaya, G. Vincent and S. Delager, Appl. Phys. Lett. 49 (1986) 271. [9] L.F. Mattheiss and D.R. Hamann, Phys. Rev. B37 (1988) 10623. [lo] R. Hull, A.E. White, K.T. Short and J.M. Bonar, J. Appl. Phys. 68 (1990) 1629. [ll] J.O. Osenbach, A.E. White, K.T. Short, H.C. Praefcke and V.C. Kannon, unpublished. 1121 A. Schuppen, S. Mantl, L. Vescan and H. Luth, Proc. ESSDERC, Nottingham, UK, 1990. 1131T. Inoue and T. Yoshii, Appl. Phys. Lett. 36 (1980) 64; S.S. Lau, S. Matteson, J.W. Mayer, P. Revesz, J. Gyulai, J. Roth, T.W. Sigmon and T. Cass, Appl. Phys. Lett. 34 (1980) 76; I. Golecki, G. Kinoshita and B.M. Paine, Nucl. Instr. and Meth. 182/183 (1981) 675. (141A.E. White, K.T. Short, R.C. Dynes, J.M. Gibson and R. Hull, Mater. Res. Sot. Symp. Proc. 100 (1988) 3. 1151 K. Maex, A.E. White, K.T. Short, Y.-F, Hsieh, R. Hull, J.O. Osenbach and H.C. Praefcke, J. Appl. Phys. 68 (1990) 5641. Devices, 2nd ed. 1161S.M. Sze, Physics of Semiconductor (Wiley, New York, 1981) p. 156.
VI. HIGH-E/-DOSE
IMPLANTATION
(1991) 693-697
693
North-Holland
Exploiting Si/CoSi JSi heterostructures
grown by mesotaxy
Alice E. White, K.T. Short, Karen Maex ‘, R. Hull, Yong-Fen Hsieh, S.A. Audet, K.W. Goossen, D.C. Jacobson and J.M. Poate AT&T Bell Laboratories,
600 Mountain Avenue, Murray Hill, NJ 07974, USA
Buried single-crystal silicide layers in silicon formed by ion implantation and annealing have many potential applications (some more practical than others!) including metal base transistors (operating at 77 K), buried collector contacts for bipolar transistors, and buried groundplanes for ultrahigh-speed electronics. Fabrication of prototype devices is complicated by the presence of defects in the overlayer silicon, but preliminary results are reported.
1. Introduction Devices incorporating buried metal layers as active or passive elements were proposed over 30 years ago, but materials-related difficulties hampered their development. Now, the ability to grow high-quality (lOO)-oriented Si/metal-silicide/Si heterostructures using ion implantation (mesotaxy [l-5]) means that some of these concepts can be revisited. In particular, we have been investigating three potential applications for these structures: metal base transistors, buried collector contacts for bipolar transistors, and buried groundplanes for microstrip transmission lines. A metal base transistor requires base thicknesses that are less than the electron mean free path for ballistic operation. To make the silicide layers as thin as possible, it is necessary to reduce the straggle of the implant profile as well as the dose. This has been accomplished by reducing the implant energy, but the concomitant reduction in implantation range leaves only a thin Si overlayer. Recently, we demonstrated that an additional overlayer of crystalline Si can be grown on these structures by chemical vapor deposition. Then by carefully choosing a set of implantation parameters for a small extra dose of Si, we can selectively amorphize the Si surrounding the CoSi, allowing a reduction of the defect density in the Si by solid phase epitaxy while retaining the original crystalline quality of the silicide layer. Schottky diodes fabricated on such structures show good characteristics for the back CoSi,/Si interface but not yet for the front. Similar Si/CoSi,/Si structures, which cannot yet be grown by other techniques, may find several uses in integrated electronics. For example, using such a layer
’ Permanent address: IMEC, Leuven, Belgium. O168-583X/91/%03.50
as a buried collector contact for a bipolar transistor should lower the collector series resistance, thereby increasing both the cutoff frequency and the maximum frequency that a bipolar can achieve. In addition, calculations have shown that if such a layer is used as a groundplane in a microstrip configuration, ultrahighspeed signals (100 GHz) can be propagated with far less dispersion than on a standard microstrip. Details of the layer formation have been reported previously [l, and references therein]. Briefly, a high dose of Co+ ions (- 1 X 1017/cm2) is implanted into a silicon wafer that is held at 350 o C to promote dynamic annealing. The energy of the ions determines the depth and the dose determines the thickness of the final layer. After a two-step anneal to 1OOO’C in vacuum the Co coalesces to form a well defined layer of stoichiometric CoSi, buried beneath the surface of the wafer. The Si/CoSi, interfaces are surprisingly abrupt as seen in high resolution transmission electron microscope (TEM) observation and the appearance of a double period reconstruction (first observed in a mesotaxy layer) is evidence for interface quality [6]. The structural integrity of these layers is confirmed by the electrical properties. In particular, the residual resistivity is as low as 2 $4 cm at 7! K, implying an electron mean free path (X) of - 500 A. This suggests the possibility of ballistic transport across the CoSi, layer if it can be made thin enough.
2. Metal base transistor If coherent ballistic transmission of electrons across the metal base of a transistor could be achieved, the device would have the possibility for very-high speed operation. First, however, three conditions must be met [7]: (1) The metal/silicide interfaces must be smooth
0 1991 - Elsevier Science Publishers B.V. (North-Holland)
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A. E. White et al. / Si / CoSi, / Si heterostructures
and parallel to conserve k and obtain high transmission. (2) The Bloch states in the metal and the silicon must line up. (3) The electron mean free path in the metal must be greater than the base thickness at the temperature of operation. Previous work on MBE-grown Si/CoSi z/Si heterostructures in (1 11)-oriented silicon [8] satisfied conditions (1) and (3) but not (2). Calculations have shown that condition (2) is satisfied in (lOO)-oriented heterostructures [9], however. Since (100) structures are difficult to grow by MBE, we thought that this device was an excellent candidate for mesotaxy. The effort has proceeded along two fronts: making thinner CoSi, layers and characterizing the Schottky barrier heights at the Si/CoSi, interfaces. The thickness of the silicide layers can be reduced by lowering the Co dose during the implantation, but there is a threshold peak concentration of Co (- 18 at.%) below which the layer does not coalesce during annealing [l]. This threshold translates into a condition on the “connectedness” of the CoSi, precipitates that are present already in the as-implanted sample [lo]. If these precipitates are touching before the anneals, they fill in to form a well defined layer. If they are isolated, they grow primarily along (111) facets, forming large octahedral precipitates. This transition from layer formation to isolated precipitates occurs over a very narrow dose range, - 10% at 200 keV. To overcome this limitation, the implant energy can be lowered, but eventually the Si surface gets in the way. Nonetheless, layers as thin as 400 A have been created by the mesotaxy technique and there is enough surface Si (300 A) to serve as a seed for epitaxial growth of additional Si. This has been successfully accomplished by conventional chemical vapor deposition (CVD) [ll] as well as by rapid thermal CVD and low-pressure vapor phase epitaxy (LPVPE) [12]. The implantation damage causes defects in the Si above the CoSi, layer and in the substrate directly below the layer that will degrade the performance of devices fabricated in these structures. A technique that has been used to improve the quality of Si on sapphire [13] and Si on buried SiO, layers [14] can also be used in this situation. Implantation conditions for a low dose of Si can be chosen so that the Si directly above and below the CoSi, layer is amorphized, but the crystallinity of the CoSi, layer and of a thin Si surface layer are retained. When the structure is regrown using the Si surface layer and the substrate as a seed, significantly lower defect densities are achieved [15]. To characterize the Schottky barriers, mesa-transistors (- 10e2 cm2) were fabricated in Si/CoSi,/Si heterostructures using standard photolithographic techniques and a combination of reactive ion and wet chemical etching. The emitter contact was produced by a low energy Sb + implant and the backside collector contact was formed by deposition of Sb and laser
V (mv) Fig. 1. I-Vcharacteristic
for a typical collector-base
CoSi,/Si junction. The somewhat noisier trace is the ideality (referenced to the right-hand scale). The Schottky barrier height determined from this measurement was 0.64 eV.
annealing. Emitter-base junctions were non-ideal with a high reverse leakage (7 X 10e4 A) and a Schottky barrier height (determined from a Norde plot) of 0.57 eV. Presumably this low value is due to defects in the overgrown Si. Collector-base junctions had idealities that were about 1.1, lower reverse leakage currents (10m5 to lop6 A), a long linear region in the forward-biased curve, and Schottky barrier heights (determined from the extrapolation of the linear region to zero bias) of 0.64 eV. An Z-V characteristic (with the ideality, n) from a typical junction is shown in fig. 1. The amorphization and regrowth technique was applied to the back interface of a sample which had no Si overgrowth. Compared to a control, the diodes had lower leakage currents (by a factor of 5) and idealities that were either unchanged or closer to 1; however, there were sample-to-sample variations in these quantities as well. So, at the very least, the process did not degrade the diodes. Work on the front interface where the room for improvement is much greater is underway. In summary, CoSi, layers as thin as 400 A can be created in a (lOO)-oriented Si wafer by implantation and annealing as long as the threshold peak concentration for layer formation is exceeded. Vertical transport measurements on mesa-transistor structures give good Z-I’ characteristics for the collector-base junction, but the emitter-base junctions have degraded characteristics, presumably due to the defects in the Si overlayer. An amorphization and regrowth process which retains the crystallinity in the CoSi, layer shows promise for improved electrical performance. Recently the group from Jiilich [12] has reported the first demonstration of a permeable base transistor with a buried CoSi, gate formed by ion implantation in (lOO)-oriented Si. The grating was fabricated by implanting Co through an oxide mask followed by rapid
A. E. White et al. / Si / CoSi, / Si heterostructures
thermal annealing (750°C for 30 s and 1150°C for 10 s). The thick (8200 A) overlayer was grown by LPVPE. Using the back-contact as the source, the transistor characteristics were encouraging, with a breakdown voltage of 8 V. With the back contact as the drain, the breakdown voltage was lower and the range of gate voltages was smaller, but the transconductance was higher, 11 mS/mm. Now that they have demonstrated the feasibility of using a mesotaxy silicide layer in a permeable base transistor, they are working on performing high-frequency measurements and optimizing the device parameters. 3. Buried collector contacts Figures of merit for high-speed bipolar transistors include jr, the cutoff frequency (where the current gain, the maximum oscillation 8, equals I) and f,,,, frequency, (where the unilateral gain equals 1) [16]. These two quantities are related by f,,,, af:/2.The cutoff frequency depends, among other things, on the collector series resistance-capacitance product. The traditional approach to lowering the collector series resistance has been to fabricate the transistor on an epi wafer. This has several disadvantages: it n/n+ results in larger transistor sizes, the lateral diffusion of the n+ layer degrades performance, and autodoping from the n+ layer during Si epi overgrowth limits the minimum epilayer thickness. Using a mesotaxy silicide layer as a buried collector contact should lower the collector series resistance (the CoSi, has a room temperature resistivity of < 20 p0 cm). Furthermore, the stability of the CoSi, means that there will be no lateral diffusion or autodoping problems. Results from a sample device are shown in fig. 2. The 3 in. (100) Si substrate was processed in a standard 500
,
I
I
8
,
I
Fig. 2. Common emitter output characteristics of a bipolar transistor with a buried collector contact made using mesotaxy. The base current is varied from 0 to 60 pA in 20 CA steps. Breakdown occurs at 8 V and fi is 7.5.
695
manufacturing line except for the Co+ implantation and annealing (which was performed in a research laboratory). The definition of the contact area and the formation of the buried silicide layer were done first. Then the contacts were patterned, implanted and diffused to form the bipolar transistor in the standard way. The output characteristics were obtained in the common emitter configuration. The breakdown voltage is 7-8 V and the transistor has a current gain, B, of - 7.5 that is constant with base current. This is a factor of 10 lower than the /3 values for the transistors from a control wafer. Also, these transistors are too leaky to perform high frequency measurements. Both the low gain and the excess leakage are probably due to threading dislocations in the top Si. Although the transistor performance is degraded, the test run provided a demonstration that the mesotaxy silicide layers are stable to processing. Moreover, if there were excess Co in the overlayer Si (in precipitates decorating the dislocations, for example), the devices would not have worked at all.
4. Interconnects for ultrahigh-speed ICs As the switching times of electronic devices become shorter than 10 ps, the role of the interconnect in ultrahigh-speed integrated circuits becomes extremely important. Dispersion occuring along the interconnect can negate the performance of high speed devices after propagation of only a few hundred micrometers. A microstrip is the simplest high-speed interconnect used in integrated circuits, but dispersion of the fundamental mode occurs at 46 GHz. Dispersion could be pushed to higher frequencies by making the substrate thinner, but this results in increased breakage and reduced heat sinking. Calculations predict enhanced performance if the center conductor-groundplane spacing, h, can be reduced, so we have proposed using a buried silicide layer as a ground plane. Dispersion in the transmission line is caused by a change in the phase velocity in the guide with frequency, the effective index of the where ncff, “phase = c/n,,, guide, is midway between the substrate and air at zero frequency and is determined by the number of field lines of the fundamental mode in either at higher frequencies. As the frequency increases, more of the field lines get concentrated in the substrate until, at high frequencies, the index of the guide is equal to the index of the substrate. As a result, a pulse, which consists of a broad spectrum of frequencies, undergoes dispersion. The effective index as a function of frequency for a 10 pm center conductor with three different values of h is plotted in fig. 3. For the standard Si wafer with an Al backplane (h = 500 pm), the change in index from the static value to that of the substrate occurs over 2 decades in frequency, resulting in large dispersion. ReVI. HIGH-E/-DOSE
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INPUT PULSE
100
10’s
10”
4 10’2
AFTER PROPA6ATlND 2
mm
10'3
FR~9UENCY (Hz)
Fig. 3. The effective index of microstrip with a 10 pm wide Al center conductor for three different center conductorgroundplane spacings (h) as a function of frequency.
ducing h pushes the dispersion to higher frequencies and reduces the total dispersion. The higher resistivity of the silicide layer compared to Al means that signals on the buried groundplane microstrip will suffer more loss, but a complete time domain analysis shows that this loss is not severe. This is shown in fig. 4, where a 10 ps signal with a 2.3 ps rise time is sampled after traveling 2 mm along both a standard microstrip and a buried groundplane microstrip. It is clear that the signal on the buried groundplane microstrip has suffered much less dispersion. Although the losses are higher, they are not severe. In contrast, the rise time of the signal on the standard microstrip has increased to 6.6 ps and the signal is highly distorted. The fabrication requirements for the buried groundplane are severe, but we have created several substrates using high energy, high dose implantation of Co+ to make the 3000 A thick layers that are necessary. A cross-sectional TEM view of such a substrate is shown in fig. 5. The implantation was done at 1.5 MeV
0
10
ED
so
1
40
TIME DELAY (DW)
Fig. 4. Results of a calculation for propagation of a 100 GHz pulse 2 mm along a standard microstrip and a buriedgroundplane microstrip.
to a dose of 8.5 x 1017 Co+/cm’. After annealing to llOO°C for 1 h, the Co had coalesced to form a 3000 .& layer of CoSi, buried under 8600 A of crystalline Si. This should serve as an excellent foundation for testing the concept.
5. Summary
The ability to fabricate buried crystalline CoSi, layers in (lOO)-oriented silicon with the mesotaxy technique offers the potential for several novel devices. Although the defect density in the Si overlayer is still a major problem, the feasibility of using these layers has been demonstrated in some preliminary experiments on prototype devices. Mesa-transistors fabricated on thin (700 A) silicide layers have good collector-base junctions but the emitter-base junction is leaky. A bipolar transistor with an implanted silicide layer as a buried
Fig. 5. Cross-sectional TEM micrograph of a buried CoSi, layer fabricated by implanting 8.5 X 10” Coc/cm2 at 1.5 MeV into a (lOO)-oriented Si wafer held at 350°C. The surface of the wafer is indicated by arrows. Similar layers are being used as substrates for microstrip to test the predictions for high-speed transmission.
A. E. White et al. / Si / Co%, / Si heterostructures
collector contact was processed in a standard manufacturing line and had a reasonable breakdown voltage albeit reduced gain. Schuppen et al. [12] have demonstrated a permeable base transistor with a transconductance as high as 11 mS/mm. Calculations show that using a mesotaxy silicide as a buried groundplane for microstrip may reduce dispersion of high-speed electronic signals. As a first step toward demonstration of this design, we have fabricated 3000 A thick silicide layers buried under almost a micrometer of crystalline Si using high-energy implantation.
Acknowledgements Work on the buried collector contacts was performed in collaboration with J.O. Osenbach and H. Praefcke. We have benefitted greatly from technical discussions with R. Tung, M. Green, R.C. Dynes, and W.F. Brinkman.
References [l] A.E. White, K.T. Short, R.C. Dynes,
R. Hull and J.M. Vandenberg, Nucl. Instr. and Meth. B39 (1989) 253. [2] A.H. van Ommen, J.J.M. Ottenheim. A.M.L. Theunissen and A.G. Maiwan, Appl. Phys. Lett. 53 (1988) 669. [3] J.C. Barbour, ST. Picraux and B.L. Doyle, Mater. Res. Sot. Symp. Proc. 107 (1988) 269.
691
[4] K. Kohlhof, S. Mantl, B. Stritzker and W. Jager, Nucl. Instr. and Meth. B39 (1989) 276. [5] H. Vanderstraeten, Y. Bruynseraede, M.F. Wu, A. Vantomme, G. Langouche and J.M. Phillips, Appl. Phys. Lett. 57 (1990) 135. 161 D. Loretto. J.M. Gibson and S.M. Yalisove, Phys. Rev. Lett. 63 (1989) 298. [7] J.C. Hensel, A.F.J. Levi, R.T. Tung and J.M. Gibson, Appl. Phys. Lett. 47 (1985) 151. [8] E. Rosencher. P.A. Badoz, J.C. Pfister, F. Arnaud d’Avitaya, G. Vincent and S. Delager, Appl. Phys. Lett. 49 (1986) 271. [9] L.F. Mattheiss and D.R. Hamann, Phys. Rev. B37 (1988) 10623. [lo] R. Hull, A.E. White, K.T. Short and J.M. Bonar, J. Appl. Phys. 68 (1990) 1629. [ll] J.O. Osenbach, A.E. White, K.T. Short, H.C. Praefcke and V.C. Kannon, unpublished. 1121 A. Schuppen, S. Mantl, L. Vescan and H. Luth, Proc. ESSDERC, Nottingham, UK, 1990. 1131T. Inoue and T. Yoshii, Appl. Phys. Lett. 36 (1980) 64; S.S. Lau, S. Matteson, J.W. Mayer, P. Revesz, J. Gyulai, J. Roth, T.W. Sigmon and T. Cass, Appl. Phys. Lett. 34 (1980) 76; I. Golecki, G. Kinoshita and B.M. Paine, Nucl. Instr. and Meth. 182/183 (1981) 675. (141A.E. White, K.T. Short, R.C. Dynes, J.M. Gibson and R. Hull, Mater. Res. Sot. Symp. Proc. 100 (1988) 3. 1151 K. Maex, A.E. White, K.T. Short, Y.-F, Hsieh, R. Hull, J.O. Osenbach and H.C. Praefcke, J. Appl. Phys. 68 (1990) 5641. Devices, 2nd ed. 1161S.M. Sze, Physics of Semiconductor (Wiley, New York, 1981) p. 156.
VI. HIGH-E/-DOSE
IMPLANTATION