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Exploration of baking temperature effects on 28 nm BEOL reliability
Microelectronics Reliability 72 (2017) 1–4
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Exploration of baking temperature effects on 28 nm BEOL reliability XiangFu Zhao ⁎, Wei Ting Kary Chien Semiconductor Manufacturing International Corp., 18 Zhangjiang Road, Pudong New Area, Shanghai 201203, China
a r t i c l e
i n f o
Article history: Received 20 October 2016 Received in revised form 16 March 2017 Accepted 16 March 2017 Available online 28 March 2017 Keywords: Cu interconnect SM EM ILD
a b s t r a c t The effects of baking temperature on back-end-of-line (BEOL) reliability were explored on 28 nm technology node. We found that stress migration (SM) worse temperature showed up around 200 °C and apparent negative resistance (R) shifts appeared after baking at high temperatures. The Electromigration (EM) performance behaved the temperature dependence and the high baking temperature improved the main time-to-failure (TTF) distribution. Interlayer dielectric (ILD) time dependence dielectric breakdown (TDDB) performance was enhanced at low baking temperatures. © 2017 Elsevier Ltd. All rights reserved.
1. Introduction With the fast development of semiconductor technology, reliability has been widely studied. To shorten product time to market and reduce reliability test costs, a build-in reliability system was announced for fast response, early alarm, and closed-loop control [1]. Under such situation, some new test patterns and test methodologies were developed to improve wafer level reliability control test effectiveness, accuracy, and stability [2]. However, standard test procedures are needed to assess reliability and this is the main concern of customers. As devices shrink into the nanoscale, the interconnect critical dimension (CD) becomes a key index for process engineering because a smaller CD brings higher interconnect resistance. To reduce the RC (resistance-capacitance) delay, copper metallization and low k dielectric materials are comprehensively applied in semiconductor manufacturing [3]. Meanwhile, a smaller interconnect CD also brings variations on BEOL reliability evaluations for its large surface to body ratio, which is very sensitive to interface treatments. It was reported that EM and ILD TDDB lifetimes can be improved through interface engineering [4]; both the line resistance and dielectric breakdown can be affected by interconnect line edge roughness [5]. One of the most important factors that affects interconnect interface characteristics is the temperature. In this paper, the baking temperature was explored on the BEOL reliability. We found that SM showed negative shifts and the EM main TTF distribution improved after high-temperature baking. The ILD TDDB displays a good TTF distribution after low-temperature baking. Our research offers atomistic ⁎ Corresponding author. E-mail address: [email protected] (X. Zhao).
http://dx.doi.org/10.1016/j.microrel.2017.03.019 0026-2714/© 2017 Elsevier Ltd. All rights reserved.
Fig. 1. R shifts of all SM structures for the wafer without baking.
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Fig. 2. The R shifts of all SM structures for wafers after 168-hour baking at different temperatures (a) 150 °C (b)175 °C (c)200 °C (d)225 °C (e)250 °C.
X. Zhao, W.T.K. Chien / Microelectronics Reliability 72 (2017) 1–4
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understandings of the complicated problems caused by the influence of SM and anneal effects in semiconductor BEOL interconnects. 2. Experiments Six wafers were selected for SM reliability evaluations. One control wafer without baking was to monitor the accuracy and precision of the measurement system. The other 5 wafers were baked at 150 °C, 175 °C, 200 °C, 225 °C and 250 °C for 168 h, respectively. Via chains with different metal widths and chain numbers were used to monitor the SM effect. In order to observe the temperature effects, we did EM and ILD tests on the wafers baking at 150 °C, 200 °C, and 250 °C. The ILD TDDB was estimated through Via1 (V1) and Metal 1(M1) combto-comb structures with minimum spaces. EM was evaluated on Via3 downstream (V3D) and upstream (V3U) structures. All test structures were complied with JESD87 standard and the related design rules. 3. Results and discussions Fig. 1 shows R shifts of all SM structures for the wafer without baking. The non-obvious R shift proves a good accuracy and precision of the measurement system. Fig. 2 displays R shifts of the same SM test structures for wafers after 168-hour baking at 150 °C, 175 °C, 200 °C, 225 °C and 250 °C. The largest positive R shift was observed on the wafer baked at 200 °C, which means the worst temperature is around 200 °C. This is consistent with what was mentioned in Ref. [6]. It was reported that there are two competing factors affecting the R shift after baking: one is the SM effect which increases the R shift, and the other is the anneal effect which decreases the R shift [7]. This is because with the same baking time, the higher temperature generates larger grain sizes and thus leads to lower stress-induced void failure rate [8]. When the baking temperature increases close to 200 °C, SM plays the main role. Thus, an obvious positive R shift is observed on the wafer after 168-hour baking at 175 °C. When the baking temperature increases over 200 °C, the anneal effect acts as the dominant role. Thus, apparent negative R shifts were observed on the wafer after 168-hour baking at 250 °C. There are two reasons accountable for the negative R shifts. Firstly, a large negative R shift may be caused by the grain boundaries underneath the via, which results in broken barriers after the SM stress [9]. The second factor is the grain size growth due to the anneal effect [8]. SM and anneal effects can be well observed in Fig. 3, which shows R shift of a representative structure after 168-hour baking at different temperatures. The SM and the anneal effect after baking also have impacts on the EM performance. Fig. 4(a) shows TTF lognormal distribution of V3D after 168-hour baking at 150 °C, 200 °C and 250 °C, respectively. It can be observed that there is no obvious difference for V3D TTF distribution between the wafer without baking and the wafer after 168-hour baking at 150 °C. This phenomenon coincides with the SM results since there is no apparent R shift for the wafer with no baking (shown in Fig. 1) and the wafer after 168-hour baking at 150 °C (shown in Fig. 2(a)). For the wafer after 168-hour baking at 200 °C, V3D TTF lognormal distribution shows the largest sigma value, which means metal or via uniformity is the worst due to the vacancies formed in metal or via by SM after baking (the positive R shift in Fig. 2(c)). However, for the wafer after 168-hour baking at 250 °C, V3D TTF lognormal distribution shows the smallest sigma value, meaning the metal or via uniformity is the best due to the anneal effect after baking (Negative R shift in Fig. 2(e)). Similar results can be found from Fig. 4(b) which shows V3U TTF lognormal distributions of wafers after 168-hour baking at 150 °C, 200 °C and 250 °C, respectively. For ILD TDDB performance after baking, TTF Weibull distributions of V1 and M1 comb to comb structures were shown in Fig. 5(a) and (b). The blue circle with a solid cross line, red circle, solid black dot and solid green triangle represent data measured from wafers without baking, after 168-hour baking at 150 °C, 200 °C and 250 °C, respectively. In Fig. 5(a), we observed that 150 °C baking temperature brings higher ILD TTF slope value, which means that ILD TDDB performance improved by
Fig. 3. The R shifts of a representative structure for wafers after 168-hour baking at different temperatures.
the lower temperature baking. Annealing at a lower temperature can improve the via interface [4], which enhances the ILD TDDB performance. However, when the baking temperature increases, the ILD TTF slope
Fig. 4. TTF lognormal distributions of EM for wafers without baking and after 168-hour baking at 150 °C, 200 °C and 250 °C, respectively (a) V3D (b) V3U.
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Fig. 5. TTF Weibull distributions of ILD comb to comb structures without baking and after 168-hour baking at 150 °C, 200 °C and 250 °C, respectively (a) V1 (b) M1.
degrades because diffusion of the residual ions generated in the process and the barrier/capping layer degradation. Higher baking temperatures accelerate ions diffusions into the dielectric, which degrades the ILD performance even though the via interface is improved under higher baking temperatures. Similar results can be found in Fig. 5(b). 4. Conclusions SM, EM and ILD TDDB performances were evaluated after 168-hour baking at five different temperatures on the 28 nm technology node. We found that SM worse temperature showed up around 200 °C and a higher temperature often results in a negative resistance shift due to the anneal effect. The EM performance was improved after a hightemperature baking due to the better via and metal uniformity after annealing. The EM performance degraded after 168-hour baking at 200 °C because of the vacancies in metal and via caused by the SM effect. The ILD TDDB performance was enhanced by a low-temperature baking as annealing can enhance the via and metal interface. A hightemperature baking degrades the ILD TDDB TTF distribution due to the
ions' faster diffusions into the dielectrics. Our research showed that the 150 °C baking has little effect on the SM and EM performance but improves the ILD TDDB performance significantly. References [1] W.-T.K. Chien, H.-J.C. Huang, IEEE Trans. Reliab. 51 (4) (2002) 469–481. [2] S. Tseng, W.T.K. Chien, W. Wang, A. Zhao, E. Gong, IEEE Annual International Reliability Physics Symposium (2005), 2005 676–677. [3] N. Suzumura, S. Yamamoto, D. Kodama, H. Miyazaki, M. Ogasawara, J. Komori, E. Murakami, IEEE Annual International Reliability Physics Symposium (2008), 2008 138–143. [4] A. Ishii, et al., IEEE International Interconnect Technology Conference (2005), 2005 21–23. [5] F. Chen, et al., IEEE Annual International Reliability Physics Symposium (2008), 2008 132–137. [6] E.T. Ogawa, IEEE Annual International Reliability Physics Symposium (2002), 2002 312–321. [7] X.-F. Zhao, J. Wu, V. Chang, Microelectron. Eng. 129 (2014) 86–90. [8] R. Kitao, K. Noda, E. Nakazawa, Y. Tsuchiya, K. Fujii, IEEE International Interconnect Technology Conference and 2011 Materials for Advanced Metallization (2011), 2011 1–3. [9] X.-F. Zhao, D.-L. Wang, H. Gan, K. Zheng, J. Wu, V. Chang, W.-T.K. Chien, IEEE Annual International Reliability Physics Symposium (2014), 2014 IT.1.1–IT.1.3.
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Exploration of baking temperature effects on 28 nm BEOL reliability XiangFu Zhao ⁎, Wei Ting Kary Chien Semiconductor Manufacturing International Corp., 18 Zhangjiang Road, Pudong New Area, Shanghai 201203, China
a r t i c l e
i n f o
Article history: Received 20 October 2016 Received in revised form 16 March 2017 Accepted 16 March 2017 Available online 28 March 2017 Keywords: Cu interconnect SM EM ILD
a b s t r a c t The effects of baking temperature on back-end-of-line (BEOL) reliability were explored on 28 nm technology node. We found that stress migration (SM) worse temperature showed up around 200 °C and apparent negative resistance (R) shifts appeared after baking at high temperatures. The Electromigration (EM) performance behaved the temperature dependence and the high baking temperature improved the main time-to-failure (TTF) distribution. Interlayer dielectric (ILD) time dependence dielectric breakdown (TDDB) performance was enhanced at low baking temperatures. © 2017 Elsevier Ltd. All rights reserved.
1. Introduction With the fast development of semiconductor technology, reliability has been widely studied. To shorten product time to market and reduce reliability test costs, a build-in reliability system was announced for fast response, early alarm, and closed-loop control [1]. Under such situation, some new test patterns and test methodologies were developed to improve wafer level reliability control test effectiveness, accuracy, and stability [2]. However, standard test procedures are needed to assess reliability and this is the main concern of customers. As devices shrink into the nanoscale, the interconnect critical dimension (CD) becomes a key index for process engineering because a smaller CD brings higher interconnect resistance. To reduce the RC (resistance-capacitance) delay, copper metallization and low k dielectric materials are comprehensively applied in semiconductor manufacturing [3]. Meanwhile, a smaller interconnect CD also brings variations on BEOL reliability evaluations for its large surface to body ratio, which is very sensitive to interface treatments. It was reported that EM and ILD TDDB lifetimes can be improved through interface engineering [4]; both the line resistance and dielectric breakdown can be affected by interconnect line edge roughness [5]. One of the most important factors that affects interconnect interface characteristics is the temperature. In this paper, the baking temperature was explored on the BEOL reliability. We found that SM showed negative shifts and the EM main TTF distribution improved after high-temperature baking. The ILD TDDB displays a good TTF distribution after low-temperature baking. Our research offers atomistic ⁎ Corresponding author. E-mail address: [email protected] (X. Zhao).
http://dx.doi.org/10.1016/j.microrel.2017.03.019 0026-2714/© 2017 Elsevier Ltd. All rights reserved.
Fig. 1. R shifts of all SM structures for the wafer without baking.
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X. Zhao, W.T.K. Chien / Microelectronics Reliability 72 (2017) 1–4
Fig. 2. The R shifts of all SM structures for wafers after 168-hour baking at different temperatures (a) 150 °C (b)175 °C (c)200 °C (d)225 °C (e)250 °C.
X. Zhao, W.T.K. Chien / Microelectronics Reliability 72 (2017) 1–4
3
understandings of the complicated problems caused by the influence of SM and anneal effects in semiconductor BEOL interconnects. 2. Experiments Six wafers were selected for SM reliability evaluations. One control wafer without baking was to monitor the accuracy and precision of the measurement system. The other 5 wafers were baked at 150 °C, 175 °C, 200 °C, 225 °C and 250 °C for 168 h, respectively. Via chains with different metal widths and chain numbers were used to monitor the SM effect. In order to observe the temperature effects, we did EM and ILD tests on the wafers baking at 150 °C, 200 °C, and 250 °C. The ILD TDDB was estimated through Via1 (V1) and Metal 1(M1) combto-comb structures with minimum spaces. EM was evaluated on Via3 downstream (V3D) and upstream (V3U) structures. All test structures were complied with JESD87 standard and the related design rules. 3. Results and discussions Fig. 1 shows R shifts of all SM structures for the wafer without baking. The non-obvious R shift proves a good accuracy and precision of the measurement system. Fig. 2 displays R shifts of the same SM test structures for wafers after 168-hour baking at 150 °C, 175 °C, 200 °C, 225 °C and 250 °C. The largest positive R shift was observed on the wafer baked at 200 °C, which means the worst temperature is around 200 °C. This is consistent with what was mentioned in Ref. [6]. It was reported that there are two competing factors affecting the R shift after baking: one is the SM effect which increases the R shift, and the other is the anneal effect which decreases the R shift [7]. This is because with the same baking time, the higher temperature generates larger grain sizes and thus leads to lower stress-induced void failure rate [8]. When the baking temperature increases close to 200 °C, SM plays the main role. Thus, an obvious positive R shift is observed on the wafer after 168-hour baking at 175 °C. When the baking temperature increases over 200 °C, the anneal effect acts as the dominant role. Thus, apparent negative R shifts were observed on the wafer after 168-hour baking at 250 °C. There are two reasons accountable for the negative R shifts. Firstly, a large negative R shift may be caused by the grain boundaries underneath the via, which results in broken barriers after the SM stress [9]. The second factor is the grain size growth due to the anneal effect [8]. SM and anneal effects can be well observed in Fig. 3, which shows R shift of a representative structure after 168-hour baking at different temperatures. The SM and the anneal effect after baking also have impacts on the EM performance. Fig. 4(a) shows TTF lognormal distribution of V3D after 168-hour baking at 150 °C, 200 °C and 250 °C, respectively. It can be observed that there is no obvious difference for V3D TTF distribution between the wafer without baking and the wafer after 168-hour baking at 150 °C. This phenomenon coincides with the SM results since there is no apparent R shift for the wafer with no baking (shown in Fig. 1) and the wafer after 168-hour baking at 150 °C (shown in Fig. 2(a)). For the wafer after 168-hour baking at 200 °C, V3D TTF lognormal distribution shows the largest sigma value, which means metal or via uniformity is the worst due to the vacancies formed in metal or via by SM after baking (the positive R shift in Fig. 2(c)). However, for the wafer after 168-hour baking at 250 °C, V3D TTF lognormal distribution shows the smallest sigma value, meaning the metal or via uniformity is the best due to the anneal effect after baking (Negative R shift in Fig. 2(e)). Similar results can be found from Fig. 4(b) which shows V3U TTF lognormal distributions of wafers after 168-hour baking at 150 °C, 200 °C and 250 °C, respectively. For ILD TDDB performance after baking, TTF Weibull distributions of V1 and M1 comb to comb structures were shown in Fig. 5(a) and (b). The blue circle with a solid cross line, red circle, solid black dot and solid green triangle represent data measured from wafers without baking, after 168-hour baking at 150 °C, 200 °C and 250 °C, respectively. In Fig. 5(a), we observed that 150 °C baking temperature brings higher ILD TTF slope value, which means that ILD TDDB performance improved by
Fig. 3. The R shifts of a representative structure for wafers after 168-hour baking at different temperatures.
the lower temperature baking. Annealing at a lower temperature can improve the via interface [4], which enhances the ILD TDDB performance. However, when the baking temperature increases, the ILD TTF slope
Fig. 4. TTF lognormal distributions of EM for wafers without baking and after 168-hour baking at 150 °C, 200 °C and 250 °C, respectively (a) V3D (b) V3U.
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Fig. 5. TTF Weibull distributions of ILD comb to comb structures without baking and after 168-hour baking at 150 °C, 200 °C and 250 °C, respectively (a) V1 (b) M1.
degrades because diffusion of the residual ions generated in the process and the barrier/capping layer degradation. Higher baking temperatures accelerate ions diffusions into the dielectric, which degrades the ILD performance even though the via interface is improved under higher baking temperatures. Similar results can be found in Fig. 5(b). 4. Conclusions SM, EM and ILD TDDB performances were evaluated after 168-hour baking at five different temperatures on the 28 nm technology node. We found that SM worse temperature showed up around 200 °C and a higher temperature often results in a negative resistance shift due to the anneal effect. The EM performance was improved after a hightemperature baking due to the better via and metal uniformity after annealing. The EM performance degraded after 168-hour baking at 200 °C because of the vacancies in metal and via caused by the SM effect. The ILD TDDB performance was enhanced by a low-temperature baking as annealing can enhance the via and metal interface. A hightemperature baking degrades the ILD TDDB TTF distribution due to the
ions' faster diffusions into the dielectrics. Our research showed that the 150 °C baking has little effect on the SM and EM performance but improves the ILD TDDB performance significantly. References [1] W.-T.K. Chien, H.-J.C. Huang, IEEE Trans. Reliab. 51 (4) (2002) 469–481. [2] S. Tseng, W.T.K. Chien, W. Wang, A. Zhao, E. Gong, IEEE Annual International Reliability Physics Symposium (2005), 2005 676–677. [3] N. Suzumura, S. Yamamoto, D. Kodama, H. Miyazaki, M. Ogasawara, J. Komori, E. Murakami, IEEE Annual International Reliability Physics Symposium (2008), 2008 138–143. [4] A. Ishii, et al., IEEE International Interconnect Technology Conference (2005), 2005 21–23. [5] F. Chen, et al., IEEE Annual International Reliability Physics Symposium (2008), 2008 132–137. [6] E.T. Ogawa, IEEE Annual International Reliability Physics Symposium (2002), 2002 312–321. [7] X.-F. Zhao, J. Wu, V. Chang, Microelectron. Eng. 129 (2014) 86–90. [8] R. Kitao, K. Noda, E. Nakazawa, Y. Tsuchiya, K. Fujii, IEEE International Interconnect Technology Conference and 2011 Materials for Advanced Metallization (2011), 2011 1–3. [9] X.-F. Zhao, D.-L. Wang, H. Gan, K. Zheng, J. Wu, V. Chang, W.-T.K. Chien, IEEE Annual International Reliability Physics Symposium (2014), 2014 IT.1.1–IT.1.3.