InP core shell nanowire transistor

Journal of Crystal Growth 378 (2013) 511–514

Contents lists available at SciVerse ScienceDirect

Journal of Crystal Growth journal homepage: www.elsevier.com/locate/jcrysgro

Fabrication and characterization of a d-dope InAs/InP core shell nanowire transistor Zhixin Cui a,n, Tomotsugu Ishikura a, Fauzia Jabeen b, J.-C. Harmand b, Kanji Yoh a a b

Research Center for Integrated Quantum Electronics (RCIQE), Hokkaido University, Kita-ku, Sapporo 060-8628, Japan CNRS-Laboratoire de Photonique et de Nanostructures, Route de Nozay, 91460 Marcoussis, France

a r t i c l e i n f o

abstract

Available online 10 January 2013

We report the fabrication and the characterization of a transistor based on modulation-dope (d-dope) InAs/InP core shell nanowire which was grown on InAs (111) substrate by VLS techniques using MBE. The mobility of the core shell nanowire was 13,600 cm2/Vs at room temperature, which is approximately 7-fold increase comparing to the simple InAs nanowire. Estimated mobility at Vds ¼ 0.1 V increased from 13,600 cm2/Vs at RT to 15,600 cm2/Vs at low temperature. A gate voltage dependent crossover from weak-localization to weak-antilocalization was observed. We extracted the spin relaxation length and coherence length using a quasi-one-dimensional model of the conductance. The effectiveness of the InP shell passivation was confirmed. & 2013 Elsevier B.V. All rights reserved.

Keywords: A1. Low dimensional structures A1. Magnetic fields B2. Semiconducting III–V materials B3. Field effect transistors

1. Introduction The rapid progress in vapor–liquid–solid (VLS) nanowire growth by MBE has stimulated the experimental investigations of 1D quantum devices [1]. The length, diameter, growth rate and density of the nanowire can be controlled by the effect of growth temperature, source flux ratio and substrate orientation [2]. InAs nanowire was reported as 1D nanostructure with outstanding promise for device applications because of its high electron mobility [3,4]. Furthermore, InAs is also a good candidate for the spin device channel material because Rashba and Dresselhaus spin orbit interactions (SOI) of InAs are both large and comparable [5]. In the case of Datta–Das spin transistor [6], the electron spins which are injected from a ferromagnetic contact into a semiconductor channel controllably undergo precession during their passage from source to drain by means of the Rashba spin orbit coupling. The relaxation of the spin coherence along the channel is one of the most important issues for the feasible operation of Datta–Das type spin transistor. According to the prediction of reduced spin relaxation in quasi-1D channel [7,8], we investigated the Datta–Das spin transistor based on InAs nanowire 1D channel. However, due to the surface scattering, mobilities of InAs nanowires are substantially lower than the bulk values and the nanowires are fragile to perform stable spin device characteristics. In order to enhance the transport properties, d-dope InAs/InP core shell heterostructure nanowires have been

n

Corresponding author. Tel.: þ81 11 706 7174. E-mail address: [email protected] (Z. Cui).

0022-0248/$ - see front matter & 2013 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.jcrysgro.2012.12.076

grown by the MBE system. Quantum-confined, high-mobility electron carriers and 1D transport properties could be expected in this structure and InP shell protection might lead to enhanced robustness. Fabrications and characterizations of d-dope InAs/InP core shell nanowire transistor were investigated, while enhanced transport properties and robustness of d-dope InAs/InP core shell nanowire were confirmed by comparing with the simple InAs nanowire devices fabricated in parallel. Our studies also aim at confirming 1D transport properties and spin precession behaviors of core shell nanowires, thus magenetoconductance properties such as weak-localization (WL) and weak-antilocalization (WAL) of the same structure transistor devices were observed at low temperature [9,10]. The gate voltage dependence WL–WAL crossover was investigated using a quasi-one-dimensional model. The extracted spin relaxation length (  290 nm) is longer than the previous report [10] which indicates reduced spin relaxation in our core shell nanowires.

2. Experiment The InAs nanowires were grown by the VLS process in a Riber MBE system using Au-colloid seed solution on InAs (111) substrate. As we reported [2], the length and diameter of nanowires were determined by the growth temperature, growth time, In source pressure and As source pressure. After the InAs nanowire was grown, InP shell growth was performed for 2-min followed by a Si–d layer and 2-min growth of InP shell. The InAs/ InP nanowire has a length of  2 mm and a diameter of  40 nm,

512

Z. Cui et al. / Journal of Crystal Growth 378 (2013) 511–514

while the InP shell has a thickness of 6 nm which was confirmed by a TEM (Transmission Electron Microscope). Schematic diagram of the core shell structure is depicted in Fig. 1. Nanowires were dissolved into ethanol solution and dispersed onto an addressed highly doped p-type Si substrate with a 100 nm thick SiO2 layer. Device schematic structure and SEM micrograph are shown in Fig. 2. All of the lithograph patterns were defined by electron beam (EB) lithography and Ti/Au (20 nm/50 nm) were used as contact pads. Nanowire was surface treated in (NH4)2Sx solution [11] to remove the native oxide and a part of InP shell prior to the formation of Ni (70 nm) electrodes without annealing process.

As the reference, we fabricated the same structure devices with simple InAs nanowires whose diameter is 40 nm.

3. Disscussions By characterizing the transistor performances, the electrical transport properties of d-dope core shell nanowire were studied. Room temperature transistor characteristics of a d-dope core shell nanowire device with a diameter of 40 nm and channel length (L) of 1 mm (Fig. 2) are shown in Fig. 3(a) and (b). Both Ids–Vds and Ids–Vgs curves of core shell transistor show stable characteristics compared with the simple InAs nanowire transistor. This is presumably caused by the better InAs surface (InAs/InP interface) in the core shell structure. At a drain-source voltage (Vds) of 20 mV, a peak transconductance (gm) of  0.11 mS/mm and oncurrent of 0.5 mA are able to be recognized from drain-source current (Ids) versus gate voltage (Vgs) data (Fig. 3b). According to FET charge control model, dIds =dV g ¼ g m ¼ mDC ox V ds =L

Fig. 1. Schematic of an InAs/InP nanowire and the corresponding band diagram. Diameter of InAs core is  28 nm and thickness of InP shell is  6 nm.

Fig. 2. (a) Schematic image of the back gate nanowire devices InAs/InP core shell nanowire. Highly doped p-type silicon substrate with 100 nm SiO2 layer was used as address substrate with back gate electrode. Au/Ti pad area and Ni contact part were formed by EB lithography. L is the channel length. Inset is the SEM image of core shell nanowire device. (b) A microscope image of the 4-terminal device for nanowire resistance measurements.

ð1Þ

where m is the mobility, D is the diameter of InAs core and Cox calculated as 257.8 mF/m2 is the dielectric layer capacitance which contains 100 nm SiO2 layer and 6 nm InP shell. In order to calculate the mobility, contact resistances (Rc) were taken into account because the ohmic contact formation in these devices had not been optimized. The two-terminal resistance could be valued from Fig. 3(a) at Vgs ¼0 V which is 50 kO. With a fourterminal device, as shown in Fig. 2(b), we measured the nanowire resistance as  28.1 kO/mm. For this transistor device case which is L¼1 mm and D ¼28 nm, the resistance of nanowire (Rnw) was estimated as 28.1 kO. At Vds ¼20 mV, Vchannel ¼VdsRnw/(Rnw þRc)¼ 11.24 mV was used to replace Vds of Eq. (1) for mobility calculation, while the mobility m was calculated as  13,600 cm2/Vs. For comparison, InAs nanowire devices were also fabricated in parallel with the same device scales whose transistor characteristics were shown in Fig. 3(c) and (d). Comparison of our d-dope InAs/InP core shell nanowire and simple InAs nanowire device gm at Vds ¼20 mV shows an increase for core shell (gm ¼0.11 mS/mm) versus simple nanowire (gm ¼0.04 mS/mm), which corresponds to the enhanced electron mobility. Mobility of InAs nanowire device at Vds ¼20 mV was also calculated to be  1800 cm2/Vs with the same model as Eq. (1). An approximately 7-fold increase of mobility was obtained for core shell InAs/InP nanowire device. Drastically improved mobility is presumably caused by the InP shell passivation which reduced the surface scattering and formed a quantum confined electron gas in the d-dope InAs/InP core shell nanowire heterostructure. The effect of strain to the transport properties cannot be separated from the improved interface effect at the moment. Moreover, the drain-source current degradation during measurements, which is a common phenomenon for the simple InAs nanowire devices, was not observed in InAs/InP core shell nanowire transistors which indicates the enhanced robustness of core shell nanowires. We also investigated the temperature dependence of the d-dope InAs/InP core shell nanowire transistor performance. Ids versus Vgs measurements were carried out at room temperature (RT), 90 K, 25 K and 1.5 K (Fig. 4a). At low temperature less than 90 K, the on current decreased from 2 mA (RT) to 0.9 mA which could be caused by the contact resistance increase. The threshold voltage also shifted 4 V approximately which might reflect a freeze-out of surface states [12]. Mobility at Vds ¼0.1 V of each case was calculated and increased from 13,600 cm2/Vs at RT and then saturated at 15,600 cm2/Vs for the temperature less than 90 K (Fig. 4b). The weak temperature dependence of mobility might reflect the interface scattering domination with such a

Z. Cui et al. / Journal of Crystal Growth 378 (2013) 511–514

513

Fig. 3. (a) and (b) Characteristics of a simple InAs nanowire fabricated in parallel with the same device scales as the core shell nanowire device. (c) and (d) The Ids–Vds and Ids–Vgs of a representative d-dope core shell nanowire device with a diameter of 40 nm (28 nm InAs core) and channel length (L) of 1 mm (Fig. 2).

Fig. 4. (a) The Ids–Vgs characteristics of a representative d-dope core shell nanowire device (Fig. 2) at RT, 90 K, 25 K and 1.5 K. (b) Calculated electron mobility of the representative core shell InAs/InP nanowire device at different temperatures.

narrow InAs core diameter even though the better interface passivation was obtained. In order to confirm 1D transport properties and spin precession behaviors of core shell nanowires, magenetoconductance properties of low magnetic field regime were investigated. Magnetoconductance, offset to zero at the zero magnetic field, at a temperature of 20 K was plotted in Fig. 5 for different gate voltages without smoothing process. The WAL peak at high back gate voltage and a crossover from WL to WAL correction, when the gate voltage is increased, are clearly visible, despite the measurement noise and conductance fluctuations due to a short elastic scattering length. To extract the spin relaxation length (lso) and coherence length (lj), we fitted the correction of the

conductance DG(B) as the solid lines in Fig. 5 by [13,14], 2 !ð1=2Þ !ð1=2Þ 3 2e2 43 1 4 1 1 1 1 5 DGðBÞ ¼  þ 2 þ þ  2 l2 Dc tB hL 2 l2 3lso Dc tB j j ð2Þ with Dc being the diffusion constant and tB the magnetic relaxation time. For large gate voltage, we extracted lso  290 nm and lj  360 nm which are both longer than the previous report [10]. Reduced spin relaxation and enhanced 1D transport properties in our core shell nanowires are presumably attributed to small diameter and the InP shell passivation.

514

Z. Cui et al. / Journal of Crystal Growth 378 (2013) 511–514

current and mobility, suggesting the effectiveness of the InP shell passivation which reduced the surface scattering. Temperature dependence of the d-dope InAs/InP core shell nanowire transistor performance was also investigated by Ids versus Vgs measurements. Decent transport properties and reduced spin relaxation were revealed by extracting lso and lj from a crossover from WL to WAL. In summary, the present InAs/InP core shell transistor is suitable to be applied to spintronic transistor devices.

References

Fig. 5. Magnetoconductance, offset to zero at zero magnetic field, plotted for four different gate voltages at a temperature of 20 K. A crossover from WL to WAL takes place as the gate voltage is increased. Solid lines are fits to Eq. (2).

4. Conclusions By comparison with simple InAs nanowire devices fabricated separately, superiority of core shell samples were verified in drain

[1] L. Samuelson, et al., Physica E 25 (2004) 313–318. [2] J. Bubesh Babu, Kanji Yoh, Journal of Crystal Growth 322 (2011) 10–14. [3] Shadi A. Dayeh, David P.R. Aplin, et al., Semiconductor Science and Technology 25 (2010) 024004. ¨ [4] Tomas Bryllert, Lars-Erik Wernersson, Linus E. Froberg, Lars Samuelson, IEEE Electron Device Letters 5 (2006) 323–325. [5] T. Matsuda, Kanji Yoh, Physica E 42 (2010) 979–983. [6] S. Datta, B. Das, Applied Physics Letters 56 (1990) 665. [7] J. Schliemann, J.C. Egues, D. Loss, Physical Review Letters 90 (2003) 146801. [8] R. Winkler, Physical Review B 69 (2004) 045317. ¨ [9] A.E. Hansen, M.T. Bjork, C. Fasth, C. Thelander, L. Samuelson, Physical Review B 71 (2005) 205328. [10] P. Roulleau, T. Choi, S. Riedi, T. Heinzel, I. Shorubalko, T. Ihn, K. Ensslin, Physical Review B 81 (2010) 155449. ¨ [11] D.B. Suyatin, C. Thelander, M.T. Bjork, I. Maximov, L. Samuelson, Nanotechnology 18 (2007) 105307. [12] C.H. Liu, et al., Japanese Journal of Applied Physics 41 (2002) 2423. [13] B.L. Altshuler, et al., JETP Letters 33 (1981) 499. [14] C. Kurdak, A.M. Chang, A. Chin, T.Y. Chang, Physical Review B 46 (1992) 6846.