Fabrication and characterization of low-cost ultrathin flexible polyimide interposer

Microelectronics Reliability xxx (2015) xxx–xxx

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Fabrication and characterization of low-cost ultrathin flexible polyimide interposer Yu-Jung Huang a,⇑, Ming-Kun Chen b, Yi-Lung Lin b, Shen-Li Fu a a b

Department of Electronic Engineering, I-Shou University, Kaohsiung, Taiwan ASE Test, Inc., 10, west 5th street N.E.P.Z., Kaohsiung, Taiwan

a r t i c l e

i n f o

Article history: Received 9 January 2015 Received in revised form 29 May 2015 Accepted 29 May 2015 Available online xxxx Keywords: Interposer Flexible substrate Semi-additive process

a b s t r a c t A passive interposer, which is a way to bridge the feature gap between the integrated circuit (IC) and the package substrate, is a key building block for high performance 3-D systems. In this paper, polyimide (PI) is proposed as an alternative to glass and silicon based interposers for cost-effective 2.5-D/3-D IC integration. The development of interconnect technology using an ultrathin flexible polyimide interposer (UFPI) for 2.5-D/3-D packaging applications is described in detail. A semi-additive process consisting of copper seed layer deposition, photolithography, and electrolytic copper pattern plating is used for fabricating a double-sided flexible fan out interposer. A UFPI with electrodeposited micro-scale copper (Cu) fine patterns and laser drilling microvia is investigated using a scanning electron microscope (SEM), energy-dispersive spectrometry (EDS), X-ray spectrometry, and an optical 3-D profilometer. The UFPI with fine pitch on 12.5 lm thin PI substrates has been demonstrated. The result is a proof-of-concept to exploit the opportunities of cost-effective 2.5D flexible interposer production. Ó 2015 Elsevier Ltd. All rights reserved.

1. Introduction The performance and productivity of microelectronics has increased continuously over the last four decades due to the enormous advances in photolithography, wafer size, process technology, and devices. The semiconductor industry, through transistor scaling, can obtain a better performance-to-cost ratio for products, which has led to exponential growth in the semiconductor market [1]. This has led to the development of technologies that allow the ultra-miniaturization of electronic systems. However, the performance improvement gained in transistor scaling is insignificant compared to the negative effects of interconnect scaling [2]. The delay of global interconnects increases with technology scaling [3]. The International Technology Roadmap for Semiconductors (ITRS) roadmap predicts that three-dimensional (3-D) integration will be a key technique in overcoming this ‘‘wiring crisis’’ [4]. 3-D technology, an alternative solution for the scaling problems, is a well-accepted approach for ‘‘More than Moore’’ applications. 3-D integration is generally defined as fabrication of stacked and vertically interconnected device layers. In 3-D integration, the silicon interposer and the through-silicon-via (TSV) are the primary enablers that can achieve higher electrical performance ⇑ Corresponding author. E-mail addresses: [email protected] (Y.-J. Huang), [email protected] (M.-K. Chen).

through shorter interconnect architectures with stacked dies [5– 7]. Instead of stacking the dies on top of each other, the interposer-based interconnection technologies, the 2.5-D ICs, allow the integration of active dies and/or heterogeneous functions with package substrates. The interposers aim to replace the traditional printed circuit board (PCB) laminate or ceramic technologies for the sake of extreme miniaturization and performance. This interposer can be made of ultrathin silicon, glass, or even organic substrate [8,9]. However, a silicon substrate cannot be utilized as a medium for signal transmission, as the interconnects on the silicon substrate suffer from substrate losses caused by the penetration of the electric and magnetic field. Glass has many advantages as an interposer material over silicon, such as the ultra-high resistivity and its availability in thin and large sizes. Glass has been studied as an interposer material, with the main focus on metalized through-glass-via (TGV) in thick glass substrates using laser ablation [10]. Polyimide (PI) films have a high degree of thermal stability, which enables them to withstand processing at elevated temperatures. Because their coefficient of thermal expansion (CTE) is close to copper over a fairly wide temperature range, the mechanical stresses induced in copper during thermal excursions are minimized [11]. In terms of the mismatch in the CTE, silicon is attractive because of its CTE matching that of integrated circuit chips (3  106 K1). For most polyimides, their CTE values are in the

http://dx.doi.org/10.1016/j.microrel.2015.05.017 0026-2714/Ó 2015 Elsevier Ltd. All rights reserved.

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range of 10–40 ppm/°C [12,13]. Since the thermal stresses are largely driven by CTE mismatch, this is of great importance. The CTEs of polyimides have been lowered in the past by linearizing the polymer molecular structure or by controlling the orientation of the polyimide film [13]. Many of the new Pls have been synthesized to have CTE values less than 10 ppm/°C [13,14]. A polyimide chemistry has been identified which allows for a significant lowering of the CTE can be achieved [13,14]. Hence there is a strong motivation to match the CTE of PI to that of silicon. An interposer-based 2.5D-IC can achieve a more compact semiconductor package configuration. It also raises challenges related to thermal management, as it may be quite difficult to control the operating temperature of semiconductor dies mounted beneath the interposer due to space and/or airflow limitations. Typical thermal management solutions use some combination of aluminum or copper heat sinks, fans, thermal spreaders/heat pipes, and thermal pastes or adhesives (Thermal Interface Materials or ‘‘TIMS’’) to form a low thermal resistance path between the semiconductor chip and the ambient. Another conventional technique for providing improved thermal management is the use of micro-channels. This results in an array of micron-sized rectangular tubes through which a cooling liquid is forced so as to provide for dissipating the heat generated within the integrated circuit chip. The microchannel heat sink using carbon nanotubes (CNTs) for applications as TIMS was reported in [15]. Materials with lower dielectric constants in the wiring substrate become key factors for raising system performance, since a material with a lower dielectric constant allows faster transmission signals. In addition, reduction of the wiring delay depends mainly on the reduction of the electric capacitance of the wiring; thus, a fine signal line and a low dielectric constant material are required. The dielectric constant for PI is between 2.8 and 3.2 [16], which is less than that of Si and glass materials [17]. PI appears to be a strong candidate to meet the above demand, since it has a lower dielectric constant, the capability of high density, and finer signal pattern formation due to its smooth surface [16]. The metallization of PIs has therefore been the subject of intense study in recent years [18]. Copper (Cu) has attracted much attention for application in the interconnections of integrated circuits (IC) as a replacement for aluminum, due to its lower resistivity and high electro-migration resistance. However, a copper foil with large surface roughness that uses the conventional subtractive process is too rough to fabricate the interconnections without bridge faults. This is because rough Cu foil surfaces are difficult to fine pattern with the conventional etchants process [19]. The conventional subtractive method is cost-effective and the most widely used method in Cu line formation. However, the lateral etching of copper results in a trapezoidal shape effect, which causes a serious problem in the subtractive method. In order to produce the increasingly narrow line widths and spacing (L/S) required in the 2.5-D interposer, a shift from subtractive techniques to the semi-additive process (SAP) is being driven by the inherent limitations of etch resolution in the subtractive processes. For minimizing the size of the device, the realization of metallization lines at a scale of a few micrometers on the flexible substrate is very important. In this paper, the electro-deposition of fine pitch Cu lines on an ultrathin flexible polyimide interposer (UFPI) using the SAP is presented. The objective of this study is to investigate the effects of applying electroforming to metalize UFPI surfaces with Cu, since this processing technique is inexpensive and can treat large areas. The micro-scale fine pattern Cu metallization process on UFPI is described. An optical profiler is used to analyze the 3-D surface profile of Cu foil to subsequently determine its roughness and thickness with high accuracy. The rest of this paper is organized as follows. Section 2 describes the design and fabrication process of the ultrathin flexible polyimide interposer. The

characterization of the UFPI is presented in Section 3. Finally, discussion and conclusions are drawn in Section 4.

2. Design and fabrication process The interposer is fabricated on polyimide substrates, including the PI base film, a Cu seed coat layer, and a layer of electrodeposited copper. Microvias were drilled with ultraviolet (UV) (Nd:YAG) lasers and metallized using an SAP with a pattern plating process [20]. These fine pitch patterns were fabricated using photolithographic techniques for fine pattern generation, vacuum evaporation techniques for seed layer formation, and special electro-deposition methods for the copper build-up process. Taiflex PI was chosen as the flexible substrate since it exhibits a good balance of physical, chemical, and electrical properties with a low loss factor over a high speed range. Taiflex PI offers a very low profile while being very robust, with a peel strength of 0.7 kgf/cm and an insulation resistance of 10+15 X cm. The flexible Cu-coated PI substrate was composed of 12.5 lm of a polymerized PI layer with a size of 2 cm  3 cm. The PI substrate was baked on a hot plate for 10 min at 110 °C to remove any surface-absorbed moisture. The PI substrate was ultrasonically cleaned using ethanol and then rinsed with deionized (DI) water and dried with nitrogen gas. Fig. 1 schematically illustrates the experimental procedures for a double-sided UFPI with laser-drilled microvias. The PI substrates are mounted on a carrier plate for further processing as shown in Fig. 1(a). Microvias were drilled with ultraviolet (UV) (Nd:YAG) lasers as indicated in Fig. 1(b). To overcome the disadvantages of subtractive etching, an SAP with a pattern plating process was designed. The key steps in SAP used in this research including (i) Cu seed layer formation (ii) photolithography (iii) copper electroplating (iv) photoresist stripping and seed layer removal process. Fig. 1(c)–(m) illustrates the process sequence. The thermal evaporator consists of a vacuum chamber. Vacuum is created using mechanical and diffusion pump. The pressure inside the chamber is maintained in the order of 106 Torr. The resistive evaporation is accomplished by passing a large current through a resistive element containing the material to be deposited. The current values for the seed layer deposition are 60 A. The deposition rate can be increased by increasing the current. The typical deposition rate is 3–5 Å. A seed layer of 200 nm Cu was deposited on the surface of the PI substrate using a thermal-evaporation process without a catalyst or pre-deposited buffer layers. The purpose of the Cu seedcoat is to provide sufficient electrical conductivity to permit electroplating to the final Cu thickness. Next, the interconnect routing patterns on the interposer were generated using standard photolithographic techniques. The substrate was spin-coated with AZ4620 photoresist (PR) at a spin speed of 3000 rpm (RPM) for 30 s to give a thickness of about 6 lm before baking. The photoresist-coated substrate was then soft baked at 90 °C for 3 min and subsequently exposed through the photomask with a dose of UV illumination of 350– 450 nm wavelengths at 100 mJ/cm2 intensity. Then the photoresist was developed in the desired pattern in the developer solution by mixing 1 part AZ 400 K developer with 3 parts DI water for about 5 min. In the electroplating process, the Cu trace plating solution is based on Cu sulfate dissolved in dilute sulfuric acid. To obtain Cu layers with a 2–15 lm thickness, the current was varied in the range of 2–10 mA and the plating time was controlled in the range of 200–1000 s. A stirring hot plate for simultaneous heating and stirring was used to mix the plating solution during the electroplating. The agitation effect can prevent non-uniformity in the thickness of the deposit layer. First, Cu electroplating was performed to fill the microvia. Following the via-filling process, the

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Y.-J. Huang et al. / Microelectronics Reliability xxx (2015) xxx–xxx PR

S1818

Carrier

(k) Electroforming

(a) Pi Carrier Laser PI

(b) Laser drilling

(l) Remove PR Seed layer PI

(m) Remove Seed layer

(c) Evaporation PR

PI

(d) Spin Coating UV

UV

UV

(n) Flip over Seed layer

Via Mask

(o) Evaporation

(e) Exposure

PR

(p) Spin Coating

(f) Development Cu

PR

UV

UV

UV

Mask PR

UV

(g) Electroforming

(q) Exposure

(h) Remove PR

(r) Electroforming

(i) Flatten

(s) Remove PR

UV

UV

Mask PR

(j) Exposure

(t) Remove Seed layer

Fig. 1. A Schematic illustration for the fabrication processes flow of a double sided UFPI with laser drilled microvias.

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spin-coating, photolithography steps, and Cu electroplating process were repeated to fabricate the interconnection pattern on the front and the back of the UFPI as shown in Fig. 1(n)–(t). A double-sided interposer has been designed, and it can be used for converting a fine pitch to a larger pitch or for connecting active dies on both sides for 3D IC integration applications. The diameter of the via is 20 lm. The interposer layout designs for the front and back are shown in Fig. 2(a) and (b), respectively. Both of the front and back redistribution layers can be used for connecting the chip to the interposers. In addition, it can be used for single and multi-die fan-out package platforms. Within the interposer, the signals are distributed and fanned-out to a large area array. The PI-based interposer is designed to meet the requirements of fan-out for a 50 lm pitch I/Os to a larger pitch that is suitable for larger, thicker substrate/board connection. The designed interconnection patterns on the mask were transferred to both sides of the UFPI using the fabrication processes described in Fig. 1. After the conductive pattern on the seed layer has been formed, the final copper build-up is done using the electroplating process. In addition, the final Cu trace thickness can be tailored to the application needs, and it can be different on the two sides of the UFPI. 3. Interposer characterization A 3-D Zygo surface profiler (Zygo NewView 7300), which uses the white light interferometry technique to produce a 3-D topographical map, is used to verify the experimental results obtained in this study. The data obtained from the 3-D Zygo surface profiler can be used to characterize and quantify the roughness of the surface specimen. Typically, the output roughness parameters of a 3-D profilometer are PV, Ra, and Rrms. PV is defined as the mean peak-to-valley amplitude. Ra is the arithmetic average deviation from the mean line within the assessment length l. The formula usually adopted for the Ra is given by [21]:

Ra ¼

1 l

Z

x¼l

jyðxÞjdx

ð1Þ

x¼0

where j j indicates that the sign is ignored and y(x) is the profile measured from the mean line at position x.

Rrms is the root mean square (rms) value corresponding to the Ra. The Rrms value can be calculated as shown below.

Rrms

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Z 1 x¼l ¼ yðxÞ2 dx l x¼0

ð2Þ

The measurements were taken in several different positions to ensure the desired fine pitch patterns of UFPI following the fabrication process. Fig. 3(a) shows the 3-D Zygo surface profiler’s front view of the UFPI layout in Fig. 2(a). 3-D laser confocal microscopy was also used to analyze the front and back conductive patterns on the UFPI interposer. As shown in Fig. 3(b), the depth profiles indicate the average thickness of the Cu trace was 6 lm and the average pitch was 50 lm. The fanout pattern shown in Fig. 2 has different pitch spacings between adjacent traces. After examining the height of the Cu traces, a Scanning Electron Microscope (SEM) was used to observe the shape of the traces. The electrodeposited Cu traces were characterized by a 2400 magnification environmental scanning electron microscope (E-SEM) coupled with energy-dispersive spectroscopy (EDS). The E-SEM image of electroplated Cu traces on UFPI is shown in Fig. 4. The incorporation of Cu in the electroplated Cu surface was verified by the presence of the Cu peak in the EDS spectrum, as indicated in Fig. 5. According to the IPC test method [22], Cu foil profiles can be characterized using an Ra (or Rz) parameter. The laser-drilled vias and the surface quality of the UFPI were further examined using a 3-D Optical Surface Profiler. The cross-sectional profile of the laser-drilled via is shown in Fig. 6. It has a top via diameter of 21 lm, a bottom via diameter of 18 lm, and a depth of 15 lm. After Cu filling, a top view profile of the Cu-plated via after polishing is shown in Fig. 7. The average surface roughness of the Cu-plated via is 0.6 lm. Various samples were measured to characterize the quality of the trace surface. The roughness profile results of the UFPI interconnection obtained by the proposed method are shown in Fig. 8, where the PV was found to be 1.236 lm with an Ra value of 0.164 lm. The deposited Cu thickness proved to be linear as a function of the deposition time, with zero incubation time at 50 °C

(a)

(b)

Fig. 2. Schematic illustrations of the conductive patterns on the UFPI. (a) Front view. (b) Back view.

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Fig. 3. Surface characterization. (a) 3-D Zygo surface profile. (b) Depth profiles with laser confocal microscopy.

temperatures, and the agitation speed of 50 rpm. The general calculation of the current density in the plating operation will depend on the power supply, plating pattern, plating cell geometry. In the electroplating process, cathode current density must be held within the proper interval with respect to bath composition and temperature. Insufficient current for given task will result in poor coverage of recesses/vias. Low current densities tend to result higher impurity presence in the deposits. Excessively high current densities also produce dull or burned plate. The optimum current density range for given plating bath is depending on composition, operating conditions and the type of the plating sought. Form our previous failure analysis, it was found that 3–5 amps per square decimeter (ASD) is within our optimum current density range for present experimental set-up [23]. Fig. 9 shows the thickness and roughness of the Cu-plated interconnection traces at room temperature under 3 ASD of direct

Fig. 4. E-SEM image of electroplated Cu traces on UFPI.

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current (DC). A good prediction of deposited Cu layer thickness on the PI surface is of prime importance for the reliability of the interconnection. The film growth (thickness) was observed to be linear with plating time. As shown in Fig. 9, the equation of the least square regression line for predicting deposited thickness from plating time is y = 0.0104x + 0.75. For roughness estimation, the least square regression analysis shows y = 0.0012x + 0.55. The corresponding R square values for prediction of thickness and roughness are 0.9918 and 0.9888, respectively. The morphology became rougher as the plating time increased. The Ra of the 800 s under 3 ASD was 1.5 lm. A Cu seed layer provides nucleation sites for the formation of a continuous film. Cu growth progressed three-dimensionally. The higher the film thickness the more large grains exist due to coarsening effects. It was reported that the increase in surface roughness of the films was due to increasing average grain size or the intersection of grain boundaries [24]. In general, grain boundaries (GBs) can be transparent for surface diffusing atoms or introduce a diffusion barrier, which we call the GB crossing barrier. Both this barrier and the initial equilibrium grain shape with a groove at the root of the GB cause a termination of the flowing steps at the position of the GBs. This effect leads to mound formation, thereby increasing the overall film roughness [25]. This roughness evolution is accompanied by changes in both the grain orientations and the average grain size. As the grain diameter increases, so does the height variation on each grain. This leads to a gradual increase in film roughness, which is proportional to the average grain diameter. The electrical characteristics of plating metallic Cu films were measured using a commercial Agilent 34401 multimeter, HP 6177C DC current source, and the four-point probe station. The electrical resistivities of metallic Cu films on UFPI as a function of plating thickness are depicted in Fig. 10. The resistivity of the electroplated Cu films was about 1.9–2.0 lX cm when the thickness of the electroplated Cu films exceeded 0.5 lm [26]. The resistivity of Cu film decreases when the electroplated Cu film thickness is increased to 3 lm. At a thickness larger than 1.45 lm, the saturation resistivities 1.9 lX cm, which is close to the resistivity of bulk Cu  1.76 lX cm. The resistivity measurements for Cu films and wires are discussed within the theoretical framework by Fuchs [27] and Sondheimer [28] for electron scattering at surfaces and by Mayadas and Shatzkes [29] for electron scattering at grain boundaries. As the film thickness decreases and approaches its mean free path, the film resistivity increases due to an increased relative contribution from surface scattering. If the metal film has polycrystalline grains, then electrons scattering from grain boundaries contribute to further increases in resistivity. The resistivity of electroplated films is found to increase with thinner layers. It has been shown that this depends on grain-boundary scattering,

Fig. 5. EDS counting spectrum for the electroplated Cu measured at the mark position in the inset.

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Fig. 6. Top view profile of the laser-drilled via taken by a Zygo surface profiler.

Fig. 7. Top view profile of the Cu plated via after polishing.

Fig. 8. Roughness image of the UFPI sample obtained with an optical profilometer.

thickness

roughness

least square fit (roughness)

least square fit (thickness)

10 8

2.1 7.1

7 6

Resistivity (μΩ-cm)

Thickness/Roughness (μm)

8.9

y = 0.0104x + 0.75 R² = 0.9918

9

5.2

5 4 2.6

3 2

0.8

1

1.2

1

y = 0.0012x + 0.55 R² = 0.9888 1.5

2.04

2.05 2

1.94

1.95

1.93

1.91

1.9

1.91 1.915

1.85 1.8 1

0 0

100

200

300

400

500

600

700

800

900

1.5

2

2.5

3

3.5

4

Thickness (μm)

Plating time (s) Fig. 9. Variation of the copper thickness and surface roughness under 3 ASD.

Fig. 10. Resistivity of electroplated Cu films as a function of electroplating time @4.6 ASD.

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Fig. 11. The two-Cu-metal layer prototype of bendability UFPI with Cu interconnection.

where the grains grow in size approximately proportional to the layer thickness [30]. An optical image of the two-Cu-metal layer prototype of bendable UFPI after fabrication is shown in Fig. 11. The use of Cu layers on ultra-thin PI enabled defect-free handling of UFPI even at a thickness of 20 lm.

4. Discussion and conclusions The 2.5D interposer is the key enabling technology for integrating multi-functional dies to achieve higher electrical performance and smaller package form factors. Silicon interposers are being developed widely around the globe. However, the silicon interposer is a costly technology because of expensive wafer-level back end of line (BEOL) facilities, tools, materials, and processes. The difficulties associated with precisely thinning a silicon substrate down to a thickness of 100 lm or less are manifold. First, the thinning process is time-consuming and costly, typically involving multiple steps, including grinding, chemical–mechanical polishing, and silicon etching. Second, the thinning process is difficult to control, since the actual thickness of the silicon substrate is difficult to determine accurately while material is being removed therefrom. Third, handling silicon substrates thinned to 100 lm or less without cracking the substrate is challenging. The UFPI of the present study has lower material costs and uses more common and lower cost processing equipment. In addition, the electrolytic plating method has a significant advantage in terms of cost-effectiveness with large-volume production. Among performance and cost issues, most of the technologies focus on the smallest footprint or chip/package area ratio. In fact, 3D package thinning is one of the key factors for further reduction of the package height. The proposed UFPI allowed further reduction in the size and weight of 3D package systems. The main feature of this technology is that the conductor lines on the UFPI are prepared using the SAP. The dependence of the surface roughness on the deposited layer thickness was analyzed using least square fit method. These results imply that an increase in the average grain size results in a rougher surface. The grain size is known to be a non-linear function of the film thickness. This relationship is especially important in modern integrated circuit devices having sub-micrometer, high-aspect ratio contact openings, where electron scattering effects can significantly contribute to the series resistance of metal interconnects. The most studied electron scattering mechanisms that lead to the size effect in Cu are (1) scattering at external surfaces or interfaces, which causes an increase in the resistivity of interconnect lines as the thickness and/or the line width decrease; (2) scattering at grain boundaries, which typically

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increase in density with decreasing film thickness; and (3) surface roughness, which reduces the effective cross-sectional area of interconnect lines. The grain boundaries play an important role in the evolving film structure, as they initiate mound formation, thereby significantly increasing the film roughness. The grain boundary scattering also plays a decisive role in the resistivity behavior of the electroplated Cu films. A good surface uniformity of plated Cu films with fine pitch patterns was successfully fabricated on UFPI and characterized by SEM, EDS, and 3-D topography maps. The deposition rate of Cu film on UFPI based on the plating current and plating time is set as a guideline for reliable generating fine pitch patterns. In addition, the process presented in this work is very useful, since the Cu thickness can be tailored to the application need. One of the possible solutions to improve the low thermal conductivity of polyimide is implementation of an ultra-thin heat sink using carbon nanotubes (CNTs) as micro cooling fins attached directly onto the UFPI. In summary, a cost-competitive processing sequence for the preparation of UFPI used for 2.5-D/3-D integration applications was developed and experimentally evaluated. Acknowledgment This work was supported in part by the Ministry of Science and Technology under Grants MOST 103-2221-E-214-054-MY2. References [1] Cavin RK, Lugli P, Zhirnov VV. Science and engineering beyond Moore’s law. Proc IEEE 2012;100(special centennial issue):1720–49. [2] Ho R, Mai KW, Horowitz MA. The future of wires. Proc IEEE 2001;89(4):490–504. [3] Ho PS, Smith L, Tong HM, Zschech E. Forward to the special section on materials, processing, and reliability of 3-D interconnects. IEEE Trans Dev Mater Reliab 2012;12(2):188. [4] International Technology Roadmap for Semiconductors; 2011 ed. . [5] Garrou P, Bower C, Ramm P. Handbook of 3D integration: technology and applications of 3D integrated circuits. Wiley-VCH; 2008. [6] Beyne E. Through-silicon via technology for 3D IC in ultra-thin chip technology and applications. Springer; 2011. p. 93–108. [7] Liu X, Chen Q, Sundaram V, Tummala RR, Sitaraman SK. Failure analysis of through-silicon vias in free-standing wafer under thermal-shock test. Microelectron Reliab 2013;53(1):70–8. [8] Zhang R, Lo JC, Lee S. Design and fabrication of a silicon interposer with TSVs in cavities for three-dimensional IC packaging. IEEE Trans Dev Mater Reliab 2012;12(2):189–93. [9] Sukumaran V, Bandyopadhyay T, Sundaram V, Tummala R. Low-cost thin glass interposers as a superior alternative to silicon and organic interposers for packaging of 3-d ics. IEEE Trans Compon, Pack Manuf Technol 2012;2(9):1426–33. [10] Schroder H, Brusberg L, Erxleben R, Ndip I, Topper M, Nissen N, Reichl H. Glasspack—a 3d glass based interposer concept for sip with integrated optical interconnects. In: Electronic components and technology conference (ECTC), 2010 Proceedings of 60th IEEE; 2010. [11] Bergstresser TR, Sallo JS. Adhesiveless copper on polyimide for flexible circuit, hdi and microvia applications. In: Proceedings of the IPC 5th annual flexible circuits national conference. Denver, CO; 1999. [12] Myung BY, Ahn CJ, Yoon TH. Synthesis and characterization of polyimides from novel 1-(30 ,50 -bis(trifluoromethyl)benzene) pyromelliticdianhydride (6FPPMDA). Polymer 2004;45:3185–93. [13] Numata S, Kinjo N, Makino D. Chemical structures and properties of low thermal expansion coefficient polyimides. Polym Eng Sci 1988;28(14):906–11. [14] Merriman BT, Craig JD, Nader AE, Goff DL, Pottiger MT, Lautenberger WJ. New low coefficient of thermal expansion polyimide for inorganic substrates. In: Proceedings of 39th ECC; 1989. p. 155–9. [15] Yao Y, Tey JN, Li Z, Wei J, Bennett K, McNamara A, et al. High-quality vertically aligned carbon nanotubes for applications as thermal interface materials. Trans Compon, Pack Manuf Technol 2014;4(2):232–9. [16] Ahmad Z, Polymer dielectric materials. In: Marius Alexandru Silaghi editor. Dielectric material; 2012. . [17] Mittal KL. Metallized plastic: fundamentals and applications, vol. 43. CRC Press; 1997. [18] Vecherkina E, Kudaikulova S, Iskakov R, Zhubanov B, Voitekunas V, Abadie J. Metallized polyimide films: metallization and mechanism of the process. Polym Sci Ser A 2007;49(2):142–7.

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Please cite this article in press as: Huang Y-J et al. Fabrication and characterization of low-cost ultrathin flexible polyimide interposer. Microelectron Reliab (2015), http://dx.doi.org/10.1016/j.microrel.2015.05.017