Fabrication compatibility of integrated silicon smart physical sensors

Sensorsand Achutom A, 41-42 (1994) 11-28

11

Fabrication compatibility of integrated silicon smart physical sensors* R.F Wolffenbuttel Lubomtoryfor ElectromcInmunentatwn,Departmentof ElectncolEngzmmn&De& Unrwrsttyof Techno~, 2628 CD De& {Netherlands)

Mekehveg4,

Abstract

Integrated sd~con smart sensors are complete data-acquwtlon systems on a single slhcon chip The celebrated matenal compatlbtity of sillcon sensors with rmcroelectromc clrcmts m &con 1s a necessary but msufficient prerequisite for such an mtegratlon The essential issue IS rather the fabncatron compatiidlty of the sensor, sensor-related analog mnzroelectromc circuits and d@al mterface clrcmts Fabncahon compatrblllty mcludes mergmg of sensor processing wth analog and drgtal mlcroelectromc nrcurt processmg, both on the wafer level, m terms of doping profile, thermal budget and equipment utlhzatlon, and on the die level, wth respect to testmg, dsmg, bonding and packagmg The mncentrves, opportumtles and problems m mergmg sensor processes with a typical standard bipolar process are discussed In some applications the structures to be merged are fundamentally fabncatlon mcompatible Special post-processing steps are available that eltber extend the capablhtles of the bipolar process, such as selective epltaxlal growth and epltaxlaf lateral overgrowth, or allow the fabncatloncompatiblhty problem to be postponed unhl the bondmg phase, such as wafer-to-wafer bondmg and fhp-ciup bonding Fmally, the economics of Integrated silicon smart sensors are mvestlgated The shortcommgs of the conventmnal approach adopted from the microelectromcs industry and armmg solely at die-area rnimmlzaUon, whenever possible for the sake of yield m mass production, are Identified tn ylew of fabncahon compatl%lhty, production volume and costs of testmg and packagmg. Moreover, the discrepancy between the prune motlvafion for fabncatmg Integrated sdlcon smart sensors, namely enhancmg the level of abstractlon of the complete dataacqulsitlon unit and ita reahzatlon on the smallest possible matenal tamer, the chop, m order to nnprove user fnendlrness and mamtamabdlty m an effort to gam market acceptance, versus the hmltatlon of functional complex@ unposed by die-area economics IS discussed

introduction

A sensor is part of a data-acqutsltlon system, which 1s m turn part of an electromc measurement and control system as shown m Fig 1 The data-acqulsltion system IS deslgned to acquire information from an object (a phenomenon, process or system of physical, chenucal or blologxal nature) and to transform these data mto a format that 1s smtable for mampulatlon m the data

Fig 1 Structure of a measurement and control system

‘Imted paper

0924-4247/94/$0700 Q 1994 Elsevler Sequoia All nghts reserved SSDI 0924-4247(93)00402-P

processor The desired mformatlon 1s contamed m an energetic signal domam In the case of a non-electrxxl slgnal tamer (mechamcal, radmnt, magnetic, chemical or thermal), a sensor IS required, which, based on some transductron effect m the matenal used, enables the sIgna to change from the energetic carrier, without loss of mformation content of the mtended sIgna source or mterference from any undesired slgnal source These condltmns are, of course, only met up to a certain extent III a practical sensor, whxh exhiilts offset, nonlmeanty, cross_sensltMy to parantic non-electrical signal sources at the input and a susceptlblllty to electrical signals at the output termmals S~gnal-condalonmg Calcults are unplemented to reduce these effects by offset cancellation, non-hnear mverse transfer functions, compensation using multi-sensor mformatlon and output nnpedance transformation, amphficatlon or filtering, respectwely [l] The data-acquisition structure shown m Fig 1 is not the only possible approach Integrated smart sensors

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based on bitstreams usmg delta-sigma modulators are mvestlgated for provlchng a d@al output slgnal [2] A mlcroprocessor 1s typically used for data processmg, so analog-to-d@al (AD) converslon IS reqmred Obv~ously, next to reducing the effect of sensor nonideal&es, the amphfication m the signal-processmg umt should be designed to match the dynamic range of the sensor output signal to that of the AD converter mput Therefore, the analog functions to be implemented m the sIgnal-processmg part are highly sensor-specdic, which brmgs up the Idea of reahzmg the complete dataacqmslhon system on the same matenal carrier by mergmg the sensing element and the rmcroelectromc readout clrcurts Such a device IS often referred to as an ‘mtegrated &on smart sensor’ This ambition threctly explams the present extensive research actlvltles on slhcon sensors Although &con exhibits amongst others photoelectric, thermoelectnc, plezoelectnc and Hall effects and can be nucromachmed, it IS nonplezoelectnc, non-magnetizable, unsmtable for direct photon enusslon, due to the Indirect band gap, and only smtable for operation up to about 200 “C, due to the magnitude on the band gap These properties mean slhcon IS not an outstandmg sensor matenal for many apphcatlons, but it ~111be shown that the advantages resultmg from Its matenal compahbihty Hrlth nncroelectromc clrcmts often prevad Sihcon microelectromc technology has evolved m the last few decades towards a means for h&-density Integration of complex analog and dlgtal functions Complex digital clrcmts have been integrated m &on usmg advanced MOS processes Demandmg analog specdicatlons are met by fabncahon m a bipolar process Dlgtal and analog Integrated clrcmts ongmahng from these technologies have expenenced an unprecedented market acceptance In retrospect, it can be concluded that the rapid penetration of these products m electromc systems IS because such an mtegrated clrcmt can be regarded as a bmldmg block wth a high level of abstractlon vvlth respect to the details of the mternal crcmts A specdication of a d@al mtegrated crcmt m terms of the logic levels on the mput and output terminals, combmed with a functional descnption of the mput/output sequences mcludmg practical hmmg constramts, along with the range of power supphes, IS suffictent for lmplementatlon and has strongly contnbuted to this rapid acceptance Although to a smaller extent, a slmdar mechamsm applies for analog mtegrated grcmts A specfication m terms of transfer function and characterishc mput and output parameters, such as offset, Impedance, equivalent mput noise sources, voltage range, common-mode performance and frequency range, IS sufficient for apphcatlon, Hnthout the user havmg to go mto the details of the Internal operation

Tlus approach can basically also be apphed to the &on sensor One of the major disadvantages of stateof-the-art sticon sensors ISthat, hke non-slhcon sensors, only the basic sensing element IS available on the material carrier and the designer or user of a measurement and control system has to go mto the details of the sensor non-ldeahty to add the remammg parts of the data-acqumtlon system The electrical output can be a voltage, a change m capaatance, etc , and IS strongly dependent on the type of sensor Moreover, only the output sIgna of the basic sensor element IS avdable, which nnphes that no compensahon of the undesned charactenstics mentioned IS nnplemented The trend m sillcon sensor research IS finally to cash m the potential of the material compatlblhty and to merge the slhcon sensing element with electronic circuits m &con on one chip to realize a smart sensor with a standard d@al microprocessor-compatible output on which the undesirable charactenstlcs of the sensmg element do not appear The mam problem Hrlthsuch an ObJectwe is actually to merge the fabncahon processes of the vanous components Addmg one type of device should not interfere with the proper operation of the other This problem was already relevent III the early 198Os,when mixed analogld@al designs were to be merged m order to reduce the number of chips m electronic slgnal-processmg systems, such as those used m telecommumcatron The actrve components m a MOS process are optmuzed for swltchmg apphcatlons and demonstrate a poor performance when used for lmear amplification, and vice versa This fabrlcatlon compatlbihty issue, the mergmg of analog and d@al clrcmtry, has resulted m the BlCMOS process, which combmes the merits of bipolar processmg for analog functions with the highdens@ mtegratlon of dlgtal funchons m a CMOS process, wlthout loss of the performance of either and at the expense of a shght increase m process complex@ An integrated &con smart sensor imposes even higher demands on the compatlblllty of the processes mvolved Not only are the analog and d@al cmxnts to be merged, but also the sensor has to be mcorporated The degree to which the fabncation of smart sensors IS hmdered by the compatlbtity problem IS strongly dependent on the actual non-electrical sIgna domam The nnpact of the fabrication-compatUty problem on several types of Integrated sihcon smart sensor with a bipolar process IS discussed m the next Section An overview descntnng the smtablllty of MOS processes for smart nucromechamcal sensors 1s presented m the literature [3] Fabrication compatibility in a bipolar process The technology parameters, such as doping levels, temperature and epltaxlal layer thickness, are optmuzed

13

m a standard bipolar process to give high-performance actrve components Since the verWa1 npn transistor IS the most nnportant element, the process parameters are designed mainly to yteld a high-performance npn transistor with reasonable performance of the other actlve components, such as the lateral pnp and the JFET transistors Figure 2 shows a typical vertical doping profile of an integrated npn bipolar Junction trannstor, where the base width, W,, IS defmed as the distance between the two Junctions [4] From the Figure It can be seen that W, depends largely on the epltaxlal layer dopmg concentration if the other process parameters are kept constant The essential performance parameters of both the vertical npn transistor (the commonemitter forward current gam, & the Early voltage, VA, and the storage time constant, 7,) and the lateral pnp transistor (& and 1/A) are plotted m Figs 3 and 4, respectively, as a function of epltaxlal layer width and dopmg and additional post-processmg tigh-temperature steps [5] The common-enutter current gam and Early voltage prnnanly influence analog performance, whereas the storage time constant IS of importance m switching clrcults and non-saturating logx IS to be used m the case of large vanatlons m epllayer thickness The epllayer serves as the collector m the vetical npn and the base m the lateral pnp transistors The & of the npn transistor decreases with epllayer doping, due to the increased base width resulting from the deeper base-collector Junction, whereas & of the lateral pnp transistor mcreases with decreasing epllayer dopmg as a result of the mcreasmg collector-base depletion layer The Early voltage of the vertical npn increases with decreasmg epllayer doping, because the base-collector depletion layer mcreasmgly extends mto the epilayer and thus reduces the base-collector voltageinduced base width modulation, whereas VA of the pnp decreases due to the increased base width modulation m the epfiayer Addmona high-temperature processmg results m further Junction drive-m and lateral outdlffusion of dopants This effect IS espeaally dommant

60

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600

400

200

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(c) FIN 3 (a) a, @) VA and (c) 7r of the vertxal npn trannstoc as a function of ephxA dopmg concentration antb post-processmg temperature steps and epdayer Hrldth as parameter

141 00

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15 DEPTH

Fig 2 Vertxal process

20

[pm]

dopmg profile of the reference standard bipolar

m the lateral pnp transistor, where the lateral dlfiunon reduces the base Hrldth and thus enhances & up to a ht where the transistor IS not practically apphcable and mask dimensions have to be increased This bnef ovemew of a typical standard bipolar process mdlcates that dticultles are to be expected when changmg technologcal parameters At this stage

14

The inghly sunphfied schematlc diagram of such a proportional to absolute temperature (PTAT) cxcult IS depicted 111Fig 5(a) [6] The sensor supphes an output current Z(T)=

ld”

ld7

10’” Nepl l&-3

(a)

ld”

lOI

]

1i7

and IS suitable for integration m any bipolar process that provides transistors of acceptable performance for analog integrated cmxuts The only fabncatlon-compatlblhty problem arlsmg m this type of integrated slhcon smart temperature sensor IS self-heatmg of the chop due to internal power dlsslpatlon, m combmatlon with the hnuted heat conductance of the conventional moulded plastic package Self-heatmg would lead to a measurement error equal to AT=P,,,R,, and directly determmes the sensor inaccuracy specfication A photograph of an integrated silicon smart temperature IS shown m Fig S(b) The second well-estabhshed temperature effect 111 silicon IS the Seebeck effect [7] Integrated thermopdes can be fabricated by placmg a number of thermocouples electncally m series and thermally m parallel over a temperature gradlent on the chip, as shown m Fig vt 1

(b)

1

1

EPY I(T)

Fig 4 (a) BF and (b) VA of the lateral pnp transrstor as a function of epltaxlal dopmg mncentratlon wth post-processmg temperature steps as parameter

it is important to investigate whether such changes are necessary m practical silicon sensor types that are generally expected to have a large potential for reallzatlon as mtegrated &con smart sensors

$ In(m)T

I(T)

m R

(a)

Thermal sensors

The thermal domain is the least demanding nonelectrical signal domain with respect to fabncatlon compatlblhty Sdlcon exhibits profound temperature effects, such as the temperature dependence of the junction forward voltage drop due to the temperature dependence of the band gap, and the Seebeck effect The temperature dependence of the Junction forward voltage IS usually regarded as a nuisance m analog circuit design, and special measures are taken to mamtam proper operation of the clrcult over a wide temperature range However, this temperature dependence, V,=V, ln(ZJZ.J, where V,=kT/q and Z, denotes the saturation current, can also be used to realrze integrated thermal sensors urlthout any special sensor processmg

@) Frg 5 (a) Slmpldied scbematlc diagram of the PTAT arctut (b) Photograph of a commercial Integrated s~hconsmart thermal sensor

15

6(a) A voltage 1s generated proportional to the temperature dtfference and the number of thermocouples Thermocouples with a reasonably high Seebeck coefficient (up to 1 mVK per Junction) can be realrzed using srhcon-alummmm luncttons or lunctrons between r&on layers with dtierent doping The fabrtcatron of mtegrated thermoprles IS, therefore, dtrectly compatible with standard bipolar processmg However, mtegrated sthcon thermoprles cannot be practrcally apphed wtthout addrtronal spectal sensor processmg The high thermal conductance of srhcon prevents a temperature gradtent from being built up by internal or external heatmg sources of reasonable power The wafer has to be subjected to bulk mtcromachmmg after completion of

p-typesubstrate

Fig 6 (a) Integrated thermopde m sdlmn (b) Integrated sd~con smart thermal tkw sensor usmg the flow-Induced temperature gradlent over a heated chip surface

the standard bipolar processmg before the mtegrated smart sensor IS suitable for, e g, thermal mfrared detector or thermal flow-sensing (Fig 6(b)) apphcatrons The extent of the fabrtcatron-compattty problem for thermoprle-based sensors rs, therefore, determmed by the compattbthty of mrcromachinmg and packaging technologies wtth a bipolar process, which 1s drscussed below for the compattbrhty of mechanical sensors

Magnetic sensors Sensors for magnetic signals are also relatrvely easy to merge wrth a bipolar process The most popular types of sthcon magnetrc sensors are the Hall plate and the dual-collector magnetotransrstor [8] Figure 7 shows a typrcal mtegrated Hall plate Electnc current 1s flowing between the current contacts C, and C, In the case of a magnetic field normal to the srhcon surface, the movmg charge carriers expenence a deflecting Lorenz force, which gives nse to a Hall field perpendrcular to the dtrectron of the current The resulting Hall voltage 1s measured over the sense contacts S1 and S2 as

where r, denotes the Hall constant, G a geometrrc factor, NH the layer dopmg concentration and tH the thickness of the Hall plate Obvrously, the sensttrvtty is maxmuzed when the factor NHtH 1s mmlmlzed In a bipolar process NH = N,, and tH = tsp,-LX The typtcal standard bipolar process used here wrth tH = tcp,results m a sensrtrvtty S=r,l(qN_epr) = 150 V/A T, which increases lmearly with decreasing epttaxral layer doping concentratton However, on reducmg NcP, below a certam level, the assumptton tH= tep,no longer holds due to the mcreasmg epr-substrate depletron-layer thickness extending mto the eprlayer The thickness of the depleted eprlayer IS

Fig 7 Integrated

S~KXXIHall plate

16

2eV

DL=

4

l/2

P Nsucm(N: ~N,,,,r)

(3)

Moreover, tH becomes susceptible to changes 111V,, which directly hts the inaccuracy speclficatlon Generally, the mdlcated sensltlvlty IS suffiaent, as the bt of detect&y 1s set by o&et and the mere sensor reqmrements gve httle reason to depart from the standard bipolar process, which, conveniently, also ensures fabncatlon compatlblhty on the wafer level In the Hall sensor the fabrrcatlon-compatlblllty problem arises on the die level during packagmg Encapsulation stress IS introduced durmg cool-down after die bondmg of the silicon chip on to a matenal of dtierent thermal expansion coefficient or after packaging The piezoresistive effect causes a sheet reslstlvlty non uniform@ m the Hall plate, which m turn results 111a Hall voltage offset Offset can m prmaple be compensated dunng caltbratlon, however, offset dnft due to creep m the adhesive matenal determines the detection lumt The effect of the encapsulation stress ISmmmuzed by aligning the Hall plate along the crystal axe Hrlth the mmimum plezoreslstwe effect and by usmg bulk-nucromachmmg techniques to fabncate suspension structures to separate the Hall plate from the bonded area [9] The dual-collector magnetotranslstor shown m Fig 8 1s the second type of magnetic-field sensor with sufficient potential to be considered for reahzatlon as an mtegrated s&con smart sensor m a bipolar process Charge tamers are inJected from the emitter into the base, m which a fraction recombines An increasing part of this base current flows, at an mcreasmg magnetic field of the mdlcated polar@, from the left-hand extrinsic base, resulting m an mcreasmg enutter-base locahzed forward voltage drop and, consequently, leadmg to increased mIe&on at the left-hand side of the emitter-base Junction [9] The resulting asymmetry in collector current, AZ&=SB, Hrlth S= 10% as a sensit&y factor, 1s measured Recombmation m the collector should be avoided, wluch Implies depletion of

\

/

n epllayer

IL

i

I

n+

Fig 8 Dual-collector

I p substrate magnetotranslstor

I

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the entire epilayer underneath the Junction About 2 pm of epltaxlal layer thickness remams m between the buned layer and the extrmslc base layer, resultmg m V, > (2 pm)” (qN,Jk) - 32 V Lower values of this reverse voltage are requu-ed to avoid breakdown, therefore, a lower epltaxml dopmg concentration 1spreferred m this type of device Reducmg the eptiayer doping concentration to N_ = 1 x 10” cm-” results in the acme device performance mdlcated m Figs 3-4 &, ,,,,,,= 54 mstead of 90 and Vhnpn -250 mstead of 65, smnlarly, instead of 38 and vkpnp=2 5 mstead of 10 PF_,=65 The performance of the lateral pnp transistor 1s, therefore, senously nnpalred and the collector-emtter spacmg has to be mcreased The conventional moulded plastic package does not slgnticantly mterfere Htlth magnetic fields and thus does not add to the fabncafioncompatlbtity problem

Radiant sensors Although most radiant sensors are optical devices operatmg m the vlslble part of the spectrum, this category extends over the entire electromagnetic spectrum and m prmciple includes microwave devices and X-ray detectors Slhcon demonstrates relatively strong photoelectnc effects The photoJunction and photoresistance effects are the most notable A charactenstlc of radiant sensors 1sthe need for a wmdow m front of the sens.itlve area, which 1s transparent for the part of the spectrum under conslderatlon Rather akm to the thermoelectnc effect, Impmgng hght IS a nmsance m cucult desw, as It adds to the leakage current m actwe devices This observation suggests a fabrlcatlon mmmpatrblhty m the packagmg phase of mtegrated s&on radiant smart sensors, unless specml measures are taken durmg wafer processmg to prevent acuve devices from berg dlummated as well Research on hlgh-clenslty CCD unagmg sensors could m a way be considered as the smart opt& sensor field with the oldest tradition, as readout and charge-transportation clrcltlts are mtegrated However, this statement 1s not quite correct, as special fabncatlon techmques are apphed; no effort has been made to obtam fabncation compatibtity with a standard process, but a special process for mtegratlon of readout clrcmts has been designed mstead Nevertheless, many of the solutions ongmatmg from ttus field, such as the drwlon of the die mto a sensitwe area and a readout area covered by an opaque film, are very suitable for adoption m mtegrated op&al smart sensors to reheve the above-mentioned compatibtity problem Incident photons of sufficient energy (&> 112 eV, A<1100 run) are able to u&ate band-gap crossings and to generate electron-hole pans When such an effect takes place at a pn p&Ion, the electron-hole

17

pairs are separated by the build-m electnc field and the open-cncmt potential is modulated or, when shortclrcultmg the junction, an external current becomes avadable When the electron-hole generation takes place m a slab of doped s~hcon, excess charge carriers become available and the sheet reslshv@ of that layer 1s lowered A common complication m &con optical detectors 1s the wavelength dependence of the absorption coefficient m the vlslble part of the spectrum, resultmg m a penetration depth rangmg between about 01~at1\=400nmandabout10~math=650nm A typrcal photo]unction detector rehes on the ddfuslon of shallowly generated mmonty charge tamers generated by short-wavelength hght down to the Junchon, and the d&ion of bulk-generated charge carriers,, generated by long-wavelength hght, upwards However, due to the hmlted hfetune of mmonty charge tamers and the Junction depth, which 1s at about 0 5-l q when using bipolar process-compatible layers, the spectral response of silicon photodiodes 1s wavelength dependent with a maxunum at about A= 550 nm, which IS acceptable m general-purpose photodetectors In a photoconductor this wavelength dependence of the absorption coefficient determmes the mmunum lsyer thickness In some optical devices, such as the integrated &con colour sensor depicted in Fig 9, special sensor requlrements force departures from the standard bipolar process [ll, 121 Sensor operation 1s based on the

-----------------------

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------_______________--------

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1

I

L

P-SUBSTRATE

(4

FIN 9 (a) Structure of the mtegrated uhcon colour sensor (b) Photograph of a realued dewce

wavelength dependence of the absorption coefficient menhoned above A well-defined photocharge collection volume 1s estabhshed by depletmg the upper part of a nhcon layer down from a shallow Junction and the complementary part up from a lower Junction Applymg a small reverse voltage across the upper Junchon, while mamtammg a suffiaently high reverse voltage across the lower Junction to achieve complete deplehon of the epdayer m between, results m a superficml absorbing layer and thus m a predonunantly short-wavelength (blue) response Increasing the reverse voltage across the shallow Junction, while adJustlng that over the epdayer-substrate Junction until pinch-off m an mtegrated JFET takes place results m an enhanced longwavelength (red) response and enables the spectral response to be tuned electronically A 10 pm thick epitaxlal layer 1s required to enable efficient electronic control of the response up to wavelengths of about 600 nm The epitaxlal dopmg has to be lowered from that used m the standard bipolar process to about 1 X 10” crnm3 to enable full depletion of the epllayer to take place with moderate values of the reverse voltage Mergmg of a colour sensor with bipolar processes therefore unposes the followmg modifications rep, from 4 to 10 m and NC,,, from 1 x 1016 to 1x10” cnm3 As can be derwed from Figs 3-4, such changes have considerable unpact on the stahc and dynanuc performance of integrated active devices Nevertheless, mtegrated silicon smart colour sensors have been realized m the bipolar process mdlcated and the result is shown m Fig 9(b) Adjustment of a number of processing steps (epltaxlal growth conditions and deep-boron Isolahon dnve-m) and design rules (lateral pnp collector-emitter spacing) IS reqmred to obtain a sensor and active components of sufficient, although sub-optunum, performance The absorption coeffiaent m mhcon for high-energy radiation IS m the range 1-10m2 cm-’ Therefore, even larger photon-absorption/charge-collection layers are required In a practical mlcrostrrp radiation detector shown m Fig 10, the full 4” wafer thlclmess of 525 pm 1s depleted [13] This prmclple 1s fundamentally mcompatlble with standard bipolar processing How-

Fig 10 Structure of the mtegrated silicon mwostnp nuclear detector

18

ever, exactly this device would benefit greatly from integration as a smart sensor The strip detector 1s a lmear array sensor wfh over 1000 strips per wafer and on-&p multlplexmg circuits strongly reduce the output connection problem Moreover, each stnp can be regarded as a current source with a relatively small capacitance and on-chip readout clrcmtry largely reduces the susceptibility to stray capacitances that would otherwise attenuate the slgnal Therefore, the special post-bipolar-processing techniques to be presented are of special interest m this apphcatlon

Mechanical sensors Mechamcal sensors rely on the mlcromachmmg technologles that have been developed to sculpt mlcromechanical structures, such as membranes, cantdevers and beams Two techniques are widely employed for this purpose, bulk mlcromachmmg and surface mlcromachmmg, which both have serious nnphcatlons with respect to fabrication compatlbdlty [14] Bulk micromachmmg involves the removal of selected parts of bulk slhcon using either lsotroplc etching, with an equal etch rate m all directions, or amsotroplc etching, with a preferential etch along one of the crystal planes Generally, anisotropic etchmg IS preferred for fine feature-sue definition using a backside dlelectnc mask Automatic etch-stop techniques are essential to obtam thm mlcromechamcal structures of high thickness umform@ at the frontside after etchmg through the entire wafer thickness A bipolar process 1s compatible with the electrochenucal etch-stop technique The thtckness of the epltaxlal layer defines the thickness of the eventual mlcromachmed structure when applying a reverse voltage across the epllayer-substrate Junction during anlsotroplc etching m KOH [15] An alternatrve technique for automatic etch-stop IS based on the etch-rate reduction at high boron concentrations (> 5 X 1019cme3) However, this technique IS poorly compatible with standard bipolar processmg Etching ISinitiated from patterns m a backside mtnde mask and proceeds through the wafer along the (111) planes until the epllayer IS reached There are several comphcatlons of this technique First, the etching along the (111) planes results in a bevel with a 54 7” slope In a 525 pm thick 4” standard wafer, a minimum lateral spacmg of 2~525/tan(54 7) =740 pm IS required for moat etching, which implies inefficient use of expensive s&con die area Secondly, the bulk etchmg reduces the wafer integrity Tlnrdly, electrical contact has to be made to the frontside of the wafer durmg etching and, as the etching IS performed as a post-processing step after completion of the entire bipolar process, a special protective etch holder ISrequired to protect the frontsrde

alummrum interconnect Fmally, care should be taken to avoid electrically isolated parts of the epltaxml layer from coming mto contact with the etchant, as nonreverse biased parts are removed Fabncatlon compatlblhty IS nevertheless ensured, although confhctmg demands on optnnum epllayer thickness could m prmaple result from mechanical versus electrical reqmrements The epllayer thickness IS one of the parameters that determines the sttffness of the mlcromechamcal structure, whereas it also affects the dynamic performance of the integrated active bipolar components, as shown already m Fig 3(c) The possible occurrence of such a ccmfllct m a practical device could be Investigated using the pressure sensor and the accelerometer as examples The deflection of the centre of a circular membrane, shown m Fig 11, can be expressed as a function of applied pressure and for a diameter much larger than the deflection, as [16] 1n

(4) This equation indicates that the sensltwlty of deflection to pressure IS mamly determined by membrane radius a, which can be designed to match a prescribed measurement range irrespective of membrane thickness The deflection IS either measured directly using capacitive techniques or the deflection-mduced stress 1s measured usmg integrated plezoreslstors The membrane thickness IS defined by the thickness of the epitaxial layer, h = t_,, which should be sufficient to prevent the pressure-induced stress from exceedmg the yielding stress Usually, more stringent condltlons are imposed and a maximum stress less than 2-5% of the yield limit stress IS specified to mamtam hneanty Piezoreslstors of reasonable gauge factor can be fabricated using the doped layers already present m a bipolar process Care should be taken to mmnnlze temperature effects [17] Dtierentlal pressure sensors therefore do not require major modtications m a standard bipolar process However, a few complications arise m practical deaces Fast, the pressure sensor of most interest is the absolute type, which requires a reference cavity The bulk-mlcromachmed wafer can be evacuated for that purpose and hermetically sealed dunng packaging

1111111111111 p -2aFig

11 Structure

of the bulk-msromachmed

pressure

sensor

19

Moreover, specral gas-access holes have to be drrlled 111the package. These manufacturmg steps apply for any type of pressure sensor; however, m a smart pressure sensor the co-mtegrated crrcmts should be able to wnhstand the die-bondmg techniques used ‘flus fabncatron problem IS, therefore, not fundamental, but does atfect the econoIlltc feasibrhty of mtegrated smart pressure sensors, which wrll be drscussed m the final Sectron The key element m a bulk-micromachmed accelerometer IS the suspended senamc mass shown schematrcally rn Frg 12 [18] llns structure forms a mass-sprmg system and two ad&tronal cappmg wafers are used to realize a cavrty that determmes the squeezedfilm au dampmg The sensrtrvrty and the resonance frequency can be calculated as

respectrvely The epdayer thrckness determmes the thickness of the suspennon beams h =&, However, the relatron clearly mdrcates that h IS not the only possible variable to set the parameter of mterest, so any sensrtrvuy can be selected at any value of h wtlm the hmrts of the yreld stress by admsting I and b Slrmlar to the pressure sensor, the electrrc constramts on the eprlayer, therefore, do not rmply a mechanical hmrtatron Fabncatron of the mass wafer does not rmpose a maJor compatrbrhty problem apart from the post-processmg bulk mlcromachmmg However, an accelerometer IS a _LLLLLLLLLLLLLLLLLLLLL _LLLLLLLLLLLLLLLLLLLL.

_CLLLLLLLLLLLLLLLLLL_ _LLLLLLLLLLLLLLLLLLLL_ h

tF=MZl

Fig 12 Structure of the muh-wafer accelerometer

three-wafer devrce and wafer-to-wafer bonding techmques are employed Care should be taken not to endanger the compaubrhty m the bonding phase Waferbondmg aspects are drscussed m the next Sectron Surface rmcromachmmg mvolves the deposrtron of thm layers on a srhcon substrate and the subsequent selectrve removal of some of these layers (the sacrdicral layers) m order to obtam free-standing structural layers [19] Polysrhcon IS routmely used as the structural layer and phospho-srhcate glass (PSG) as the sacr&al layer, due to us hrgh etch rate and under-etch rate m HF (typrcally > 50 &s and > 30 &mm, respectrvely) The layers are deposited on the substrate by low-temperature LPCVD No special requrrements are unposed on the substrate other than those resultmg from equipment constraints (such as the matenals that are allowed msrde the LPCVD reactor). Thus techmque can, therefore, be used as a post-processmg step after (almost) completmg the brpolar process Fabncatron compatrbrhty with standard btpolar processing IS m prmcrple mamtamed when the surface rmcromachlmng IS camed out near the end of the standard processing However, a number of comphcations have to be taken mto account Ftrst, hlghtemperature residual stress anneal IS requued m conventtonally deposrted polysrhcon layers after release of the structure Secondly, as HP IS used to etch the sacnfictal layer, conventional oxrdes cannot be used to passwate the surface durmg standard bipolar processmg Finally, the mterconnect IS evaporated or sputtered on the wafer after mtcrostructure formatron, so special care should be taken to avoid damage or sideways filhng of the cavrtres, causmg the released structure to be stuck after mterconnect patterning The first problem 1s the most fundamental Conventmnally LPCVD polysrhcon deposited at about 600 “C requues a 1000 “C anneal for 2 h to convert hrghly compressive stress mto about 1000 gstram tensrle stress that IS reqmred to obtain flat free-standing beams [20] Once a polycrystallme layer 1s deposrted, a hrgh-energy anneal IS required to obtain crystallographrc changes to release stress Thus problem IS cucumvented when deposrtmg amorphous srhcon at about 570 “C by LPCVD Gram boundanes are not formed durmg deposrtron, but rather an amorphous layer 1sleft m between the grams Therefore, amorphous deposited films have less compressive stress than those depostted as polysrhcon Furthermore, relatrvely little energy 1s reqmred for stress relief and an uz srtu anneal, after LPCVD at 600 “C for 1 h, IS sufficrent to convert this lower compressrve stress mto low tensde stress [21] Dopmg 1s reahzed by ion uuplantatron and anneahng at 850 “C for 30 mm, grvmg only a mmor addition to the thermal budget, so fabncatron compatrbrhty wrth a standard bipolar process IS mamtamed Surface mr-

20

cromachmmg IS, therefore, expected to fullI rts pronnse as a techmque for the fabncatton of versatile mtegrated sihcon smart mechanical sensors

Special compatrble post-processing Compatible post-processmg technologtes are defined as the range of techniques that are employed to compensate for the shortcommgs of sthcon as a sensor material or to add features to the standard processmg that are essential for proper operahon of the sensing element, Hrlthout Jeopardlvng proper operation of the actwe components already integrated The first group of technologtes mclude deposttlon of ZnO to add piezoelectnc propertres to sthcon m order to enable the fabrication of surface acoustic wave (SAW) devmes [22], electrodeposmon of NlFe on a &con surface to enable the fabrication of microelectromagnets [23] and the growth of GaAs on a sthcon substrate to enable the reallzatlon of mtegrated optics m sthcon, despite Its indirect band gap [24] These techmques involve non-stlrcon materlais and are not dlscussed m more detail here The second category of techniques could be regarded as escape routes to be pursued when the mere standard bipolar process does not provide sufficient options to be merged wtth a particular sensor Processes m this group are bulk and surface mlcromachmmg, wafer-level bondmg, selective eplttaxlal growth (SEG) and epltaxlal lateral overgrowth (ELO) of silicon Mlcromachmmg has already been discussed for mtegrated mechanical smart sensors Mechamcal sensors often require some degree of movement, which implies etchmg of mmromechamcal structures As shown for the Seebeck-effect-based thermal sensors, rmcromachmmg IS also a convenient tool m non-mechamcal sensors, as tt can be applied to remove bulk srhcon m order to reduce the thermal conductance between an on-chip temperature difference [25] Bulk mlcromachmg IS also employed to fabricate access channels m order to ensure a well-defined mteractlon between sensing element and measurand An example IS the mass-flow sensor shown m Rg 13 Flow IS forced through the V-groove and under a mtnde bridge with a heater on one end and a ptezoreslstwe detector on the other The velocity of propagatton of a heat pulse along the bridge depends on convection through the flow and thus on the mass flow [26] Surface mtcromachmmg has been employed for the fabrication of large arrays of torsronal mrrrors These are composed of polyslhcon covered by reflective metal and suspended m the centre by a beam, as shown m Fig 14, and are intended for apphcatron m unage prolectlon [27] Applymg a voltage between either side

Fig 13 Bulk-mlcromachmed

Fig 14 ElectrostatIcally

mass-flow sensor

deflectable

mrror

array

of the plate and the substrate causes electrostattc ttltmg of the plate towards the side where the voltage IS applied and thus enables the control of the projectron of mcrdent light and the realtxatton of a two-dnnenstonal image on a screen This application IS very suitable for mtegratton m a smart slhcon actuator, owing to the need for on-chip multlplexmg m order to hmrt the number of interconnects, whde at the same tune enabling each mdlvtdual deflection element to be addressed Water-to-wafer bonding is employed elther when the mechanical complextty of a devtce exceeds the capablhttes of the angle-wafer mrcromachmmg techniques or when the sensor and readout processes are fundamentally mcompattble The accelerometer IS an example of the first motwauon, as it IS extremely difficult to etch both the selsmlc mass and the dampmg cavtttes m a single wafer, a suspended sersmlc mass IS bulk mlcromachmed in one wafer and recesses are etched m two others mstead The three wafers are subsequently wafer-to-wafer bonded and a devtce results as shown m Fig 15 The electronic ctrcuits can be integrated m any of the three wafers, however, the wafer-to-wafer

21

Fig 15 Cixnmercmlly avadable wafer-to-wafer bonded accelerometer (courtesy IC Sensors)

bondmg &elf has to be compatible with the standard nucroelectronic processmg The second motlvatlon for usmg wafer-to-wafer bondmg IS the opportunity to fabncate separately the sensor wafer and the wafer on which the nucroelectromc cmxnts are mtegrated until the very last fabncation step The wafer can therefore be designed for m-urn sensor performance, without affecting the performance of mtegrated active bipolar components Moreover, the sep aratlon also allows for the use of dtierent speclahzed foundries for the processing of the sensor wafer and the readout wafer Wafer-to-wafer bonding takes place afterwards and can basically be considered as assembly on the wafer level Relatively simple equipment IS required and fabrication compaublhty IS cmzumvented by postponmg the mergmg until after completing the wafer processmg This does not unply that no compatibility mfrmgement could take place, compatiblhty problems anse m the bonding itself and the we bonding Fu-st, as wafer-to-wafer bondmg takes place after onwafer metal mterconnect deposition and patterning, severe requirements have to be met to satisfy the thermal budget Not only should compatlblhty be ensured with respect to Junction outddfuwon, but also the conventlonally used alummmm mterconnect should be able to withstand the bonding temperature The most wdely employed wafer-to-wafer bonding technique IS based on fusion bondmg at 1100 “C [28] The eutectlc temperature of alummmm IS at 577 “C, which lmphes that it would become viscous at higher temperature due to the low softening temperature m the bmary alummmml srhcon phase diagram, and consequently pattern mformation IS lost Although a rapid thermal anneal for 3 mm at 1000 “C has been reported to be sufficient for reliable wafer-to-wafer fusion bonding and the Junetlon dlffuslon is hardly affected by this temperature step, this technique remains incompatible with on-wafer

metal [29] Therefore, wafer-to-wafer bondmg has to be performed at temperatures not exceeding about 400 “C Even at those temperatures careful processing IS required to avoid Junction splkmg, however, bondmg can 111prmclple be combined mth smtermg Lowtemperature wafer-to-wafer bonding 1s usually based on intermediate wafer-to-wafer bonding techniques and low-temperature softening glass or eutectlc gold are used as intermediate matenal to obtain rehable bonds [30-321 Secondly, through-wafer mterconnect 1s required to enable electrical contacting to all wafers from the surface of the upper wafer Hnthout losing batch fabrrcatlon Mlcromachmmg techniques are employed to reahze metalhzed pits down from the top wafer [33] Fhp-chip bonding IS also employed to bond a completely processed wafer to a functional unit on the wafer level Solder bumps are formed on both wafers to be bonded As shown m Fig 16, one wafer IS flipped over and the wafers are subsequently brought into contact at an elevated temperature (below 400 “C, depending on the solder used) The advantage of this technique IS the high flexlblhty, as not only slhcon wafers can be bonded together, but also ddferent matenals (e g , GaAs on SI), and the self fme alignment The cohesive forces between the solder bumps pull them together after coarse alignment [34] Postponmg the fabncatlon compatlblhty also has nnportant impacts on the econormcs of smart sensors Sensor manufacturers often regard wafer-to-wafer bondmg and flip-chip bondmg as intermediate steps between fabncatlon of basic sensing element and mtegrated silicon smart Sensors This philosophy and its econonuc vahdlty are discussed m more detail m the next Section SEG and EL0 offer opportunities to alleviate cornpatiblhty problems when a vertical dopmg profile IS Wettable pad

+ Flip wafer Soldei pad

Base wafer Solder bonds /I

/

\

I

Bonded wafers Fig 16 Prmctple of thp-chop bondmg

22

reqmred for the sensmg element that IS completely dtierent from the results of the standard bipolar process SEG takes place on parts of a s&on wafer that are not covered by a dlelectrrc layer (mtnde or thermally grown or deposited oxide) These seed holes are defined m a bipolar process by the contact holes Under special conditions, T=950 “C, P= 100 Torr and using an SlH,Cl,-HCl-H, gas system, crystallme growth takes place through the seed windows and proceeds over the ddectnc, after reaching the surface, to form an EL0 slhcon layer Figure 17 shows the SEG and EL0 structures SEG of &con basically enables the stackmg of Junctions m add&on to those resultmg from the standard bipolar process A vertical dopmg profile can be reahzed m the EL0 layer that IS optuntzed for the sensing element lrrespectnre of the bipolar devices already integrated m the substrate A 2 ,um thick SEG layer requires 950 “C for 30 mm Although this addition to the thermal budget cannot sunply be disregarded, the effect on actnre bipolar components ISusually acceptable The crystal quality of the SEG depends on seed hole

size and onentatlon Diodes m SEG mdlcate an almost ideal performance of the (lOO)-onented devxe (ldeahty factor 1s 108) Layer thickness umfornuty over the wafer 1s hnuted by maskmg effects to 6% [35] Defects are mamly formed along the SEG layer cmxnnference Research on SEG has so far mamly been auned at sub-mtcron high-speed actwe devices Due to the high defect density resultmg from the relatively large ctrcumference/area ratio, SEG technology has never been very successful m thus apphcation However, this 1s due to the very small seed holes mandatory m those devices [36] SEG IS expected to become a successful technology m mtegrated slhcon smart sensors Usmg SEG to stack additional Junctions on top of the standard bipolar process for fabncatlon of an nnproved-performance colour sensor has been developed based on the wavelength dependence of the absorption coeffictent already discussed Junctions are fabncated at 50 nm, 700 nm and 15 pm depth, resultmg m photocharge collection layers between 50 and 200 MI, 200 and 800 nm and for 800 nm down to 5 pm depth, respectively The spectral responses of the three photodlodes are depicted m Fig 18 and enable the unambiguous reproduction of the colour of nnpmgmg light m terms of the trl-colonmetnc coordmate EL0 layers of high crystalline quahty are m prmctple formed by unrestramed growth of the slhcon over the dlelectnc surface and a subsequent planarrzatlon Surprlsmgly few defects are formed at the interface when the overgrown layers meet due to the growth at 950 “C As the verWa1 and lateral growth rates are about equal, improved quahty EL0 layers are fabricated using confined growth m a surface-rmcromachmed poiysdrcon cavity [37] EL0 enables the electrical and structural separation between dtierently doped parts (the sub-

(4

c 1

OS

06

04 02 ;i =?.! 0

(b)

@)

Fig 17 (a) (100) SEC layer m a contact wmdow (b) EL0 layer grown from two contact wmdow strips spaced 2 /NII apart

Fig 18 (a) Schematx structure of the Improved colour sensor (b) Spectral response of the stacked photodlodes

23

strate contammg the bipolar readout circuits and the overgrown layer the sensmg element or vice versa), while mamtammg the physlcal and functional unity of the integrated slhcon smart sensor This prmclple IS bemg mvestlgated for apphcatlon m integrated smart high-energy radlatlon detectors, as shown m Fig 19(a), where the bipolar devices are fabncated m the overgrown layer on a high-punty substrate EL0 is also investigated for apphcatlon m sIllcon on insulator (SOI) Plasma etchmg of the ongmal seed windows ISperformed to ensure complete isolation from the substrate, as shown m Fig 19(b) Finally, the buned oxide layer can be used as an etch-stop m bulk mlcromachmmg to result m devices as depicted m Fig 19(c) [38] These applications clearly demonstrate the technical feaslblhty of SEG and EL0 m integrated slhcon smart sensors to circumvent some of the fabncatlon-compatlblllty problems However, the processmg complexity 1s slgmficantly Increased, so that careful evaluation of a

C

I

I

I’

II

B

-

I

I

I

n

I

,

I

the economic feanblhty of apphcatlon m smart sensors IS required Generally, an mtegrated smart sensor based on these technologes comes ~rlthm the realm of the posslbllltles m those apphcatlons where conventIona solutions are inadequate and a slgmficant added value IS to be expected when applymg the smart sensor concept Therefore, SEG and EL0 are expected to have a serious unpact prnnanly m matnx sensors These and other issues related to the econonuc feaslblllty of integrated silicon smart sensorsversus hybrid integration are dlscussed m the next Section

The economics of integrated silicon smart sensors The economics of integrated rmcroelectromc arcmts are dictated by defect-lumted yield and Its dependence on die area The yield, Y, 1s defined as the probabdity of zero defects over the die area, Ad When assummg a random defect dlstrlbutlon over the wafer, the Poisson yield model applies Y= exp( -D&J, where D, denotes the average defect density defined as the number of defects per wafer, N,,, over the wafer area, A, D, = NJ A, As defects are not randomly dlstnbuted over the wafer, but rather clustered, the Poisson yield model usually provides too pesslmlstlc a prediction More realistic yield predictions are made using the gamma function instead with a clustermg parameter cu, givmg the expression

g-smb@mte

Y&)=1/(

I

I

Fig 19 ApplytngEL0 111 (a) readout of nuclear radlatlon detector array, (b) SO1 and (c) bulk mlcromachmmg

1+

y)

(6)

Note that for cr-, m the expression gwes the Poisson yield model [39] Practical processes result m 0 5 < ar< 4, where the smaller values of (Ymdlcate a higher degree of process matunty [40] This modellmg can be apphed to evaluate a few general opmlons on the fabncatlon yield of integrated s&con smart sensors Fust, the Poisson model IS narvely adopted to explain the popular mlsconceptlons Obviously, mcreasmg the active die area results m a reduced yield irrespective of the model Addmg a sensor of die area A, to an integrated circuit consummg a die area A,, thus gwmg a total de area A,+A,, leads to a device with a poorer fabncation yield, Y., = exp[ - D&4, +A,)] < exp( -Da,) However, the readout electronics have to be included one way or another, so the yield of an integrated smart sensor should rather be compared Hrlth that of a hybnd device, Yhr In a hybrid smart sensor a sensor chip of die area A, 1s processed m a process with defect density D, and IS put in a package with a chip containing the nucroelectromc circuits of die area A, and defect density D, In the following the positive effect of die selectlon on hybrid sensor yield IS dlsregarded Electrical connection between the

24

two chips 1s made usmg wire bonding Assummg the wire bondmg does not mtroduce a yield loss, the defect densities m the sensor wafer and the circuit wafer are statistically mdependent and applymg the Poisson yield model gwes

and Yti=exp(-DJ,)

exp(-D&J

Obviously, D_A.. < 1 and D.&,-C 1 in a commercial process The choice of an Integrated &con smart sensor IS only econormcally accountable If Y,, > YhS However, mergmg a sensor process with a mlcroelectromc process usually results m an increased complex@ and thus m an increasing defect dens&y. D, a max{D,, DA T’herefore, D&4, +A=) > DJ, + Da, and the general opmIon would indeed be confirmed for any combmatlon of A, and A, However, as mentioned already, defects are clustered and the Potsson yield model has already been abandoned m the mlcroelectromcs industry Assummg a reasonably mature process (a= l), for the Integrated slhcon smart sensor, we get Y,=[l+D,(A,+A,)]-l and for the hybnd sensor Yti= I(1 +DoPN

+&A)l-’

Again, mergmg two processes of a certam defect density results m a compatible process with a defect density larger than m any of the basic processes D, a max{D,, DoF} Various types of smart sensors can now be analysed W&I respect to the economic vlablhty based on waferprocessing yield The first case IS the mtegrated thermal sensor where Do = D, = D, and A, YhS, so (Y=1 results in

+D,DJPJ(A,+A,)

=D&

+D0&2)

Agam technolopcal constraints Impose D, a max{D,, D,} = D, = D, Both restrIcttons are therefore met in an mtegrated thermal smart sensor and a commercial integrated &con thermal smart sensor based on the design deplcted already m Fig S(b), which IS technologlcally and economlcally feasible when consldenng only wafer processing The second type of integrated sillcon smart sensor of special interest IS the simple smart sensor, which IS characterized by D,A,, thus Y,> Yhs for

=LhI(A

+A,)(1+QJA,)
This condltlon IS not m agreement Hrlth Doamax{D,, D,}, so a sunple smart sensor IS not economlcally viable accordmg to the yield cntenon Pius conclusion 1s apphcable to the device m Fig 6 Alternatively, a complex integrated &con smart sensor 1scharacterized by D,Yh. for D,
+A3

+A,)

-D~,I@,+4(2+DJJ Both the technological and econonuc constraints can be satisfied for a wide range of A,, A,, D, D, Generally, from the yield vlewpomt It can be concluded that when one takes the trouble to merge sensor and readout electromcs it IS better not to be restncted to a few transistors, but rather to make It worthwhile Figure 20 mdlcates the requirements for economic mtegrated slhcon smart sensor fabncatlon as a function of (Yand DJDA fundamental problem m applymg the yield models developed m the rmcroelectromc mdustry 1s the fact that these only lead to a sensible econonuc cnterlon m mass production, where the variable umt costs exceed the fixed costs dlvlded by the productlon volume These econormes of scale are rarely met m sensors, because of the high initial costs per design (photohthographlc masks) and the lower volume compared to rmcroelectromc circuits, since a sensor is not a umversal component Furthermore, It has to be emphasized that the cost of any mlcroelectromc device 1scomposed of wafer processing, wafer-level testing, dlcmg, bondmg, packaging and final component testing In microelectronic circuits almost all of the testing can be done on the wafer level and only little yield loss is detected at the final component testmg Automated wafer testing IS very efficient and ensures a high throughput with little unnecessary further processmg of defectlve devices Moreover, non-electrical testmg IS merely reqmred to vex@ the envvonmental operatmg range specficatlon, such as temperature and hunudlty, so the costs of testing are relatively low Relatrvely inexpensive standardlzed moulded plastic packages are used for encapsulation Therefore, wafer processmg contnbutes to a sign&ant part of the fabncatlon costs m microelectronic circuits For integrated s&con smart sensors, the contnbutions of the different types of costs are quite different Extensive testmg IS required on the packaged device for two reasons First, a sensor 1s convertmg signals

25

as the cap on the reference cavity 111an absolute pressure sensor or the capped wafers for determmmg the damping m an accelerometer Therefore, most of the testmg has to be done on packaged deuces and adds a much larger share to the fabncatlon costs m an integrated smart sensor compared to an integrated mlcroelectromc cir06

(a)

cult

0

02

Ob

06

05

I

0

02

04

06

08

I

0

02

04

06

05

I

06

04

(b)

06

04

tc.

---.

Fig 20 Y,JY,,s,l for (a) a=05, (b) n=l and (c) a=4 and D&Da= 1, 12 and 15 A reduced process control also reduces the margms of tbe econonuc v~abrhty of the Integrated smart Sensor

from a non-electrical domam mto electrical signals, unhke nucroelectromc arcuits, so extenswe electrical and non-electrical testing IS requved The packagmg often influences the performance, such as encapsulatlonstress-induced offset m a Hall plate, or the package may be an essential part of the sensor structure, such

Packagmg IS a special problem m sensors Mrcroelectronic clrcmts are routmely packaged m moulded plastic m order to provide suffiaent protection against environmental mfluences, such as moisture and mechanical stress Thus package provides an effective ISOlatlon from external hazards, however, a sensor by definition reqmres some degree of enmronmental access As mentioned already, thermal sensors are the least demandmg wth respect to packagmg The problems are the most severe m chermcal sensors The fundamental dmrepancy between the need for contact between the sensing element and the substance m order to have an mformatlon exchange and the corroswe effects hampers development m integrated smart chemical sensors A solution to this dilemma 1s the mtroduction of a chenucal interface A umversal problem m sensor packagmg B the lack of standarduahon, due to the dlverslty of apphcatlons and the apphcatlon dependence of the package Dlfferent requuements are, for example, unposed on a pressure-sensor package m a blomedlcal apphcatlon (measurmg the pressure m the coronary artery) and in automotive applications [41] The pressure-sensing elements could well operate m the same pressure range and ongmate from the same design Adding the volume of all apphcahons together would lead to the conclusion that a pressure sensor IS one of the few sensor areas where mass production on the wafer level IS achieved Present annual fabncatlon volume in Europe amounts to 14 mllhon and forecasts predict 35 nulhon m five years [42] However, the Hnde range of d@erent packages makes the fabncatlon of packaged and tested pressuresensing devices a small-volume operation The testmg and packagmg issues discussed here cause the costs of integrated silicon smart senmrs to be little affected by wafer processmg Evaluation of the dtierent types of costs m the fabncahon of an mtegrated ahcon smart sensor leads to the conclusion that its ment can hardly be discussed in terms of wafer-processmg yield The popular nusconception that the yield 111two separate dies wdl always be better than the yield of the merged device, which consumes the same total area, no longer holds Also the llrmted volume m integrated sensors and the fact that wafer-processmg costs amount to only a frachon of the total costs, due to the larger share for testmg and packagmg, make the wafer-yield approach and the emphasis on die-area mmmuzation madequate means

26

for estunatmg the econouuc vlabtity of an integrated slhcon smart sensor An analysis m terms of added value would be more appropriate Any commercial operation on a product, whether manufacturmg, storage or transportation, adds to its value Generally, storage and transportation (transaction costs) are included m between each manufactnnng step, so for sunphc~ty the dlscusslon IS lnmted to the clearly dlstmgulshable manufacturmg steps Usually, the market sets the pnce of the complete system, such as the antllock brakmg system (ABS) or the rurbag, which IS usually based on what ISconsidered a reasonable fraction of the total costs of the particular consumer product (the automobde) and IS of the order of hundreds of dollars at the tune of mtroductlon of such a system on the market Tracing back the conventional manufacturmg procedure (component fabncatlon, sub-system assembly and system mtegratlon) results 111a maxnnum allowable cost for basic sensing-element fabrlcatlon m the range of several doliars This pnce tag is often also wrongly attached to mtegrated s&on smart sensors, which are basically complete data-acqulsltion subsystems and are therefore on a higher hlerarchlcal system level Obviously, an Integrated slhcon smart sensor would not have to compete cvlth a general-purpose mtegrated circuit Many integrated circuits are used m combmatlou with an elementary sensmg element, constituting a conventional data-acqulatlon subsystem on the PCB level The latter device 1s a system of higher added value and the actual contender of the mtegrated slhcon smart sensor The economic vlablhty of special compatible post-processing steps should also be regarded m this context The econonuc mcentwe of growing EL0 on layers on high-purity substrates for integrated smart radlatlon detectors should be considered ~th respect to the costs of packaged elementary drift chambers and external readout and selection cucmts, mcludmg wire bonding an assembly on a PCB Not every integrated silicon smart sensor that is techmcally feasible wdl meet the economic constraints for commercial success (even if this would solely depend on ObJeCtlve cnteria such as costs) An applicationspecific uncertainty ts the magnitude of the added value, as reference has to be made to the state-of-the-art m that specific field based on conventionally fabricated devices Generally, the added value IS maxumzed by convertmg the sensing element into a data-acqulslhon subsystem that provides a bus-orgauued digital output code of standard format free from any sensor nonldeahtles The complex@ of the bus mterface should be sufficient to allow the system controller to regard the data-acqulsltlon umt as a data source of a high level of abstraction that does not cause much overhead and 1s equipped wtth self-test, self-cahbratlon and an error-handlmg capability These requirements, com-

bmed with the lmnted impact of wafer-processmg costs on the total costs of integrated silicon smart sensors, make it undesirable to compronuse on complexity solely for the sake of the yield m wafer processmg

Conclllsions

This paper 1s about the technolwcal feasibility and the econormc vlablllty of the integrated nhcon smart sensor concept Integrated slhcon smart sensors are technologically feasible m a standard bipolar process for sensing of many dtierent parameters m the thermal, magnetic, radiant and mechanical domains The fabncatlon-compatlblhty problem IS virtually non-exlstent m some sensor types, such as the temperature sensor, as the sensor processmg gves no reason for process adJustment Many sensors, such as the magnetotransister, @ve rise to minor process adJustments and others, such as the basic colour sensor, result m a major performance degradation of some of the active bipolar components Nevertheless, layout dnnenslons can remain unchanged in a careful design Moreover, circuits can be designed to be tolerant to processmgfluctuatlons, such as using non-saturatmg logs Special compatible post-processmg techniques are available, such as bulk mlcromachmmg for proper operation of an on-chip thermopde, or are under development, such as SEG and ELO, to extend the capablhtles of the standard bipolar process without compromlsmg the performance of actwe components already integrated therem Lowtemperature wafer-to-wafer boudmg 1s used m the case of fabncatlou-mcompatlble sensor and cuzult processmg Both are fully processed and bonded m a final processing step, before dicing, using relatively simple equipment Such an approach 1sespecially advantageous for relatively small sensor companies There are several reasons why the wafer-processmg yield 1snot a suitable measure for the economic vlablhty of an integrated silicon smart sensor This analysmg technique quite rightIy donunates the economics of integrated circuits, but, due to the common technologcal roots, is mistakenly mtroduced too often to Judge wrongly the mtegrated s&on smart sensor as an econonucally marginal product First, when mcorporatmg the defect clustenng m the wafer yield prediction model, fabncatlon of mtegrated &con smart sensors of high complex@ could gwe economic advantages compared to hybrid integration Secondly, the wafer yield 1s not a sutable means to evaluate the integrated sillcon smart sensor, because of the larger mlluence of testmg and packagmg on the total cost compared to the dommatmg wafer-processmg cost m integrated clrcults The rapid market acceptance of dlgltal and analog Integrated arcults was largely due to the high level of

27

abstration of the internal operation Such a feature IS also essential for penetration of the stiam sensor market The slhcon sensor should either have a supenor spec&atlon compared to, e g , a de facto mdustnal standard such as the PtlOO temperature sensor, or the inherent advantages of the matenal compatiilllty unth mtegrated clrcmts m s&con should actually be explcuted Fabncatlon compahlxhty = reqmred to achxve such a goal by convertmg the basic s&on sensmg element mto an mtegrated data-acqumtlon subsystem (mtegrated slhcon smart sensor), which supplies a standard dlgtal output signal, not corrupted by sensor nonldeahties, over a sensor bus to a system controller The mtemal functlonal complexity of the mtegrated slhcon smart sensor should be suffiaent to (a) allow unplementabon 111a system wthout knowledge about the detads of mtemal operation; and (b) ht overheads to the system controller to such an extent that suffiaent added value IS ensured for it to be consldered as a complete data-acqulsltlon subsystem m a measurement and control system m order to make It economically viable

Ackuowledgements

The author is mdebted to all those participating 111 the fabncatlon-compat&uhly projects at the Laboratory for Electromc Instrumentation of the Department of Electrlcal Engmeermg of the Delhi Umverslty of Technology M Bartek, B van Dneenhmzen, J Foerster, P French, P Genmssen, J Goosen, G de Graaf, R van Kampen, T Kwa, Y L,I, K. Mahmoud, D. Poenar, M Rutka, P Sarro (DIMES) and M Woiffenbuttel Also to Carole Polma for grantmg just suffiaent opportumty, despite early amval, to enable completion of the manuscnpt m tune Thus work s funded m part by FOM and STW

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