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Fabrication of combinatorial nm-planar electrode array for high throughput evaluation of organic semiconductors
Applied Surface Science 252 (2006) 2568–2572 www.elsevier.com/locate/apsusc
Fabrication of combinatorial nm-planar electrode array for high throughput evaluation of organic semiconductors M. Haemori a,*, T. Edura b, K. Tsutsui b, K. Itaka a,c, Y. Wada b,c, H. Koinuma a,c,d a
Materials and Structures Laboratory, Tokyo Institute of Technology, 4259 Nagatsuta, Midori-ku, Yokohama 226-8503, Japan b Nanotechnology Research Laboratory, Waseda University 513 Wasedatsurumaki, Shinjuku-ku, Tokyo 162-0041, Japan c CREST-JST, 4-1-8 Honcho, Kawaguchi, Saitama 332-0012, Japan d NIMS-COMET, 1-2-1 Sengen, Tsukuba, Ibaraki 305-0047, Japan Received 5 March 2005; accepted 27 May 2005 Available online 3 October 2005
Abstract We have fabricated a combinatorial nm-planar electrode array by using photolithography and chemical mechanical polishing processes for high throughput electrical evaluation of organic devices. Sub-nm precision was achieved with respect to the average level difference between each pair of electrodes and a dielectric layer. The insulating property between the electrodes is high enough to measure I–V characteristics of organic semiconductors. Bottom-contact field-effect-transistors (FETs) of pentacene were fabricated on this electrode array by use of molecular beam epitaxy. It was demonstrated that the array could be used as a pre-patterned device substrate for high throughput screening of the electrical properties of organic semiconductors. # 2005 Elsevier B.V. All rights reserved. PACS: 42.82.Cr Keywords: Combinatorial electrodes; Nm-planar; Organic semiconductor; Chemical mechanical polishing; High throughput
1. Introduction Organic field-effect-transistors (FETs) have attracted tremendous attention, due to their potential * Corresponding author. Fax: +81 45 924 5377. E-mail address: [email protected] (M. Haemori).
application in low-cost large-area flexible displays and electronics [1,2]. The variety of derivatives of organic materials provides a promising potential for new functional materials. New organic materials with the possibility of device application are being synthesized by chemists on a day-to-day basis. Because electric devices are composed of several different layers such as electrode and dielectric layers, the optimization of these
0169-4332/$ – see front matter # 2005 Elsevier B.V. All rights reserved. doi:10.1016/j.apsusc.2005.05.080
M. Haemori et al. / Applied Surface Science 252 (2006) 2568–2572
layers and their dimensions requires much time and intense effort. Thus, it is difficult to find serendipitous candidates for organic semiconductors from the enormous number of possible organic materials. These issues can be very efficiently and elegantly handled by the combinatorial method. The concept of the combinatorial method consists of two factors: large-scale paralleled synthesis and high throughput screening [3]. The integrated circuit (IC) process, including microelectro-mechanical systems (MEMS), is a powerful method with which to realize the largescale synthesis of devices. Recently, combinatorial substrates with mechanical cantilevers were used for investigating ferroelectrics oxides [4]. However, very few results have been reported on the application of the combinatorial method for investigating the electrical properties of organic semiconductors [5]. In this paper, we report a novel approach to screen the electrical properties of organic semiconductors. We successfully fabricated integrated electrodes on a Si/SiO2 substrate by using photolithography and chemical mechanical polishing (CMP) processes. This combinatorial electrode array chip, which has two remarkable advantages over conventional structures, viz., the electrodes were combinatorially designed to have various combinations of channel widths (W = 10–100 mm) and channel lengths (L = 0.7–20 mm) of FETs, and the other is that they have a flattened structure between the electrodes and the dielectric layer interface (i.e., the electrodes are embedded in the insulating layer). This flatness enables us to observe the organic nanostructure within the electrode gap after deposition and confirm structural effects on the grains. This pre-patterned device substrate is useful for the simultaneous high throughput investigation of the electrical properties of organic semiconductors and their structural contributions.
2. Experimental Fig. 1 shows a schematic diagram of the processing steps for fabricating the combinatorial nm-planar electrode array. The substrate was heavily doped n-type Si with a 500-nm thick layer of thermally grown silicon dioxide (SiO2). Initial cleaning of the substrate was done by soaking in hot H2SO4:H2O2
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Fig. 1. Schematic diagram of the processing steps for fabricating our combinatorial nm-planar electrode array: (a) the substrate was thermally grown SiO2 on Si; (b) electrodes patterning by use of photolithography; (c) Ti and Au as electrodes (source and drain contacts) material were deposited by electron beam deposition; (d) development and lift-off; (e) TEOS-SiO2 deposited onto substrate entirely; (f) dielectric layer polished by CMP.
(1:1) solution for 10 min, then rinsing thoroughly with deionized water (Fig. 1(a)). The lithography process steps for fabricating the electrode pattern are shown in Fig. 1(b). First, hexamethyldisilazane (HMDS) was coated with a spin-coater (4000 rpm, 10 s) to modify the SiO2 surface. Then, positive photo-resist (TSMR-V9015cp) was coated on the substrate (700 rpm, 5 s and 2000 rpm, 30 s) and baked on a hotplate (100 8C, 60 s). The resist layer was exposed by use of a chrome mask with various electrode patterns followed by a postexposure baking (110 8C, 90 s). It was then submerged in developer to produce a positive image of the electrode pattern (60 s). Thus, the objective electrode patterns were delineated by immersing the substrate. The substrate thus prepared was deposited with a 20-nm thick Ti layer and an 80-nm thick Au layer successively by electron beam deposition to form the electrodes (source and drain contacts) (Fig. 1(c)). The substrate was soaked in acetone and methanol to liftoff the metal layers and to form the electrode structures and was subsequently rinsed with deionized water (Fig. 1(d)). Then, a 300-nm thick SiO2 layer was deposited by the plasma chemical vapor deposition (CVD) method with tetraethoxysilane (TEOS) as a source material; the substrate temperature was 300 8C. The TEOSSiO2 layer was used as a gate insulator of the FET, as indicated in Fig. 1(e).
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Finally, a chemical mechanical polishing (CMP) process was carried out with a colloidal silica slurry to planarize the rugged surface due to the protruding electrode layers. The TEOS-SiO2 layer was polished to conform the height of the dielectric layer to that of the electrode. Thus, the combinatorial nm-planar electrode array was completed, as shown in Fig. 1(f). The evaluation of the fabricated combinatorial nmplanar electrode array was carried out in terms of the flatness between the electrodes and the electrical insulation property. The flatness between the electrodes was observed with an atomic force microscope (Pacific Nanotechnology Inc., AFM), and the isolation property between the electrodes was measured with a semiconductor parameter analyzer (Keithley Instruments Inc., 4200-SCS) in air at room temperature. The efficiency of the electrode substrate was evaluated by fabricating a bottom-contact-type FET and examining its operation. We used the organic semiconductor pentacene, which is a conventional ptype semiconductor. Pentacene was evaporated by use of a combinatorial molecular beam epitaxy system, which was equipped with a Knudsen cell. The substrate temperature was 100 8C, and the base pressure was an ultrahigh vacuum condition (10 9 Torr). In order to deposit pentacene onto the gap between the source and drain electrodes selectively, a stencil metal mask covered the electrode array. The I–V characteristics of the pentacene FET were evaluated in air.
Fig. 2. The optical micrographic image (top view) of the combinatorial nm-planar electrode array (20 mm 20 mm) and its electrode pattern size. The combinatorial parameters of the electrode array were the channel length (L = 10–100 mm) and the channel width (W = 0.7–20 mm).
electrode area (scan area, 20 mm 20 mm), in which the Au electrodes regions are depicted by dotted lines. These results indicate that the surface of the electrode and the dielectric layer are almost perfectly planarized down to the nm-level. Fig. 3(c) shows the crosssectional profile between the electrodes, which confirms the average level difference to be approximately 1 nm or less. We measured the leakage current between the electrodes, and this was of the order of 10 12 A for the
3. Results and discussion Fig. 2 shows the top view of the combinatorial nmplanar electrode array. The chip size is 20 mm 20 mm and can be cut into four chips by dicing. In the figure, the patterned electrodes are shown by the dotted line indicate the pattern size. The electrodes have two parameters, viz., channel length (L = 10–100 mm) and channel width (W = 0.7–20 mm). The electrode pad size is 100 mm 100 mm. This pattern is repeated periodically, and systematic data of the electrical properties can be obtained by this combinatorial electrode design. Fig. 3 shows an optical micrograph and an AFM image of the fabricated electrode. The designed electrode size was L = 3 mm and W = 10 mm as shown in Fig. 3(a). Fig. 3(b) indicates an AFM image of the
Fig. 3. (a) Optical microscopic image of electrode (L = 3 mm and W = 10 mm). (b) AFM image of electrodes. The Au electrodes existing in this region are indicated by a dotted line. (c) Crosssectional profile between electrodes. The average level difference was approximately 1 nm or less.
M. Haemori et al. / Applied Surface Science 252 (2006) 2568–2572
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Fig. 5. AFM images (scan area 5 mm 5 mm) of pentacene thin films; (a) on TEOS-SiO2 and (b) on the edge of the Au electrodes. The AFM image in (a) shows a clear related to the c-axis length of pentacene.
Fig. 4. (a) Typical Vd–Id characteristics of a pentacene bottomcontact FET (W = 60 mm and L = 5 mm); (b) FET mobilities as a function of L/W.
measured electrodes. This is an appropriate value as an SiO2 surface leakage current and satisfies insulating properties of the nm-planar electrode to measure the electrical properties of organic semiconductors. Fig. 4 shows typical I–V characteristic of a pentacene FET on the combinatorial nm-planar electrode array. Fig. 4(a) shows the Vd–Id characteristic of on FET with W = 60 mm and L = 5 mm. We observed typical p-type behavior, and the carrier mobility was 2.0 10 4 cm2 V 1 s 1. This value was calculated from the linear religion of the I–V characteristic. Fig. 4(b) shows the FET mobilities as a function of L/W. The maximum mobility of the device was up to 1.1 10 3 cm2 V 1 s 1. These plots indicate that, as the value of L/W was increased, the FET performance improved. Generally, the characteristics of the bottom-contact-type FET are inferior to that of the top-contacttype FET. This is primarily due to the fact that in many
organic semiconductors, the thin film growth mode differs from substrate to substrate. For example, the grain size is generally larger on insulators than that on conductors. Therefore, we observed the surface morphology of the pentacene thin film between the electrodes. Fig. 5 shows AFM images (scan area, 5 mm 5 mm) of the pentacene thin film around the electrode. On TEOS-SiO2, the grain size of pentacene was about 2–3 mm, with clear step-and-terrace structure, as shown in Fig. 5(a). However, the grain size of the pentacene on the edge of the Au electrode became much smaller than that of pentacene on the TEOS-SiO2 and the Au electrode, as shown in Fig. 5(b). Low FET characteristics were caused by the difference in the growth mode of the pentacene at the edge of the Au electrode. The source-drain current is affected by the contact resistance. Thus, the FET characteristics can be improved by lowering the contact resistance and by using a surface modification technique such as a self-assembled monolayer (SAM), as previously reported [6].
4. Conclusion In summary, we fabricated combinatorial nmplanar electrode arrays by using photolithography and CMP processes, and the successful fabrication of the substrate was realized with an average flatness of 1 nm or less between Au, TEOS-SiO2 and Au. The leakage current between the electrodes was of the order of about 10 12 A for every electrode. A pentacene bottom-contact FET was fabricated, and the
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characteristics of the device clearly showed p-type operation. In addition, the grain size of the pentacene layer can be evaluated by AFM, which cannot be achieved without the nm-planar electrode. Therefore, this novel approach can be applied to fabricate nanoscale gap electrodes for molecular electronics.
Acknowledgements This work supported by ‘‘Nanotechnology Support Project’’ of the Ministry of Education, Culture, Sports, Science and Technology (MEXT), Japan.
References [1] C.D. Dimitrakopoulos, P.R.L. Malenfant, Adv. Mater. 14 (2) (2002) 99. [2] Z. Bao, Adv. Mater. 12 (3) (2000) 227. [3] H. Koinuma, I. Takeuchi, Nat. Mater. 3 (2004) 429. [4] I. Takeuchi, O.O. Famodu, J.C. Read, M.A. Aronova, K.-S. Chang, C. Craciunescu, S.E. Lofland, M. Wuttig, F.C. Wellstood, L. Knauss, A. Orozco, Nat. Mater. 2 (2003) 180. [5] H. Fukumoto, Y. Muramatsu, T. Yamamoto, J. Yamaguchi, K. Itaka, H. Koinuma, Macromol. Rapid Commun. 25 (2004) 196. [6] C.D. Dimitrakopoulos, S. Purushothaman, IEEE Trans. Electron Dev. 48 (2001) 1060.
Fabrication of combinatorial nm-planar electrode array for high throughput evaluation of organic semiconductors M. Haemori a,*, T. Edura b, K. Tsutsui b, K. Itaka a,c, Y. Wada b,c, H. Koinuma a,c,d a
Materials and Structures Laboratory, Tokyo Institute of Technology, 4259 Nagatsuta, Midori-ku, Yokohama 226-8503, Japan b Nanotechnology Research Laboratory, Waseda University 513 Wasedatsurumaki, Shinjuku-ku, Tokyo 162-0041, Japan c CREST-JST, 4-1-8 Honcho, Kawaguchi, Saitama 332-0012, Japan d NIMS-COMET, 1-2-1 Sengen, Tsukuba, Ibaraki 305-0047, Japan Received 5 March 2005; accepted 27 May 2005 Available online 3 October 2005
Abstract We have fabricated a combinatorial nm-planar electrode array by using photolithography and chemical mechanical polishing processes for high throughput electrical evaluation of organic devices. Sub-nm precision was achieved with respect to the average level difference between each pair of electrodes and a dielectric layer. The insulating property between the electrodes is high enough to measure I–V characteristics of organic semiconductors. Bottom-contact field-effect-transistors (FETs) of pentacene were fabricated on this electrode array by use of molecular beam epitaxy. It was demonstrated that the array could be used as a pre-patterned device substrate for high throughput screening of the electrical properties of organic semiconductors. # 2005 Elsevier B.V. All rights reserved. PACS: 42.82.Cr Keywords: Combinatorial electrodes; Nm-planar; Organic semiconductor; Chemical mechanical polishing; High throughput
1. Introduction Organic field-effect-transistors (FETs) have attracted tremendous attention, due to their potential * Corresponding author. Fax: +81 45 924 5377. E-mail address: [email protected] (M. Haemori).
application in low-cost large-area flexible displays and electronics [1,2]. The variety of derivatives of organic materials provides a promising potential for new functional materials. New organic materials with the possibility of device application are being synthesized by chemists on a day-to-day basis. Because electric devices are composed of several different layers such as electrode and dielectric layers, the optimization of these
0169-4332/$ – see front matter # 2005 Elsevier B.V. All rights reserved. doi:10.1016/j.apsusc.2005.05.080
M. Haemori et al. / Applied Surface Science 252 (2006) 2568–2572
layers and their dimensions requires much time and intense effort. Thus, it is difficult to find serendipitous candidates for organic semiconductors from the enormous number of possible organic materials. These issues can be very efficiently and elegantly handled by the combinatorial method. The concept of the combinatorial method consists of two factors: large-scale paralleled synthesis and high throughput screening [3]. The integrated circuit (IC) process, including microelectro-mechanical systems (MEMS), is a powerful method with which to realize the largescale synthesis of devices. Recently, combinatorial substrates with mechanical cantilevers were used for investigating ferroelectrics oxides [4]. However, very few results have been reported on the application of the combinatorial method for investigating the electrical properties of organic semiconductors [5]. In this paper, we report a novel approach to screen the electrical properties of organic semiconductors. We successfully fabricated integrated electrodes on a Si/SiO2 substrate by using photolithography and chemical mechanical polishing (CMP) processes. This combinatorial electrode array chip, which has two remarkable advantages over conventional structures, viz., the electrodes were combinatorially designed to have various combinations of channel widths (W = 10–100 mm) and channel lengths (L = 0.7–20 mm) of FETs, and the other is that they have a flattened structure between the electrodes and the dielectric layer interface (i.e., the electrodes are embedded in the insulating layer). This flatness enables us to observe the organic nanostructure within the electrode gap after deposition and confirm structural effects on the grains. This pre-patterned device substrate is useful for the simultaneous high throughput investigation of the electrical properties of organic semiconductors and their structural contributions.
2. Experimental Fig. 1 shows a schematic diagram of the processing steps for fabricating the combinatorial nm-planar electrode array. The substrate was heavily doped n-type Si with a 500-nm thick layer of thermally grown silicon dioxide (SiO2). Initial cleaning of the substrate was done by soaking in hot H2SO4:H2O2
2569
Fig. 1. Schematic diagram of the processing steps for fabricating our combinatorial nm-planar electrode array: (a) the substrate was thermally grown SiO2 on Si; (b) electrodes patterning by use of photolithography; (c) Ti and Au as electrodes (source and drain contacts) material were deposited by electron beam deposition; (d) development and lift-off; (e) TEOS-SiO2 deposited onto substrate entirely; (f) dielectric layer polished by CMP.
(1:1) solution for 10 min, then rinsing thoroughly with deionized water (Fig. 1(a)). The lithography process steps for fabricating the electrode pattern are shown in Fig. 1(b). First, hexamethyldisilazane (HMDS) was coated with a spin-coater (4000 rpm, 10 s) to modify the SiO2 surface. Then, positive photo-resist (TSMR-V9015cp) was coated on the substrate (700 rpm, 5 s and 2000 rpm, 30 s) and baked on a hotplate (100 8C, 60 s). The resist layer was exposed by use of a chrome mask with various electrode patterns followed by a postexposure baking (110 8C, 90 s). It was then submerged in developer to produce a positive image of the electrode pattern (60 s). Thus, the objective electrode patterns were delineated by immersing the substrate. The substrate thus prepared was deposited with a 20-nm thick Ti layer and an 80-nm thick Au layer successively by electron beam deposition to form the electrodes (source and drain contacts) (Fig. 1(c)). The substrate was soaked in acetone and methanol to liftoff the metal layers and to form the electrode structures and was subsequently rinsed with deionized water (Fig. 1(d)). Then, a 300-nm thick SiO2 layer was deposited by the plasma chemical vapor deposition (CVD) method with tetraethoxysilane (TEOS) as a source material; the substrate temperature was 300 8C. The TEOSSiO2 layer was used as a gate insulator of the FET, as indicated in Fig. 1(e).
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Finally, a chemical mechanical polishing (CMP) process was carried out with a colloidal silica slurry to planarize the rugged surface due to the protruding electrode layers. The TEOS-SiO2 layer was polished to conform the height of the dielectric layer to that of the electrode. Thus, the combinatorial nm-planar electrode array was completed, as shown in Fig. 1(f). The evaluation of the fabricated combinatorial nmplanar electrode array was carried out in terms of the flatness between the electrodes and the electrical insulation property. The flatness between the electrodes was observed with an atomic force microscope (Pacific Nanotechnology Inc., AFM), and the isolation property between the electrodes was measured with a semiconductor parameter analyzer (Keithley Instruments Inc., 4200-SCS) in air at room temperature. The efficiency of the electrode substrate was evaluated by fabricating a bottom-contact-type FET and examining its operation. We used the organic semiconductor pentacene, which is a conventional ptype semiconductor. Pentacene was evaporated by use of a combinatorial molecular beam epitaxy system, which was equipped with a Knudsen cell. The substrate temperature was 100 8C, and the base pressure was an ultrahigh vacuum condition (10 9 Torr). In order to deposit pentacene onto the gap between the source and drain electrodes selectively, a stencil metal mask covered the electrode array. The I–V characteristics of the pentacene FET were evaluated in air.
Fig. 2. The optical micrographic image (top view) of the combinatorial nm-planar electrode array (20 mm 20 mm) and its electrode pattern size. The combinatorial parameters of the electrode array were the channel length (L = 10–100 mm) and the channel width (W = 0.7–20 mm).
electrode area (scan area, 20 mm 20 mm), in which the Au electrodes regions are depicted by dotted lines. These results indicate that the surface of the electrode and the dielectric layer are almost perfectly planarized down to the nm-level. Fig. 3(c) shows the crosssectional profile between the electrodes, which confirms the average level difference to be approximately 1 nm or less. We measured the leakage current between the electrodes, and this was of the order of 10 12 A for the
3. Results and discussion Fig. 2 shows the top view of the combinatorial nmplanar electrode array. The chip size is 20 mm 20 mm and can be cut into four chips by dicing. In the figure, the patterned electrodes are shown by the dotted line indicate the pattern size. The electrodes have two parameters, viz., channel length (L = 10–100 mm) and channel width (W = 0.7–20 mm). The electrode pad size is 100 mm 100 mm. This pattern is repeated periodically, and systematic data of the electrical properties can be obtained by this combinatorial electrode design. Fig. 3 shows an optical micrograph and an AFM image of the fabricated electrode. The designed electrode size was L = 3 mm and W = 10 mm as shown in Fig. 3(a). Fig. 3(b) indicates an AFM image of the
Fig. 3. (a) Optical microscopic image of electrode (L = 3 mm and W = 10 mm). (b) AFM image of electrodes. The Au electrodes existing in this region are indicated by a dotted line. (c) Crosssectional profile between electrodes. The average level difference was approximately 1 nm or less.
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Fig. 5. AFM images (scan area 5 mm 5 mm) of pentacene thin films; (a) on TEOS-SiO2 and (b) on the edge of the Au electrodes. The AFM image in (a) shows a clear related to the c-axis length of pentacene.
Fig. 4. (a) Typical Vd–Id characteristics of a pentacene bottomcontact FET (W = 60 mm and L = 5 mm); (b) FET mobilities as a function of L/W.
measured electrodes. This is an appropriate value as an SiO2 surface leakage current and satisfies insulating properties of the nm-planar electrode to measure the electrical properties of organic semiconductors. Fig. 4 shows typical I–V characteristic of a pentacene FET on the combinatorial nm-planar electrode array. Fig. 4(a) shows the Vd–Id characteristic of on FET with W = 60 mm and L = 5 mm. We observed typical p-type behavior, and the carrier mobility was 2.0 10 4 cm2 V 1 s 1. This value was calculated from the linear religion of the I–V characteristic. Fig. 4(b) shows the FET mobilities as a function of L/W. The maximum mobility of the device was up to 1.1 10 3 cm2 V 1 s 1. These plots indicate that, as the value of L/W was increased, the FET performance improved. Generally, the characteristics of the bottom-contact-type FET are inferior to that of the top-contacttype FET. This is primarily due to the fact that in many
organic semiconductors, the thin film growth mode differs from substrate to substrate. For example, the grain size is generally larger on insulators than that on conductors. Therefore, we observed the surface morphology of the pentacene thin film between the electrodes. Fig. 5 shows AFM images (scan area, 5 mm 5 mm) of the pentacene thin film around the electrode. On TEOS-SiO2, the grain size of pentacene was about 2–3 mm, with clear step-and-terrace structure, as shown in Fig. 5(a). However, the grain size of the pentacene on the edge of the Au electrode became much smaller than that of pentacene on the TEOS-SiO2 and the Au electrode, as shown in Fig. 5(b). Low FET characteristics were caused by the difference in the growth mode of the pentacene at the edge of the Au electrode. The source-drain current is affected by the contact resistance. Thus, the FET characteristics can be improved by lowering the contact resistance and by using a surface modification technique such as a self-assembled monolayer (SAM), as previously reported [6].
4. Conclusion In summary, we fabricated combinatorial nmplanar electrode arrays by using photolithography and CMP processes, and the successful fabrication of the substrate was realized with an average flatness of 1 nm or less between Au, TEOS-SiO2 and Au. The leakage current between the electrodes was of the order of about 10 12 A for every electrode. A pentacene bottom-contact FET was fabricated, and the
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M. Haemori et al. / Applied Surface Science 252 (2006) 2568–2572
characteristics of the device clearly showed p-type operation. In addition, the grain size of the pentacene layer can be evaluated by AFM, which cannot be achieved without the nm-planar electrode. Therefore, this novel approach can be applied to fabricate nanoscale gap electrodes for molecular electronics.
Acknowledgements This work supported by ‘‘Nanotechnology Support Project’’ of the Ministry of Education, Culture, Sports, Science and Technology (MEXT), Japan.
References [1] C.D. Dimitrakopoulos, P.R.L. Malenfant, Adv. Mater. 14 (2) (2002) 99. [2] Z. Bao, Adv. Mater. 12 (3) (2000) 227. [3] H. Koinuma, I. Takeuchi, Nat. Mater. 3 (2004) 429. [4] I. Takeuchi, O.O. Famodu, J.C. Read, M.A. Aronova, K.-S. Chang, C. Craciunescu, S.E. Lofland, M. Wuttig, F.C. Wellstood, L. Knauss, A. Orozco, Nat. Mater. 2 (2003) 180. [5] H. Fukumoto, Y. Muramatsu, T. Yamamoto, J. Yamaguchi, K. Itaka, H. Koinuma, Macromol. Rapid Commun. 25 (2004) 196. [6] C.D. Dimitrakopoulos, S. Purushothaman, IEEE Trans. Electron Dev. 48 (2001) 1060.