ARTICLE IN PRESS Solar Energy Materials & Solar Cells 92 (2008) 1352– 1357
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Solar Energy Materials & Solar Cells journal homepage: www.elsevier.com/locate/solmat
Fabrication of nanoporous antireflection surfaces on silicon Mao-Jung Huang a, Chii-Rong Yang b,, Yuang-Cherng Chiou a, Rong-Tsong Lee a a b
Department of Mechanical and Electro-Mechanical Engineering, National Sun Yat-Sen University, Kaohsiung 804, Taiwan Department of Mechatronic Technology, National Taiwan Normal University, 162, Sec. 1, Ho-Ping E. Road, Taipei 106, Taiwan
a r t i c l e in f o
a b s t r a c t
Article history: Received 28 December 2007 Accepted 19 May 2008 Available online 1 July 2008
After the surface of a silicon wafer has been texturized, the reflectance of the wafer surface can be reduced to increase the power generation efficiency of a silicon-based solar cell. This study presents the integration of self-assembled nanosphere lithography (SANSL) and photo-assisted electrochemical etching (PAECE) to fabricate a nanostructure array with a high aspect ratio on the surface of silicon wafer, to reduce its reflectance. The experimental results show that the etching depth of the fabricated nanopore array structure is about 6:2 mm and its diameter is about 90 nm, such that the aspect ratio of the pore can reach about 68:1. The weighted mean reflectance of a blank silicon wafer is 40.2% in the wavelength range of 280–890 nm. Five-minute PAECE without SANSL reduces the weighted mean reflectance to 5.16%. Five-minute PAECE with SANSL reduces the weighted mean reflectance to 1.73%. Further coating of a 200 A˚ thick silicon nitride layer on the surface of a nanostructure array reduces the weighted mean reflectance even to 0.878%. The novel fabrication technology proposed in this study has the advantage of being low cost, and the fabricated nanostructure array can be employed as an antireflection structure in single crystalline silicon solar cells. & 2008 Elsevier B.V. All rights reserved.
Keywords: SANSL PAECE Nanopore array Antireflection structure
1. Introduction In recent years, many studies have been performed on the surface texture of silicon wafer [1–5]. The purpose is to produce a micro/nanostructure on the surface of silicon wafer, to reduce the reflectance of the silicon wafer, and increase the power generation efficiency of the silicon-based solar cell Because when the surface of the silicon wafer has a subwavelength structure (SWS) that is smaller than the wavelength of light and the structure has a periodic arrangement, a strong antireflection effect can be produced [5]. Usually, the random pyramid antireflection structure is currently used for the texturization of the silicon solar cell [6]. The random pyramids on the silicon surface are produced in KOH or NaOH etchant after etching for about 40 min at an etching temperature of over 70 1C. Although such an alkaline etching technique is simple and low cost, it has drawbacks of being timeconsuming, requires heating and yields poor uniformity The etching solution must be mechanically agitated for better uniformity of the textured structure on silicon surface [7] Besides, the presence of alkali metal ions in KOH or NaOH etchant, incompatible with IC processing, may be detrimental to the fabrication of a silicon-based solar cell.
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E-mail address:
[email protected] (C.-R. Yang). 0927-0248/$ - see front matter & 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.solmat.2008.05.014
Traditionally, advanced lithography methods such as electronbeam (E-beam) [8] or focus ion-beam (FIB) [9,10] and deep ultraviolet lithography (DUV) [11,12] are adopted to define periodic nanoscale patterns. Afterwards, inductively coupled plasma reactive ion etching (ICP–RIE) or electron cyclotron resonance (ECR) plasma etching can be used to form silicon nanopore or nanopillar array structures with high aspect ratios [11–14]. Although such methods can be used to define the nanoscale pattern precisely, they are not suited to fabricate a large-area structure, because the process is time-consuming, and the cost of equipment or process is very high. Moreover, the nanoscale array pattern can be also defined on the surface of the silicon wafer by the self-assembly of a polystyrene nanosphere [15–17], and the shape and size of the pattern can be determined effectively by appropriately selecting the size of the sphere and controlling the layer number of nanosphere. This fabrication method is also called self-assembled nanosphere lithography (SANSL). Similarly, the expensive ICP-RIE etching procedure must be employed to form a silicon array structure with a high aspect ratio [18]. This study combines the SANSL process and photo-assisted electrochemical etching (PAECE) to fabricate a nanostructure array with a high aspect ratio on the surface of a silicon wafer, to fabricate the antireflection structure of a silicon-based solar cell. In fact, PAECE is a well-known etching approach [19–25]. It has the advantage of being low cost, and the aspect ratio of etched nanopores can be as high as 250:1 [26]. Some studies have applied
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PAECE technique to produce photonic crystals [27–29]. PAECE technique can also overcome the drawback of reactive ion etching (RIE) lag [30]. RIE lag is a frequently seen defect during a plasma etching process, especially found in etching high-aspect-ratio trenches into silicon. In general, smaller trench openings are etched slower than those that are wider, significantly affecting etching uniformity of the feature geometrical shape. This study combines SANSL and PAECE techniques to fabricate a periodic nanostructure array on the surface of a silicon wafer as the antireflective structure of a silicon-based solar cell. Compared to the fabrication method of the currently used random pyramids, our approach can form the periodic nanostructure array as antireflection surface under the conditions of short etching time, room temperature, and without the presence of alkali metal ions in hydrofluoric acid (HF). Except evaluating the etching characteristics of PAECE, the effects of experimental parameters on the reflectance are also discussed under the conditions of whether SANSL is conducted and whether a silicon nitride layer is coated on the surface of nanostructure array.
Nanosphere deposited using spin coater.
Nitride layer etched by reactive ion etching.
2. Experimental design Fig. 1 shows the flow chart for the fabrication of a periodically arranged nanopore array. The major processes are SANSL and PAECE, and the experimental steps are detailed as follows. This study uses a 4-in (100 mm) N-type silicon wafer. The resistance of the silicon wafer is 0:0120:018 O=cm, and its thickness is 525 mm. A 200 nm thick layer of silicon nitride is initially deposited on the wafer surface by low pressure chemical vapor deposition (LPCVD), and is used as an etching mask in PAECE. The wafer is cut to 18 18 mm to fit the etching tank. A 2.5% (w/v) suspension of polystyrene nanosphere (200 nm diameter) (Polysciences, Inc.) is mixed with methanol and Triton X-100 (surfactant) in a volume ratio of 800:400:1. Before nanospheres are spin-coated, the sample is cleaned in the ultrasonic vibrator using piranha solution (H2 SO4 : H2 O2 ¼ 3 : 1 by volume), acetone and methanol for 1 h, 30 min and 30 min, respectively, at a vibrating power of 100 W. It is rinsed in deionized (DI) water for 5 min to eliminate cross contamination between any two aforementioned cleaning processes. Finally, the sample is maintained in methanol. A 1–1.2 ml volume of the suspension of polystyrene nanospheres is dropped on the sample. Spin coating is performed at 1300 rpm to arrange the nanospheres uniformly on the sample. The coated sample is placed on the hot plate, and baked at 40 1C for 5 min to remove the solvent. RIE is used to etch the exposed silicon nitride among the nanospheres in 10 sccm of CF4 at 60 m Torr and 180 W for 12 min, to generate the etching window of PAECE. Finally, the sample is placed in dichloromethane and acetone to remove polystyrene nanospheres. After these steps have been completed, the pattern of nanospheres can be transferred into a silicon nitride layer, and then the PAECE process implemented. The PAECE process was performed according to the experimental scheme shown in Fig. 2. The potentiostat (EG&G Model 263A) was adopted to apply a positive bias to the sample, and the distance between the platinum cathode and the anodic sample was 4 cm. A 340 W xenon lamp was applied to radiate the back of sample, and the distance between the radiating source and the sample was 7 cm. The conductive layer of the anode electrode was composed of chromium film (5 nm) and copper film (200 nm), which were deposited at the back of sample, such that the etching bias voltage was distributed uniformly on the sample. The HF concentration of the electrolyte used herein was 2.5 wt% (DI water: ethanol: HF (50 wt%), 14:5:1 by volume). The area of the sample exposed to the electrolyte was 1:13 cm2 . An etching
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Removal of nanospheres and deposition of Cu/Cr films on backside of wafer.
Photo-assisted electrochemical etching.
Removal of nitride layer in RIE process. Nanosphere
Silicon wafer
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Fig. 1. Process flow for fabricating periodic nanopore array structure.
Etching cell
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Fig. 2. Schematic diagram of PAECE setup.
voltage of 1 V was used, and the etching time was set 2.5, 5, 7.5, 10 and 12.5 min. The etching temperature was 22 1 C, and no agitation was used in the experiment. After the PAECE process had been completed, the periodic array of nanopores was formed, and the RIE was then used to remove the silicon nitride layer from the
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surface. Finally, the periodic nanostructure array formed an antireflection surface used to estimate reflectance Scanning electron microscopes (SEM) (JEOL JSM-6360) were employed to observe the pattern of the surface generated by each process and the experimental results were discussed. Finally, a spectrometer (Perkin Elmer Lambda 900) was used to evaluate the weighted mean reflectance in the wavelength range of 200–890 nm. The mean reflectance in this study is weighted with the solar spectrum AM 1.5 g and the spectral response of the single crystalline silicon into the weighted mean reflectance. The data of the solar spectrum AM 1.5 g are in the wavelength range of 280–1100 nm. The major evaluated items include the relationship between the etching time and the reflectance, and the effect of SANSL on the reflectance. Sputtering was used to evaluate the feasibility of coating a 200 A˚ thick silicon nitride layer to reduce reflectance.
3. Experimental results 3.1. Fabrication of nanopore array structure Fig. 3(a), indicates that the nanosphere array with a nearly perfect arrangement can be obtained by spin coating. Fig. 3(b) presents the sample of Fig. 3(a) after etching by RIE and then removing the nanospheres. The periodically arranged nanodots are formed on the silicon nitride layer, becoming smaller as the RIE etching time increases. The pores among the silicon nitride nanodots can be used as etching windows in PAECE, and the size of the etching window can be controlled by varying the RIE etching time, which can affect the diameter of the pores that were etched by PAECE. Fig. 3(c) presents six nanopores periodically arranged around the nanodots after PAECE etching. The diameter of the etched pores is about 70–90 nm, which is smaller than the minimum wavelength of the evaluated test light source (200 nm). Fig. 4 indicates that the mean etching depth is 2.3 and 6:2 mm at etching time of 5 and 12.5 min, respectively. The direction of formation of the etched pores is perpendicular to the sample surface. Fig. 4(b) shows that when the etching time is 12.5 min, the etching depth of the pores is 6:2 mm; their diameter is about 90 nm, and its aspect ratio is up to 68:1. Fig. 4 indicates that as the etching time increases, the variation in etching depth is significant, but the increase in pore width is relatively small. This fact explains why the PAECE process easily yields a high aspect ratio. Fig. 5 indicates that the relationship between the etching time and the pore depth is linear. An etching of 1 V is applied, and the etching speed is maintained at 0:45 mm=min for various etching time. Although increasing the etching voltage can increase the etching speed, the pore can be easily expanded, and nanopores cannot be easily obtained. Fig. 5 also indicates that although the etching depth increases, the etching speed remains constant. 3.2. Reflectance test The Lambda 900 spectrometer from Perkin Elmer is adopted to obtain the reflection spectrum in the range of 200–890 nm, but the weighted mean reflectance is calculated in the range of 280–890 nm due to limited data of the solar spectrum AM 1.5 g. Fig. 6 indicates that the weighted mean reflectance of a blank silicon wafer is 40.2%. If sputtering is performed to coat a 200 A˚ thick silicon nitride antireflection coating (ARC) on the surface of a blank silicon wafer, then the reflectance is reduced to 39%. After 1 and 2.5 min of PAECE, the weighted mean reflectance is reduced to 6.94% and 4.34%, respectively. Etching for 5 min yields the
Fig. 3. SEM micrographs of (a) nanosphere array deposited by spin coater; (b) silicon nitride nanodot array formed after RIE process and removal of nanospheres; (c) nanopore array formed after PAECE, six nanopores around a silicon nitride nanodot produced.
strongest antireflection effect, and the weighted mean reflectance is 1.73%. Hence, as the etching time increases, the antireflection character of the sample becomes stronger. Ref. [31] shows that when the effective depth of the periodic structure exceeds the wavelength of incident light, the effect of the depth of the
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90 blank silicon wafer
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silicon wafer with SiN ARC PAECE 1 min PAECE 2.5 min
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PAECE 5 min
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60 50 40 30 20 10 0 200
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400
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Wavelength (nm) Fig. 6. Comparison of reflectance of blank silicon wafer with and without ARC and PAECE samples at various etching times.
18 PAECE without nanosphere lithography
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PAECE with nanosphere lithography
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PAECE with nanosphere lithography and 200 Å Si3N4
Fig. 4. Nanopore array structures formed by PAECE at etching voltage of 1 V for etching times (a) 5 min, (b) 12.5 min.
10 8
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Fig. 7. Comparison of reflectance among PAECE samples etched for 5 min under various process treatments.
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Fig. 5. Graph of etching depth against etching time; the gradient of the line is about 0:45 mm=min, which is the etching rate.
structure on the reflectance is insignificant. Besides, Ref. [31] also indicates that the decrease in reflectance in the UV/visible range for a nanostructure-arrayed silicon surface is caused by the ‘motheye effect’. On increasing the depth of the periodic structure, the decrease in reflectance becomes more pronounced and slowly tends toward stability. Therefore, the reflectance in our work does not change significantly after etching over 1 min, and etching for 5 min yields the strongest effect of the weighted mean reflectance of 1.73%. Fig. 7 indicates that the weighted mean reflectance of the sample that was etched for 5 min without SANSL is 5.16%. Fig. 8 indicates that etching pores with high aspect ratios can also be
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3. After performing SANSL and 5 min PAECE, the weighted mean reflectance can be improved to 1.73% from 40.2% of a blank silicon wafer under the wavelength range of 280–890 nm. 4. When 200 A˚ of silicon nitride has been coated on the periodic array of nanostructure, the weighted mean reflectance is only 0.491% in the wavelength range of 280–700 nm, indicating that the weighted mean reflectance can be improved to 85 times lower than that of the blank silicon wafer.
Acknowledgements
Fig. 8. Formation of nanopore structures by PAECE with etching times of 5 min and etching of 1 V but without lithographic treatment of nanospheres.
The authors would like to thank the National Science Council of the Republic of China, Taiwan, for financially supporting this research under Contract no. NSC 96-2221-E-003-009. Moreover, the Chemical Systems Research Division of Chung-Shan Institute of Science and Technology (CSIST), Taiwan, and the Office of Research and Development of Nation Taiwan Normal University (NTNU), Taiwan, are also appreciated for their support of funding. References
formed without the definition of a pattern by SANSL. Since these pores are not periodically arranged, and the etching pores on the surface are very tiny, the texture is poorer than that obtained with SANSL. The SANSL technique yields a good texture upon the etched sample. When 200 A˚ of silicon nitride was coated on the sample that had been etched by PAECE for 5 min with SANSL conducted, the weighted mean reflectance was further reduced to 0.878%. Moreover, the weighted mean reflectance was 0.491% for the aforesaid specimen and 41.8% for a blank silicon wafer when the evaluated test light source is in the wavelength range of 280–700 nm. This implies that the texturing method herein improves the weighted mean reflectance by a factor of 85 times. Hence, when SANSL and PAECE are performed to treat the sample and the silicon nitride coated, an antireflection structure with excellent antireflective character can be generated. The antireflection structure formed by the nanostructure array has the potential to be applied in single crystalline solar cells. The SWS antireflection surface of this study effectively suppresses the reflection over a wide spectral bandwidth; then the reflectance is controlled under 1% in the wavelength range of 200–890 nm. Traditional random pyramid structure without period and symmetry, therefore it cannot induce the ‘‘moth-eye effect’’. Ref. [32] has presented a solar cell with random pyramid structure its reflectance is about 2.5–18% in the wavelength range of 280–890 nm, and the reflectance is over 15% in the wavelength range of 450–890 nm.
4. Conclusions This work integrates SANSL and PAECE techniques to fabricate a nanostructure array with a high aspect ratio, which can reduce the reflectance of a silicon wafer. The etching feature of PAECE is discussed, and the effect of various process conditions is evaluated. The experimental results support the following conclusions. 1. The formed nanopores are periodically arranged. After 12.5 min of PAECE, the etching depth of the pores is about 6:2 mm; their diameter is about 90 nm, and their aspect ratio is up to 68:1. 2. When an etching of 1 V is applied, the etching rate is about 0:45 mm=min, and does not decline as the etching depth increases.
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