Ag wafer bonding

Microelectronics Reliability 52 (2012) 381–384

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Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel

Invited Paper

Fabrication of vertical thin-GaN light-emitting diode by low-temperature Cu/Sn/Ag wafer bonding Y.J. Chen a, C.C. Chang a, H.Y. Lin a, S.C. Hsu b, C.Y. Liu a,⇑ a b

Department of Chemical and Materials Engineering, National Central University, Taiwan Department of Chemical and Materials Engineering, Tamkang University, Taiwan

a r t i c l e

i n f o

Article history: Received 3 November 2010 Received in revised form 16 November 2010 Accepted 23 November 2010 Available online 30 December 2010

a b s t r a c t Vertical thin-GaN LED was successfully fabricated on the GaN LED epi-layers grown on the patternedsapphire substrate with the pyramidal pattern by low-temperature Cu/Sn/Ag wafer bonding at 150 °C. An inverted pyramidal pattern formed on the n-GaN surface after the GaN epi-layer was transferred onto Si wafer, which resulted from the pyramidal pattern on the patterned-sapphire substrate. The inverted pyramidal pattern has an equivalent function with roughening the n-GaN surface. With higher inverted pyramidal pattern coverage, the light extraction efficiency can be greatly enhanced. In addition, we found that the 4-fold increase (from 13.6% to 53.8%) in the pyramidal pattern coverage on patterned-sapphire substrate only gives the GaN LED epi-layer about 5.7% enhancement in the internal quantum efficiency. Ó 2010 Elsevier Ltd. All rights reserved.

1. Introduction Recently, a new LED structure (vertical-GaN LED) was developed for the high-power LED applications [1–4]. The two key processes of vertical-GaN LEDs are (1) wafer bonding and (2) laser-lift off (LLO) techniques. First, the GaN/sapphire wafer has to be bonded with the transferring Si wafer. Then, the sapphire wafer was stripped off by KrF excimer laser (248 nm). Finally, the initial GaN LED epi-layers were transferred onto the Si wafer. So far, vertical thin-GaN LED are fabricated by using the GaN LED epi-layer grown on the planer sapphire substrate. The flat n-GaN/sapphire interface seems having better process window for focusing the laser beam during the laser lift-off process. Recently, the patterned-sapphire substrate techniques have been widely used in GaN-based LEDs [5,6]. With the break-through of the patternedsapphire substrate technique, the efficacy of high-brightness GaN-based LEDs has been driven to a record-high of 150 lm/W [7,8]. The efficacy enhancement of GaN-based LEDs with the patterned-sapphire substrate technique is generally attributed to the improvement in both light extraction efficiency and internal quantum efficiency [9–13]. The regular patterns created on the sapphire substrate, which counteracts the effect of the total internal reflection (TIR) at the GaN/sapphire interface [9]. And, the enhancement in the internal quantum efficiency benefits from the reduction of threading dislocations by possible lateral growth of GaN epi-layer on the patterned-sapphire substrate [9,14–17]. Owing to the advantages of the patterned-sapphire substrate mentioned above, it would be of interest to fabricate the vertical ⇑ Corresponding author. E-mail address: [email protected] (C.Y. Liu). 0026-2714/$ - see front matter Ó 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2010.11.010

thin-GaN LED chips with the GaN LED epi-layers grown on the patterned-sapphire substrate. For fabricating the vertical thin-GaN LED, the GaN LED epi-layers wafer first has to be bonded with a transferring substrate wafer by wafer bonding. Then, the patterned-sapphire substrate wafer would be stripped off. As a result, the GaN LED epi-layers can be transferred onto the desired transferring substrate, such as, Si wafer. How do the vertical thin-GaN LED fabrication processes affect the merits of the GaN LED epilayers on the patterned-sapphire substrate has not yet been studied. For example, after the patterned-sapphire substrate being stripped off, the n-GaN layer with the inverted pattern would become the emitting surface. So, how does the inverted pattern on the n-GaN surface affect the light extraction efficiency (gLEE), is an important issue to be understood. In this study, we fabricate the vertical thin-GaN LED chips with the GaN LED epi-layers grown on the patterned-sapphire substrate and study the effect of the inverted pattern on the performance of the vertical thin-GaN LED. 2. Experimental procedures Numerous patterning features produced on the patterned-sapphire substrate by either dry etching or wet etching processes, which includes circle cavities, square cavities, hemispheric bumps and trenched stripes, have been studied [1,9,18–20]. Yet, no matter what etching process is used to create the patterns, a hard-mask (SiO2 in most cases) lithographic process is required on the flat c-plane sapphire wafer. In this study, a mask-free wet-etching process was used to produce a so-called nature-patterned-sapphire substrate (n-pss). The n-pss wafers was done by immersing planar sapphire wafers into a mixing solution (H3PO4:H2SO4 = 3:1) at 260 °C for 30 min, and 60 min. Fig. 1 shows the SEM image of the

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Fig. 2. The finished structure of a vertical thin-GaN LED chip on the Si substrate.

Fig. 1. SEM image of the pyramidal pattern on the etched sapphire wafer.

facet pyramids on the etched sapphire surface. The height and the width of the pyramid is about 0.2 lm and 1–2 lm, respectively. Then, GaN LED epi-layers were grown on the n-pss wafer with the pyramidal pattern by MOCVD process. The LED epi-layer structure includes a 1.8 lm thick undoped GaN layer and a 2.5 lm thick Si-doped n-type GaN cladding layer, an active region of 450 nm emitting wavelength with six periods of InGaN/GaN multiple quantum wells (MQWs), and a 0.3 lm thick Mg-doped p-type GaN cladding layer. After MOCVD epitaxial process, the GaN epitaxial n-pss wafers are ready for the fabrication processes of the vertical thin-GaN LED chips. For fabricating the vertical-GaN LED structure, an excellent reflective metal layer is essential for the p-contact scheme on the p-GaN layer. Ag is known to have a high reflectivity in the visible regime. Prior to the deposition of the Ag reflective layer, a 20 Å Ni adhesion layer has to be deposited on the p-GaN surface. Then, a 2-lm Ag reflective layer are deposited on the p-GaN surface of the GaN epitaxial/sapphire wafers. Beside the function of the reflective layer the thick 2-lm Ag layer also serves as the bonding layer on the GaN/sapphire wafer side. For the wafer bonding process, the Cu/Sn/Ag bonding system was studied in this present work. On the GaN/sapphire wafer side, 2-lm Ag layer is deposited as the bonding layer to bond with the Si wafer. On the Si wafer side, Cu/Sn bonding metallizations are prepared. The Cu/Sn metallization on the Si wafers were sequentially deposited with a 500-Å Cr adhesion layer, a 500-Å Pt barrier layer, a 500-nm Cu layer, and a 2-lm Sn bonding layer. The above metallization structures were deposited by E-Gun deposition process. The wafer bonding process is described below. First, the Si wafer and GaN/sapphire sapphire wafer with proper bonding metallizations were loaded into a graphite bonding fixture. Both wafers were intimately contacting with a compressive pressure of 2 MPa. Then, the sapphire/Si wafer bonding pair is placed in a vacuum furnace with a base pressure of 5  102 torr at 150 °C for 30– 60 min. After the GaN/sapphire wafer is bonded with the Si wafer, the back-side of the sapphire wafer was irradiated by KrF 248 nm excimer laser. A thin GaN buffer-layer right above the sapphire substrate absorbs the energy of the incident eximer laser and decomposed to Ga droplets and N2 gas. As a result, the GaN epilayer can be striped-off from the initial grown sapphire wafer. The by-product of the Ga metal droplets resided on the n-GaN surface, which would affect the subsequent analysis on the transferred GaN epi-layer. The dilute HCl acid solution (10%) was used to remove Ga droplets on the n-GaN surface. Then, the suitable n-contact metal Cr/Pt/Au pad can be fabricated on the cleaned n-GaN epi-layer. Fig. 2 illustrates the finished structure of a vertical

thin-GaN LED chip on the Si substrate. The chip size is about 1 mm  1 mm. After the process of n-contact pad, the finished LED chips were measured by an integral sphere measurement system. 3. Results and discussions Fig. 3 shows the SEM cross-sectional images on the bonding interface at 150 °C for 30–60 min. The SEM examination result

Fig. 3. The SEM cross-sectional images on the bonding interface at 150 °C for (a) 30 and (b) 60 min.

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suggests that the sapphire epi-wafers can be bonded with the Si wafers by a low-temperature Cu/Sn/Ag wafer bonding system. With a 30-min bonding time, the Sn bonding layer still can be found at the bonding interface. After a prolonged 60-min bonding time, the Sn bonding layer has been completely consumed by the interfacial reaction. The Cu6Sn5 and Ag3Sn are the only two phases can be observed at the boning interface. Fig. 4a and b show the top emitting n-GaN surface of two thinGaN LED chips with different coverage densities of the inverted pyramidal pattern. The insert in Fig. 4a is the enlarged SEM image of an inverted pyramid on the emitting n-GaN surface of the thin-GaN LED chip. Clearly, the shape of the original rectangular pyramids on the n-pss wafer was completely preserved. The light output power of two thin-GaN LED chips with different coverage densities were measured by an integral sphere measurement system. The light output of the thin-GaN LED chip with a higher inverted pyramidal pattern coverage is larger than the light output power of the thin-GaN LED chip with a lower inverted pyramidal pattern coverage by 82.2% at 350 mA input current. We realize that the larger light output of the thin-GaN LED chip with a higher inverted pyramidal pattern coverage could attribute to two factors; (1) the enhancement in the internal quantum efficiency (gIQE); the denser pyramidal pattern on the n-pss wafer possibly encourages more lateral growth of the GaN LED epi-layers and leads to the improvement in the crystalline quality of the MOCVD-grown GaN LED epi-layer. (2) the enhancement in the light extraction efficiency (gLEE) caused by the denser inverted pyramidal pattern on the n-GaN surface. The surface-roughening on the emitting n-GaN surface is an important issue for vertical thin-GaN LED chips [22]. The inverted pyramidal pattern on the

top emitting n-GaN surface could potentially function as roughened surface and enhance the light extraction efficiency. Therefore, the denser inverted pyramidal pattern on the n-GaN surface could promote the light extraction efficiency (gLEE) of the n-GaN emitting surface. The effective light extraction efficiency (gLEE) of the n-GaN emitting surface with the inverted pyramids can be modified as:

gLEE ¼ gLEE;flat ð1  CÞ þ AgLEE;flat C

ð1Þ

where gLEE,flat is the light extraction efficiency of the flat n-GaN emitting surface, A is the enhancing factor defined as the ratio between the light extraction efficiency of the n-GaN emitting surface with the inverted pyramids and the light extraction efficiency of the flat n-GaN emitting surface, and C is the coverage percentage of the inverted pyramidal pattern on the n-GaN emitting surface. Then, the LEE ratio between the thin-GaN LED chip with a higher pyramidal coverage (gLEE,high) and the thin-GaN LED chip with a lower pyramidal coverage (gLEE,low) can be written as:





gLEE;high gLEE;flat ð1  C high Þ þ AC high ¼ gLEE;low gLEE;flat fð1  C low Þ þ AC low g

ð2Þ

where the subscripts of high and low represent the thin-GaN LED chip with a higher pyramidal coverage and the thin-GaN LED chip with a lower pyramidal coverage, respectively. Typically, the product of the internal quantum efficiency (gIQE) and the light extraction efficiency (gLEE), gEQE = gIQE gLEE, counts for the external quantum efficiency (gEQE) of the thin-GaN LED chip. So, the EQE ratio between the thin-GaN LED chip with a higher pyramidal coverage (gEQE,high) and the thin-GaN LED chip with a lower pyramidal coverage (gEQE,low) can be equated as:





gEQE;high gIQE;high gLEE;flat ð1  C high Þ þ AC high ¼  gEQE;low gIQE;low gLEE;flat fð1  C low Þ þ AC low g

ð3Þ

The enhancing factor, A, for the light extraction efficiency of the inverted pyramids on the n-GaN emitting surface can deduced to be about 3.38 from the Sun’s simulation results [21]. Previously, we have shown that the light output of the thin-GaN LED chip with a higher inverted pyramidal pattern coverage is larger than the light output power of the thin-GaN LED chip with a lower inverted pyramidal pattern coverage by 82.2% at 350 mA input current. Generally, the light output is corresponding to the external quantum efficiency (EQE). So, the EQE ratio between the thin-GaN LED chips with a higher and a lower pyramidal pattern coverage would to be 1.822 at 350 mA input current. From Fig. 4a and b, the coverage percentages of the inverted pyramidal pattern on the n-GaN emitting surface of the two thin-GaN chips are estimated to be 13.6% and 53.8%, respectively. Plug in the above obtained parameters into Eq. (3), then, the gIQE ratio between the thin-GaN LED chips with a higher and a lower pyramidal pattern coverage can be obtained to be about 1.057. It means that the internal quantum efficiency of the GaN LED epi-layer grown on the n-pss wafer with a higher pyramidal pattern coverage (53.8%) is larger than that of the GaN epi-layer grown on the n-pss wafer with a lower pyramidal pattern coverage (13.6%) by about 5.7%. It is equivalent to saying that the higher pyramidal pattern coverage indeed can result in a better epitaxial quality of GaN epi-layer, i.e., internal quantum efficiency. Yet, surprisingly, the 4-fold increase in the pyramidal pattern coverage (increasing from 13.6% to 53.8%) on the n-pss wafer only enhanced the internal quantum efficiency by about 5.7%. 4. Conclusions

Fig. 4. (a) SEM image of n-GaN surface after laser lift-off with a lower pyramidal pattern coverage. (b) SEM image of GaN surface after laser lift-off with a higher pyramidal pattern coverage.

In conclusion, the GaN LED epi-layer grown on pyramidsapphire surface was successfully fabricated into vertical thinGaN LED chips. The present results show that the original pyramidal pattern on the n-pss wafer resulted in an inverted pyramidal

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pattern on the top emitting n-GaN surface of the thin-GaN LED chip after the epi-layer transferring. The inverted pyramidal pattern has an equivalent function with the surface roughening process, which can greatly enhance the light extraction efficiency. Yet, surprisingly, the 4-fold increase in the pyramidal pattern coverage (increases from 13.6% and 53.8%) only enhanced the internal quantum efficiency by about 5.7%. Acknowledgement The authors would like to acknowledge the financial support of the National Science Council (NSC). References [1] Hsu SC, Liu CY. Fabrication of thin-GaN LED structures by Au–Si wafer bonding. Electrochem Solid State Lett 2006;9:G171–3. [2] Chen PH, Lin CL, Liu YK, Chung TY, Liu CY. Diamond heat spreader layer for high-power thin-GaN light-emitting diodes. IEEE Photon Technol Lett 2008;20:845–7. [3] Chang CL, Chuang YC, Liu CY. Ag/Au diffusion wafer bonding for thin-GaN LED fabrication. Electrochem Solid State Lett 2007;10:H344–6. [4] Lee CE, Lee YC, Kuo HC, Lu TC, Wang SC. Further enhancement of nitride-based near-ultraviolet vertical-injection light-emitting diodes by adopting a roughened mesh-surface. IEEE Photon Technol Lett 2008;20:803–5. [5] Koike M, Shibata N, Kato H, Takahashi Y. Development of high efficiency GaNbased multiquantum-well light-emitting diodes and their applications. IEEE J Sel Top Quantum Electron 2001;8:271–7. [6] Lydecker SH, Leadford KF, Ooyen CA. Lighting industry acceptance of solid state lighting. Proc SPIE 2004;5187:22–33. [7] LEDs magazine, 21 December 2006. . [8] Narukawa Y, Narita J, Sakamoto T, Deguchi K, Yamada T, Mukai T. Ultra-high efficiency white light emitting diodes. Jpn J Appl Phys 2006;45:L1084–6. [9] Lee YJ, Kuo HC, Lu TC, Su BJ, Wang SC. Fabrication and characterization of GaNbased LEDs grown on chemical wet-etched patterned sapphire substrates. J Electrochem Soc 2006;153:G1106–11.

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