Sensors and Actuators A 97±98 (2002) 215±220
Fabrication, RF characteristics and mechanical stability of self-assembled 3D microwave inductors Gerald W. Dahlmanna,*, Eric M. Yeatmana, Paul Youngb, Ian D. Robertsonb, Stepan Lucyszyna a
Department of Electrical and Electronic Engineering, Imperial College, Exhibition Road, London SW7 2BT, UK b School of Electronics, Computing and Mathematics, University of Surrey, Guildford GU2 7XH, UK Received 11 June 2001; received in revised form 30 October 2001; accepted 4 December 2001
Abstract We present a method for the fabrication of vertical inductors for radio-frequency and microwave applications. This process uses ®ve levels of lithography and electroplating, with no substrate removal, high temperatures or serial process steps. Rotation of the inductors perpendicular to the substrate is achieved by surface tension driven self-assembly, giving separation from the substrate and therefore increasing substantially the Q and self-resonant frequencies. Meander and spiral air-bridged inductors of up to 5.5 nH are demonstrated. The Q of 2 nH inductors shows an increase from 4 to 20 after having undergone the self-assembly process. Mechanical sensitivity is evaluated through ®nite element modelling, and the maximum displacements indicated are below 10 nm for 1 g of loading. Mechanical resonance frequencies are found within the 6±15 kHz range. # 2002 Elsevier Science B.V. All rights reserved. Keywords: RF-MEMS; High-Q inductors; Self-assembly
1. Introduction One important limitation in achieving higher levels of integration and further reduction of fabrication costs in the front-end of microwave transceivers is set by the dif®culty of achieving high-Q in microwave on-chip inductors. This is because an inductor coil in proximity to the semiconductor substrate tends to produce excessive losses at frequencies above 1 GHz, and moreover, parasitic capacitance between coil and substrate causes self-resonance and thus restricts the frequency range of operation. Recent progress in micromachining techniques, however, has brought about some novel approaches to overcome these limitations. Most of these approaches are based on creating physical separation between the inductor coil and the lossy semiconductor substrate. For instance, research groups have investigated fabrication methods employing thick dielectric layers [1], using multiple CMOS metallisation layers in parallel [2], patterned ground shields [3,4], air-bridged coils [5], or removing the substrate underneath the coil, which can either be done from the backside, leaving the inductor on a membrane [6], or from the frontside, leaving the inductor *
Corresponding author. Tel.: 44-20-7594-6260; fax: 44-20-7594-6308. E-mail address:
[email protected] (G.W. Dahlmann).
suspended [7,8]. A recently published work has shown that etching substrate trenches in between the tracks of the coil [9] leads to a signi®cant performance improvement as well, when applied on high resistivity silicon substrate. More advanced techniques have been proposed, including the fabrication of solenoid coils using a 3D-lithography technique [10] and self-assembly using an upward buckling lifting mechanism actuated by scratch drives [11]. An approach that is similar to the one presented in this paper is based on self-assembly in a magnetic ®eld, where inductors are rotated away from the substrate by plastic deformation of the anchor hinges [12]. In this case, the coils are coated with permalloy to allow the actuation mechanism to function, which introduces some additional loss. Very recently, a group from Georgia Institute of Technology has presented a power ampli®er [13] with post-processed MEMS solenoid inductors, fabricated using thick photoresist lithography [14]. These techniques generally have some limitations; either in not providing suf®cient separation, or in involving fabrication methods which are disadvantageous because they involve non-parallel process steps, or because they are not fully compatible with pre-processed electronic devices or standard electronic processing. The approach described in this paper, using self-assembly to achieve separation between substrate and inductor, has a
0924-4247/02/$ ± see front matter # 2002 Elsevier Science B.V. All rights reserved. PII: S 0 9 2 4 - 4 2 4 7 ( 0 1 ) 0 0 8 5 1 - 2
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number of features which may be advantageous. Firstly, a very substantial separation between substrate and coil can be achieved (up to several hundred micrometres), without the need for deep etching, or lithography over deep topography created by previous steps. Secondly, the fabrication process is entirely parallel, and has a low peak process temperature. It is not speci®c to any particular substrate type, and may be suitable as a post-process for RFICs or MMICs. 2. Fabrication The fabrication process is based on a self-assembly technique developed previously by our group [15±17]. Fig. 1 outlines the principle: structures are fabricated in a planar batch process with a meltable hinge pad placed between a substrate anchor and a released portion of the device. Subsequently, the hinge pads are melted and surface tension force rotates the released portion of the device out of the substrate plane. The folding angle at which the structure reaches the equilibrium of the occurring forces is determined by the dimensions of the hinge pads. Once this equilibrium position is reached, the structures are cooled down, the hinges resolidify, and thus the ®nal position is ®xed. Initially, a process was investigated in which the inductors were deposited directly onto the substrate (with a thin intervening insulating layer of SiO2), by plating copper into photoresist moulds. Solder (Pb±Sn) hinges were also plated in a second photoresist layer. This involved only two mask layers, with meander inductor geometries avoiding the need for crossovers in the electrical path. Release from the substrate was achieved by wet etching of the oxide layer, followed by anisotropic etching of the Si substrate in tetramethyl ammonium hydroxide (TMAH), and the de®nition of released and unreleased parts of the copper structure was determined by the presence or absence of etch access holes in the conventional manner. This approach illustrates a critical dif®culty in this system, which is to obtain etch compatibility given the range of materials. More speci®cally, a suitable etchant for Si which does not attack the much more reactive Pb±Sn hinge was not identi®ed; TMAH gave the best results, but these were still not satisfactory as can be seen in Fig. 2. Oxidation quickly consumes the hinge,
Fig. 1. Self-assembly technique.
Fig. 2. Solder hinge region after TMAH etch.
which has a large surface-to-volume ratio, and then interferes with the subsequent melting step. The deteriorated hinges are also mechanically weak, leading to detachment of the inductor structure. Furthermore, substrate etching is not well suited to postprocessing on integrated circuits, and does not allow the use of the substrate real-estate below the inductor in these circuits. In addition, meander inductors provide low inductance for a given area, so that a multiple layer process with air-bridging capabilities was needed, so that spiral coils could be implemented. Fig. 3 shows the process sequence which we have developed. An intermediate process reported in [18] adds an
Fig. 3. Fabrication process sequence.
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Fig. 4. Self-assembled meander inductors (L 2 nH).
additional copper layer under the inductor tracks for mechanical support, so that photoresist is used as the sacri®cial layer and substrate etching is avoided. This allowed the fabrication of vertical meander inductors (Fig. 4). Here, two additional lithography and plating levels have successfully been implemented to provide the airbridge; in total, ®ve photolithography steps are involved, each providing a mould for electroplating (four in copper and one in solder), with the solder and third copper levels being coplanar. All sacri®cial photoresist is removed by boiling in solvent. The low stress levels achieved in the plated layers avoids deformation after release, in which stiction is avoided by the use of freeze-drying. Low resistivity (1±10 O cm) silicon substrates were used in all cases. Each of the three copper layers which build up the coil is about 7 mm in height, resulting in a total structural height of just over 20 mm. Fig. 5 shows a three-turn spiral inductor folded to 908, separated from the substrate by about 300 mm at the centre of the coil. Figs. 6 and 7 show the hinge pads before and after self-assembly. The improved quality of the hinge material after subsequent processing is clear with comparison to Fig. 2. Re¯ow of the solder hinges is carried out at just above the eutectic melting temperature of 183 8C, which is the highest temperature in the process. All process steps are fully parallel, and could be carried out on fully
217
Fig. 6. Solder hinge region before self-assembly.
Fig. 7. Solder hinge region after self-assembly.
processed CMOS (or other) wafers, with appropriate vias in the passivation layer for electrical contact. Since no etching of the substrate is required, and with the high degree of separation provided by this technique, use of the wafer area directly under the pre-rotated inductors for the active circuit should be possible. 3. Results 3.1. RF characterisation
Fig. 5. Self-assembled spiral inductor (L 3:5 nH).
High frequency characteristics of inductors have been obtained from measurements using the Agilent 8510XF vector network analyser. The measured results include a strong loading effect from the feedlines used for probing, as these are separated from the low resistivity Si substrate by only a thin (0.1 mm) oxide layer and so have a high capacitance to the substrate. The subsequent de-embedding is based on a SONNET model of the feedlines which is adjusted to measurements of the feedlines in open and short circuit con®guration. The two-port data obtained from the model is then used to compute the net characteristics of the inductor.
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Table 1 Geometric and RF characteristics for different inductor geometries Type
Outer coil dimensions (mm)
Track width (mm)
Track spacing (mm)
L (nH)
Qmax
fpeak (GHz)
Three-turn meander Four and a half-turn meander Six-turn meander Two-turn spiral Three-turn spiral Four-turn spiral
360 360 360 360 360 360 360 360 360 360 360 360
40 24 17 40 24 17
40 24 17 40 24 17
1.5 2.0 2.5 2.0 3.5 5.5
17 20 13 NA NA NA
3.5 3 3 NA NA NA
Table 1 summarises the geometry and RF characteristics of different versions of the meander inductor. We are currently also characterising the spiral inductors, but reliable data is not available yet; the loading by the feedlines is in this case rather more severe, as the higher inductance values combine with the parasitic capacitance to greatly lower the self-resonance frequency. Improved feedline geometries are under development. These will also seek to reduce the loading effect of the hinges and anchors. Inductance values ranging from 1.5 to 5.5 nH have been realised. The highest Q measured so far has been just above 20 for a 2 nH meander inductor [19]. The ef®ciency of the self-assembly technique towards improving the inductor performance is demonstrated by measuring the peak Q as a function of the folding angle. A 2 nH meander inductor which is released from the substrate, but not self-assembled, yields a peak Q of 4 at 1 GHz, while the same inductor has a peak Q of 20 at 3 GHz, when folded to 908. 3.2. Mechanical stability Mechanical stability and robustness are possible concerns for these structures, which are effectively cantilevered to the substrate by the solder hinges. However, mechanical shock and vibration will cause deforming forces by applying a relative acceleration between the suspended structure and the substrate, and the associated force for any part of the structure will be determined by this acceleration multiplied by its mass. Because the masses of micro-engineered structures are very small, the forces are also small, and so their tolerance of shock and vibration is high. Practical evidence for this comes from handling of dies with the free standing inductors, where only the most severe handling, i.e. direct physical impact with the vertical structures, has been seen to cause damage. Since this evidence is not systematic, a
simpli®ed analytical model for the meander geometries was derived, based on a straight beam equal to the total path length of the meander. This model predicts maximum displacements of up to 0.3 mm for 1 g (gravitational) acceleration. However, this model greatly exaggerates the deformation, as the meandering of the beam adds greatly to its stiffness. More accurate results were obtained using mechanical ®nite element modelling (ANSYS), initially to predict the deformation caused by static acceleration of the substrate. The results are given in Table 2, with an example of the deformation distribution in Fig. 8. Maximum displacement is less than 10 nm for 1 g loading, and the maximum stresses are orders of magnitude below the yield strength of copper (400 MPa). While these results indicate that static loads encountered in operation should not cause signi®cant alteration to electrical properties, dynamic loading is likely to be more signi®cant, as the maximum displacement will be signi®cantly higher for loads at the mechanical resonance frequencies. ANSYS modelling was also used to ®nd the frequencies of the lower order resonant modes for different meander lengths, and these are also given in Table 2. Fig. 9 shows an example of the mode shape for the ®rst (lowest frequency) mode. The resonances are found to be in the higher audio range from 6 to 18 kHz; noise at these frequencies is likely to be less prevalent and more easily blocked by appropriate mounting than vibrations below 1 kHz, but raising the frequencies to the ultrasonic range, e.g. by increasing metallisation thickness, should give reduced sensitivity. Deformation amplitudes will be increased by the quality factor Q of the mechanical resonances. Taking Q, from typical reported values for MEMS (in air), to be in the few hundreds range, we can estimate that maximum displacements could be up to about 1 mm for vibrations at resonant frequencies of magnitude 1 g (at the chip). At such levels some noticeable electrical noise could
Table 2 Mechanical characteristics of meander type inductors Type
Maximum deformation per g (nm)
Maximum stress per g (kPa)
First mechanical self-resonant frequency (kHz)
Second mechanical self-resonant frequency (kHz)
Third mechanical self-resonant frequency (kHz)
Three-turn meander Four and a half-turn meander Six-turn meander
4.3 5.5 9.8
33 39 54
9.7 7.4 6.0
12.8 9.3 7.2
17.6 15.1 12.4
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for additional strengthening, and like many MEMS structures, may not be compatible with plastic encapsulation packaging. However, the approach can be thought of as a generic one for high aspect ratio metal structures, for which other applications besides inductors are anticipated.
Acknowledgements
Fig. 8. Contour plot of deformation under static mechanical loading of 1 g acceleration.
We are grateful for ®nancial support by the UK Engineering and Physical Science Research Council. Furthermore, we would like to thank R.R.A. Syms and K.W. Lee for their assistance in obtaining the results presented in this paper.
References
Fig. 9. Shape of first mechanical self-resonant mode.
result, and therefore measures could be needed in packaging to limit such effects. However, permanent deformation remains unlikely except for very violent mechanical disturbances. 4. Conclusion Surface tension driven self-assembly has been demonstrated as a possible technique for adding high-Q inductors to electronic circuits. Fabrication can be achieved by a fully parallel process, which should be compatible with postprocessing on CMOS or other electronic wafers. ANSYS modelling indicates that the deformation of such vertical structures by static mechanical shock or vibration off resonance is likely to be negligible; however, acoustic noise at the mechanical resonance frequencies of the structure could cause signi®cant dynamic variation of electrical parameters. The structures will present some special challenges and requirements for packaging, which may include the need
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Biographies Gerald W. Dahlmann was born in Frankfurt am Main, Germany, in 1972. He received his Masters degree in electrical engineering from Technical University of Darmstadt, Germany, and from Ecole Centrale de Lyon, France in 1998. He then joined the Optical and Semiconductor Devices Group at Imperial College, London, UK, where he is currently studying towards a PhD. His research interests include MEMS RF passives, switches and phase shifters as well as surface micromachining and assembly techniques for metallic microstructures. Eric M. Yeatman obtained his PhD from Imperial College in 1989. Since then he has been a member of staff in the college's Electrical and
Electronic Engineering Department, Optical and Semiconductor Devices Group, currently as deputy head of group. He has published and lectured widely on integrated optics, optical devices and materials, and microstructure fabrication. His current research includes microstructures for microwave applications, integrated optics for communication networks and scanners, and micromechanical actuators. Paul Young obtained his PhD from the University of Kent at Canterbury in the area of electromagnetic analysis of dielectric waveguides. Since 2000, he has been Lecturer in electronics at the University of Kent. His research interests are in microwave and millimetre-wave measurements, electromagnetic modelling of passive millimetre-wave devices and transmission lines, and the application of MEMS technology for microwave and millimetre-wave devices. Ian D. Robertson is currently a Professor of microwave subsystems engineering at the University of Surrey, UK. He has been involved in the design of over 200 MMICs on 30 wafer runs and has authored/co-authored over 280 papers. His interests are in the design and applications of RFICs and MMICs. He is Honorary Editor of IEE ProceedingsÐMicrowaves, Antennas and Propagation. Stepan Lucyszyn was born in Bradford, England, in 1965. He received his Bachelors degree in electronic and communication engineering from the Polytechnic of North London in 1987. In his final year, he was awarded The 1987 Departmental Prize. The following year he went on to gain a Masters degree in Satellite Communication Engineering from the University of Surrey. This was then followed by a year in the British and French space industries, working as a consultant on a broad range of projects. In 1992, he received his PhD in electronic engineering from the University of London (King's College). He then went on to become a Post-doctoral Researcher Fellow at King's College London. There he adapted his PhD research to investigate advanced microwave analogue signal processing. At the University of Surrey, Stepan was appointed as a Lecturer in RF Electronics in August 1995, and then promoted to Senior Lecturer in April 2000. In June 2001, he joined Imperial College (University of London) as Senior Lecturer, working within the optical and semiconductor devices group.