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Factors controlling the reservoir accumulation of Triassic Chang 6 Member in Jiyuan-Wuqi area, Ordos Basin, NW China
Tu3H-1 A 38-GHz-Band Power Amplifier with Analog Pre-distortion for 1600MHz Transmission Bandwidth 64-QAM OFDM Modulated Signal Yu-Chun Chen#1, Tsung-Ching Tsai#, Jeng-Han Tsai*, Tian-Wei Huang#2 # Graduate Institute of Communication Engineering, National Taiwan University, Taipei, Taiwan * Department of Electrical Engineering, National Taiwan Normal University, Taipei, Taiwan 1 [email protected], [email protected] Abstract—A 38-GHz-band transformer based high linear power amplifier with analog pre-distortion for wideband modulated signal in 65-nm GP CMOS process is presented in this paper. The output power is based on the two-way transformer current combining structure. The driver amplifier which is biased in deep class-AB acts as an AM-AM pre-distorter to produce better OP1dB and improve the third order intermodulation distortion (IMD3). Also a PMOS capacitor is used to compensate the AM-PM distortion of the input capacitor at the driver stage. In the continuous-wave measurement, this power amplifier achieves 14.4-dB small-signal power gain, 20.7dBm PSAT, 35% PAEMAX, 20.2-dBm OP1dB, and 32.8% PAE1dB at 39 GHz. In the modulated signal measurement, this power amplifier achieves 13.2-dBm output power, 7.1% PAE, and EVM < -25 dBc at 1600-MHz channel bandwidth of 64-QAM OFDM with 38-GHz carrier frequency. The highest transmission data rate of the proposed power amplifier reaches up to 6.98 Gb/s. Keywords—power amplifiers, predistortion, 5G mobile communication, CMOS integrated circuits, quadrature amplitude modulation, millimeter wave integrated circuits.
II. CIRCUIT DESIGN The schematic of the proposed power amplifier is shown as Fig. 1. The circuit design is two-stage transformer based power amplifier. Each stage contains a common source differential pair with capacitive neutralization to make the transistor stable and to obtain higher power gain, output power, and PAE [1], [2], [9]. In the power stage, current-combining topology is adopted to get larger power. In the interstage transformer matching, two transformer based baluns are used to split the differential output of the driver stage to drive the power stage.
I. INTRODUCTION Next generation wireless communication will be widely used in the millimeter wave band above 24 GHz to get higher transmission rate (e.g. Gb/s). Among these bands, the 28 GHz and 38 GHz bands will be the main bands used in mobile communications. For a transceiver, a key issue is how to design high linearity and high efficiency power amplifiers in these bands [1], [2], [3]. In order to achieve a higher data rate, high order digital modulation (e.g. 64-QAM and 256-QAM) with OFDM is used. However, complex digital modulation usually has a higher peak-to-average-power-ratio (PAPR), so in order to avoid signal distortion, the power amplifier must operate in the linear power region. Therefore, improving the output power and efficiency of the power amplifier in the linear region is a very important issue in circuit design. In previous studies [1], [2], [6], [7], it has been shown that to achieve wide-band digital modulation in the design of power amplifiers, it is necessary to have less AM-AM and AM-PM distortion in a wide-band transmission channel. In this paper, an analog pre-distortion power amplifier for wideband digital modulation signal in the 38GHz band is proposed without any digital pre-distortion. In section II, the method of the circuit design will be discussed. In section III, the process and results of the circuit measurement will be presented. Also, in section IV, the characteristics of the circuit will be integrated.
978-1-7281-1309-8/19/$31.00 © 2019 IEEE
Fig. 1. Circuit schematic
The power stage is biased in high class-AB. The total gate width of the power stage is 768 μm and its value of the neutralization capacitance is 53 fF. The capacitive neutralization using a metal M5 to M9 interdigital structure allows a more compact layout. With the load pull simulation, the highest intrinsic device PAE and output power are 55.9% and 22.6-dBm at 38 GHz. The driver stage is biased in the deep class-AB region which provides AM-AM pre-distortion and improves the IMD3 [4]. The total gate width of the driver stage is 224 μm and its biased region is shown in Fig. 2. The driver stage biased in deep class-AB region is used for AM-AM pre-distortion. It enables higher linear power and PAE. However, it causes more AM-PM distortion due to the non-linear input capacitance at the driver stage. In Fig. 3, by using the AM-AM pre-distortion, the OP1dB of the power amplifier is improved from 16.8 dBm to 19.8 dBm. But the AM-PM distortion is increased by about 7 deg. In order to overcome AM-PM distortion, the PMOS capacitance is used to compensate the variation of the input capacitance from input voltage swing [2], [5]. And, in the previous research [2],
312
2019 IEEE/MTT-S International Microwave Symposium
the coupling factor of the interstage transformer matching plays a key role in the broadband AM-PM distortion. The interstage and input matching are implemented by using transformer structure with a coupling factor of 0.5-0.6 to obtain less AM-PM distortion for the frequency response. The overall effect of the AM-PM pre-distortion by adding PMOS capacitance is shown in Fig. 4. The best bias of the AM-PM pre-distortion is 1.4V.
In the bias network design, the two path on chip bypass network is used at the drain bias to overcome the memory effect which causes the asymmetric AM-AM and AM-PM of the IMD3 while the two path on chip bypass network at the gate bias is used to avoid the oscillation of the power amplifier [2], [10]. III. MEASUREMENT RESULT The chip layout and micrograph under the on-wafer measurement is shown in Fig. 5 and Fig. 6. The chip size including the PADs is 640×685 μm2. The 6-pin PGPPGP DC probes are set on the top and bottom of the chip, and the 3-pin GSG RF probes are set on the left and right of the chip. The power supply voltage is 1.2V. S-parameters are measured with Keysight N5247A network analyzer. The simulation and measurement results are shown in Fig. 7. The small-signal half power gain bandwidth is from 33 GHz to 41 GHz, and the peak small-signal gain is 14.4-dB at 39 GHz.
Fig. 2. Driver stage biased region
Fig. 5. Chip layout
Fig. 3. AM-AM pre-distortion at 38 GHz
Fig. 6. Chip micrograph under the on-wafer measurement
Fig. 4. AM-PM pre-distortion at 38 GHz
Fig. 7. Simulated and measured S-parameters
313
In the large-signal measurement, input power is produced from Agilent E8257D analog signal generator, and the received power is carefully measured with Agilent E4448A spectrum analyer. The single tone large-signal simulation and measurement results are shown in Fig. 8 and Fig. 9. At the 39 GHz, this power amplifier provides 14.4-dB small-signal power gain, 20.7-dBm PSAT, 35% PAEMAX, 20.2-dBm OP1dB, and 32.8% PAE1dB. The two-tone large-signal measurements for the IMD3 with different frequency spacing from 100-MHz to 1600-MHz are shown in Fig. 10 and Fig. 11. In the Fig. 10 and Fig. 11, the IMD3 is clearly improved for the frequency spacing of 100-1600 MHz. Fig. 11. Measured the IMD3 at upper side band
The modulated signal measurement is setup with Agilent M8190A arbitrary waveform generator, Keysight E8267D vector signal generator, and Keysight DSA-Z334A oscilloscope. The power amplifier is measured under a 64QAM OFDM modulated signal with 9.8-dB PAPR, 1600MHz channel bandwidth, and 38-GHz carrier frequency. The power amplifier achieves 13.2-dBm output power and 7.1% PAE with an EVM of less than -25 dBc in the measurement shown in Fig. 12 and Fig. 13. In Fig. 13, it can be clearly found that the output power by using analog pre-distortion technique in the power amplifier is increased from 10 dBm to 13.2 dBm in the high order digital modulation compared to the traditional class A power amplifier.
Fig. 8. Simulated and measured large-signal at 39GHz
(a)
(b)
Fig. 12. (a) Measured constellation; (b) channel bandwidth Table 1. Comparison table of the modulated signal measurements. Fig. 9. Measured Pout and PAE vs. frequency
Ref.
This work
[2]
[3]
[1]
Tech.
65-nm CMOS
28-nm CMOS
40-nm CMOS
28-nm CMOS
38
34
27
30
1600
1350
800
250
Modulated Signal
64-QAM OFDM
64-QAM
64-QAM OFDM 8-CC
64-QAM OFDM
PAPR [dB]
9.8
8.3
9.7
9.6
PAE [%]
7.1
2.3
11
9
Pout [dBm]
13.2
5.9
6.7
4.2
Carrier Frequency [MHz] Transmission Bandwidth [MHz]
Fig. 10. Measured the IMD3 at lower side band
314
Table 2. Comparison table of the continuous-wave measurements.
PSAT [dBm] 20.7
PAEMAX [%] 35
OP1dB [dBm] 20.2
PAE1dB [%] 32.8
Core Area 2 [mm ]
18
16.6
24.2
13.4
12.6
0.16
15.8
15.6
41
14
34.7
0.24
20.8
15.3
32.9
12.9
N/A
0.11
27
22.4
15.1
33.7
13.7
31.1
0.23
27
20.5
18.1
41.5
16.8
37.6
0.36
30
15.7
14
35.5
13.2
34.3
0.16
Ref.
Tech.
This work
65-nm CMOS
Freq. [GHz] 39
[2]
28-nm CMOS
30
[7]
65-nm CMOS
28
[8]
65-nm CMOS
32
[3]
40-nm CMOS
[9]
40-nm CMOS
[1]
28-nm CMOS
Gain [dB] 14.4
0.21
[6]
28-nm CMOS
28
13.6
19.8
43.3
18.6
41.4
0.28
[11]
65-mn CMOS
28
8.9
14.4
40.1
13.6
37.2
0.11
[12]
45-nm SOI CMOS
39
10.5
18.5
41.2
16.3
N/A
0.14
[13]
65-nm CMOS
34
13.8
19.9
25.8
17
14.5
0.37
[3]
[4]
[5]
[6]
[7] Fig. 13. EVM versus output power
IV. CONCLUSION The comparison tables of the modulated signal and continuous-wave measurement are shown in Table 1 and Table 2. In the continuous-wave measurement, the proposed power amplifier provides 20.2-dBm OP1dB with 32.8% PAE. In the modulated signal measurement, the proposed power amplifier achieves 13.2-dBm output power and 7.1% PAE on 64-QAM OFDM modulated signal with the 1600-MHz channel bandwidth and 9.8-dB PAPR in Table 1. The proposed power amplifier with analog pre-distortion has high linear output power and high efficiency for the wideband digital modulated signal. The highest transmission data rate of the proposed power amplifier reaches up to 6.98 Gb/s.
[8]
[9]
[10]
[11]
[12]
REFERENCES [1] S. Shakib, H. Park, J. Dunworth, V. Aparin and K. Entesari, "A highly efficient and linear power amplifier for 28-GHz 5G phased array radios in 28-nm CMOS," IEEE Journal of Solid-State Circuits, vol. 51, no. 12, pp. 3020-3036, Dec. 2016. [2] M. Vigilante and P. Reynaert, "A wideband class-AB power amplifier with 29–57-GHz AM–PM compensation in 0.9-V 28-nm bulk CMOS,"
315
[13]
IEEE Journal of Solid-State Circuits, vol. 53, no. 5, pp. 1288-1301, May 2018. S. Shakib, M. Elkholy, J. Dunworth, V. Aparin and K. Entesari, "A wideband 28GHz power amplifier supporting 8×100MHz carrier aggregation for 5G in 40nm CMOS," in IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2017, pp. 44-45. C. Fager, J. C. Pedro, N. B. de Carvalho, H. Zirath, F. Fortes and M. J. Rosario, "A comprehensive analysis of IMD behavior in RF CMOS power amplifiers," IEEE Journal of Solid-State Circuits, vol. 39, no. 1, pp. 24-34, Jan. 2004. C. Wang, L. E. Larson and P. M. Asbeck, "A nonlinear capacitance cancellation technique and its application to a CMOS class AB power amplifier," in IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Phoenix, AZ, USA, 2001, pp. 39-42. B. Park, Daechul Jeong, J. Kim, Y. Cho, Kyunghoon Moon and B. Kim, "Highly linear CMOS power amplifier for mm-wave applications," in IEEE MTT-S International Microwave Symposium (IMS), San Francisco, CA, 2016, pp. 1-3. S. N. Ali, P. Agarwal, J. Baylon, S. Gopal, L. Renaud and D. Heo, "A 28GHz 41%-PAE linear CMOS power amplifier using a transformerbased AM-PM distortion-correction technique for 5G phased arrays," in IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2018, pp. 406-408. H. Jia, C. C. Prawoto, B. Chi, Z. Wang and C. P. Yue, "A full Ka-Band power amplifier with 32.9% PAE and 15.3-dBm power in 65-nm CMOS," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 9, pp. 2657-2668, Sept. 2018. Y. Zhang and P. Reynaert, "A high-efficiency linear power amplifier for 28GHz mobile communications in 40nm CMOS," in IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Honolulu, HI, 2017, pp. 33-36. J. P. Martins, P. M. Cabral, N. Borges Carvalho and J. C. Pedro, "A metric for the quantification of memory effects in power amplifiers," IEEE Transactions on Microwave Theory and Techniques, vol. 54, no. 12, pp. 4432-4439, Dec. 2006. S. N. Ali et al., "A 40% PAE frequency-reconfigurable CMOS power amplifier with tunable Gate–Drain neutralization for 28-GHz 5G Radios," IEEE Transactions on Microwave Theory and Techniques, vol. 66, no. 5, pp. 2231-2245, May 2018. T. Li and H. Wang, "A continuous-mode 23.5-41GHz hybrid class-F/Fl power amplifier with 46% peak PAE for 5G massive MIMO applications," in IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Philadelphia, PA, 2018, pp. 220-230. S. Chang, C. Chen and H. Wang, "A Ka-Band dual-mode power amplifier in 65-nm CMOS technology," IEEE Microwave and Wireless Components Letters, vol. 28, no. 8, pp. 708-710, Aug. 2018.
II. CIRCUIT DESIGN The schematic of the proposed power amplifier is shown as Fig. 1. The circuit design is two-stage transformer based power amplifier. Each stage contains a common source differential pair with capacitive neutralization to make the transistor stable and to obtain higher power gain, output power, and PAE [1], [2], [9]. In the power stage, current-combining topology is adopted to get larger power. In the interstage transformer matching, two transformer based baluns are used to split the differential output of the driver stage to drive the power stage.
I. INTRODUCTION Next generation wireless communication will be widely used in the millimeter wave band above 24 GHz to get higher transmission rate (e.g. Gb/s). Among these bands, the 28 GHz and 38 GHz bands will be the main bands used in mobile communications. For a transceiver, a key issue is how to design high linearity and high efficiency power amplifiers in these bands [1], [2], [3]. In order to achieve a higher data rate, high order digital modulation (e.g. 64-QAM and 256-QAM) with OFDM is used. However, complex digital modulation usually has a higher peak-to-average-power-ratio (PAPR), so in order to avoid signal distortion, the power amplifier must operate in the linear power region. Therefore, improving the output power and efficiency of the power amplifier in the linear region is a very important issue in circuit design. In previous studies [1], [2], [6], [7], it has been shown that to achieve wide-band digital modulation in the design of power amplifiers, it is necessary to have less AM-AM and AM-PM distortion in a wide-band transmission channel. In this paper, an analog pre-distortion power amplifier for wideband digital modulation signal in the 38GHz band is proposed without any digital pre-distortion. In section II, the method of the circuit design will be discussed. In section III, the process and results of the circuit measurement will be presented. Also, in section IV, the characteristics of the circuit will be integrated.
978-1-7281-1309-8/19/$31.00 © 2019 IEEE
Fig. 1. Circuit schematic
The power stage is biased in high class-AB. The total gate width of the power stage is 768 μm and its value of the neutralization capacitance is 53 fF. The capacitive neutralization using a metal M5 to M9 interdigital structure allows a more compact layout. With the load pull simulation, the highest intrinsic device PAE and output power are 55.9% and 22.6-dBm at 38 GHz. The driver stage is biased in the deep class-AB region which provides AM-AM pre-distortion and improves the IMD3 [4]. The total gate width of the driver stage is 224 μm and its biased region is shown in Fig. 2. The driver stage biased in deep class-AB region is used for AM-AM pre-distortion. It enables higher linear power and PAE. However, it causes more AM-PM distortion due to the non-linear input capacitance at the driver stage. In Fig. 3, by using the AM-AM pre-distortion, the OP1dB of the power amplifier is improved from 16.8 dBm to 19.8 dBm. But the AM-PM distortion is increased by about 7 deg. In order to overcome AM-PM distortion, the PMOS capacitance is used to compensate the variation of the input capacitance from input voltage swing [2], [5]. And, in the previous research [2],
312
2019 IEEE/MTT-S International Microwave Symposium
the coupling factor of the interstage transformer matching plays a key role in the broadband AM-PM distortion. The interstage and input matching are implemented by using transformer structure with a coupling factor of 0.5-0.6 to obtain less AM-PM distortion for the frequency response. The overall effect of the AM-PM pre-distortion by adding PMOS capacitance is shown in Fig. 4. The best bias of the AM-PM pre-distortion is 1.4V.
In the bias network design, the two path on chip bypass network is used at the drain bias to overcome the memory effect which causes the asymmetric AM-AM and AM-PM of the IMD3 while the two path on chip bypass network at the gate bias is used to avoid the oscillation of the power amplifier [2], [10]. III. MEASUREMENT RESULT The chip layout and micrograph under the on-wafer measurement is shown in Fig. 5 and Fig. 6. The chip size including the PADs is 640×685 μm2. The 6-pin PGPPGP DC probes are set on the top and bottom of the chip, and the 3-pin GSG RF probes are set on the left and right of the chip. The power supply voltage is 1.2V. S-parameters are measured with Keysight N5247A network analyzer. The simulation and measurement results are shown in Fig. 7. The small-signal half power gain bandwidth is from 33 GHz to 41 GHz, and the peak small-signal gain is 14.4-dB at 39 GHz.
Fig. 2. Driver stage biased region
Fig. 5. Chip layout
Fig. 3. AM-AM pre-distortion at 38 GHz
Fig. 6. Chip micrograph under the on-wafer measurement
Fig. 4. AM-PM pre-distortion at 38 GHz
Fig. 7. Simulated and measured S-parameters
313
In the large-signal measurement, input power is produced from Agilent E8257D analog signal generator, and the received power is carefully measured with Agilent E4448A spectrum analyer. The single tone large-signal simulation and measurement results are shown in Fig. 8 and Fig. 9. At the 39 GHz, this power amplifier provides 14.4-dB small-signal power gain, 20.7-dBm PSAT, 35% PAEMAX, 20.2-dBm OP1dB, and 32.8% PAE1dB. The two-tone large-signal measurements for the IMD3 with different frequency spacing from 100-MHz to 1600-MHz are shown in Fig. 10 and Fig. 11. In the Fig. 10 and Fig. 11, the IMD3 is clearly improved for the frequency spacing of 100-1600 MHz. Fig. 11. Measured the IMD3 at upper side band
The modulated signal measurement is setup with Agilent M8190A arbitrary waveform generator, Keysight E8267D vector signal generator, and Keysight DSA-Z334A oscilloscope. The power amplifier is measured under a 64QAM OFDM modulated signal with 9.8-dB PAPR, 1600MHz channel bandwidth, and 38-GHz carrier frequency. The power amplifier achieves 13.2-dBm output power and 7.1% PAE with an EVM of less than -25 dBc in the measurement shown in Fig. 12 and Fig. 13. In Fig. 13, it can be clearly found that the output power by using analog pre-distortion technique in the power amplifier is increased from 10 dBm to 13.2 dBm in the high order digital modulation compared to the traditional class A power amplifier.
Fig. 8. Simulated and measured large-signal at 39GHz
(a)
(b)
Fig. 12. (a) Measured constellation; (b) channel bandwidth Table 1. Comparison table of the modulated signal measurements. Fig. 9. Measured Pout and PAE vs. frequency
Ref.
This work
[2]
[3]
[1]
Tech.
65-nm CMOS
28-nm CMOS
40-nm CMOS
28-nm CMOS
38
34
27
30
1600
1350
800
250
Modulated Signal
64-QAM OFDM
64-QAM
64-QAM OFDM 8-CC
64-QAM OFDM
PAPR [dB]
9.8
8.3
9.7
9.6
PAE [%]
7.1
2.3
11
9
Pout [dBm]
13.2
5.9
6.7
4.2
Carrier Frequency [MHz] Transmission Bandwidth [MHz]
Fig. 10. Measured the IMD3 at lower side band
314
Table 2. Comparison table of the continuous-wave measurements.
PSAT [dBm] 20.7
PAEMAX [%] 35
OP1dB [dBm] 20.2
PAE1dB [%] 32.8
Core Area 2 [mm ]
18
16.6
24.2
13.4
12.6
0.16
15.8
15.6
41
14
34.7
0.24
20.8
15.3
32.9
12.9
N/A
0.11
27
22.4
15.1
33.7
13.7
31.1
0.23
27
20.5
18.1
41.5
16.8
37.6
0.36
30
15.7
14
35.5
13.2
34.3
0.16
Ref.
Tech.
This work
65-nm CMOS
Freq. [GHz] 39
[2]
28-nm CMOS
30
[7]
65-nm CMOS
28
[8]
65-nm CMOS
32
[3]
40-nm CMOS
[9]
40-nm CMOS
[1]
28-nm CMOS
Gain [dB] 14.4
0.21
[6]
28-nm CMOS
28
13.6
19.8
43.3
18.6
41.4
0.28
[11]
65-mn CMOS
28
8.9
14.4
40.1
13.6
37.2
0.11
[12]
45-nm SOI CMOS
39
10.5
18.5
41.2
16.3
N/A
0.14
[13]
65-nm CMOS
34
13.8
19.9
25.8
17
14.5
0.37
[3]
[4]
[5]
[6]
[7] Fig. 13. EVM versus output power
IV. CONCLUSION The comparison tables of the modulated signal and continuous-wave measurement are shown in Table 1 and Table 2. In the continuous-wave measurement, the proposed power amplifier provides 20.2-dBm OP1dB with 32.8% PAE. In the modulated signal measurement, the proposed power amplifier achieves 13.2-dBm output power and 7.1% PAE on 64-QAM OFDM modulated signal with the 1600-MHz channel bandwidth and 9.8-dB PAPR in Table 1. The proposed power amplifier with analog pre-distortion has high linear output power and high efficiency for the wideband digital modulated signal. The highest transmission data rate of the proposed power amplifier reaches up to 6.98 Gb/s.
[8]
[9]
[10]
[11]
[12]
REFERENCES [1] S. Shakib, H. Park, J. Dunworth, V. Aparin and K. Entesari, "A highly efficient and linear power amplifier for 28-GHz 5G phased array radios in 28-nm CMOS," IEEE Journal of Solid-State Circuits, vol. 51, no. 12, pp. 3020-3036, Dec. 2016. [2] M. Vigilante and P. Reynaert, "A wideband class-AB power amplifier with 29–57-GHz AM–PM compensation in 0.9-V 28-nm bulk CMOS,"
315
[13]
IEEE Journal of Solid-State Circuits, vol. 53, no. 5, pp. 1288-1301, May 2018. S. Shakib, M. Elkholy, J. Dunworth, V. Aparin and K. Entesari, "A wideband 28GHz power amplifier supporting 8×100MHz carrier aggregation for 5G in 40nm CMOS," in IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2017, pp. 44-45. C. Fager, J. C. Pedro, N. B. de Carvalho, H. Zirath, F. Fortes and M. J. Rosario, "A comprehensive analysis of IMD behavior in RF CMOS power amplifiers," IEEE Journal of Solid-State Circuits, vol. 39, no. 1, pp. 24-34, Jan. 2004. C. Wang, L. E. Larson and P. M. Asbeck, "A nonlinear capacitance cancellation technique and its application to a CMOS class AB power amplifier," in IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Phoenix, AZ, USA, 2001, pp. 39-42. B. Park, Daechul Jeong, J. Kim, Y. Cho, Kyunghoon Moon and B. Kim, "Highly linear CMOS power amplifier for mm-wave applications," in IEEE MTT-S International Microwave Symposium (IMS), San Francisco, CA, 2016, pp. 1-3. S. N. Ali, P. Agarwal, J. Baylon, S. Gopal, L. Renaud and D. Heo, "A 28GHz 41%-PAE linear CMOS power amplifier using a transformerbased AM-PM distortion-correction technique for 5G phased arrays," in IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2018, pp. 406-408. H. Jia, C. C. Prawoto, B. Chi, Z. Wang and C. P. Yue, "A full Ka-Band power amplifier with 32.9% PAE and 15.3-dBm power in 65-nm CMOS," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 9, pp. 2657-2668, Sept. 2018. Y. Zhang and P. Reynaert, "A high-efficiency linear power amplifier for 28GHz mobile communications in 40nm CMOS," in IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Honolulu, HI, 2017, pp. 33-36. J. P. Martins, P. M. Cabral, N. Borges Carvalho and J. C. Pedro, "A metric for the quantification of memory effects in power amplifiers," IEEE Transactions on Microwave Theory and Techniques, vol. 54, no. 12, pp. 4432-4439, Dec. 2006. S. N. Ali et al., "A 40% PAE frequency-reconfigurable CMOS power amplifier with tunable Gate–Drain neutralization for 28-GHz 5G Radios," IEEE Transactions on Microwave Theory and Techniques, vol. 66, no. 5, pp. 2231-2245, May 2018. T. Li and H. Wang, "A continuous-mode 23.5-41GHz hybrid class-F/Fl power amplifier with 46% peak PAE for 5G massive MIMO applications," in IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Philadelphia, PA, 2018, pp. 220-230. S. Chang, C. Chen and H. Wang, "A Ka-Band dual-mode power amplifier in 65-nm CMOS technology," IEEE Microwave and Wireless Components Letters, vol. 28, no. 8, pp. 708-710, Aug. 2018.