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Fast electromigration wafer mapping for wafer fab process monitoring and improvement
Microelectronics Reliability 48 (2008) 1388–1392
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Fast electromigration wafer mapping for wafer fab process monitoring and improvement Yuan Li *, Leo van Marwijk, Som Nath NXP Semiconductors, Gerstweg 2, 6534 AE Nijmegen, The Netherlands
a r t i c l e
i n f o
Article history: Received 30 June 2008 Available online 15 August 2008
a b s t r a c t In this work, a set up for fast wafer level electromigration (WL-EM) is developed with the use of a standard electrical analyser, a semi-auto probe station with a hot chuck, and a PC. EM tests on multiple test structures are carried out simultaneously and tests are done at multiple locations (EM mapping) across the wafer. Measured data are imported into MS EXCEL and analysed with a macro automatically. Good correlations are demonstrated between the fast WL-EM test and classical package level EM at 0.1% failure rate. For several years reliable EM monitoring charts are created with the fast WL-EM set up. The fast EM mapping test does not only exploit the advantages of fast WL-EM test in terms of short throughput time and low cost (without packaging) for process monitoring, the additional information on EM performance across the wafer makes the test extremely valuable for process improvement. Ó 2008 Elsevier Ltd. All rights reserved.
1. Introduction Electromigration (EM) is one of the important reliability concerns for wafer fab processing in the semiconductor industry. Process changes in the wafer fab backend process, which may impact the EM performance, require typically extensive re-qualification effort. Furthermore, regular EM monitoring is required by the wafer fab and customers to demonstrate both process control and process improvement. However, to effectively extend the EM monitoring to multiple processes in a fab is not an easy task with the use of the conventional package level EM (PL-EM) measurement. First of all, the long throughput time of PL-EM (typically more than four weeks) due to the packaging of samples and the EM test in time-to-failure (TTF) makes the monitoring less effective in giving feedback in time to capture possible process drifts. Secondly, costs are enormous: the purchase of dedicated equipment, the wafers, and the packaging of samples in ceramic housings. For these reasons fast wafer level EM (WL-EM) has been given a lot of attention and many investigations have been carried out in the past two decades [1–11]. Despite intensive investigations to develop different test methods, data on correlation between the PL-EM and the fast WL- EM are rarely reported. In cases such correlations are dealt with the median points of the TTF distributions (TTF50%) are compared [2,9], or a trend is observed at 0.1% failure rate [9]. However, the industry evaluates the reliability of the processes at the 0.1% failure rate as a standard. Therefore, it is essential to demonstrate a good correlation between a fast WL-EM and the PL-EM test before the * Corresponding author. Tel.: +31 24 3535357; fax: +31 24 3533878. E-mail address: [email protected] (Y. Li). 0026-2714/$ - see front matter Ó 2008 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2008.07.048
fast WL-EM could be used for real production monitoring. In addition, no practically workable fast WL-EM test set up with capability of EM wafer mapping is reported for production monitoring. In this work, a set up for fast WL-EM is developed with the use of a standard parameter analyser, a semi-automatic probe station with a hot chuck, and a PC, focusing on short throughput time, ease to use, low cost and capable of EM performance mapping across the wafer. Specially designed scribe lane test structures are placed in a row next to each other, making it possible to test multiple test structures simultaneously. The stress conditions and the measured TTF are imported into MS EXCEL and analysed with a macro automatically. Good quantitative correlations are demonstrated between the fast WL-EM and the classical PL-EM at the standard 0.1% failure rate. The additional information of EM performance across the wafer makes it a very valuable technique for process improvement. The set up has been used and proved to have delivered reliable EM data for process monitoring and process improvements in one of NXP’s wafer fabs over the past few years. 2. The test structures VIA chain test structures are used to develop the fast WL-EM test set up. The choice is made based on the following considerations. Firstly, the VIA chain test structures consist of VIAs connected with metal lines with minimum line width (Fig. 1). The stress currents needed for the fast EM tests are relatively low, making the VIA chain test structures more suitable for the fast WL-EM tests with the use of probe card. Secondly, for AlCu interconnect technology with tungsten VIA plugs the EM process actually takes place only in the AlCu metal lines rather in the VIAs. With the test of VIA chains consisting of VIAs and metal lines the EM monitoring
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b a Fig. 1. Schematic description of the VIAi test structure with Mi in a length of a and Mi+1 in a length of b.
on both VIA process modules and the AlCu interconnect process are covered. Attention is paid in the design to draw the metal lines connecting any two VIAs (characterized by lengths a and b in Fig. 1) with a length much longer than the Blech length and the metal-VIA overlay in the minimum to reflect worst design cases. Test structures are placed in the scribe lane of the production wafers. This makes it easier to obtain wafers for EM tests for process improvement or monitoring. The design is made following the same rules as for the scribe lane Parametric Control Modules (PCM), except that some pads are removed in order to optimise the test structure layout for EM test (Fig. 2). All EM test structures are placed adjacent to each other in the scribe lane, making it possible to test a large number of test structures simultaneously. 3. The test methodology The iso-current (constant current) method is chosen for the fast WL-EM in this work. The choice is made based on the consideration that this method is similar to that of the PL-EM so that correlating the WL-EM results with that of the PL-EM would be more straightforward. In addition, this test method is simple thus easier for data collection and extrapolation. A hot chuck is used to heat the wafer to a certain initial temperature instead of using purely the Joule heating in order to limit the effect of temperature gradient on the EM results. A higher chuck temperature is preferred in order to carry out the test faster. But there are some practical limitations on the set up to allow a too high chuck temperature. For example, the microscope and the parts of the probe card/station which are close to the surface of the wafer should not be exposed to too high temperature. The temperature of the test structures is calculated based on the chuck temperature plus the Joule heating with the stress current. A 5% resistance increase, instead of 10% or 20% for PL-EM normally, is taken as the failure criterion. The reason behind is that the resistance increases very sharply after a first increase of 5% in WL-EM due to the high stress current. In some cases the resistance increase is so fast that there will be no time to record additional data points for every 1% resistance increase, and the TTF taken at 5% is very similar as that taken at 10% or 20%. 4. The equipment set up and software The set up consists of a HP4155A or a Keithley 4200 analyser with high power capability, a semi-auto probe station with a heat chuck up to 150/250 °C, and a PC. The use of a dedicated probe card makes it possible to stress multiple test structures of different levels simultaneously at each test location. The software is made of two parts. The first part is the software to operate the analyser to carry out the test procedure, raw data collection and TTF determination and to control the probe station. To improve the contact of the probe card with the test pads all test structures are pre-stressed with the stress currents for a short time
before the resistances are measured at a current of 1 mA at the chuck temperature. The measured resistance values are part of the inputs for the determination of the Joule heating under stress currents for all the test structures under test. The temperature increase due to Joule heating is calculated from the increase of resistance measured at 1 mA and at the stress currents, with the use of a pre-determined Temperature Coefficient of Resistance (TCR) value. The change of the resistance during stress is monitored continuously and the measured resistance value is saved at certain time points determined by the software or when the resistance change reaches 1% above the last-saved value, until the failure criterion of 5% resistance increase, or voltage compliance, is reached. When all the test structures at a location have failed or a maximum stress time is reached, the probes are re-positioned automatically to the next available site and the test is repeated, until all test structures at the pre-programmed locations are tested. The second part is the software to convert the test conditions and the data measured by the analyser into an Excel data sheet, calculate the temperature of the test structures under stress conditions, fit the data for each VIA level in lognormal distribution, extrapolate the data to the use temperature/current and to the failure rate of 0.1%. All these are done with a macro in MS EXCEL. To fit the data with lognormal distribution plotting is done using the failed fraction f = (m 0.3)/(N + 0.4), in which m is the number of failed test structures and N the total sample size. Black’s equation with no line width term is used for the calculation of lifetime from the test conditions to the use conditions:
TTFð50%Þ ¼ AJ n expðEa =kTÞ;
ð1Þ
where a current accelerating factor n of 2 and activation energies (Ea) determined by PL-EM for each generation of technologies are used. The results are reported for a certain operation temperature and a failure rate of 0.1% in two ways: (1) output an allowed current (Iallowed) for 10 years’ continuous operation, and (2) output a lifetime at the design current (Ispec). The lifetime and the Iallowed under the same operation temperature and the same failure rate are linked with each other with a formula deduced from Eq. (1) as
Iallowed ¼ Ispec ðlifetime=10Þ1=2 :
ð2Þ
5. The experiments and the results A good set of test parameters (chuck temperature, stress current etc.) is determined by experiments for each generation of processes, with a criterion that for a large variation of wafers the TTFs fall always in a time frame of 200–2000 s. For a too short TTF under a too high stress current the test is expected to be less reliable/ accurate. On the other hand, the TTF must be short enough to make it possible to EM-map a wafer in 24 h at 20 or more locations. In Table 1 an optimal set of the stress conditions is given for one of our process families in production. The stress currents used for the fast WL-EM are about only three times of that normally used for PL-EM tests. The failure mechanisms found in the WL-EM are the same as in the PL-EM: failure is caused by voids formation under or above the VIAs. This has been proved by failure analysis on a number of samples from different test runs. Table 1 Chuck temperature and stress current settings for a process in production Chuck temperature
Fig. 2. The layout of a typical scribe lane VIA chain test module of two test structures.
125 °C
Stress current (mA) VIA1
VIA2
VIA3
VIA4
VIA5
23
21
19
20
27
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6
30 V1
V3
V5
25
4
y = 0.8104x - 0.125
3
Fast WL EM
(R/Ro-1)*100 (%)
5
2 1 0 -1
20
15
10
-2 1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
5
Stress Time (s) Fig. 3. Relative resistance change with time.
0 0
In Fig. 3 the relative resistance changes in time at a test location for 3 VIA levels are given. One TTF data point is obtained for each VIA level at this location on the wafer. When the stress test is repeated at more locations across the wafer a set of TTF data points are obtained for each VIA level tested. The TTF data points are fitted in lognormal distribution as a function of time. An example is shown in Fig. 4 for TTF, extrapolated to use conditions, for 4 VIA levels tested. The lifetime at 0.1% failure rate can be obtained for each VIA level from such a fitting. To demonstrate correlations between the fast WL-EM and the PL-EM, wafers with varying EM performances need to be tested. For that purpose engineering wafers where the processes are varied deliberately, which are expected to have impact on the EM performances of VIAs and metal lines, are selected for this experiment. To rule out any impact of possible wafer-to-wafer variations all wafers are cleaved into two pieces: half of the wafer is tested by PL-EM and the other half is tested with the fast WL-EM. The results are then compared between the two test methods. The PL-EM experiments are carried out with the use of a commercial EM tester where samples of multiple levels can be stressed simultaneously with a reasonable sample size per group. In Fig. 5 the allowed currents for various wafers from the fast WL-EM (y-axis) and from the PL-EM (x-axis) are shown. Those data points lie in nearly a straight line, indicating a good correlation, with a fixed factor (about 0.8), between the fast WL-EM and the standard PL-EM test methods.
99.93 VIA2 chain VIA4 chain
VIA3 chain VIA1 chain
5
10
15
20
25
30
Standard EM Fig. 5. Correlation in Iallowed between the fast WL-EM and the standard PL-EM for various wafers and test structures. Note that WL-EM differs with a factor of 0.8 (the slope of the fitting line) from the PL-EM.
For monitoring purpose the allowed current is normalized to its design manual value. This makes it easier to judge whether the EM performances of the monitored wafers are satisfactory (with Iallowed/Ispec 1) or not (with Iallowed/Ispec < 1), independent of which processes are being monitored. The monitoring chart for one of the NXP processes is shown in Fig. 6. The control limit for monitoring with fast WL-EM is set to 0.8 (Fig. 6) because of the difference between WL-EM and PL-EM as described in Fig. 5. Engineering data from a fab incident are put in the same graph for references showing that the test is sensitive to process problems. For each VIA level the TTF measured can be plotted as a function of the position on the wafer so that a TTF mapping can be made. An example of TTF mapping (half of a wafer) is shown in Fig. 7. For a well-processed wafer the EM TTF distribution across the wafer should be more or less random, as is shown by Fig. 7. If the TTF mapping shows a clear pattern, e.g. centre versus edge, or half versus the other half of the wafer, this indicates there is some process problem there. An example is shown in Fig. 8 from a worst engineering wafer of a VIA4 process windowing experiment. In the centre-left part (notch down) of the wafer the recorded TTF is shorter than that of the rest of the wafer, suggesting that the process is out of control for this process condition. This can be seen more clearly from the cumulative TTF distribution plots of the data points from the centre-left and other part of the wafer, as are shown in Figs. 9 and 10, respectively. VIA3 data are shown in Figs. 9 and 10 as well
84.11
6.0 5.0
50.00
Iallowed/ISPEC
Cumulative Failure (%)
97.72
-1 15.9
V1
V2
V3
V4
V5
LCL
4.0 3.0 2.0
-2 2.3
1.0 -3 0.1 1.E+08
0.0
1.E+09
1.E+10
1.E+11
1.E+12
Incident of temperature too high at metal deposition
Time Sequence
Time (second) Fig. 4. TTF extrapolated to a use temperature of 70 °C and SPEC currents, plotted in lognormal distribution. The lifetime at 0.1% cumulative failure rate can be obtained.
Fig. 6. EM monitoring chart of one of the NXP processes created from fast WL-EM mapping. Engineering data from a fab incident are put in the same graph showing that the test is sensitive to process problems.
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3 99.9 VIA3, edge
Fig. 7. TTF mapping (the half of a wafer). The size of the circles refers to log(TTF)constant.
7
Cumulative failure (%)
2 97.7
VIA4, edge
1 84.1
0 50.0 15.9 -1
-2 2.3
6 -3 0.1 1.E+04
5
1.E+06
1.E+07
1.E+08
1.E+09
Time (second)
4
Notch
1.E+05
Fig. 10. Cumulative (in lognormal) distribution of TTF of VIA4 and VIA3 for the rest part of the engineering wafer with the VIA4 processed in a bad condition.
3 2
6. Discussion
1 0 -1 -2
-1
0
1
2
3
4
5
6
Fig. 8. TTF mapping showing that the central-left (notch down) part of an engineering wafer where VIA4 is processed in a bad condition, has shorter TTF than the rest of the wafer. The size of the circles refers to log(TTF)-constant.
99.9 VIA3, center
Cumulative failure (%)
97.7
VIA4, center
84.1 0 50.0
-1 15.9
-2 2.3
-3 0.1 1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
1.E+09
Time (second) Fig. 9. Cumulative (in lognormal) distribution of TTF of VIA4 and VIA3 for the centreleft part of the engineering wafer with the VIA4 processed in a bad condition.
as reference. Clearly VIA4 is poorer than VIA3, especially in the centre-left of the wafer VIA4 TTFs show a very pronounced earlier failure distribution leading to very poor EM lifetime. For VIA3, however, there is no significant difference between the wafer centre-left and the rest of the wafer. It is worth to note that the original VIA4 resistance values differ/vary less than 50% from that of the normally processed wafers. This suggests that fast WL-EM mapping can provide valuable information for process improvement as well.
The slope of the fitting line in Fig. 5 is about 0.8, meaning that the EM performance determined by the fast WL-EM is weaker than what is measured by PL-EM. Among others an underestimation of the temperature of the devices under test (DUT) in WL-EM is probably the main cause for that difference. The temperature of the DUT is calculated by the resistance increase under the stress current. It is thus an average value for the whole DUT. Because of a higher thermal resistivity for a metal line farther away from the substrate, under the high stress current the temperature of metal Mi+1 (see Fig. 1) will be higher than that of Mi and than the average temperature. Data extrapolation with the use of the calculated DUT temperature will thus underestimate the EM performance of the DUT as a whole. Improvements concerning this issue could be achieved by splitting the VIA chain test structure for each VIA level into two: one with b a (a Blech length while b < Blech length) to test the formation of voids under the VIAs while the other with a b to test the formation of voids above the VIAs. Caution is advised in interpreting the fast WL-EM results in two extreme cases. In the first case some ‘‘defects” in the DUTs may cause a significant resistance increase locally but the resistance of the DUT does not change much. In fast WL-EM such defects may be decorated much strongly because of the higher stress current, resulting in a much poorer EM results than that of the standard PL-EM. That is, the EM performance might be underestimated by WL-EM. But anyway in this case the VIAs are abnormal and for monitoring it is still worthful to give an alarm. To evaluate if the EM performance is still acceptable, a test needs to be repeated with the PL-EM – this could be an OCAP (out-controlplan) for the fast WL-EM. In the second case the original resistance of the DUT might be very high due to, for example, residues in the VIAs. With the fast WL-EM the high voltage drop across the residues would cause a break-though of the residues resulting in some recovery of the DUT, leading to better EM performance of the DUT based on the use of the 5% resistance increase failure criterion. As such the EM performance is over-estimated by the WL-EM test. In practice this kind of DUTs should be always treated as zero yield devices and there is no need to consider the reliability of these devices. The wafers tested with fast WL-EM on scribe lane test structures for monitoring experienced only a moderate temperature
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step (125 °C) for less than 24 h. For a process which is qualified with the High Temperature Storage Life test at 150 °C for 1000 h, the fast WL-EM test would have no negative impact on the reliability of the products on the same wafer. This points to a possibility of using production wafers for monitoring without scraping them, which will significantly reduce the cost of monitoring further. 7. Summary and conclusions In this work a set up for fast WL-EM mapping is developed with the use of a standard electrical analyser, a semi-auto probe station with a hot chuck, and a PC. EM tests on multiple test structures are carried out simultaneously and EM mapping across the wafer can be done. Good correlations are demonstrated between the fast WL-EM test and standard PL-EM at 0.1% failure rate. Reliable EM monitoring chart is created with the fast WL-EM set up. The fast EM mapping test does not only exploit the advantages of fast WL-EM test in terms of short throughput time and low cost for process monitoring, the additional information on EM performance across the wafer makes the test extremely valuable for process improvement. Further improvements and cautions in data interpretation are discussed. Acknowledgement The authors would like to thank Miss J. van den Ent and Mr. I. Mohammed for their support to create and improve the software.
References [1] Root Bryan J, Turner Tim. Wafer level electromigration tests for production monitoring. In: IEEE IRPS proceedings; 1985. p. 100–7. [2] Pierce Donald G, Brusius Phili G. Correlation between highly and moderately accelerated electromigration tests. IEEE Electron Dev Lett 1993;14(6):277–9. [3] Zitzelsberger A, Pietsch A, von Hagen J. Electromigration testing on via line structures with a SWEAT method in comparison to standard package level tests. IEEE IRW final report; 2000. p. 57–60. [4] Lepper M, Bauer R, Zitzelsberger AE. A correlation between highly accelerated wafer level and standard package level electromigration tests on deel submicron via-line structures. IEEE IRW final report; 2000. p. 70–3. [5] Sullivan Tim D, Lee Tom, Tibel Deborah. Basic BEOL parameters from isothermal wafer level electromigration testing. IEEE IRW final report; 2000. p. 80–4. [6] von Hagen Jochen, Antonin Georg, Fazekas Josef, Head Linda, Schafft Harry. New SWEAT method for fast, accurate and stable electromigration testing on wafer level. IEEE IRW final report; 2000. p. 85–9. [7] Dion Michael J. Standardizing EM structures for evaluation and qualification of aluminum alloys with barriers metals. IEEE IRW final report; 2000. p. 167–70. [8] Lee Tom C, Tibel Deborah, Sullivan Timothy D, Forhan Sheri. Comparison of isothermal, constant current and SWEAT wafer level EM testing methods. In: IEEE IRPS proceedings; 2001. p. 172–83. [9] Lee Shun-Yi, Lai JB, Lee SC, Chu LH, Huang YS, Shiue RY, et al. Real case study for isothermal EM test as a process control methodology. In: IEEE IRPS proceedings; 2001. p. 184–8. [10] Ryu C, Tsai Tse-Lun, Rogers A, Jesse C, Brozek T, Zarr D, et al. Experimental comparison of wafer level reliability (WLR) and packaged electromigration tests. In: IEEE IRPS proceedings; 2001. p. 189–93. [11] Tibel Deborah, Sullivan Timothy D. Comparison of via/line package level vs. wafer level results. In: IEEE IRPS proceedings; 2001. p. 194–9.
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Fast electromigration wafer mapping for wafer fab process monitoring and improvement Yuan Li *, Leo van Marwijk, Som Nath NXP Semiconductors, Gerstweg 2, 6534 AE Nijmegen, The Netherlands
a r t i c l e
i n f o
Article history: Received 30 June 2008 Available online 15 August 2008
a b s t r a c t In this work, a set up for fast wafer level electromigration (WL-EM) is developed with the use of a standard electrical analyser, a semi-auto probe station with a hot chuck, and a PC. EM tests on multiple test structures are carried out simultaneously and tests are done at multiple locations (EM mapping) across the wafer. Measured data are imported into MS EXCEL and analysed with a macro automatically. Good correlations are demonstrated between the fast WL-EM test and classical package level EM at 0.1% failure rate. For several years reliable EM monitoring charts are created with the fast WL-EM set up. The fast EM mapping test does not only exploit the advantages of fast WL-EM test in terms of short throughput time and low cost (without packaging) for process monitoring, the additional information on EM performance across the wafer makes the test extremely valuable for process improvement. Ó 2008 Elsevier Ltd. All rights reserved.
1. Introduction Electromigration (EM) is one of the important reliability concerns for wafer fab processing in the semiconductor industry. Process changes in the wafer fab backend process, which may impact the EM performance, require typically extensive re-qualification effort. Furthermore, regular EM monitoring is required by the wafer fab and customers to demonstrate both process control and process improvement. However, to effectively extend the EM monitoring to multiple processes in a fab is not an easy task with the use of the conventional package level EM (PL-EM) measurement. First of all, the long throughput time of PL-EM (typically more than four weeks) due to the packaging of samples and the EM test in time-to-failure (TTF) makes the monitoring less effective in giving feedback in time to capture possible process drifts. Secondly, costs are enormous: the purchase of dedicated equipment, the wafers, and the packaging of samples in ceramic housings. For these reasons fast wafer level EM (WL-EM) has been given a lot of attention and many investigations have been carried out in the past two decades [1–11]. Despite intensive investigations to develop different test methods, data on correlation between the PL-EM and the fast WL- EM are rarely reported. In cases such correlations are dealt with the median points of the TTF distributions (TTF50%) are compared [2,9], or a trend is observed at 0.1% failure rate [9]. However, the industry evaluates the reliability of the processes at the 0.1% failure rate as a standard. Therefore, it is essential to demonstrate a good correlation between a fast WL-EM and the PL-EM test before the * Corresponding author. Tel.: +31 24 3535357; fax: +31 24 3533878. E-mail address: [email protected] (Y. Li). 0026-2714/$ - see front matter Ó 2008 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2008.07.048
fast WL-EM could be used for real production monitoring. In addition, no practically workable fast WL-EM test set up with capability of EM wafer mapping is reported for production monitoring. In this work, a set up for fast WL-EM is developed with the use of a standard parameter analyser, a semi-automatic probe station with a hot chuck, and a PC, focusing on short throughput time, ease to use, low cost and capable of EM performance mapping across the wafer. Specially designed scribe lane test structures are placed in a row next to each other, making it possible to test multiple test structures simultaneously. The stress conditions and the measured TTF are imported into MS EXCEL and analysed with a macro automatically. Good quantitative correlations are demonstrated between the fast WL-EM and the classical PL-EM at the standard 0.1% failure rate. The additional information of EM performance across the wafer makes it a very valuable technique for process improvement. The set up has been used and proved to have delivered reliable EM data for process monitoring and process improvements in one of NXP’s wafer fabs over the past few years. 2. The test structures VIA chain test structures are used to develop the fast WL-EM test set up. The choice is made based on the following considerations. Firstly, the VIA chain test structures consist of VIAs connected with metal lines with minimum line width (Fig. 1). The stress currents needed for the fast EM tests are relatively low, making the VIA chain test structures more suitable for the fast WL-EM tests with the use of probe card. Secondly, for AlCu interconnect technology with tungsten VIA plugs the EM process actually takes place only in the AlCu metal lines rather in the VIAs. With the test of VIA chains consisting of VIAs and metal lines the EM monitoring
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b a Fig. 1. Schematic description of the VIAi test structure with Mi in a length of a and Mi+1 in a length of b.
on both VIA process modules and the AlCu interconnect process are covered. Attention is paid in the design to draw the metal lines connecting any two VIAs (characterized by lengths a and b in Fig. 1) with a length much longer than the Blech length and the metal-VIA overlay in the minimum to reflect worst design cases. Test structures are placed in the scribe lane of the production wafers. This makes it easier to obtain wafers for EM tests for process improvement or monitoring. The design is made following the same rules as for the scribe lane Parametric Control Modules (PCM), except that some pads are removed in order to optimise the test structure layout for EM test (Fig. 2). All EM test structures are placed adjacent to each other in the scribe lane, making it possible to test a large number of test structures simultaneously. 3. The test methodology The iso-current (constant current) method is chosen for the fast WL-EM in this work. The choice is made based on the consideration that this method is similar to that of the PL-EM so that correlating the WL-EM results with that of the PL-EM would be more straightforward. In addition, this test method is simple thus easier for data collection and extrapolation. A hot chuck is used to heat the wafer to a certain initial temperature instead of using purely the Joule heating in order to limit the effect of temperature gradient on the EM results. A higher chuck temperature is preferred in order to carry out the test faster. But there are some practical limitations on the set up to allow a too high chuck temperature. For example, the microscope and the parts of the probe card/station which are close to the surface of the wafer should not be exposed to too high temperature. The temperature of the test structures is calculated based on the chuck temperature plus the Joule heating with the stress current. A 5% resistance increase, instead of 10% or 20% for PL-EM normally, is taken as the failure criterion. The reason behind is that the resistance increases very sharply after a first increase of 5% in WL-EM due to the high stress current. In some cases the resistance increase is so fast that there will be no time to record additional data points for every 1% resistance increase, and the TTF taken at 5% is very similar as that taken at 10% or 20%. 4. The equipment set up and software The set up consists of a HP4155A or a Keithley 4200 analyser with high power capability, a semi-auto probe station with a heat chuck up to 150/250 °C, and a PC. The use of a dedicated probe card makes it possible to stress multiple test structures of different levels simultaneously at each test location. The software is made of two parts. The first part is the software to operate the analyser to carry out the test procedure, raw data collection and TTF determination and to control the probe station. To improve the contact of the probe card with the test pads all test structures are pre-stressed with the stress currents for a short time
before the resistances are measured at a current of 1 mA at the chuck temperature. The measured resistance values are part of the inputs for the determination of the Joule heating under stress currents for all the test structures under test. The temperature increase due to Joule heating is calculated from the increase of resistance measured at 1 mA and at the stress currents, with the use of a pre-determined Temperature Coefficient of Resistance (TCR) value. The change of the resistance during stress is monitored continuously and the measured resistance value is saved at certain time points determined by the software or when the resistance change reaches 1% above the last-saved value, until the failure criterion of 5% resistance increase, or voltage compliance, is reached. When all the test structures at a location have failed or a maximum stress time is reached, the probes are re-positioned automatically to the next available site and the test is repeated, until all test structures at the pre-programmed locations are tested. The second part is the software to convert the test conditions and the data measured by the analyser into an Excel data sheet, calculate the temperature of the test structures under stress conditions, fit the data for each VIA level in lognormal distribution, extrapolate the data to the use temperature/current and to the failure rate of 0.1%. All these are done with a macro in MS EXCEL. To fit the data with lognormal distribution plotting is done using the failed fraction f = (m 0.3)/(N + 0.4), in which m is the number of failed test structures and N the total sample size. Black’s equation with no line width term is used for the calculation of lifetime from the test conditions to the use conditions:
TTFð50%Þ ¼ AJ n expðEa =kTÞ;
ð1Þ
where a current accelerating factor n of 2 and activation energies (Ea) determined by PL-EM for each generation of technologies are used. The results are reported for a certain operation temperature and a failure rate of 0.1% in two ways: (1) output an allowed current (Iallowed) for 10 years’ continuous operation, and (2) output a lifetime at the design current (Ispec). The lifetime and the Iallowed under the same operation temperature and the same failure rate are linked with each other with a formula deduced from Eq. (1) as
Iallowed ¼ Ispec ðlifetime=10Þ1=2 :
ð2Þ
5. The experiments and the results A good set of test parameters (chuck temperature, stress current etc.) is determined by experiments for each generation of processes, with a criterion that for a large variation of wafers the TTFs fall always in a time frame of 200–2000 s. For a too short TTF under a too high stress current the test is expected to be less reliable/ accurate. On the other hand, the TTF must be short enough to make it possible to EM-map a wafer in 24 h at 20 or more locations. In Table 1 an optimal set of the stress conditions is given for one of our process families in production. The stress currents used for the fast WL-EM are about only three times of that normally used for PL-EM tests. The failure mechanisms found in the WL-EM are the same as in the PL-EM: failure is caused by voids formation under or above the VIAs. This has been proved by failure analysis on a number of samples from different test runs. Table 1 Chuck temperature and stress current settings for a process in production Chuck temperature
Fig. 2. The layout of a typical scribe lane VIA chain test module of two test structures.
125 °C
Stress current (mA) VIA1
VIA2
VIA3
VIA4
VIA5
23
21
19
20
27
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6
30 V1
V3
V5
25
4
y = 0.8104x - 0.125
3
Fast WL EM
(R/Ro-1)*100 (%)
5
2 1 0 -1
20
15
10
-2 1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
5
Stress Time (s) Fig. 3. Relative resistance change with time.
0 0
In Fig. 3 the relative resistance changes in time at a test location for 3 VIA levels are given. One TTF data point is obtained for each VIA level at this location on the wafer. When the stress test is repeated at more locations across the wafer a set of TTF data points are obtained for each VIA level tested. The TTF data points are fitted in lognormal distribution as a function of time. An example is shown in Fig. 4 for TTF, extrapolated to use conditions, for 4 VIA levels tested. The lifetime at 0.1% failure rate can be obtained for each VIA level from such a fitting. To demonstrate correlations between the fast WL-EM and the PL-EM, wafers with varying EM performances need to be tested. For that purpose engineering wafers where the processes are varied deliberately, which are expected to have impact on the EM performances of VIAs and metal lines, are selected for this experiment. To rule out any impact of possible wafer-to-wafer variations all wafers are cleaved into two pieces: half of the wafer is tested by PL-EM and the other half is tested with the fast WL-EM. The results are then compared between the two test methods. The PL-EM experiments are carried out with the use of a commercial EM tester where samples of multiple levels can be stressed simultaneously with a reasonable sample size per group. In Fig. 5 the allowed currents for various wafers from the fast WL-EM (y-axis) and from the PL-EM (x-axis) are shown. Those data points lie in nearly a straight line, indicating a good correlation, with a fixed factor (about 0.8), between the fast WL-EM and the standard PL-EM test methods.
99.93 VIA2 chain VIA4 chain
VIA3 chain VIA1 chain
5
10
15
20
25
30
Standard EM Fig. 5. Correlation in Iallowed between the fast WL-EM and the standard PL-EM for various wafers and test structures. Note that WL-EM differs with a factor of 0.8 (the slope of the fitting line) from the PL-EM.
For monitoring purpose the allowed current is normalized to its design manual value. This makes it easier to judge whether the EM performances of the monitored wafers are satisfactory (with Iallowed/Ispec 1) or not (with Iallowed/Ispec < 1), independent of which processes are being monitored. The monitoring chart for one of the NXP processes is shown in Fig. 6. The control limit for monitoring with fast WL-EM is set to 0.8 (Fig. 6) because of the difference between WL-EM and PL-EM as described in Fig. 5. Engineering data from a fab incident are put in the same graph for references showing that the test is sensitive to process problems. For each VIA level the TTF measured can be plotted as a function of the position on the wafer so that a TTF mapping can be made. An example of TTF mapping (half of a wafer) is shown in Fig. 7. For a well-processed wafer the EM TTF distribution across the wafer should be more or less random, as is shown by Fig. 7. If the TTF mapping shows a clear pattern, e.g. centre versus edge, or half versus the other half of the wafer, this indicates there is some process problem there. An example is shown in Fig. 8 from a worst engineering wafer of a VIA4 process windowing experiment. In the centre-left part (notch down) of the wafer the recorded TTF is shorter than that of the rest of the wafer, suggesting that the process is out of control for this process condition. This can be seen more clearly from the cumulative TTF distribution plots of the data points from the centre-left and other part of the wafer, as are shown in Figs. 9 and 10, respectively. VIA3 data are shown in Figs. 9 and 10 as well
84.11
6.0 5.0
50.00
Iallowed/ISPEC
Cumulative Failure (%)
97.72
-1 15.9
V1
V2
V3
V4
V5
LCL
4.0 3.0 2.0
-2 2.3
1.0 -3 0.1 1.E+08
0.0
1.E+09
1.E+10
1.E+11
1.E+12
Incident of temperature too high at metal deposition
Time Sequence
Time (second) Fig. 4. TTF extrapolated to a use temperature of 70 °C and SPEC currents, plotted in lognormal distribution. The lifetime at 0.1% cumulative failure rate can be obtained.
Fig. 6. EM monitoring chart of one of the NXP processes created from fast WL-EM mapping. Engineering data from a fab incident are put in the same graph showing that the test is sensitive to process problems.
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3 99.9 VIA3, edge
Fig. 7. TTF mapping (the half of a wafer). The size of the circles refers to log(TTF)constant.
7
Cumulative failure (%)
2 97.7
VIA4, edge
1 84.1
0 50.0 15.9 -1
-2 2.3
6 -3 0.1 1.E+04
5
1.E+06
1.E+07
1.E+08
1.E+09
Time (second)
4
Notch
1.E+05
Fig. 10. Cumulative (in lognormal) distribution of TTF of VIA4 and VIA3 for the rest part of the engineering wafer with the VIA4 processed in a bad condition.
3 2
6. Discussion
1 0 -1 -2
-1
0
1
2
3
4
5
6
Fig. 8. TTF mapping showing that the central-left (notch down) part of an engineering wafer where VIA4 is processed in a bad condition, has shorter TTF than the rest of the wafer. The size of the circles refers to log(TTF)-constant.
99.9 VIA3, center
Cumulative failure (%)
97.7
VIA4, center
84.1 0 50.0
-1 15.9
-2 2.3
-3 0.1 1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
1.E+09
Time (second) Fig. 9. Cumulative (in lognormal) distribution of TTF of VIA4 and VIA3 for the centreleft part of the engineering wafer with the VIA4 processed in a bad condition.
as reference. Clearly VIA4 is poorer than VIA3, especially in the centre-left of the wafer VIA4 TTFs show a very pronounced earlier failure distribution leading to very poor EM lifetime. For VIA3, however, there is no significant difference between the wafer centre-left and the rest of the wafer. It is worth to note that the original VIA4 resistance values differ/vary less than 50% from that of the normally processed wafers. This suggests that fast WL-EM mapping can provide valuable information for process improvement as well.
The slope of the fitting line in Fig. 5 is about 0.8, meaning that the EM performance determined by the fast WL-EM is weaker than what is measured by PL-EM. Among others an underestimation of the temperature of the devices under test (DUT) in WL-EM is probably the main cause for that difference. The temperature of the DUT is calculated by the resistance increase under the stress current. It is thus an average value for the whole DUT. Because of a higher thermal resistivity for a metal line farther away from the substrate, under the high stress current the temperature of metal Mi+1 (see Fig. 1) will be higher than that of Mi and than the average temperature. Data extrapolation with the use of the calculated DUT temperature will thus underestimate the EM performance of the DUT as a whole. Improvements concerning this issue could be achieved by splitting the VIA chain test structure for each VIA level into two: one with b a (a Blech length while b < Blech length) to test the formation of voids under the VIAs while the other with a b to test the formation of voids above the VIAs. Caution is advised in interpreting the fast WL-EM results in two extreme cases. In the first case some ‘‘defects” in the DUTs may cause a significant resistance increase locally but the resistance of the DUT does not change much. In fast WL-EM such defects may be decorated much strongly because of the higher stress current, resulting in a much poorer EM results than that of the standard PL-EM. That is, the EM performance might be underestimated by WL-EM. But anyway in this case the VIAs are abnormal and for monitoring it is still worthful to give an alarm. To evaluate if the EM performance is still acceptable, a test needs to be repeated with the PL-EM – this could be an OCAP (out-controlplan) for the fast WL-EM. In the second case the original resistance of the DUT might be very high due to, for example, residues in the VIAs. With the fast WL-EM the high voltage drop across the residues would cause a break-though of the residues resulting in some recovery of the DUT, leading to better EM performance of the DUT based on the use of the 5% resistance increase failure criterion. As such the EM performance is over-estimated by the WL-EM test. In practice this kind of DUTs should be always treated as zero yield devices and there is no need to consider the reliability of these devices. The wafers tested with fast WL-EM on scribe lane test structures for monitoring experienced only a moderate temperature
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step (125 °C) for less than 24 h. For a process which is qualified with the High Temperature Storage Life test at 150 °C for 1000 h, the fast WL-EM test would have no negative impact on the reliability of the products on the same wafer. This points to a possibility of using production wafers for monitoring without scraping them, which will significantly reduce the cost of monitoring further. 7. Summary and conclusions In this work a set up for fast WL-EM mapping is developed with the use of a standard electrical analyser, a semi-auto probe station with a hot chuck, and a PC. EM tests on multiple test structures are carried out simultaneously and EM mapping across the wafer can be done. Good correlations are demonstrated between the fast WL-EM test and standard PL-EM at 0.1% failure rate. Reliable EM monitoring chart is created with the fast WL-EM set up. The fast EM mapping test does not only exploit the advantages of fast WL-EM test in terms of short throughput time and low cost for process monitoring, the additional information on EM performance across the wafer makes the test extremely valuable for process improvement. Further improvements and cautions in data interpretation are discussed. Acknowledgement The authors would like to thank Miss J. van den Ent and Mr. I. Mohammed for their support to create and improve the software.
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