- Email: [email protected]
Fast switching and low drift of TiSbTe thin films for phase change memory applications
Materials Science in Semiconductor Processing 91 (2019) 399–403
Contents lists available at ScienceDirect
Materials Science in Semiconductor Processing journal homepage: www.elsevier.com/locate/mssp
Fast switching and low drift of TiSbTe thin films for phase change memory applications
T
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Yuan-Guang Liua,b, Yi-Feng Chena, , Dao-Lin Caia, Yao-Yao Lua,b, Lei Wua,b, Shuai Yana,b, Yang Lia,b, Zhi-Tang Songa a
State Key Laboratory of Functional Materials for Informatics and Nanotechnology Laboratory, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, People's Republic of China b University of Chinese Academy of Sciences, Beijing 100080, People's Republic of China
A R T I C LE I N FO
A B S T R A C T
Keywords: Phase-change random-access memory (PCRAM) TiSbTe (TST) High speed Low drift 4 Mb chip Embedded application
As the non-volatile storage medium of the next generation, phase-change random-access memory (PCRAM) has characteristics such as high density, low cost and a wide range of market applications. However, the write speed of GST-based PCRAM falls short of the current DRAM memories and its applications domain expansion is limited. In this article, TiSbTe (TST) shows good performance both in high speed and low drift due to its fast crystallization rate and titanium-centered stable octahedral structure. The promising properties of this new material are illustrated in a 4 Mb chip for embedded applications and tested at wafer level, and the results show that the crystallization speed of TST is improved by 80% and a smaller resistance drift is achieved, with the drift exponent coefficient of highest resistance level being as low as is 0.02, compared with GeSbTe (GST).
1. Introduction Phase-change random access memory (PCRAM) has been attracting more attention as one of the most promising nonvolatile candidates for the next-generation unified memory devices because of its prominent performance, such as low operation voltage, logic compatibility and large sensing signal [1–5]. PCRAM utilizes the characteristic of chalcogenide material which can reversibly switch between amorphous state (high resistance) and crystalline state (low resistance) by applying electrical pulses to store information ('0' and '1'). With the development of CMOS standard process which scales down to nanometer length, the PCRAM have a broader market application prospects in the future [6,7]. So far, Ge2Sb2Te5 (GST) is the main stream material used in PCRAM. However, it has several drawbacks in the application, such as slow SET speed compared with dynamic random-access memory (DRAM), high RESET current [8]. For the realization of future fast speed PCRAM to meet DRAM-like applications, SET speed should be totally investigated. Some researchers point out new structure such as T-shape cell and the confined-cell, programming circuit and the new chemical vapor deposition technology can help the realization of high speed [9,10]. These methods mainly focus on single cell and microstructure characteristic, the performance of material on a statistics level is not well studied yet for embedded application. Besides, multilevel-cell (MLC) storage of
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PCRAM is one of the future development trends to meet the growing high-density demand, and resistance drift has been a major concern to achieve sustainable MLC reliability. In this paper, we report the good performance of the phase-change device using a new chalcogenide material of TiSbTe (TST) alloy and examined its characteristics in 4 M phase-change memory device. The devices based on TST material show a fast crystallization speed and low resistance drift characteristic. 2. Material and device In this work, the experiment data are collected on cells of a 4 Mb PCRAM test chip with an Automatic test equipment (ATE) machine which uses automation to quickly performs tests on the electronic devices and systems. The performance of the PCRAM device based on TST material has been assessed demonstrating the significant potential application prospects. The PCRAM test chip depicted in Fig. 1(a) consists of one-transistor-and-one-resistor (1T1R) memory cells integrated in 40 nm CMOS technology. The storage cells are the specific PCRAM devices, using TST alloy as phase change material, with the blade-type heat electrode made by titanium nitride (TiN) and metal tungsten (W) top-bottom electrode, the structure of which is displayed in Fig. 1(b). The 100 nm thick TST layer is deposited by a physical vapor deposition (PVD) method on the heat electrode contact with TiN as the adhesive
Corresponding author. E-mail address: [email protected] (Y.-F. Chen).
https://doi.org/10.1016/j.mssp.2018.12.009 Received 30 September 2018; Received in revised form 5 November 2018; Accepted 6 December 2018 1369-8001/ © 2018 Elsevier Ltd. All rights reserved.
Materials Science in Semiconductor Processing 91 (2019) 399–403
Y.-G. Liu et al.
and 6-step staircase down pulses. Fig. 2(b) illustrates the measured Shmoo that shows the SET current (ISET) dependency of average SET resistance for using the above pulses while TSET is fixed in 360 ns. The 16 Kbits cells are initially operated to the amorphous state with identical RESET pulses of 50 ns,1 mA before applying the different shape SET pulses. The color gradient corresponds to the logarithmic scale of SET resistance. In the case of various program pulses, the ISET which is capable of reducing the logarithm of SET resistance under 4.5 is different. When the ISET increases, the pulses with few steps might fail to program the cell to the crystalline state. The dark blue color indicates that pulses with more steps possess more obvious SET characteristics. To further investigate the difference of resistance between various step SET pulses, the distributions from an array of 16 K cells of the resulting minimum SET resistance using those pulses are shown in Fig. 3(a). It suggests that the minimum SET resistance of more staircase steps program pulses is lower than that from using fewer steps pulses. For 6-step pulses, the miss rate from an array that fails to program the logarithm of cells resistance under the 4.5 is lowest. It is more obvious in Fig. 3(b) that as the staircase step increases, the minimum set resistance decrease and the cells consistency becomes better. For the SET process, staircase-down pulses with more steps are more conducive to achieving lower minimum SET resistance distribution. Base on the study above, we conduct some researches about the speed limit of TST PCRAM device using the 6-step staircase down SET pulse. Hereinafter the staircase down pulse mentioned in the following research default is 6-step. Fig. 4(a) shows the average SET resistance as a function of the current with various pulse-widths by measuring the 16 K PCRAM cells. RESET pulse condition is fixed at 1 mA, TRESET = 50 ns before each SET program. The SET operation is achieved by staircase down pulse to guarantee a completely crystalline state and a better SET resistance distribution. For the TST devices, the cell resistance transition from amorphous state to crystalline state begins at 0.3 mA. It can be noted that as the current increases, the set-state resistance also decreases slowly and tends to be stable. However, when the SET current increases up to 0.6 mA, the SET resistance increases a little larger for the shorter
Fig. 1. (a) 1T1R memory cell structure. (b) TEM image of the blade-type PCRAM device.
layer. The programming pulse used to switch the PCRAM cells is generated by internal current source and external clock source which is controlled to meet experimental requirements. The resistance is calculated by applying dc readout voltage of 0.3 V after each programming operation. 3. Result and discussion 3.1. High speed performance characterization There are two basic types of current pulses, SET pulse and RESET pulse, to program a PCRAM cell to crystalline and amorphous states. The SET pulse usually is a smaller and longer single pulse that heats the phase change material to the crystalline temperature and slow-quench the material for re-crystallization, compared with the RESET pulse. In addition to the conventional SET pulses, an improved SET operation in our work allows the 6-step staircase-down SET pulse to stop at any step. Fig. 2(a) shows the different shape of the SET pulses which are 1-, 2-, 4-,
Fig. 2. (a) Schematic of various staircase down SET pulses discussed in this work (b) Measured SET Shmoo for using different staircase down SET steps. 400
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Fig. 3. (a) The resulting minimum resistance distribution of 16 K cells using above SET pulses. (b) Box plot of four different SET pulses.
Fig. 4. (a) SET current dependence of average SET resistance of PCRAM cells. The PCRAM cells are programmed to the same RESET state before each SET operation. (b) The impact of SET pulse width on SET resistance distribution plot of PCRAM cells. The low resistance state (crystalline) can be reached within 45 ns.
pulse. The high temperature caused by the greater current amplitude in short pulse-width case, which is more likely to RESET the cell, is mainly responsible for this phenomenon. In the case of shorter SET pulses, the pulse current needs to be optimized to prevent such a situation. The SET distribution plot of a 16 K sample obtained with the staircase down pulses using different pulse widths, from which SET current of the device is 0.6 mA, is illustrated in Fig. 4(b). Before each SET operation, the same RESET pulses are applied to the devices, which results in the same RESET resistance. It is noticed that when the SET pulse time increases, providing sufficient energy for crystal growth, the SET resistance tends to be lower. On the other hand, when the pulse duration is longer than 90 ns, the difference between the SET resistance distributions is very small. Data collected at an array level shows that the SET operation at 45 ns has also succeeded in turning high impedance memory cell into low impedance state with one order of magnitude difference. It is important to reduce the TSET for realizing fast PCRAM operation since TSET is much longer than TRESET for the PCRAM programming in general. The SET pulse width (TSET) dependency of SET resistance is characterized with different materials. Fig. 5 compares the SET time for SET operations between TST and traditional GST memory devices when the amplitude of current pulses is set to be 0.6 mA to provide sufficient energy for the SET transition. Therefore, we make comparisons of the shortest pulse with a significant difference in resistance. It can be found that the programming time of the TST device can be as low as 45 ns, which is only 20% of the SET time of GST device. This result illustrates that the TST device can operate with a much shorter SET pulse for
Fig. 5. The average SET resistance of PCRAM cells using TST and GST alloy as a function of SET time. The SET programming is achieved by staircase down pulses.
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amorphous volume have more structural relaxation (SR) centers are more inclined to drift as compared with lower resistance levels. As showed in Fig. 6(a), the full RESET resistance which corresponds to the highest resistance level has a resistance-drift coefficient v as low as 0.02, while reported v of GST-225 is about 0.096. It is also noticeable that the drift of TST cell at crystalline state is negligible [14]. The low drift property of TST alloy is conducive to the realization of MLC storage in PCRAM. To investigate the drift at the array level, the cumulative distributions of full RESET state resistance, which is the highest resistance drift level of TST, with increasing time are evaluated. Resistance–time (R–t) relationship were characterized by collecting at data at the array level in the following procedures: First, all the cells in the array are programmed to the amorphous state, and then, the resistance is read at a read voltage VREAD = 0.3 V with increasing times. Care is taken to ensure that the elapsed time elapsed between RESET/SET operation and resistance readout for all the cells in the array are the same. Fig. 6(b) shows that the distribution shifts toward to the right which means resistances become larger, with the distribution spread being very slow. While the average value in the distribution is in good agreement with the same power-law drift ν as in Fig. 6(a). Another reliability of the PCRAM is cycle endurance, and further improvement of cycle performance could be achieved by a control of dopants in the TST alloy or by crafts optimization. Fig. 7 compares the cycling endurance characteristics of PCRAM devices based on GST and TST materials. The cycling endurance characteristic of TST is one order of magnitude better than that of GST under the same cycle condition. The PCRAM device based on TST material exhibits a cycling endurance performance up to 106 without failure. It is noticeable that the ratio between amorphous and polycrystalline state resistance of TST is almost two orders of magnitude before resistance destruction failure, enabling the use of PCRAM for DRAM and the embedded application.
4. Conclusions In summary, the performance of a phase change nonvolatile memory device employing TST chalcogenide alloy has been characterized. It is proved that the fabricated device using TST described a kind of memory programming operation with higher speed TSET and lower drift v, compared with the operation behaviors of the device utilizing a conventional GST material, still conserve a moderate cycling performance. Based on these obtained results, we can conclude that TST has a high potential for one of the most promising PCRAM materials with lower drift and higher speed operations.
Fig. 6. (a) Measured resistance as a function of time after the program, for different resistance levels. (b) Cumulative distributions of the RESET resistance for increasing times measured at room temperature. The RESET condition is fixed as TRESET = 50 ns, IRESET = 1 mA.
crystallization as compared with GST device, higher speed for recrystallization, which is related to the Ti-centered atomic motifs (TCAMs), as these structures could act as nucleation centers to facilitate faster transition [11]. Meanwhile, the ratio between amorphous and crystalline states of TST material is higher than that of GST, which is helpful to distinguish between logic 0 and 1 and improve the stability during the whole life of a device. 3.2. Drift of the TST phase-change device and endurance The MLC storage in PCRAM, which can store more than one bit of information per memory cell [12], leads to more device functionality and are currently of high demand due to the rapid increase in big-data storage applications [13]. Resistance drift is a major concern for MLC programming because it limits the number of different resistance levels that can be reliably readout. The resistance drift is generally described by a power-law dependence on time t given by the empirical formula R (t) = R0(t/t0)v, where R0 and t0 are normalization constants and v is drift exponent coefficient [9]. Fig. 6(a) shows the drift phenomenon of TST PCRAM device programmed to different resistance levels. The varying resistance of those states is drawn as a function of the measurement time at room temperature. It can be found that levels of higher resistivity exhibit higher values of v since higher resistance levels which stem from a larger
Fig. 7. Cycling endurance characteristics of the PCRAM device based on GST and TST material. 402
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Acknowledgements
[5] S.J. Ahn, Y.J. Song, C.W. Jeong, J.M. Shin, Y. Fai, Y.N. Hwang, S.H. Lee, K.C. Ryoo, S.Y. Lee, J.H. Park, H. Horii, Y.H. Ha, J.H. Yi, B.J. Kuh, G.H. Koh, G.T. Jeong, H.S. Jeong, K.K.K. Kim, B.I. Ryu, Highly manufacturable high density phase change memory of 64Mb and beyond IEDM, Tech. Dig. - Int. Electron Devices Meet. (2004) 907–910. [6] H.-S.P. Wong, S. Raoux, S. Kim, J. Liang, J.P. Reifenberg, B. Rajendran, M. Asheghi, K.E. Goodson, Phase change memory, Proc. IEEE 98 (2010) 2201–2227. [7] B.C. Lee, E. Ipek, O. Mutlu, D. Burger, Architecting phase change memory as a scalable dram alternative, ACM SIGARCH Comput. Archit. News 37 (2009) 2. [8] H.Y. Cheng, T.H. Hsu, S. Raoux, J.Y. Wu, P.Y. Du, M. Breitwisch, Y. Zhu, E.K. Lai, E. Joseph, S. Mittal, R. Cheek, a. Schrott, S.C. Lai, H.L. Lung, C. Lam, A high performance phase change memory with fast switching speed and high temperature retention by engineering the GexSbyTez phase change material, IEEE Int. Electron Devices Meet. (2011) (3.4.1-3.4.4). [9] J.H. Wang, J. Zhou, W.L. Zhou, H. Tong, D.Q. Huang, J.J. Sun, L. Zhang, X.M. Long, Y. Chen, L.W. Qu, X.S. Miao, A high speed asymmetric T-shape cell in NMOS-selected phase change memory chip, Solid. State Electron. 81 (2013) 157–162. [10] J. Lee, S. Cho, D. Ahn, M. Kang, S. Nam, H.K. Kang, C. Chung, Scalable high-performance phase-change memory employing CVD GeBiTe, IEEE Electron Device Lett. 32 (2011) 1113–1115. [11] M. Zhu, M. Xia, F. Rao, X. Li, L. Wu, X. Ji, S. Lv, Z. Song, S. Feng, H. Sun, S. Zhang, One order of magnitude faster phase change at reduced power in Ti-Sb-Te, Nat. Commun. 5 (2014) 1–6. [12] F. Bedeschi, R. Fackenthal, C. Resta, E.M. Donze, M. Jagasivamani, E.C. Buda, F. Pellizzer, D.W. Chow, A. Cabrini, G.M.A. Calvi, R. Faravelli, A. Fantini, G. Torelli, D. Mills, R. Gastaldi, G. Casagrande, A bipolar-selected phase change memory featuring multi-level cell storage, IEEE J. Solid-State Circuits 44 (2009) 217–227. [13] A. Athmanathan, M. Stanisavljevic, N. Papandreou, H. Pozidis, E. Eleftheriou, Multilevel-cell phase-change memory: a viable technology, IEEE J. Emerg. Sel. Top. Circuits Syst. 6 (2016) 87–100. [14] D. Ielmini, S. Lavizzari, D. Sharma, A.L. Lacaita, Physical interpretation, modeling and impact on phase change memory (PCM) reliability of resistance drift due to chalcogenide structural relaxation, Tech. Dig. - Int. Electron Devices Meet. IEDM (2007) 939–942.
This work was supported by the National Key Research and Development Program of China (2017YFA0206101, 2017YFB0701703), "Strategic Priority Research Program" of the Chinese Academy of Sciences (XDA09020402), National Integrate Circuit Research Program of China (2009ZX02023-003), National Natural Science Foundation of China (61874178, 61376006, 61401444, 61504157, 61622408), Science and Technology Council of Shanghai (17DZ2291300). References [1] S.M. Yoon, N.Y. Lee, S.O. Ryu, K.J. Choi, Y.S. Park, S.Y. Lee, B.G. Yu, M.J. Kang, S.Y. Choi, M. Wuttig, Sb-Se-based phase-change memory device with lower power and higher speed operations, IEEE Electron Device Lett. 27 (2006) 445–447. [2] F. Pellizzer, A. Pirovano, F. Ottogalli, M. Magistretti, M. Scaravaggi, P. Zuliani, M. Tosi, A. Benvenuti, P. Besana, S. Cadeo, T. Marangon, R. Morandi, R. Piva, A. Spandre, R. Zonca, A. Modelli, E. Varesi, T. Lowrey. A. Lacaita, G. Casagrande, P. Cappelletti, R. Bez, Novel µ trench phase-change memory cell for ebedded and stand-aone non-volatile memory applications, Dig. Tech. Pap. 2004 Symp. VLSI Technol., 2004, pp. 18–9. [3] N. Takaura, M. Terao, K. Kurotsuchi, T. Yamauchi, O. Tonomura, Y. Hanaoka, R. Takemura, K. Osada, T. Kawahara, H. Matsuoka, A GeSbTe phase-change memory cell featuring a tungsten heater electrode for low-power, highly stable, and short-read-cycle operations, IEEE Int. Electron Devices Meet. 2003 (2003) 897–900. [4] S.J. Ahn, Y.N. Hwang, Y.J. Song, S.H. Lee, S.Y. Lee, J.H. Park, C.W. Jeong, K.C. Ryoo, J.M. Shin, J.H. Park, Y. Fai, J.H. Oh, G.H. Koh, G.T. Jeong, S.H. Joo, S.H. Choi, Y.H. Son, J.C. Shin, Y.T. Kim, H.S. Jeong, K. Kim, Highly reliable 50nm contact cell technology for 256Mb PRAM, Dig. Tech. Pap. - Symp. VLSI Technol. 2005 (2005) 98–99.
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Fast switching and low drift of TiSbTe thin films for phase change memory applications
T
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Yuan-Guang Liua,b, Yi-Feng Chena, , Dao-Lin Caia, Yao-Yao Lua,b, Lei Wua,b, Shuai Yana,b, Yang Lia,b, Zhi-Tang Songa a
State Key Laboratory of Functional Materials for Informatics and Nanotechnology Laboratory, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, People's Republic of China b University of Chinese Academy of Sciences, Beijing 100080, People's Republic of China
A R T I C LE I N FO
A B S T R A C T
Keywords: Phase-change random-access memory (PCRAM) TiSbTe (TST) High speed Low drift 4 Mb chip Embedded application
As the non-volatile storage medium of the next generation, phase-change random-access memory (PCRAM) has characteristics such as high density, low cost and a wide range of market applications. However, the write speed of GST-based PCRAM falls short of the current DRAM memories and its applications domain expansion is limited. In this article, TiSbTe (TST) shows good performance both in high speed and low drift due to its fast crystallization rate and titanium-centered stable octahedral structure. The promising properties of this new material are illustrated in a 4 Mb chip for embedded applications and tested at wafer level, and the results show that the crystallization speed of TST is improved by 80% and a smaller resistance drift is achieved, with the drift exponent coefficient of highest resistance level being as low as is 0.02, compared with GeSbTe (GST).
1. Introduction Phase-change random access memory (PCRAM) has been attracting more attention as one of the most promising nonvolatile candidates for the next-generation unified memory devices because of its prominent performance, such as low operation voltage, logic compatibility and large sensing signal [1–5]. PCRAM utilizes the characteristic of chalcogenide material which can reversibly switch between amorphous state (high resistance) and crystalline state (low resistance) by applying electrical pulses to store information ('0' and '1'). With the development of CMOS standard process which scales down to nanometer length, the PCRAM have a broader market application prospects in the future [6,7]. So far, Ge2Sb2Te5 (GST) is the main stream material used in PCRAM. However, it has several drawbacks in the application, such as slow SET speed compared with dynamic random-access memory (DRAM), high RESET current [8]. For the realization of future fast speed PCRAM to meet DRAM-like applications, SET speed should be totally investigated. Some researchers point out new structure such as T-shape cell and the confined-cell, programming circuit and the new chemical vapor deposition technology can help the realization of high speed [9,10]. These methods mainly focus on single cell and microstructure characteristic, the performance of material on a statistics level is not well studied yet for embedded application. Besides, multilevel-cell (MLC) storage of
⁎
PCRAM is one of the future development trends to meet the growing high-density demand, and resistance drift has been a major concern to achieve sustainable MLC reliability. In this paper, we report the good performance of the phase-change device using a new chalcogenide material of TiSbTe (TST) alloy and examined its characteristics in 4 M phase-change memory device. The devices based on TST material show a fast crystallization speed and low resistance drift characteristic. 2. Material and device In this work, the experiment data are collected on cells of a 4 Mb PCRAM test chip with an Automatic test equipment (ATE) machine which uses automation to quickly performs tests on the electronic devices and systems. The performance of the PCRAM device based on TST material has been assessed demonstrating the significant potential application prospects. The PCRAM test chip depicted in Fig. 1(a) consists of one-transistor-and-one-resistor (1T1R) memory cells integrated in 40 nm CMOS technology. The storage cells are the specific PCRAM devices, using TST alloy as phase change material, with the blade-type heat electrode made by titanium nitride (TiN) and metal tungsten (W) top-bottom electrode, the structure of which is displayed in Fig. 1(b). The 100 nm thick TST layer is deposited by a physical vapor deposition (PVD) method on the heat electrode contact with TiN as the adhesive
Corresponding author. E-mail address: [email protected] (Y.-F. Chen).
https://doi.org/10.1016/j.mssp.2018.12.009 Received 30 September 2018; Received in revised form 5 November 2018; Accepted 6 December 2018 1369-8001/ © 2018 Elsevier Ltd. All rights reserved.
Materials Science in Semiconductor Processing 91 (2019) 399–403
Y.-G. Liu et al.
and 6-step staircase down pulses. Fig. 2(b) illustrates the measured Shmoo that shows the SET current (ISET) dependency of average SET resistance for using the above pulses while TSET is fixed in 360 ns. The 16 Kbits cells are initially operated to the amorphous state with identical RESET pulses of 50 ns,1 mA before applying the different shape SET pulses. The color gradient corresponds to the logarithmic scale of SET resistance. In the case of various program pulses, the ISET which is capable of reducing the logarithm of SET resistance under 4.5 is different. When the ISET increases, the pulses with few steps might fail to program the cell to the crystalline state. The dark blue color indicates that pulses with more steps possess more obvious SET characteristics. To further investigate the difference of resistance between various step SET pulses, the distributions from an array of 16 K cells of the resulting minimum SET resistance using those pulses are shown in Fig. 3(a). It suggests that the minimum SET resistance of more staircase steps program pulses is lower than that from using fewer steps pulses. For 6-step pulses, the miss rate from an array that fails to program the logarithm of cells resistance under the 4.5 is lowest. It is more obvious in Fig. 3(b) that as the staircase step increases, the minimum set resistance decrease and the cells consistency becomes better. For the SET process, staircase-down pulses with more steps are more conducive to achieving lower minimum SET resistance distribution. Base on the study above, we conduct some researches about the speed limit of TST PCRAM device using the 6-step staircase down SET pulse. Hereinafter the staircase down pulse mentioned in the following research default is 6-step. Fig. 4(a) shows the average SET resistance as a function of the current with various pulse-widths by measuring the 16 K PCRAM cells. RESET pulse condition is fixed at 1 mA, TRESET = 50 ns before each SET program. The SET operation is achieved by staircase down pulse to guarantee a completely crystalline state and a better SET resistance distribution. For the TST devices, the cell resistance transition from amorphous state to crystalline state begins at 0.3 mA. It can be noted that as the current increases, the set-state resistance also decreases slowly and tends to be stable. However, when the SET current increases up to 0.6 mA, the SET resistance increases a little larger for the shorter
Fig. 1. (a) 1T1R memory cell structure. (b) TEM image of the blade-type PCRAM device.
layer. The programming pulse used to switch the PCRAM cells is generated by internal current source and external clock source which is controlled to meet experimental requirements. The resistance is calculated by applying dc readout voltage of 0.3 V after each programming operation. 3. Result and discussion 3.1. High speed performance characterization There are two basic types of current pulses, SET pulse and RESET pulse, to program a PCRAM cell to crystalline and amorphous states. The SET pulse usually is a smaller and longer single pulse that heats the phase change material to the crystalline temperature and slow-quench the material for re-crystallization, compared with the RESET pulse. In addition to the conventional SET pulses, an improved SET operation in our work allows the 6-step staircase-down SET pulse to stop at any step. Fig. 2(a) shows the different shape of the SET pulses which are 1-, 2-, 4-,
Fig. 2. (a) Schematic of various staircase down SET pulses discussed in this work (b) Measured SET Shmoo for using different staircase down SET steps. 400
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Fig. 3. (a) The resulting minimum resistance distribution of 16 K cells using above SET pulses. (b) Box plot of four different SET pulses.
Fig. 4. (a) SET current dependence of average SET resistance of PCRAM cells. The PCRAM cells are programmed to the same RESET state before each SET operation. (b) The impact of SET pulse width on SET resistance distribution plot of PCRAM cells. The low resistance state (crystalline) can be reached within 45 ns.
pulse. The high temperature caused by the greater current amplitude in short pulse-width case, which is more likely to RESET the cell, is mainly responsible for this phenomenon. In the case of shorter SET pulses, the pulse current needs to be optimized to prevent such a situation. The SET distribution plot of a 16 K sample obtained with the staircase down pulses using different pulse widths, from which SET current of the device is 0.6 mA, is illustrated in Fig. 4(b). Before each SET operation, the same RESET pulses are applied to the devices, which results in the same RESET resistance. It is noticed that when the SET pulse time increases, providing sufficient energy for crystal growth, the SET resistance tends to be lower. On the other hand, when the pulse duration is longer than 90 ns, the difference between the SET resistance distributions is very small. Data collected at an array level shows that the SET operation at 45 ns has also succeeded in turning high impedance memory cell into low impedance state with one order of magnitude difference. It is important to reduce the TSET for realizing fast PCRAM operation since TSET is much longer than TRESET for the PCRAM programming in general. The SET pulse width (TSET) dependency of SET resistance is characterized with different materials. Fig. 5 compares the SET time for SET operations between TST and traditional GST memory devices when the amplitude of current pulses is set to be 0.6 mA to provide sufficient energy for the SET transition. Therefore, we make comparisons of the shortest pulse with a significant difference in resistance. It can be found that the programming time of the TST device can be as low as 45 ns, which is only 20% of the SET time of GST device. This result illustrates that the TST device can operate with a much shorter SET pulse for
Fig. 5. The average SET resistance of PCRAM cells using TST and GST alloy as a function of SET time. The SET programming is achieved by staircase down pulses.
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amorphous volume have more structural relaxation (SR) centers are more inclined to drift as compared with lower resistance levels. As showed in Fig. 6(a), the full RESET resistance which corresponds to the highest resistance level has a resistance-drift coefficient v as low as 0.02, while reported v of GST-225 is about 0.096. It is also noticeable that the drift of TST cell at crystalline state is negligible [14]. The low drift property of TST alloy is conducive to the realization of MLC storage in PCRAM. To investigate the drift at the array level, the cumulative distributions of full RESET state resistance, which is the highest resistance drift level of TST, with increasing time are evaluated. Resistance–time (R–t) relationship were characterized by collecting at data at the array level in the following procedures: First, all the cells in the array are programmed to the amorphous state, and then, the resistance is read at a read voltage VREAD = 0.3 V with increasing times. Care is taken to ensure that the elapsed time elapsed between RESET/SET operation and resistance readout for all the cells in the array are the same. Fig. 6(b) shows that the distribution shifts toward to the right which means resistances become larger, with the distribution spread being very slow. While the average value in the distribution is in good agreement with the same power-law drift ν as in Fig. 6(a). Another reliability of the PCRAM is cycle endurance, and further improvement of cycle performance could be achieved by a control of dopants in the TST alloy or by crafts optimization. Fig. 7 compares the cycling endurance characteristics of PCRAM devices based on GST and TST materials. The cycling endurance characteristic of TST is one order of magnitude better than that of GST under the same cycle condition. The PCRAM device based on TST material exhibits a cycling endurance performance up to 106 without failure. It is noticeable that the ratio between amorphous and polycrystalline state resistance of TST is almost two orders of magnitude before resistance destruction failure, enabling the use of PCRAM for DRAM and the embedded application.
4. Conclusions In summary, the performance of a phase change nonvolatile memory device employing TST chalcogenide alloy has been characterized. It is proved that the fabricated device using TST described a kind of memory programming operation with higher speed TSET and lower drift v, compared with the operation behaviors of the device utilizing a conventional GST material, still conserve a moderate cycling performance. Based on these obtained results, we can conclude that TST has a high potential for one of the most promising PCRAM materials with lower drift and higher speed operations.
Fig. 6. (a) Measured resistance as a function of time after the program, for different resistance levels. (b) Cumulative distributions of the RESET resistance for increasing times measured at room temperature. The RESET condition is fixed as TRESET = 50 ns, IRESET = 1 mA.
crystallization as compared with GST device, higher speed for recrystallization, which is related to the Ti-centered atomic motifs (TCAMs), as these structures could act as nucleation centers to facilitate faster transition [11]. Meanwhile, the ratio between amorphous and crystalline states of TST material is higher than that of GST, which is helpful to distinguish between logic 0 and 1 and improve the stability during the whole life of a device. 3.2. Drift of the TST phase-change device and endurance The MLC storage in PCRAM, which can store more than one bit of information per memory cell [12], leads to more device functionality and are currently of high demand due to the rapid increase in big-data storage applications [13]. Resistance drift is a major concern for MLC programming because it limits the number of different resistance levels that can be reliably readout. The resistance drift is generally described by a power-law dependence on time t given by the empirical formula R (t) = R0(t/t0)v, where R0 and t0 are normalization constants and v is drift exponent coefficient [9]. Fig. 6(a) shows the drift phenomenon of TST PCRAM device programmed to different resistance levels. The varying resistance of those states is drawn as a function of the measurement time at room temperature. It can be found that levels of higher resistivity exhibit higher values of v since higher resistance levels which stem from a larger
Fig. 7. Cycling endurance characteristics of the PCRAM device based on GST and TST material. 402
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Acknowledgements
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