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Fast thermal nanoimprint lithography by a stamp with integrated heater
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Microelectronic Engineering 85 (2008) 1229–1232 www.elsevier.com/locate/mee
Fast thermal nanoimprint lithography by a stamp with integrated heater Massimo Tormen a,*, Radu Malureanu a,1, Rasmus Haugstrup Pedersen b, Lasse Lorenzen b, Kristian Hagsted Rasmussen b, Christopher James Lu¨scher b, Anders Kristensen b, Ole Hansen b,c a TASC Laboratory, National Institute for the Physics of Matter, S.S. 14 km. 163.5, I-34012 Basovizza-Trieste, Italy MIC – Department of Micro- and Nanotechnology, Technical University of Denmark, Building 345E, Lyngby DK-2800, Denmark c CINF – Center for Individual Nanaparticle Functionality, Technical University of Denmark, Building 345E, Lyngby DK-2800, Denmark b
Received 8 October 2007; received in revised form 14 January 2008; accepted 15 January 2008 Available online 1 February 2008
Abstract We propose fast nanoimprinting lithography (NIL) process based on the use of stamps with integrated heater. The latter consists of heavily ion implantation n-type doped silicon layer buried below the microstructured surface of the stamp. The stamp is heated by Joule effect, by 50 ls 25 Hz repetition rate current pulses flowing in the conductive layer. Using this approach we have reproducibly imprinted areas of 2 cm2 within 16 s with residual layers in the range of few tens of nm. This result paves the way for processes in the sub-1 s timescale over large area surfaces. Ó 2008 Elsevier B.V. All rights reserved. Keywords: Nanoimprint lithography; Stamps; Integrated heater; Joule effect
1. Introduction The possibility of forming sub-lm scale features in thin thermoplastic polymer within microseconds as a result of pressure and fast heating/cooling cycles has been demonstrated in a few different processes. An example is the millipede approach [1] developed at IBM (Zurich) for data storage applications, where dense arrays of 30–40 nm diameter pits are formed by an array of AFM tips independently addressed and heated by 1 ls current pulses. More recently, a process of NIL has been accomplished within 250 ns [2] by shining through a quartz stamp a single laser pulse to melt a resist film. The stamp features sink into it, being the stamp under the action of a constant pressure. *
Corresponding author. E-mail address: [email protected] (M. Tormen). 1 Present address: COM – Department of Communications, Optics and Materials, Technical University of Denmark, Building 345V, Lyngby DK2800, Denmark. 0167-9317/$ - see front matter Ó 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2008.01.065
On the contrary, the timescale at which thermal NIL [3] is currently performed is of the order of minutes [4,5], i.e. several orders of magnitude slower than the physical process limitation. The limited process speed is commonly explained with the viscous flow resistance experienced by a melt thermoplastic polymer traveling in narrow channels of 10–100 nm for distances of 1–100 lm [6]. However, as experimentally demonstrated by the two fast processes cited above [1,2], the rheological limitations could be overcome at higher temperatures, i.e. at lower polymer viscosity. In fact, the main reason for not increasing the process temperature has a more technical and practical origin, represented by the large thermal capacity of the mass (mainly the hot plates) involved in the heating/cooling cycle. This prevents a fast heating of the polymer at temperatures higher enough, so as to guarantee a sufficient viscosity reduction of the resist film and a faster imprinting process. Additional drawbacks of the current approach to thermal NIL are in that: (i) the sample and stamp substrates
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M. Tormen et al. / Microelectronic Engineering 85 (2008) 1229–1232
undergo a large thermal expansion limiting the registration accuracy in multilevel processes [7]; (ii) the thermal energy stored in the hot plates is wasted at each thermal cycle, increasing the energetic cost of the process. This fact might be very relevant in future in mass production. With the purpose of overcoming these drawbacks, which could otherwise obscure the big merits of NIL technique, i.e. ultrahigh resolution (5 nm), large area processing, and low cost, we propose an approach based on stamps with an integrated extended heater, setting a target of 1 s embossing time on wafer scale areas. In this approach the heat is obtained by dissipating the energy of a short pulse of current flowing as a uniform sheet in a resistive layer buried just below the microstructured surface of the stamp. With short duration pulses, i.e. in the range of 1–100 ls, it is possible to heat efficiently the stamp surface and the resist film by heat diffusion, without heating the entire stamp substrate.
2. Heat transport simulation As a guide to experiments we have implemented a code for calculating the heat propagation in a stack of layers of different materials. We assume that heat is produced by resistive dissipation of the energy of a square wave current pulse in a layer embedded in the stack (the stamp heater). Therefore, we have simulated potential experimental conditions corresponding to various configurations of materials and thicknesses in the stack of layers and different duration and intensity of current pulses. The output data can be plotted as temperature profile across the stack at different times during and after the pulse (heating and cooling stage). We report here the results of the simulations corresponding to the actual experiments of successful imprinting process. The plots of Fig. 1 refer to the following simulated conditions. The sequence of layers in the stack consists of (1)
Fig. 1. (A) Simulated temperature profile at different times during a 50 ls pulse according to the conditions described in the text. The inset shows the close view of the temperature profile in the region of the stamp/resist interface. (B) Simulated temperature profile at different times after the 50 ls pulse. (C) Simulated temperature profile in the stack of layers, corresponding to a continuous heating power of 30 W/cm2. (D) Temperature at the stamp/resist interface. Peaks superimpose to an average temperature build-up in the stack of layer (not all peaks are represented in the plot).
M. Tormen et al. / Microelectronic Engineering 85 (2008) 1229–1232
kapton foil (compensation layer, 150 lm), (2) silicon (stamp substrate, 498 lm), (3) highly doped silicon (heater, 2 lm), (4) resist (250 nm), (5) silicon (sample substrate, 500 lm), and (6) kapton foil (compensation layer, 150 lm). The thermal capacity and thermal diffusion coefficients of the various materials have been obtained from tabulated data. The temperature dependence of the material properties has been neglected. We assume to dissipate in the heater (layer 3) 1.2 J/cm2 in a 50 ls pulse. With a sheet resistance of 4 X square corresponding to that measured in the fabricated stamps (see below) this requires a value of 77.5 A for the current injected in the heater (2 lm 1 cm, thickness width) and an electric field 310 V/cm. The simulation shows that the temperature rises from the initial value of 25 °C (RT) to 120 °C at the end of the 50 ls pulse at the stamp/resist interface. This temperature is certainly not sufficient for the hot embossing step in such a short timescale and, indeed, this was the case also in the experiments. However, we notice that after each pulse the temperature distribution broadens, because of heat diffusion, causing an average temperature build-up in the silicon substrates (stamp and sample), we have exploited this effect in a process based on the combination of bulk and surface, ls-scale second-scale heating, as intermediate development step toward the final target. Therefore, we have simulated the temperature build-up in the stack of layers with 25 Hz repetition rate pulses. At a coarsegrained timescale, we see that after a transient of 2 s the time-averaged temperature saturates to a uniform value of 145 °C, whereas steep temperature gradients arise in
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the kapton foils, at the boundaries of the stack. Therefore, during the pulse in the region of the stamp/resist interface the 95 °C jump in the temperature is superimposed on an average temperature of 145 °C to reach a peak temperature of 240 °C. 3. Experimental A dedicated set-up consisting of a press and a high power pulse generator has been developed for the NIL experiments based on stamp with integrated heater. The press consists essentially of two concentric bellows of steel connected to a base and to a lid with an internal piston fixed to it. The press is actuated by a combination of compressed air and vacuum in the inner chamber (the inner bellow) and outer chamber (between inner and outer bellows). This allows setting independently the value of the force that the piston can exert and the pressure and the type of atmosphere in the inner chamber (vacuum, air or inert gas). This press design also provides a self tilt correction mechanism that ensures the parallelism of the stamp and sample. The maximum force is 3.5 kN and the force resolution 0.1 kN. An electric feedthrough brings the electrical pulses to the inner chamber where the stamp is connected by CuBe clamps. To avoid sparks in the inner chamber all edges had to be rounded. The pulse generator realized for the process of pulsed NIL is essentially based on the discharge of a bank of capacitors onto the load (the stamp heater, 1–5 X) through an inductance. Modifying in discrete steps the values of the capacity and the inductance
Fig. 2. Optical micrographs of imprinted gratings obtained by imprinting with 16 s (above) and 30 s (below) process time. The measured residual layer at the center and corner of the different gratings and for the different process times are given in Table 1.
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Table 1 Averaged values of resist residual layer at different location of the imprinted pattern and for different imprinting time as shown in Fig. 2 16 s Residual layer (nm)
A 32.6 ± 15.0
B 106.6 ± 7.7
C 16.3 ± 5.3
D 35.9 ± 3.7
30 s Residual layer (nm)
E 9.8 ± 5.8
F 12.2 ± 5.4
G 23.3 ± 9.5
H 65.2 ± 6.0
(between 4–27 lF and 5–20 lH, respectively) and varying continuously the charging voltage of the capacitors (up to 1500 V) the pulse duration (10–100 ls) and shape and total energy delivered (0–20 J) can be changed. The fabrication of the stamp with heater was done according to the following process sequence. Double sided polished 100 mm {1 0 0} silicon wafers were blanket implanted with a 31P ion dose of 2 1016/cm2 at 200 keV. Following an RCA clean the wafers were oxidized in water vapour at 1100 °C for 9 min and annealed in nitrogen for 36 min at the same temperature. This treatment results in a 280 nm thick oxide. Using conventional UV lithography with 1.5 lm AZ 5214 photoresist on the front side of the wafers the imprint pattern was defined in the photoresist and subsequently transferred to the oxide by wet etching in buffered hydrofluoric acid. Following a resist strip, ebeam evaporated contact metal (Cr/Au 10 nm/200 nm) was defined by lift off. The contact metal was annealed in nitrogen at 300 °C for 20 min. Finally, the 2 4cm2 stamps were diced using a dicing saw. The stamps where surface treated for antiadhesion with a solution 1 mM of dodecyltrichlorosilane in toluene.
long range polymer flow). The measurements, taken at the corner and at the center of each type of grating for the 16 s and 30 s experiments, were averaged over 10 different equivalent locations randomly selected in the imprinted area. The results are summarized in Table 1. 5. Conclusions We have demonstrated a fast process of thermal nanoimprinting lithography that employs stamps with extended integrated heater. The results appear of high quality and the residual layer can be kept in the range of few tens of nm with total process time of the order of 10 s. We believe that the process can be further improved, mainly acting on the layout of the heatable stamp, in particular by introducing a thin thermal barrier under the layer of the heater, which would reduce heat diffusion towards the stamp substrate increasing effectively the temperature that the resist film reaches during a pulse. Acknowledgements We are thankful to Mr. Valerio Rizzi for valuable discussion on the power electronics system. The partial support of the EC-funded project NaPa (Contract No. NMP4-CT-2003-500120) is gratefully acknowledged. Center for Individual Nanoparticle Functionality (CINF) is sponsored by The Danish National Research Foundation. The content of this work is the sole responsibility of the authors.
4. Results References 2
The imprinting tests were performed on 2 1 cm silicon substrates with a 240 nm thick mr-I 7000E (Microresist) resist coating. Reproducible results (Fig. 2) were obtained with the following conditions: 1100 V peak voltage, 220 A peak current, 50 ls duration, 25 Hz repetition rate. The energy delivered in each pulse was 1.2 J/cm2 with an average power of 30 W/cm2. Two sets of experiments were performed with total duration of the pulse sequence of 16 s and 30 s, respectively. The results appear uniform over the 2 1 cm2 sample area and no defects were detected (with the exception of the few ones clearly attributed to the presence of a dust particle). We measured the residual layer thickness in 20/20 and 20/80 lm L/S gratings (large structures were chosen deliberately in order to prove the process on a pattern requiring
[1] P. Vettiger, M. Despont, U. Drechsler, U. Durig, W. Haberle, M.I. Lutwyche, H.E. Rothuizen, R. Stutz, R. Widmer, G.K. Binnig, IBM J. Res. Develop. 44 (2000) 323–340. [2] Qiangfei Xia, Zhaoning Yu, He Gao, Stephen Y. Chou, Appl. Phys. Lett. 89 (2006) 073107. [3] Stephen Y. Chou, Peter R. Krauss, Preston J. Renstrom, J. Vac. Sci. Technol. B 14 (1996) 4129. [4] Babak Heidari, Ivan Maximov, Eva-Lena Sarwe, Lars Montelius, J. Vac. Sci. Technol. B 17 (6) (1999). [5] C. Gourgon, C. Perret, G. Micouin, F. Lazzarino, J.H. Tortai, O. Joubert, J.-P.E. Grolier, J. Vac. Sci. Technol. B 21 (1071) (2003). [6] Helmut Schift, Laura J. Heyderman, Nanorheology, in: C.M. Sotomayor Torres (Ed.), Alternative Lithography: Unleashing the Potentials of Nanotechnology, Kluwer Academic Publishers, 2004, ISBN 0306478587 (Chapter 4). [7] Y. Chen, J. Tao, X. Zhao, Z. Cui, J. Microlithogr., Microfabricat. Microsyst. 5 (2006) 011002.
Microelectronic Engineering 85 (2008) 1229–1232 www.elsevier.com/locate/mee
Fast thermal nanoimprint lithography by a stamp with integrated heater Massimo Tormen a,*, Radu Malureanu a,1, Rasmus Haugstrup Pedersen b, Lasse Lorenzen b, Kristian Hagsted Rasmussen b, Christopher James Lu¨scher b, Anders Kristensen b, Ole Hansen b,c a TASC Laboratory, National Institute for the Physics of Matter, S.S. 14 km. 163.5, I-34012 Basovizza-Trieste, Italy MIC – Department of Micro- and Nanotechnology, Technical University of Denmark, Building 345E, Lyngby DK-2800, Denmark c CINF – Center for Individual Nanaparticle Functionality, Technical University of Denmark, Building 345E, Lyngby DK-2800, Denmark b
Received 8 October 2007; received in revised form 14 January 2008; accepted 15 January 2008 Available online 1 February 2008
Abstract We propose fast nanoimprinting lithography (NIL) process based on the use of stamps with integrated heater. The latter consists of heavily ion implantation n-type doped silicon layer buried below the microstructured surface of the stamp. The stamp is heated by Joule effect, by 50 ls 25 Hz repetition rate current pulses flowing in the conductive layer. Using this approach we have reproducibly imprinted areas of 2 cm2 within 16 s with residual layers in the range of few tens of nm. This result paves the way for processes in the sub-1 s timescale over large area surfaces. Ó 2008 Elsevier B.V. All rights reserved. Keywords: Nanoimprint lithography; Stamps; Integrated heater; Joule effect
1. Introduction The possibility of forming sub-lm scale features in thin thermoplastic polymer within microseconds as a result of pressure and fast heating/cooling cycles has been demonstrated in a few different processes. An example is the millipede approach [1] developed at IBM (Zurich) for data storage applications, where dense arrays of 30–40 nm diameter pits are formed by an array of AFM tips independently addressed and heated by 1 ls current pulses. More recently, a process of NIL has been accomplished within 250 ns [2] by shining through a quartz stamp a single laser pulse to melt a resist film. The stamp features sink into it, being the stamp under the action of a constant pressure. *
Corresponding author. E-mail address: [email protected] (M. Tormen). 1 Present address: COM – Department of Communications, Optics and Materials, Technical University of Denmark, Building 345V, Lyngby DK2800, Denmark. 0167-9317/$ - see front matter Ó 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2008.01.065
On the contrary, the timescale at which thermal NIL [3] is currently performed is of the order of minutes [4,5], i.e. several orders of magnitude slower than the physical process limitation. The limited process speed is commonly explained with the viscous flow resistance experienced by a melt thermoplastic polymer traveling in narrow channels of 10–100 nm for distances of 1–100 lm [6]. However, as experimentally demonstrated by the two fast processes cited above [1,2], the rheological limitations could be overcome at higher temperatures, i.e. at lower polymer viscosity. In fact, the main reason for not increasing the process temperature has a more technical and practical origin, represented by the large thermal capacity of the mass (mainly the hot plates) involved in the heating/cooling cycle. This prevents a fast heating of the polymer at temperatures higher enough, so as to guarantee a sufficient viscosity reduction of the resist film and a faster imprinting process. Additional drawbacks of the current approach to thermal NIL are in that: (i) the sample and stamp substrates
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M. Tormen et al. / Microelectronic Engineering 85 (2008) 1229–1232
undergo a large thermal expansion limiting the registration accuracy in multilevel processes [7]; (ii) the thermal energy stored in the hot plates is wasted at each thermal cycle, increasing the energetic cost of the process. This fact might be very relevant in future in mass production. With the purpose of overcoming these drawbacks, which could otherwise obscure the big merits of NIL technique, i.e. ultrahigh resolution (5 nm), large area processing, and low cost, we propose an approach based on stamps with an integrated extended heater, setting a target of 1 s embossing time on wafer scale areas. In this approach the heat is obtained by dissipating the energy of a short pulse of current flowing as a uniform sheet in a resistive layer buried just below the microstructured surface of the stamp. With short duration pulses, i.e. in the range of 1–100 ls, it is possible to heat efficiently the stamp surface and the resist film by heat diffusion, without heating the entire stamp substrate.
2. Heat transport simulation As a guide to experiments we have implemented a code for calculating the heat propagation in a stack of layers of different materials. We assume that heat is produced by resistive dissipation of the energy of a square wave current pulse in a layer embedded in the stack (the stamp heater). Therefore, we have simulated potential experimental conditions corresponding to various configurations of materials and thicknesses in the stack of layers and different duration and intensity of current pulses. The output data can be plotted as temperature profile across the stack at different times during and after the pulse (heating and cooling stage). We report here the results of the simulations corresponding to the actual experiments of successful imprinting process. The plots of Fig. 1 refer to the following simulated conditions. The sequence of layers in the stack consists of (1)
Fig. 1. (A) Simulated temperature profile at different times during a 50 ls pulse according to the conditions described in the text. The inset shows the close view of the temperature profile in the region of the stamp/resist interface. (B) Simulated temperature profile at different times after the 50 ls pulse. (C) Simulated temperature profile in the stack of layers, corresponding to a continuous heating power of 30 W/cm2. (D) Temperature at the stamp/resist interface. Peaks superimpose to an average temperature build-up in the stack of layer (not all peaks are represented in the plot).
M. Tormen et al. / Microelectronic Engineering 85 (2008) 1229–1232
kapton foil (compensation layer, 150 lm), (2) silicon (stamp substrate, 498 lm), (3) highly doped silicon (heater, 2 lm), (4) resist (250 nm), (5) silicon (sample substrate, 500 lm), and (6) kapton foil (compensation layer, 150 lm). The thermal capacity and thermal diffusion coefficients of the various materials have been obtained from tabulated data. The temperature dependence of the material properties has been neglected. We assume to dissipate in the heater (layer 3) 1.2 J/cm2 in a 50 ls pulse. With a sheet resistance of 4 X square corresponding to that measured in the fabricated stamps (see below) this requires a value of 77.5 A for the current injected in the heater (2 lm 1 cm, thickness width) and an electric field 310 V/cm. The simulation shows that the temperature rises from the initial value of 25 °C (RT) to 120 °C at the end of the 50 ls pulse at the stamp/resist interface. This temperature is certainly not sufficient for the hot embossing step in such a short timescale and, indeed, this was the case also in the experiments. However, we notice that after each pulse the temperature distribution broadens, because of heat diffusion, causing an average temperature build-up in the silicon substrates (stamp and sample), we have exploited this effect in a process based on the combination of bulk and surface, ls-scale second-scale heating, as intermediate development step toward the final target. Therefore, we have simulated the temperature build-up in the stack of layers with 25 Hz repetition rate pulses. At a coarsegrained timescale, we see that after a transient of 2 s the time-averaged temperature saturates to a uniform value of 145 °C, whereas steep temperature gradients arise in
1231
the kapton foils, at the boundaries of the stack. Therefore, during the pulse in the region of the stamp/resist interface the 95 °C jump in the temperature is superimposed on an average temperature of 145 °C to reach a peak temperature of 240 °C. 3. Experimental A dedicated set-up consisting of a press and a high power pulse generator has been developed for the NIL experiments based on stamp with integrated heater. The press consists essentially of two concentric bellows of steel connected to a base and to a lid with an internal piston fixed to it. The press is actuated by a combination of compressed air and vacuum in the inner chamber (the inner bellow) and outer chamber (between inner and outer bellows). This allows setting independently the value of the force that the piston can exert and the pressure and the type of atmosphere in the inner chamber (vacuum, air or inert gas). This press design also provides a self tilt correction mechanism that ensures the parallelism of the stamp and sample. The maximum force is 3.5 kN and the force resolution 0.1 kN. An electric feedthrough brings the electrical pulses to the inner chamber where the stamp is connected by CuBe clamps. To avoid sparks in the inner chamber all edges had to be rounded. The pulse generator realized for the process of pulsed NIL is essentially based on the discharge of a bank of capacitors onto the load (the stamp heater, 1–5 X) through an inductance. Modifying in discrete steps the values of the capacity and the inductance
Fig. 2. Optical micrographs of imprinted gratings obtained by imprinting with 16 s (above) and 30 s (below) process time. The measured residual layer at the center and corner of the different gratings and for the different process times are given in Table 1.
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Table 1 Averaged values of resist residual layer at different location of the imprinted pattern and for different imprinting time as shown in Fig. 2 16 s Residual layer (nm)
A 32.6 ± 15.0
B 106.6 ± 7.7
C 16.3 ± 5.3
D 35.9 ± 3.7
30 s Residual layer (nm)
E 9.8 ± 5.8
F 12.2 ± 5.4
G 23.3 ± 9.5
H 65.2 ± 6.0
(between 4–27 lF and 5–20 lH, respectively) and varying continuously the charging voltage of the capacitors (up to 1500 V) the pulse duration (10–100 ls) and shape and total energy delivered (0–20 J) can be changed. The fabrication of the stamp with heater was done according to the following process sequence. Double sided polished 100 mm {1 0 0} silicon wafers were blanket implanted with a 31P ion dose of 2 1016/cm2 at 200 keV. Following an RCA clean the wafers were oxidized in water vapour at 1100 °C for 9 min and annealed in nitrogen for 36 min at the same temperature. This treatment results in a 280 nm thick oxide. Using conventional UV lithography with 1.5 lm AZ 5214 photoresist on the front side of the wafers the imprint pattern was defined in the photoresist and subsequently transferred to the oxide by wet etching in buffered hydrofluoric acid. Following a resist strip, ebeam evaporated contact metal (Cr/Au 10 nm/200 nm) was defined by lift off. The contact metal was annealed in nitrogen at 300 °C for 20 min. Finally, the 2 4cm2 stamps were diced using a dicing saw. The stamps where surface treated for antiadhesion with a solution 1 mM of dodecyltrichlorosilane in toluene.
long range polymer flow). The measurements, taken at the corner and at the center of each type of grating for the 16 s and 30 s experiments, were averaged over 10 different equivalent locations randomly selected in the imprinted area. The results are summarized in Table 1. 5. Conclusions We have demonstrated a fast process of thermal nanoimprinting lithography that employs stamps with extended integrated heater. The results appear of high quality and the residual layer can be kept in the range of few tens of nm with total process time of the order of 10 s. We believe that the process can be further improved, mainly acting on the layout of the heatable stamp, in particular by introducing a thin thermal barrier under the layer of the heater, which would reduce heat diffusion towards the stamp substrate increasing effectively the temperature that the resist film reaches during a pulse. Acknowledgements We are thankful to Mr. Valerio Rizzi for valuable discussion on the power electronics system. The partial support of the EC-funded project NaPa (Contract No. NMP4-CT-2003-500120) is gratefully acknowledged. Center for Individual Nanoparticle Functionality (CINF) is sponsored by The Danish National Research Foundation. The content of this work is the sole responsibility of the authors.
4. Results References 2
The imprinting tests were performed on 2 1 cm silicon substrates with a 240 nm thick mr-I 7000E (Microresist) resist coating. Reproducible results (Fig. 2) were obtained with the following conditions: 1100 V peak voltage, 220 A peak current, 50 ls duration, 25 Hz repetition rate. The energy delivered in each pulse was 1.2 J/cm2 with an average power of 30 W/cm2. Two sets of experiments were performed with total duration of the pulse sequence of 16 s and 30 s, respectively. The results appear uniform over the 2 1 cm2 sample area and no defects were detected (with the exception of the few ones clearly attributed to the presence of a dust particle). We measured the residual layer thickness in 20/20 and 20/80 lm L/S gratings (large structures were chosen deliberately in order to prove the process on a pattern requiring
[1] P. Vettiger, M. Despont, U. Drechsler, U. Durig, W. Haberle, M.I. Lutwyche, H.E. Rothuizen, R. Stutz, R. Widmer, G.K. Binnig, IBM J. Res. Develop. 44 (2000) 323–340. [2] Qiangfei Xia, Zhaoning Yu, He Gao, Stephen Y. Chou, Appl. Phys. Lett. 89 (2006) 073107. [3] Stephen Y. Chou, Peter R. Krauss, Preston J. Renstrom, J. Vac. Sci. Technol. B 14 (1996) 4129. [4] Babak Heidari, Ivan Maximov, Eva-Lena Sarwe, Lars Montelius, J. Vac. Sci. Technol. B 17 (6) (1999). [5] C. Gourgon, C. Perret, G. Micouin, F. Lazzarino, J.H. Tortai, O. Joubert, J.-P.E. Grolier, J. Vac. Sci. Technol. B 21 (1071) (2003). [6] Helmut Schift, Laura J. Heyderman, Nanorheology, in: C.M. Sotomayor Torres (Ed.), Alternative Lithography: Unleashing the Potentials of Nanotechnology, Kluwer Academic Publishers, 2004, ISBN 0306478587 (Chapter 4). [7] Y. Chen, J. Tao, X. Zhao, Z. Cui, J. Microlithogr., Microfabricat. Microsyst. 5 (2006) 011002.