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Fault-tolerance considerations for redundant binary-tree-dynamic random-access-memory (RAM) chips
Literature survey Adams, M, Qian, Yi, Tomaszunas, J, Burtscheidt, J, Kaiser, E and lubasz, C 'Conformance testing of VMEbus and Multibus II products' Vo112 No1 (February 1992) p 57 Designers working with the European Community's Conformance Testing Services programme have developed a system for testing VMEbus and Multibus II products. Conformance is necessary to allow and guarantee interoperability between products from different vendors. The EC's test system is mainly automated to reduce costs and ensure impartiality. An overview of the system's components familiarizes readers with its procedures.
Anderson, A l 'A parallel implementation of a smoothed adaptive deconvolution filter' J. MicrocompuL Appl. Vo115 (1992) pp 157-168 This paper considers a multiple processor adaptive approach to deconvolution estimation obtained by applying the extended least squares (ELS) technique. The approach adopted within the system only requires one input (the corrupted signal). This contrasts with the more common use of a FIR filter coupled with the least mean square estimation algorithm. The adaptive deconvolution smoothing filter has been implemented on a threetransputer system. The network uses a transputer to act as a digital deconvolution smoothing filter while a second transputer handles the extended l e a s t squares (ELS) parameter estimation algorithm. A third transputer calculates the gain factor for the deconvolution smoother. The three transputers operate in parallel. The example considered in this paper is of a speech signal which has passed through a distorting communication channel resulting in a narrow band signal. The distorting channel is assumed to be represented as an allpole model. This signal is then corrupted by additive wide band noise. The transputer network is used to estimate the original speech signal.
Vol 77 No 1 1993
Bansal, R K, Joshi, B K, Singh, S P and Bandopadhaya, R N 'Microprocessor based harmonic restraint differential protection scheme for a transformer' J. MicrocompuL AppL Vol 15 (1992) pp 169-176 This paper presents a microprocessor based differential protection scheme for a single phase transformer with harmonic restraint feature to avoid real-operation during inrush current conditions. The relay has been tested satisfactorily by an arranged circuit for differential protection of a test transformer in the laboratory for the above condition. The test results indicate that the relay detects the inrush or other abnormal conditions satisfactorily within an overall time of about 26/Js.
Boser, B E, Sackinger, E, Bromley, J, leCun, Y and Jackel, L D 'Hardware requirements for neural network pattern classifiers: a case study and implementation' Vo112 No 1 (February 1992) p 32 A special-purpose chip, optimized for computational needs of neural networks, performs over 2000 multiplications and additions simultaneously. Its data path is suitable particularly for the convolutional architectures typical in pattern classification networks but can also be configured for fully connected or feedback topologies. A development system permits rapid prototyping of new applications and analysis of the impact of the specialized hardware on system performance. We demonstrate the power and flexibility of the processor with a neural network for handwritten character recognition containing over 133 000 connections.
Bursky, D 'A bridge between gate array and FPGA' Elettron. Oggi No 140 (15 May 1992) pp 55-6, 58-61 The author describes a family of devices developed by Crosspoint Solutions with the characteristics of high density, flexibility and performance. They form a bridge
between the gate array and FPGAand consist of non-fusible elements and cells similar to a transistor. The antifusible approach is described, with the help of a diagram, as are also two types of logic cell and the clock distribution system. The devices make available a vast range of design tools, the more important of which are shown schematically. Problems connected with testing the antifusibles are discussed and a table gives the performance characteristics of the first six components available.
Ciciani, B 'Fault-tolerance considerations for redundant binary-tree-dynamic random-access-memory (RAM) chips' IEEE Trans. Reliab. Vol41 No 1 (March 1992) pp 139-148 The binary-tree-dynamic RAM (TRAM) architecture has been proposed to overcome the performance and testing time limits of the traditional architecture of memory chips. A 64-Mb prototype of this architecture is being built. The author investigates manufacturing yield and operational performance of redundant TRAMs with respect to variation of tree depth and redundancy level. For this purpose, a based chip area, a yield and operational performance figure of merit allowing the comparison of various choices, has been formulated and used. The yield is evaluated by a new Markov-chain-model. The memory operational performance has been analysed by an innovative technique that substitutes the notion of chip state atthe end of the mission time with the cumulative work performed by the chip during the mission time (performability). Optimum values of three tree depth and redundancy level were found for a given RAM size, the adopted reconfiguration strategy, and the kinds of redundancy.
Dal Lago, E 'Technological aspects of static memory cells' Elettron. Oggi No 139 (30 April 1992) pp 75-78 Discusses the technology of static memory cells used in FPGAs, with 47
Anderson, A l 'A parallel implementation of a smoothed adaptive deconvolution filter' J. MicrocompuL Appl. Vo115 (1992) pp 157-168 This paper considers a multiple processor adaptive approach to deconvolution estimation obtained by applying the extended least squares (ELS) technique. The approach adopted within the system only requires one input (the corrupted signal). This contrasts with the more common use of a FIR filter coupled with the least mean square estimation algorithm. The adaptive deconvolution smoothing filter has been implemented on a threetransputer system. The network uses a transputer to act as a digital deconvolution smoothing filter while a second transputer handles the extended l e a s t squares (ELS) parameter estimation algorithm. A third transputer calculates the gain factor for the deconvolution smoother. The three transputers operate in parallel. The example considered in this paper is of a speech signal which has passed through a distorting communication channel resulting in a narrow band signal. The distorting channel is assumed to be represented as an allpole model. This signal is then corrupted by additive wide band noise. The transputer network is used to estimate the original speech signal.
Vol 77 No 1 1993
Bansal, R K, Joshi, B K, Singh, S P and Bandopadhaya, R N 'Microprocessor based harmonic restraint differential protection scheme for a transformer' J. MicrocompuL AppL Vol 15 (1992) pp 169-176 This paper presents a microprocessor based differential protection scheme for a single phase transformer with harmonic restraint feature to avoid real-operation during inrush current conditions. The relay has been tested satisfactorily by an arranged circuit for differential protection of a test transformer in the laboratory for the above condition. The test results indicate that the relay detects the inrush or other abnormal conditions satisfactorily within an overall time of about 26/Js.
Boser, B E, Sackinger, E, Bromley, J, leCun, Y and Jackel, L D 'Hardware requirements for neural network pattern classifiers: a case study and implementation' Vo112 No 1 (February 1992) p 32 A special-purpose chip, optimized for computational needs of neural networks, performs over 2000 multiplications and additions simultaneously. Its data path is suitable particularly for the convolutional architectures typical in pattern classification networks but can also be configured for fully connected or feedback topologies. A development system permits rapid prototyping of new applications and analysis of the impact of the specialized hardware on system performance. We demonstrate the power and flexibility of the processor with a neural network for handwritten character recognition containing over 133 000 connections.
Bursky, D 'A bridge between gate array and FPGA' Elettron. Oggi No 140 (15 May 1992) pp 55-6, 58-61 The author describes a family of devices developed by Crosspoint Solutions with the characteristics of high density, flexibility and performance. They form a bridge
between the gate array and FPGAand consist of non-fusible elements and cells similar to a transistor. The antifusible approach is described, with the help of a diagram, as are also two types of logic cell and the clock distribution system. The devices make available a vast range of design tools, the more important of which are shown schematically. Problems connected with testing the antifusibles are discussed and a table gives the performance characteristics of the first six components available.
Ciciani, B 'Fault-tolerance considerations for redundant binary-tree-dynamic random-access-memory (RAM) chips' IEEE Trans. Reliab. Vol41 No 1 (March 1992) pp 139-148 The binary-tree-dynamic RAM (TRAM) architecture has been proposed to overcome the performance and testing time limits of the traditional architecture of memory chips. A 64-Mb prototype of this architecture is being built. The author investigates manufacturing yield and operational performance of redundant TRAMs with respect to variation of tree depth and redundancy level. For this purpose, a based chip area, a yield and operational performance figure of merit allowing the comparison of various choices, has been formulated and used. The yield is evaluated by a new Markov-chain-model. The memory operational performance has been analysed by an innovative technique that substitutes the notion of chip state atthe end of the mission time with the cumulative work performed by the chip during the mission time (performability). Optimum values of three tree depth and redundancy level were found for a given RAM size, the adopted reconfiguration strategy, and the kinds of redundancy.
Dal Lago, E 'Technological aspects of static memory cells' Elettron. Oggi No 139 (30 April 1992) pp 75-78 Discusses the technology of static memory cells used in FPGAs, with 47