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Ferroelectric thin films on silicon carbide for next-generation nonvolatile memory and sensor devices
Thin Solid Films 469–470 (2004) 444 – 449 www.elsevier.com/locate/tsf
Ferroelectric thin films on silicon carbide for next-generation nonvolatile memory and sensor devices ¨ stlinga, Sang-Mo Koob,*, Carl-Mikael Zetterlinga, Sergey Khartseva, Alex Grishina Mikael O a
Department of Microelectronics and Information Technology, Royal Institute of Technology, SE-164 40, Stockholm-Kista, Sweden b National Institute of Standards and Technology, Semiconductor Electronics Division, Gaithersburg, MD 20899, USA Available online 30 October 2004
Abstract Silicon carbide semiconductor technology has emerged as a very good candidate to replace traditional Si devices in special applications such as low loss power switching and high temperature electronics. Ferroelectric thin films exhibit interesting properties for use in semiconductor technology due to the spontaneous polarization which can be switched by an externally applied electric field, and thus are attractive for nonvolatile memory and sensor applications. In this work, the successful realization of ferroelectric thin films in SiC devices is described. The first experimental prototype devices are presented and discussed: A novel integration technique of junction metal-oxide-semiconductor field effect transistors (JMOSFETs) and nonvolatile FETs (NVFETs) on a single 4H-SiC substrate is presented. A constant current control device is based on the SiC JMOSFET. The drain current is effectively controlled and kept constant by a buried junction gate. A new high temperature SiC NVFET with a similar temperature stable current drive is also demonstrated. The nonvolatile memory device, based on the ferroelectric gate stack, was shown to operate up to 300 8C with memory effect retained up to 200 8C. D 2004 Published by Elsevier B.V. Keywords: Ferroelectric thin films; Silicon carbide; Nonvolatile memory and sensor devices
1. Introduction 1.1. Ferroelectric thin films for semiconductor devices Ferroelectric oxides such as Pb(Zr,Ti)O3, SrBi2Ta2O9, YMnO3 and (Bi,La)4Ti3O12 have been proposed for metal– ferroelectric–semiconductor (MFS) structures in siliconbased microelectronic devices due to their high dielectric constant and nonvolatile remnant polarization [1,2]. Many ferroelectrics are chemically expressed as ABO3, with an octahedron constructed by six oxygen atoms including a smaller metallic element near their center and most ABO3type ferroelectric crystals are the perovskite type. The displacement of plus ions (A and B), minus ions and their valence electrons separates the center of gravity of the * Corresponding author. Tel.: +1 301 975 8755. E-mail address: [email protected] (S.-M. Koo). 0040-6090/$ - see front matter D 2004 Published by Elsevier B.V. doi:10.1016/j.tsf.2004.09.030
positive and negative electric charges, which allows an electrical polarization moment to occur (see Fig. 1(a)). The charge amount of electrical polarization moment per unit area is electrical polarization (AC/cm2). PZT, being a solid solution of PbZrO3 and PbTiO3, is one of the most widely investigated ferroelectrics due to its high remnant polarization and stability [3]. Fig. 1(a) shows two stable states in a perovskite Pb(Zr,Ti)O3. However, the interdiffusion between the ferroelectric layer and the semiconductor at typical processing temperatures for ferroelectric oxides (500–800 8C) is a serious problem to realize MFS devices in Si or GaAs. Thus various insulators including SiO2, CeO2, Y2O3 and Al2O3 have been investigated as buffer layers in metal– ferroelectric–insulator–semiconductor structures to solve the problem. Another attempt is to insert a floating metal layer between the ferroelectric material and the semiconductor, resulting in metal–ferroelectric–metal–insulator–semiconductor structure which avoids ferroelectric–(insulator)–semi-
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Fig. 1. Schematics showing (a) unit cells and two stable states of ferroelectric PZT and (b) possible integration on the gate of field effect transistor.
conductor interface [4,5]. Both structure forms ferroelectric gate-controlled field effect transistors (FETs) (see Fig. 1(b)). 1.2. SiC device technology SiC devices can operate in harsh environments due to the wide energy bandgap and high breakdown electric field of SiC, together with its chemical stability [6]. In general, the operation of Si devices is not reliable at ~150 8C, whereas SiC devices have proved its operation at high temperature well above 300 8C and in high radiation condition. The expected performance of SiC can be compared theoretically to Si and other semiconductors using appropriate figures of merits (FM). The Baliga’s FM (BFM) [7] and highfrequency FM (BHFM) [8] are given by elE c3 and lE c2, respectively (l is the carrier mobility and e is the dielectric permittivity). Johnson’s FM (JFM) [9] sets the intrinsic transistor performance by considering the product of the critical field E c and the electron saturation velocity v sat: JFM=(E cv sat/p)2. Keyes’ FM (KFM) [10] considers the switching speed of a transistor: KFM=k(v sat/e)1/2. The thermal properties of the semiconductor, specifically the thermal conductivity k, are considered also in different quality factors (QF) given as: QF1=kelE c3 , QF2=kelE c4 and QF3=elE c3, where QF3 is the same as BFM [11]. As shown in Fig. 2, because of the high breakdown field and low intrinsic carrier concentration in SiC, high voltage and high temperature operation is made possible [12]. SiC is also suitable for high frequency device applications, because of the high saturation drift velocity and low permittivity.
While the material quality of SiC is still improving, there are still serious defect problems to overcome before large area devices can be economically viable. However, the development of fabrication processes for SiC is at a relatively advanced stage and superior to most other wide bandgap semiconductors. Presently, 6H- and 4H-SiC wafers of n- and p-type with diameters of 50–75 mm are readily available in low resistivity and semi-insulating forms while 100-mmdiameter wafers are only yet shown at a research level. Most of the key SiC process technologies including doping, dry etching, oxide growth, Schottky and ohmic
Fig. 2. Figures of merits for SiC and other semiconductors. All values are normalized to Si.
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In order to improve the high temperature stability with controlled current level, a novel SiC junction MOSFET (JMOSFET) is fabricated by adding a depletion MOS gate on top of a buried-gate JFET. SiC NVFET has similar functions to JMOSFET with additional nonvolatile memory capability due to ferroelectric gate stack. In this work, these dsmartT electronic devices have been integrated on a single 4H-SiC substrate in the same fabrication process and the devices have been tested from room temperature up to 300 8C.
2. Fabrication of ferroelectric-gated SiC transistor
Fig. 3. Fabrication process flow for the JMOSFET and the NVFET on the same 4H-SiC substrate. (a) The FET structure is formed by dry etching, oxidation and metallization. (b) A differential etching is done on the gate areas using a proper mask. The JMOSFET is covered by a shadow mask during deposition of the ferroelectric gate stack for the NVFET part. (c) Au metallization of the top gate. (d) Contact window formation for source and drain. (e) TiW metallization on the backside buried gate.
contacts are relatively mature and compatible to those in Si processing. SiC is one of the few compound semiconductors that can be thermally oxidized to form SiO2, which is crucial in both fabricating devices with metal-oxide-semiconductor (MOS) structures and passivation of surfaces. Although the detailed properties of the oxide and its interface are far different from those in Si, thermal oxides can be formed with the same oxidation equipment and techniques as for Si. SiC is normally oxidized at higher temperatures (N~1150 8C) and at slower rate, due to the stronger Si–C bonds compared to Si–Si bonds. Although the interface properties of SiO2/SiC can be improved by H2 treatment prior to the oxidation or by post-oxidation annealing in NO or N2O [13], the low MOS channel mobility is a serious problem. The highest values reported for the n-channel inversion mobility in 6HSiC is 70–100 cm2/V s whereas values of 1–20 cm2/V s are commonly found for the inversion channel mobility in 4H-SiC [14]. Investigations on alternative dielectrics on SiC such as Si3N4 or AlN have been reported but only limited information is presently available [15]. The main problem with AlN is to achieve impurity free, nonconducting films.
The schematic cross-section of the fabricated transistors is shown in Fig. 3. The JMOSFET and the NVFET have a similar epitaxial structure as conventional SiC buried-gate JFET [16] but with an additional gate to deplete the channel from the top [17]. This allows for an easy current control using a feedback loop, which sets the buried backside gate voltage such that a constant drain current is obtained for all devices (see Fig. 4). The channel region and isolation mesa structures were fabricated by dry etching of SiC in an inductively coupled plasma reactor. The transistor structures were fabricated on a 4H-SiC p-type substrate using an n-type epitaxial channel with a nominal gate width and length of 100 and 10 Am, respectively. The nitrogen donor concentration in the epitaxial n-type channel layer was ~21016 cm 3 and the p-substrate was aluminium doped to ~21018 cm 3. The channel region and mesa isolation were defined by photolithography followed by dry etching of SiC. About 200 nm thick SiO2 was grown to passivate the surface. The source and drain contacts were made by an electron beam evaporation of Ni (1500 2) followed by a lift off process. The contacts were then subjected to a rapid thermal anneal step at 950 8C in Ar for 1 min to yield good ohmic characteristics. About 40 nm thick SiO2 was thermally grown to form the top-gate dielectrics for the JMOSFET whereas the gate stack was formed by pulsed laser deposition of ferroelectric Pb(Zr,Ti)O3 for NVFET. A buffer layer was required to achieve single-phase growth of PZT on SiC and to maintain good thermal integrity of the ferroelectric gate. A 5 nm Al2O3 buffer layer was used. According to our recent investigation
Fig. 4. A simple circuit that uses one reference FET to maintain constant characteristics for JMOSFETs and NVFETs on the entire chip. The drain current in one FET can be monitored and adjusts the backside gate voltage for all devices on the chip, thereby maintaining a constant bias point for the circuit regardless of the ambient temperature.
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substrate backside junction can be used as an extra p–n junction gate, enabling additional channel modulation (see Figs. 3 and 4). The nominal gate width and channel length were 100 and 10 Am, respectively. The static I–V characteristics of JFETs were measured in a Cascade probe station using a HP 4156A semiconductor parameter analyzer from room temperature up to 300 8C.
3. Results and discussions
Fig. 5. The buried-gate characteristics (I D–V BG) of a JMOSFET from RT up to 300 8C.
[18], it also serves as a high bandgap buffer (E g~9 eV) between PZT (E g~3.5 eV) and SiC (E g~3.2 eV). About 450 nm Pb(Zr0.52Ti0.48)O3 (PZT) layer were then grown on SiC by pulsed laser deposition (PLD) using a KrF excimer laser, whereas the JMOSFETs were covered by a shadow mask during the PLD step. A 1200 2 thick Au film was evaporated and patterned to form the gate metals, and e-beam-evaporated Ni (1500 2) has been used as the source and drain contacts. The backside contact was formed by sputtered TiW. The fabricated transistors are normally on, depletion-type devices since the modulation of the channel current is controlled by depleting or accumulating the channel from the top MOS or the ferroelectric gates. In this configuration, the channel–
SiC buried-gate JFETs have stable and good high temperature properties, and have also a relatively simple fabrication process. However, they suffer from a large capacitive parasitic from the single large backside gate, which results in slow switching speed and makes separate control of each device difficult. The measured I DS–V DS characteristics of a JMOSFET for a temperature interval between 25 and 300 8C are shown in Fig. 5. Over this temperature range, the device maintains good saturation characteristics. The decrease of the drain current is attributed to the reduction in the carrier mobility at higher temperature. The bandgap of 4H-SiC (~3.2 eV) is around three times that of Si (~1.1 eV), which leads to about 17 orders of magnitude lower intrinsic carrier concentration than in silicon. Hence SiC does not suffer from the intrinsic carrier conductivity difficulties at high temperatures. As the temperature increases, the drain current and the maximum transconductance decrease to around 20% of the room temperature value at 300 8C as shown in the inset of Fig. 5. This behavior is similar to normal 4H-SiC JFETs, which agrees well with the inverse power law dependence [19]. The
Fig. 6. I D–V D characteristics of a JMOSFET. A constant current can be achieved for temperatures from RT up to 300 8C by applying a properly chosen bottomgate voltage V BG. The inset shows the V BG for different temperatures.
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Fig. 7. The top-gate characteristics showing the variation of saturated drain currents. The inset shows calculated g m.
Fig. 9. The top-gate transfer characteristics (I D–V TG) of a SiC NVFET at RT. The sweep direction is clockwise for all curves.
variation of operating point makes it difficult to use the SiC devices at high temperatures, especially in analog applications. In JMOSFETs, however, by applying a properly chosen voltage on the backside buried-gate V BG, the channel of all devices on the same wafer can be simultaneously controlled, which allows a virtually constant current level operation for different temperatures (see Fig. 6). The correspondingly chosen values of V BG, to set the operation point for different temperatures, are shown in the inset of Fig. 6. The JMOSFET has shown the feasibility for operating with constant on- and off-current levels from room temperature up to 300 8C and thus advantages of this device include the relatively high bulk channel mobility, compared to the enhancement mode MOSFET, which normally shows low inversion channel mobilities. In addition, even higher current density than that
of the JFET alone can be achieved by accumulating the channel in the JMOSFET (see Fig. 7), which unravel the reduced current problems of JFETs at high temperatures.
Fig. 8. The top-gate transfer characteristics (I D–V TG) of a SiC NVFET for the temperature range from 25 to 300 8C.
Fig. 10. (a) Retention properties of a SiC NVFET. (b) I D–V D characteristics with top-gate V TG sweep after different V TG of +12 and 12 V was applied.
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The simultaneously processed NVFET shows nonvolatile memory properties, which can be operated up to 300 8C with memory function retained up to 200 8C. Fig. 8 shows typical top-gate transfer (I D–V TG) characteristics of a SiC NVFET for different temperatures. Dual directional sweeps of V TG were performed at room temperature between d 12T and d+12T V, the drain voltage V D is kept constant at 10 V. It can be clearly seen that I D–V TG characteristics exhibit memory effect: depending on the sweep direction, two different values of drain current I D can be read in the channel at the same gate voltage. The memory window of the transistor is 5.0 V at V D=10 V, which agrees with the value reported earlier from C–V measurements on the diode structure of PZT/Al2O3/SiC [18,20]. The reduction of the memory window for elevated temperature can be ascribed to decreased amount of charge trapping and increased recombination at high temperatures as well as to reduced polarization in PZT. In the ideal case of ferroelectric field effect transistor, interface states and bound charges are absent and the concentration of the carriers on the ferroelectric/semiconductor interface is controlled mainly by superposition of gate electric field and stray electric field of ferroelectric domains. As a result, the direction of I D–V G hysteresis loop is anticlockwise [21]. Trapping of carriers on the non-ideal gate dielectric/semiconductor interface is a competing mechanism. It prevails in our case and results in an opposite direction of the hysteresis loop. The charges can be injected from the semiconductor into the ferroelectric or interface traps and attracted by the remnant polarization consequently become bounded to the ferroelectric domains when the applied field is removed. Further depletion of the channel can be achieved by biasing either the ferroelectric gate on top V G or the backside junction gate V BG (see Fig. 9). Thus all the JMOSFETs and NVFETs can essentially be controlled from the buried gate at the same time. Fig. 10a shows drain current I D at V D=10 V as a function of the retention time for two temperatures: 25 and 150 8C. A voltage pulse of 12 or +12 V was initially applied to the gate during 100 ms, after which the gate voltage was kept at 0 V for the retention measurements. The high drain current state was found to be stable without significant change during 2104 s. Fig. 10b shows the drain current I D versus the drain voltage V D characteristics.
demonstrated in novel structures such as the JMOSFETs and NVFETs. These devices were also successfully integrated together on the same 4H-SiC substrate and fully functional operation was demonstrated from room temperature up to 300 8C.
Acknowledgments This research was partially supported by the Swedish Foundation for Strategic Research, SSF.
References [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
[14] [15] [16] [17]
[18] [19] [20] [21]
4. Summary SiC devices with high temperature stable operation for potential use in analog and digital circuits have been
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S.Y. Wu, IEEE Trans. Electron Devices ED-21 (1974) 499. J.F. Scott, C.A.P. Araujo, Science 246 (1989) 1400. S.-M. Koo, L.R. Zheng, K.V. Rao, J. Mater. Res. 14 (1999) 3833. E. Tokumitsu, G. Fujii, H. Ishiwara, Appl. Phys. Lett. 75 (1999) 575. T. Li, S.T. Hsu, B.D. Ulrich, L. Stecker, D.R. Evans, J.J. Lee, IEEE Electron Device Lett. 23 (2002) 339. C.-M. Zetterling, Process Technologies for Silicon Carbide Devices, EMIS Process Series, INSPEC, IEE, London, UK, 2002. B.J. Baliga, J. Appl. Phys. 53 (1982) 1759. B.J. Baliga, IEEE Electron Device Lett. 455 (1989) 10. E.O. Johnson, RCA Rev. 26 (1963) 163. R.W. Keyes, Proc. IEEE 60 (1972) 225. K. Shenai, R.S. Scott, B.J. Baliga, IEEE Trans. Electron Devices 36 (1989) 1811. J.A. Cooper, M.R. Melloch, R. Singh, A. Agarwal, J.W. Palmour, IEEE Trans. Electron Devices 49 (2002) 658. G.Y. Chung, C.C. Tin, J.R. Williams, K. McDonald, R.K. Chanana, R.A. Weller, S.T. Pantelides, L.C. Feldman, O.W. Holland, M.K. Das, J.W. Palmour, IEEE Electron Device Lett. 22 (2001) 176. H. Yano, T. Hirao, T. Kimoto, H. Matsunami, K. Asano, Y. Sugawara, IEEE Electron Device Lett. 20 (1999) 611. ¨ stling, H. Yano, T. Kimoto, H. Matsunami, C.M. Zetterling, M. O K. Linthicum, R.F. Davis, Mat. Sci. Forum 338 (2000) 1315. J.C. Zolper, Solid-State Electron. 42 (1998) 2153. ¨ stling, S.I. Khartsev, A.M. Grishin, S.-M. Koo, C.-M. Zetterling, M. O IEEE International Electron Devices Meeting 2003, Washington, DC, Dec. 8–10, 2003, IEDM 03 Tech. Digest, 2003, p. 575. ¨ stling, S.-M. Koo, S.I. Khartsev, C.-M. Zetterling, A.M. Grishin, M. O Appl. Phys. Lett. 81 (2002) 895. C.J. Scozzie, F.B. McLean, J.M. McGarrity, J. Appl. Phys. 81 (1997) 7687. ¨ stling, S.-M. Koo, S.I. Khartsev, C.-M. Zetterling, A.M. Grishin, M. O Appl. Phys. Lett. 83 (2003) 3975. C.H. Seager, D.C. McIntyre, W.L. Warren, B.A. Tuttle, Appl. Phys. Lett. 68 (1996) 2660.
Ferroelectric thin films on silicon carbide for next-generation nonvolatile memory and sensor devices ¨ stlinga, Sang-Mo Koob,*, Carl-Mikael Zetterlinga, Sergey Khartseva, Alex Grishina Mikael O a
Department of Microelectronics and Information Technology, Royal Institute of Technology, SE-164 40, Stockholm-Kista, Sweden b National Institute of Standards and Technology, Semiconductor Electronics Division, Gaithersburg, MD 20899, USA Available online 30 October 2004
Abstract Silicon carbide semiconductor technology has emerged as a very good candidate to replace traditional Si devices in special applications such as low loss power switching and high temperature electronics. Ferroelectric thin films exhibit interesting properties for use in semiconductor technology due to the spontaneous polarization which can be switched by an externally applied electric field, and thus are attractive for nonvolatile memory and sensor applications. In this work, the successful realization of ferroelectric thin films in SiC devices is described. The first experimental prototype devices are presented and discussed: A novel integration technique of junction metal-oxide-semiconductor field effect transistors (JMOSFETs) and nonvolatile FETs (NVFETs) on a single 4H-SiC substrate is presented. A constant current control device is based on the SiC JMOSFET. The drain current is effectively controlled and kept constant by a buried junction gate. A new high temperature SiC NVFET with a similar temperature stable current drive is also demonstrated. The nonvolatile memory device, based on the ferroelectric gate stack, was shown to operate up to 300 8C with memory effect retained up to 200 8C. D 2004 Published by Elsevier B.V. Keywords: Ferroelectric thin films; Silicon carbide; Nonvolatile memory and sensor devices
1. Introduction 1.1. Ferroelectric thin films for semiconductor devices Ferroelectric oxides such as Pb(Zr,Ti)O3, SrBi2Ta2O9, YMnO3 and (Bi,La)4Ti3O12 have been proposed for metal– ferroelectric–semiconductor (MFS) structures in siliconbased microelectronic devices due to their high dielectric constant and nonvolatile remnant polarization [1,2]. Many ferroelectrics are chemically expressed as ABO3, with an octahedron constructed by six oxygen atoms including a smaller metallic element near their center and most ABO3type ferroelectric crystals are the perovskite type. The displacement of plus ions (A and B), minus ions and their valence electrons separates the center of gravity of the * Corresponding author. Tel.: +1 301 975 8755. E-mail address: [email protected] (S.-M. Koo). 0040-6090/$ - see front matter D 2004 Published by Elsevier B.V. doi:10.1016/j.tsf.2004.09.030
positive and negative electric charges, which allows an electrical polarization moment to occur (see Fig. 1(a)). The charge amount of electrical polarization moment per unit area is electrical polarization (AC/cm2). PZT, being a solid solution of PbZrO3 and PbTiO3, is one of the most widely investigated ferroelectrics due to its high remnant polarization and stability [3]. Fig. 1(a) shows two stable states in a perovskite Pb(Zr,Ti)O3. However, the interdiffusion between the ferroelectric layer and the semiconductor at typical processing temperatures for ferroelectric oxides (500–800 8C) is a serious problem to realize MFS devices in Si or GaAs. Thus various insulators including SiO2, CeO2, Y2O3 and Al2O3 have been investigated as buffer layers in metal– ferroelectric–insulator–semiconductor structures to solve the problem. Another attempt is to insert a floating metal layer between the ferroelectric material and the semiconductor, resulting in metal–ferroelectric–metal–insulator–semiconductor structure which avoids ferroelectric–(insulator)–semi-
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Fig. 1. Schematics showing (a) unit cells and two stable states of ferroelectric PZT and (b) possible integration on the gate of field effect transistor.
conductor interface [4,5]. Both structure forms ferroelectric gate-controlled field effect transistors (FETs) (see Fig. 1(b)). 1.2. SiC device technology SiC devices can operate in harsh environments due to the wide energy bandgap and high breakdown electric field of SiC, together with its chemical stability [6]. In general, the operation of Si devices is not reliable at ~150 8C, whereas SiC devices have proved its operation at high temperature well above 300 8C and in high radiation condition. The expected performance of SiC can be compared theoretically to Si and other semiconductors using appropriate figures of merits (FM). The Baliga’s FM (BFM) [7] and highfrequency FM (BHFM) [8] are given by elE c3 and lE c2, respectively (l is the carrier mobility and e is the dielectric permittivity). Johnson’s FM (JFM) [9] sets the intrinsic transistor performance by considering the product of the critical field E c and the electron saturation velocity v sat: JFM=(E cv sat/p)2. Keyes’ FM (KFM) [10] considers the switching speed of a transistor: KFM=k(v sat/e)1/2. The thermal properties of the semiconductor, specifically the thermal conductivity k, are considered also in different quality factors (QF) given as: QF1=kelE c3 , QF2=kelE c4 and QF3=elE c3, where QF3 is the same as BFM [11]. As shown in Fig. 2, because of the high breakdown field and low intrinsic carrier concentration in SiC, high voltage and high temperature operation is made possible [12]. SiC is also suitable for high frequency device applications, because of the high saturation drift velocity and low permittivity.
While the material quality of SiC is still improving, there are still serious defect problems to overcome before large area devices can be economically viable. However, the development of fabrication processes for SiC is at a relatively advanced stage and superior to most other wide bandgap semiconductors. Presently, 6H- and 4H-SiC wafers of n- and p-type with diameters of 50–75 mm are readily available in low resistivity and semi-insulating forms while 100-mmdiameter wafers are only yet shown at a research level. Most of the key SiC process technologies including doping, dry etching, oxide growth, Schottky and ohmic
Fig. 2. Figures of merits for SiC and other semiconductors. All values are normalized to Si.
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In order to improve the high temperature stability with controlled current level, a novel SiC junction MOSFET (JMOSFET) is fabricated by adding a depletion MOS gate on top of a buried-gate JFET. SiC NVFET has similar functions to JMOSFET with additional nonvolatile memory capability due to ferroelectric gate stack. In this work, these dsmartT electronic devices have been integrated on a single 4H-SiC substrate in the same fabrication process and the devices have been tested from room temperature up to 300 8C.
2. Fabrication of ferroelectric-gated SiC transistor
Fig. 3. Fabrication process flow for the JMOSFET and the NVFET on the same 4H-SiC substrate. (a) The FET structure is formed by dry etching, oxidation and metallization. (b) A differential etching is done on the gate areas using a proper mask. The JMOSFET is covered by a shadow mask during deposition of the ferroelectric gate stack for the NVFET part. (c) Au metallization of the top gate. (d) Contact window formation for source and drain. (e) TiW metallization on the backside buried gate.
contacts are relatively mature and compatible to those in Si processing. SiC is one of the few compound semiconductors that can be thermally oxidized to form SiO2, which is crucial in both fabricating devices with metal-oxide-semiconductor (MOS) structures and passivation of surfaces. Although the detailed properties of the oxide and its interface are far different from those in Si, thermal oxides can be formed with the same oxidation equipment and techniques as for Si. SiC is normally oxidized at higher temperatures (N~1150 8C) and at slower rate, due to the stronger Si–C bonds compared to Si–Si bonds. Although the interface properties of SiO2/SiC can be improved by H2 treatment prior to the oxidation or by post-oxidation annealing in NO or N2O [13], the low MOS channel mobility is a serious problem. The highest values reported for the n-channel inversion mobility in 6HSiC is 70–100 cm2/V s whereas values of 1–20 cm2/V s are commonly found for the inversion channel mobility in 4H-SiC [14]. Investigations on alternative dielectrics on SiC such as Si3N4 or AlN have been reported but only limited information is presently available [15]. The main problem with AlN is to achieve impurity free, nonconducting films.
The schematic cross-section of the fabricated transistors is shown in Fig. 3. The JMOSFET and the NVFET have a similar epitaxial structure as conventional SiC buried-gate JFET [16] but with an additional gate to deplete the channel from the top [17]. This allows for an easy current control using a feedback loop, which sets the buried backside gate voltage such that a constant drain current is obtained for all devices (see Fig. 4). The channel region and isolation mesa structures were fabricated by dry etching of SiC in an inductively coupled plasma reactor. The transistor structures were fabricated on a 4H-SiC p-type substrate using an n-type epitaxial channel with a nominal gate width and length of 100 and 10 Am, respectively. The nitrogen donor concentration in the epitaxial n-type channel layer was ~21016 cm 3 and the p-substrate was aluminium doped to ~21018 cm 3. The channel region and mesa isolation were defined by photolithography followed by dry etching of SiC. About 200 nm thick SiO2 was grown to passivate the surface. The source and drain contacts were made by an electron beam evaporation of Ni (1500 2) followed by a lift off process. The contacts were then subjected to a rapid thermal anneal step at 950 8C in Ar for 1 min to yield good ohmic characteristics. About 40 nm thick SiO2 was thermally grown to form the top-gate dielectrics for the JMOSFET whereas the gate stack was formed by pulsed laser deposition of ferroelectric Pb(Zr,Ti)O3 for NVFET. A buffer layer was required to achieve single-phase growth of PZT on SiC and to maintain good thermal integrity of the ferroelectric gate. A 5 nm Al2O3 buffer layer was used. According to our recent investigation
Fig. 4. A simple circuit that uses one reference FET to maintain constant characteristics for JMOSFETs and NVFETs on the entire chip. The drain current in one FET can be monitored and adjusts the backside gate voltage for all devices on the chip, thereby maintaining a constant bias point for the circuit regardless of the ambient temperature.
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substrate backside junction can be used as an extra p–n junction gate, enabling additional channel modulation (see Figs. 3 and 4). The nominal gate width and channel length were 100 and 10 Am, respectively. The static I–V characteristics of JFETs were measured in a Cascade probe station using a HP 4156A semiconductor parameter analyzer from room temperature up to 300 8C.
3. Results and discussions
Fig. 5. The buried-gate characteristics (I D–V BG) of a JMOSFET from RT up to 300 8C.
[18], it also serves as a high bandgap buffer (E g~9 eV) between PZT (E g~3.5 eV) and SiC (E g~3.2 eV). About 450 nm Pb(Zr0.52Ti0.48)O3 (PZT) layer were then grown on SiC by pulsed laser deposition (PLD) using a KrF excimer laser, whereas the JMOSFETs were covered by a shadow mask during the PLD step. A 1200 2 thick Au film was evaporated and patterned to form the gate metals, and e-beam-evaporated Ni (1500 2) has been used as the source and drain contacts. The backside contact was formed by sputtered TiW. The fabricated transistors are normally on, depletion-type devices since the modulation of the channel current is controlled by depleting or accumulating the channel from the top MOS or the ferroelectric gates. In this configuration, the channel–
SiC buried-gate JFETs have stable and good high temperature properties, and have also a relatively simple fabrication process. However, they suffer from a large capacitive parasitic from the single large backside gate, which results in slow switching speed and makes separate control of each device difficult. The measured I DS–V DS characteristics of a JMOSFET for a temperature interval between 25 and 300 8C are shown in Fig. 5. Over this temperature range, the device maintains good saturation characteristics. The decrease of the drain current is attributed to the reduction in the carrier mobility at higher temperature. The bandgap of 4H-SiC (~3.2 eV) is around three times that of Si (~1.1 eV), which leads to about 17 orders of magnitude lower intrinsic carrier concentration than in silicon. Hence SiC does not suffer from the intrinsic carrier conductivity difficulties at high temperatures. As the temperature increases, the drain current and the maximum transconductance decrease to around 20% of the room temperature value at 300 8C as shown in the inset of Fig. 5. This behavior is similar to normal 4H-SiC JFETs, which agrees well with the inverse power law dependence [19]. The
Fig. 6. I D–V D characteristics of a JMOSFET. A constant current can be achieved for temperatures from RT up to 300 8C by applying a properly chosen bottomgate voltage V BG. The inset shows the V BG for different temperatures.
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Fig. 7. The top-gate characteristics showing the variation of saturated drain currents. The inset shows calculated g m.
Fig. 9. The top-gate transfer characteristics (I D–V TG) of a SiC NVFET at RT. The sweep direction is clockwise for all curves.
variation of operating point makes it difficult to use the SiC devices at high temperatures, especially in analog applications. In JMOSFETs, however, by applying a properly chosen voltage on the backside buried-gate V BG, the channel of all devices on the same wafer can be simultaneously controlled, which allows a virtually constant current level operation for different temperatures (see Fig. 6). The correspondingly chosen values of V BG, to set the operation point for different temperatures, are shown in the inset of Fig. 6. The JMOSFET has shown the feasibility for operating with constant on- and off-current levels from room temperature up to 300 8C and thus advantages of this device include the relatively high bulk channel mobility, compared to the enhancement mode MOSFET, which normally shows low inversion channel mobilities. In addition, even higher current density than that
of the JFET alone can be achieved by accumulating the channel in the JMOSFET (see Fig. 7), which unravel the reduced current problems of JFETs at high temperatures.
Fig. 8. The top-gate transfer characteristics (I D–V TG) of a SiC NVFET for the temperature range from 25 to 300 8C.
Fig. 10. (a) Retention properties of a SiC NVFET. (b) I D–V D characteristics with top-gate V TG sweep after different V TG of +12 and 12 V was applied.
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The simultaneously processed NVFET shows nonvolatile memory properties, which can be operated up to 300 8C with memory function retained up to 200 8C. Fig. 8 shows typical top-gate transfer (I D–V TG) characteristics of a SiC NVFET for different temperatures. Dual directional sweeps of V TG were performed at room temperature between d 12T and d+12T V, the drain voltage V D is kept constant at 10 V. It can be clearly seen that I D–V TG characteristics exhibit memory effect: depending on the sweep direction, two different values of drain current I D can be read in the channel at the same gate voltage. The memory window of the transistor is 5.0 V at V D=10 V, which agrees with the value reported earlier from C–V measurements on the diode structure of PZT/Al2O3/SiC [18,20]. The reduction of the memory window for elevated temperature can be ascribed to decreased amount of charge trapping and increased recombination at high temperatures as well as to reduced polarization in PZT. In the ideal case of ferroelectric field effect transistor, interface states and bound charges are absent and the concentration of the carriers on the ferroelectric/semiconductor interface is controlled mainly by superposition of gate electric field and stray electric field of ferroelectric domains. As a result, the direction of I D–V G hysteresis loop is anticlockwise [21]. Trapping of carriers on the non-ideal gate dielectric/semiconductor interface is a competing mechanism. It prevails in our case and results in an opposite direction of the hysteresis loop. The charges can be injected from the semiconductor into the ferroelectric or interface traps and attracted by the remnant polarization consequently become bounded to the ferroelectric domains when the applied field is removed. Further depletion of the channel can be achieved by biasing either the ferroelectric gate on top V G or the backside junction gate V BG (see Fig. 9). Thus all the JMOSFETs and NVFETs can essentially be controlled from the buried gate at the same time. Fig. 10a shows drain current I D at V D=10 V as a function of the retention time for two temperatures: 25 and 150 8C. A voltage pulse of 12 or +12 V was initially applied to the gate during 100 ms, after which the gate voltage was kept at 0 V for the retention measurements. The high drain current state was found to be stable without significant change during 2104 s. Fig. 10b shows the drain current I D versus the drain voltage V D characteristics.
demonstrated in novel structures such as the JMOSFETs and NVFETs. These devices were also successfully integrated together on the same 4H-SiC substrate and fully functional operation was demonstrated from room temperature up to 300 8C.
Acknowledgments This research was partially supported by the Swedish Foundation for Strategic Research, SSF.
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4. Summary SiC devices with high temperature stable operation for potential use in analog and digital circuits have been
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