- Email: [email protected]
First results with prototype ISIS devices for ILC vertex detector
Nuclear Instruments and Methods in Physics Research A 624 (2010) 465–469
Contents lists available at ScienceDirect
Nuclear Instruments and Methods in Physics Research A journal homepage: www.elsevier.com/locate/nima
First results with prototype ISIS devices for ILC vertex detector C. Damerell a,n, Z. Zhang a, R. Gao b, Jaya John John b, Y. Li b, A. Nomerotski b, A. Holland c, G. Seabroke c, M. Havranek d, K. Stefanov e, A. Kar-Roy f, R. Bell g, D. Burt g, P. Pool g a
RAL, Oxon OX11 0QX, UK Oxford U, UK c Centre for Electronic Imaging, Open U, UK d Czech Technical University in Prague, Czech Republic e Sentec Ltd, Cambridge, UK f Jazz Semiconductors, California USA g e2V Technologies, Chelmsford, UK b
a r t i c l e in fo
abstract
Available online 11 June 2010
The vertex detectors at the International Linear Collider (ILC) (there will be two of them, one for each of two general purpose detectors) will certainly be built with silicon pixel detectors, either monolithic or perhaps vertically integrated. However, beyond this general statement, there is a wide range of options supported by active R&D programmes all over the world. Pixel-based vertex detectors build on the experience at the SLAC large detector (SLD) operating at the SLAC linear collider (SLC), where a 307 Mpixel detector permitted the highest physics performance at LEP or SLC. For ILC, machine conditions demand much faster readout than at SLC, something like 20 time slices during the 1 ms bunch train. The approach of the image sensor with in-situ storage (ISIS) is unique in offering this capability while avoiding the undesirable requirement of ‘pulsed power’. First results from a prototype device that approaches the pixel size of 20 mm square, needed for physics, are reported. The dimensional challenge is met by using a 0.18 mm imaging CMOS process, instead of a conventional CCD process. & 2010 Elsevier B.V. All rights reserved.
Keywords: Pixel detectors ILC Vertex detectors Monolithic CMOS pixels
1. Introduction Vertex detectors for the ILC will need to satisfy a number of challenging performance goals. The general layout will comprise 5 nested cylinders (possibly augmented by endcap layers), with overall dimensions 25 cm long and 6 cm outer radius. The detector technology will be some form of monolithic silicon pixel structure with pixel sizes 20 20 mm2, resulting in a total of 1 Gpixel, a modest factor 3 beyond the SLD vertex detector that was operating ten years ago. Measurement of low momentum tracks is important for some physics studies, and maintaining adequate precision necessitates a layer thickness not exceeding 0.1% radiation length per layer, a realistic factor 4 below that of the SLD detector. The major new challenge is in timing capability, most conveniently expressed in terms of the required sensitive window (SW). The detector of course needs to be sensitive throughout the bunch crossing interval (BCI, 1 ms duration) that occurs at a rate of 5 Hz. Integrating the signals through the 3000 bunches of the BCI (which would correspond to the SLD readout procedure) is unacceptable due to background con-
n
Corresponding author. E-mail address: [email protected] (C. Damerell).
0168-9002/$ - see front matter & 2010 Elsevier B.V. All rights reserved. doi:10.1016/j.nima.2010.04.154
siderations—the data needs to be time-sliced by a factor of 20 (hence 50 ms between readout cycles or ‘frame stores’). Several approaches to satisfy this challenging requirement are being actively pursued, and were reported in detail at the Review of R&D for the ILC Vertex Detector, during the LCWS2007 Linear Collider workshop. The slides describing the R&D programmes in detail can be found in the workshop proceedings [1] and the report of the Review Committee can be found at [2]. The classes of devices considered can be categorised in roughly increasing order of complexity as CCDs, monolithic pixels (NMOS only), monolithic pixels (full CMOS), the ISIS option (CCD-inCMOS), the DEPFET (in-house process) and most adventurously SOI and vertically integrated architectures. There are major R&D issues for each technology. Funding agencies would prefer the community to ‘pick winners’, but in so doing they would run the risk of diminishing the ILC physics capability. The preferable approach is to let the R&D groups continue their work or change direction, on the basis of their detailed understanding of all the issues. Over the past few years, some ideas have indeed been dropped (e.g. the macropixel/micropixel hybrid) and this type of healthy internal adjustment will doubtless continue as the worldwide R&D activities evolve, sustained by the information network which constantly broadens our vision.
466
C. Damerell et al. / Nuclear Instruments and Methods in Physics Research A 624 (2010) 465–469
The approaches currently under study cover a wide range of goals regarding the SW, from one or two which would provide single-bunch timing (SW of o0.3 ms) to one (the fine pixel CCD or FPCCD) which would entirely avoid the need for time slicing by integrating everything through the train, but then forming minitrack-vectors in each layer, allowing efficient rejection of background hits, due to the different direction of tightly spiraling background electrons compared with the genuine products of the high energy interaction emerging from the interaction point (IP). Details of all these approaches can be found in [1], under the headings MIMOSA, INFN Group, CAP, DEPFET, SiD Group, Fermilab Group, FPCCD, LCFI and Chronopixels. While the short-SW options are at first sight most attractive in terms of the cleanest background rejection, they inevitably (other things being equal) imply higher power during the bunch train, at a level which would need a massive liquid cooling system if sustained continuously, thereby violating the limits on material budget. The solution generally considered is ‘pulsed power’, namely to switch on the electrical power only during the bunch trains. Given the operation in a high field solenoid (3–5 T), this implies Lorentz forces which could disturb the delicate mechanical assembly. To restrict distortions and vibrations to an acceptable level, may imply mechanical supports which again violate the material budget requirements. These considerations led the review committee to conclude that extensive R&D needs to be done before any option can be considered as a serious candidate for use at ILC. The ‘acceptance criterion’ unanimously agreed in the community is for fully serviced ladders to be operating in a test beam under ILC conditions as regards spill length and duty cycle, demonstrating the critical features (material budget, mechanical stability, track reconstruction efficiency and precision, their target SW, etc.). Some R&D groups think they will be able to do this by 2012. Others assume they can be later since the timescale for making decisions may be delayed, or they consider their options to be candidates for future upgrades. There is also the possibility, first raised by Su Dong in the 2007 review (SiD Group report in [1]), and now widely favoured, of a different technology choice (say with single-bunch timing capability) for layer-1, where the background levels are highest, but where the proximity to the beampipe may permit a ‘special solution’ in terms of mechanical supports and cooling. A technology with lower performance in terms of SW (say 50 ms)
but superior material budget, might then be selected for the outer layers.
2. ISIS design concept The ISIS architecture [3,4], is one of the time-slicing approaches, but it is unique in that it does not require pulsed power, and hence might offer the most favourable material budget of all. The basic variant offers a 50 ms SW (20 frames per bunch train), but an option with finer time slicing will be discussed in Section 4. The key feature that distinguishes the ISIS (see Figs. 1 and 2) is the accumulation of 20 frames of data (raw signal charge) in a 20-pixel storage register associated with each photogate, i.e. with each imaging pixel. After each time slice during the bunch train, charge is transferred by one pixel along the storage register with negligible power dissipation. This is followed by leisurely charge-to-voltage conversion and readout at the rate of 10 ms per frame, during the quiet inter-train period of 200 ms. This sequence has the further advantage of desensitising the detector from electrical noise (beam-related or not) that may cause interference during the bunch train. Storage of a tiny signal charge in a buried channel potential well has been shown to be extremely robust against pickup which would disrupt sensitive analogue electronics associated with charge-tovoltage conversion and beyond. Regarding this issue, efforts will of course be made during ILC commissioning to reduce sources of pickup to an acceptable level, but (as happened at SLC) success cannot be guaranteed, bearing in mind the inevitable time pressure to finish commissioning the machine and permit the first detector to move onto beamline. Once that happens, further diagnosis and amelioration of pickup problems could be extremely difficult. The concept of the ISIS has its origins in commercial devices used for fast-frame optical imaging [5]. The idea for ILC vertexing is to collect signals onto an array of photogates which are biased to deplete several microns of the high-resistivity epitaxial silicon below. The location of the photogates (a slightly trapezoidal array of 20 20 mm2) defines the geometry of the imaging pixels. All the circuitry in the active area is shielded by a deep p implant, other than apertures below the photogates. To a first approximation, signal charges (electrons) are trapped in the epilayer by the
Fig. 1. Cross-section of ISIS concept.
C. Damerell et al. / Nuclear Instruments and Methods in Physics Research A 624 (2010) 465–469
Fig. 2. Plan view of ISIS concept. Target dimensions of linear register are 80 5 mm2.
potential steps to the sheets of p + material above and below, so they diffuse transversely till they encounter the depletion edges below the photogates, where they are collected. The cluster size (typically 2 2 or 3 3 with 200e threshold) is determined by the geometry of the photogates, and the extent of the ‘mushroom’ of depleted silicon below them. This steady collection of signal charge by a combination of diffusion and drift continues through the bunch train, while every 50 ms the collected charge under each photogate is shifted on by one element of a 20-element serial register. At the end of the train, the 20 frames of raw signal charge are safely stored in these buried channel registers. Readout during the inter-train period commences by selecting the first row of the array and shifting the signals by one storage element, so the earliest time slice is transferred to a conventional in-pixel readout circuit, consisting of a sensing transistor, a reset transistor and a row-select transistor (Fig. 2). Voltage signals from the selected row are propagated down column lines and sensed at the periphery of the active area, in a column-parallel architecture (i.e. a complete processing chain for each column) on a pitch of 20 mm. Voltage levels immediately before and after charge transfer are sampled by an ADC, and the difference establishes the signal with high precision (standard correlated double sampling or CDS). Since the inter-train gap allows 10 ms readout time per frame, the noise performance can be excellent (few e rms).
467
The biggest challenge faced by this concept is to satisfy the physics requirement of 20 mm pixels, set by the hit density of tracks in high energy jets. Since these jets include long-lived Bs which may decay well beyond the beampipe, the requirement of small pixels should not be relaxed in the outer layers of the vertex detector. The required density of photogates (Fig. 2) implies that the linear register plus in-pixel electronics should be restricted to an area of 400 mm2, say 5 80 mm2. So the size of each storage pixel should be approximately 5 3 mm2, leaving a region of 5 20 mm2 for the associated electronics, which is sufficient. The required dimensions of the storage pixels take us beyond the limits of CCD manufacturers for the scientific market. CCDs with few micron pixels are made by some manufacturers of imaging chips for commercial markets, but their facilities are dedicated to large volume production. What is needed is to work within the constraints of foundries supplying CMOS imaging devices, some of which cater for small-volume scientific customers. We identified Jazz Semiconductors as extremely promising, and the results reported here relate to our first prototypes using their 0.18 mm process, which offers a dual gate thickness, 12 nm in the imaging area (with 5 V devices) and 4.1 nm in the periphery (with1.8 V devices). In contrast to CCD technology where overlapping polysilicon gates are used to maximize charge transfer efficiency (CTE), a multi-layer CMOS process requires device planarisation at every step, so one is obliged to fabricate all the gates in a single layer of polysilicon, with gaps to provide electrical isolation between adjacent gates. For the Jazz process, the minimum gap is 0.23 mm, and we processed devices with gaps in the range 0.23–0.30 mm in order to explore the working range. Our simulations indicated that with 1 mm long gates (so 3 mm long 3-phase pixels) such gaps should still yield very good CTE. Note that the CTE does not need to achieve the levels of excellence usually associated with scientific imaging CCDs, due to the much smaller number of storage elements in each register (20 compared with hundreds or thousands in typical CCDs). With 2000e well capacity per mm2, the individual gates of 1 5 mm2 for a 3-phase pixel, should be entirely adequate for a detector of minimum ionizing particles, having a sensitive thickness (epilayer thickness) of 20–30 mm.
3. First results with ISIS-2 ISIS-1 was a prototype made with a CCD process, which was used successfully to establish some of the operating principles. ISIS-2 is the first prototype made with the CMOS process at Jazz Semiconductors. The linear structures satisfy the dimensional limits of 5 80 mm2, but they are arranged on a 10 mm pitch, due to layout issues with this first design. For ISIS-3, it may be possible to restrict the structure between each register to a simple, very compact channel stop, as in a standard CCD array. So we are already close to the design goal in terms of effective size of the imaging pixels of 20 mm2. So far, studies have been focused on various test structures including a short-CCD device (Fig. 3) which is a truncated version of the full array, lacking the storage cells, and comprising photogate (PG), summing gate (SG), output gate (OG) and output node. The purpose is to test all the key elements, since the storage register in the full array comprises no more than 60 additional SG-like structures. Initial attempts to get these test devices to work were unsuccessful till we realized the importance of two effects which are much less significant with CCDs we had used previously, which had pixel sizes typically 30 times larger in area than those in our register. The first of these are short-channel effects, which result in a much reduced ‘tracking factor’ (ratio of change in buried channel potential wrt change in gate potential),
468
C. Damerell et al. / Nuclear Instruments and Methods in Physics Research A 624 (2010) 465–469
Fig. 3. Short-CCD layout. PG length is 3 mm, and lengths of IG SG and OG are all 1 mm. Buried channel width under PG and SG is 5 mm, then it funnels down to the output node.
potential is reduced well below the originally expected value of 1 V. Transfer from the photogate produces a premature signal (labeled PG) on the node, unless VOG is reduced below 0 V. We found 0.2 V to give correct operation (PG signal 0), which is still above the minimum of 0.5 V set by the gate protection circuits. Another discovery with these prototypes is related to the polysilicon gates of the register. Due to the short gate length (0.7 mm of polysilicon, excluding the gaps) the standard procedures (doping and/or silicide layers) could not be accommodated within the Jazz process. This was not considered a problem since the resistivity of the undoped polysilicon was assumed to be 106 O cm, implying 1 ns risetime of the signal on the gates. It was found that this risetime was more like 10 ms, so the gate resistance is much higher than expected. This was verified by measurement of chains of undoped polysilicon resistors on the wafers. We subsequently learned that the sheet resistance of undoped polysilicon is much higher than that of pure undoped silicon, due to resistance across grain boundaries. Jazz offer a process variation (doping before patterning) which will overcome this problem, and this will be implemented on ISIS-3. We have so far observed X-ray conversions in the output diode (without clocking) as shown in Fig. 5. This confirms the simulated responsivity of the output circuit of 24 mV/e . Results are stable from 10 1C to room temperature. The observed width of the Mn(Ka) line reflects the complexity of the collection volume (moving from depleted to undepleted material) and cannot be used to infer the noise performance of the system. Subsequent to the workshop, we have observed efficient transfer of 55Fe signals from PG to node in this test structure (Fig. 3) for various PG dimensions (1 5, 3 5 and 6 5 mm2), and also from PG to node via the 20-element storage register of the full array, so the entire chain has now been demonstrated to operate correctly. Jim Janesick has done pioneering work on noise in very small FETs used in CMOS (and now also CCD) imagers [6,7]. A key feature is that the 1/f noise familiar from larger FETs manifests itself in RTS noise in very small FETs made with the deep submicron process, since the gate area is so small that 0, 1 or a few interface states determine the noise behavior. This has important implications for the noise performance of CDS circuits, such as the independence of the noise after CDS on the sampling period. In our devices, the FET sizes are still perhaps too large for this deviation from 1/f noise to be apparent, but it will be interesting to make the measurements. The performance for
Fig. 4. Signal on output node as fn of VOG. PG is premature signal and SG is on-time signal.
namely 0.5 in contrast to 0.9 in CCDs with larger pixels. In addition, there are fringing field effects, which particularly affect the potential in the channel below the output gate, due to its proximity to the output node at 5 V. Fortunately, once these points were appreciated, it was possible to achieve good charge transfer, while still respecting the rather narrow range of operating voltage of these devices, as indicated in Fig. 4, which demonstrates the failure of the output gate to restrain the charge packet from transferring prematurely to the node, unless its
Fig. 5.
55
Fe X-ray signal seen on output node.
C. Damerell et al. / Nuclear Instruments and Methods in Physics Research A 624 (2010) 465–469
469
4. Future plans
Fig. 6. Noise performance (CDS with 800 ns between samples). Standard deviation is 5.5e equivalent charge on node.
relatively fast sampling rates (relevant for our application) is shown in Fig. 6. The excellent noise performance (5.5e rms) is achieved by CDS with a measured signal risetime of 133 ns and a sampling interval of 800 ns. When we increase the bandwidth (risetime 102 ns) the noise increases to 6.1e , consistent with the expectation for a system dominated by white noise—proportional to 1/sqrt(risetime). It will be interesting to explore slower clocking and see what performance can be achieved for slowscan applications. We are in a new regime of noise performance for CCD structures, because of the greatly reduced node capacitance achievable with the CMOS process. Simulations using Silvaco-TCAD are now being run for the complete test structure, and these confirm the importance of the fringing field and short-channel effects. This simulation indicates that the potential below the output gate is raised by approximately 0.7 V due to its proximity to the output diode.
For the next step (ISIS-3), solving the gate resistance problem should allow contact to be made directly to the gates in the active area of the register, eliminating the need for doped tabs which currently swell the width of the register from 5 to 10 mm. This should allow the goal of 20 20 mm2 imaging pixels to be realised. Furthermore, the signal processing (ADCs, CDS, cluster finding and data sparsification) will next be implemented on chip. Given our experience with developing readout chips for column parallel CCDs [8], this should be relatively straightforward, since the operating conditions are greatly relaxed. ISIS-4 should be a full-scale device ( 12.5 2 cm2) to assemble into prototype ladders for evaluation as candidates for an ILC vertex detector. In the light of ongoing developments in the ILC design, it could be that a 50 ms SW may prove to be insufficient even beyond the inner layer. If the ISIS option has demonstrated its advantages in terms of mechanical stability and material budget, how could one proceed? This architecture could be preserved, while evolving to the vertically integrated or 3-D technology [9]. Tier 1 could be used for SWs 1–20, tier 2 for SWs 21–40, and so on. Whether this could be developed in time for ILC startup, or would be a candidate for an upgrade, depends on how close ILC is able to hold to the most optimistic schedule for becoming an approved project, namely 2012. If there are a few years further delay, the 3-D ISIS could be there for startup. References /http://ilcagenda.linearcollider.org/conferenceDisplay.py?confId=2208S. /http://www.linearcollider.org/wiki/doku.php?id=drdp:drdp_homeS. C.J.S. Damerell, Nucl. Instr. and Meth. A 541 (2005) 178. K.D. Stefanov, Nucl. Instr. and Meth. A 569 (2006) 48. T. Goji Etoh, et al., IEEE Trans. ED ED50 (2003) 144. J. Janesick, et al., Proc. SPIE 6276 (2006). J. Janesick, et al., Proc. SPIE 6690 (2007). M. Havranek et al., Readout chip for column parallel CCD, CPR2A, NIM A, submitted for publication. [9] R. Yarema et al., 3D IC pixel electronics—the next challenge, FERMILAB-PUB08-564 (2008). [1] [2] [3] [4] [5] [6] [7] [8]
Contents lists available at ScienceDirect
Nuclear Instruments and Methods in Physics Research A journal homepage: www.elsevier.com/locate/nima
First results with prototype ISIS devices for ILC vertex detector C. Damerell a,n, Z. Zhang a, R. Gao b, Jaya John John b, Y. Li b, A. Nomerotski b, A. Holland c, G. Seabroke c, M. Havranek d, K. Stefanov e, A. Kar-Roy f, R. Bell g, D. Burt g, P. Pool g a
RAL, Oxon OX11 0QX, UK Oxford U, UK c Centre for Electronic Imaging, Open U, UK d Czech Technical University in Prague, Czech Republic e Sentec Ltd, Cambridge, UK f Jazz Semiconductors, California USA g e2V Technologies, Chelmsford, UK b
a r t i c l e in fo
abstract
Available online 11 June 2010
The vertex detectors at the International Linear Collider (ILC) (there will be two of them, one for each of two general purpose detectors) will certainly be built with silicon pixel detectors, either monolithic or perhaps vertically integrated. However, beyond this general statement, there is a wide range of options supported by active R&D programmes all over the world. Pixel-based vertex detectors build on the experience at the SLAC large detector (SLD) operating at the SLAC linear collider (SLC), where a 307 Mpixel detector permitted the highest physics performance at LEP or SLC. For ILC, machine conditions demand much faster readout than at SLC, something like 20 time slices during the 1 ms bunch train. The approach of the image sensor with in-situ storage (ISIS) is unique in offering this capability while avoiding the undesirable requirement of ‘pulsed power’. First results from a prototype device that approaches the pixel size of 20 mm square, needed for physics, are reported. The dimensional challenge is met by using a 0.18 mm imaging CMOS process, instead of a conventional CCD process. & 2010 Elsevier B.V. All rights reserved.
Keywords: Pixel detectors ILC Vertex detectors Monolithic CMOS pixels
1. Introduction Vertex detectors for the ILC will need to satisfy a number of challenging performance goals. The general layout will comprise 5 nested cylinders (possibly augmented by endcap layers), with overall dimensions 25 cm long and 6 cm outer radius. The detector technology will be some form of monolithic silicon pixel structure with pixel sizes 20 20 mm2, resulting in a total of 1 Gpixel, a modest factor 3 beyond the SLD vertex detector that was operating ten years ago. Measurement of low momentum tracks is important for some physics studies, and maintaining adequate precision necessitates a layer thickness not exceeding 0.1% radiation length per layer, a realistic factor 4 below that of the SLD detector. The major new challenge is in timing capability, most conveniently expressed in terms of the required sensitive window (SW). The detector of course needs to be sensitive throughout the bunch crossing interval (BCI, 1 ms duration) that occurs at a rate of 5 Hz. Integrating the signals through the 3000 bunches of the BCI (which would correspond to the SLD readout procedure) is unacceptable due to background con-
n
Corresponding author. E-mail address: [email protected] (C. Damerell).
0168-9002/$ - see front matter & 2010 Elsevier B.V. All rights reserved. doi:10.1016/j.nima.2010.04.154
siderations—the data needs to be time-sliced by a factor of 20 (hence 50 ms between readout cycles or ‘frame stores’). Several approaches to satisfy this challenging requirement are being actively pursued, and were reported in detail at the Review of R&D for the ILC Vertex Detector, during the LCWS2007 Linear Collider workshop. The slides describing the R&D programmes in detail can be found in the workshop proceedings [1] and the report of the Review Committee can be found at [2]. The classes of devices considered can be categorised in roughly increasing order of complexity as CCDs, monolithic pixels (NMOS only), monolithic pixels (full CMOS), the ISIS option (CCD-inCMOS), the DEPFET (in-house process) and most adventurously SOI and vertically integrated architectures. There are major R&D issues for each technology. Funding agencies would prefer the community to ‘pick winners’, but in so doing they would run the risk of diminishing the ILC physics capability. The preferable approach is to let the R&D groups continue their work or change direction, on the basis of their detailed understanding of all the issues. Over the past few years, some ideas have indeed been dropped (e.g. the macropixel/micropixel hybrid) and this type of healthy internal adjustment will doubtless continue as the worldwide R&D activities evolve, sustained by the information network which constantly broadens our vision.
466
C. Damerell et al. / Nuclear Instruments and Methods in Physics Research A 624 (2010) 465–469
The approaches currently under study cover a wide range of goals regarding the SW, from one or two which would provide single-bunch timing (SW of o0.3 ms) to one (the fine pixel CCD or FPCCD) which would entirely avoid the need for time slicing by integrating everything through the train, but then forming minitrack-vectors in each layer, allowing efficient rejection of background hits, due to the different direction of tightly spiraling background electrons compared with the genuine products of the high energy interaction emerging from the interaction point (IP). Details of all these approaches can be found in [1], under the headings MIMOSA, INFN Group, CAP, DEPFET, SiD Group, Fermilab Group, FPCCD, LCFI and Chronopixels. While the short-SW options are at first sight most attractive in terms of the cleanest background rejection, they inevitably (other things being equal) imply higher power during the bunch train, at a level which would need a massive liquid cooling system if sustained continuously, thereby violating the limits on material budget. The solution generally considered is ‘pulsed power’, namely to switch on the electrical power only during the bunch trains. Given the operation in a high field solenoid (3–5 T), this implies Lorentz forces which could disturb the delicate mechanical assembly. To restrict distortions and vibrations to an acceptable level, may imply mechanical supports which again violate the material budget requirements. These considerations led the review committee to conclude that extensive R&D needs to be done before any option can be considered as a serious candidate for use at ILC. The ‘acceptance criterion’ unanimously agreed in the community is for fully serviced ladders to be operating in a test beam under ILC conditions as regards spill length and duty cycle, demonstrating the critical features (material budget, mechanical stability, track reconstruction efficiency and precision, their target SW, etc.). Some R&D groups think they will be able to do this by 2012. Others assume they can be later since the timescale for making decisions may be delayed, or they consider their options to be candidates for future upgrades. There is also the possibility, first raised by Su Dong in the 2007 review (SiD Group report in [1]), and now widely favoured, of a different technology choice (say with single-bunch timing capability) for layer-1, where the background levels are highest, but where the proximity to the beampipe may permit a ‘special solution’ in terms of mechanical supports and cooling. A technology with lower performance in terms of SW (say 50 ms)
but superior material budget, might then be selected for the outer layers.
2. ISIS design concept The ISIS architecture [3,4], is one of the time-slicing approaches, but it is unique in that it does not require pulsed power, and hence might offer the most favourable material budget of all. The basic variant offers a 50 ms SW (20 frames per bunch train), but an option with finer time slicing will be discussed in Section 4. The key feature that distinguishes the ISIS (see Figs. 1 and 2) is the accumulation of 20 frames of data (raw signal charge) in a 20-pixel storage register associated with each photogate, i.e. with each imaging pixel. After each time slice during the bunch train, charge is transferred by one pixel along the storage register with negligible power dissipation. This is followed by leisurely charge-to-voltage conversion and readout at the rate of 10 ms per frame, during the quiet inter-train period of 200 ms. This sequence has the further advantage of desensitising the detector from electrical noise (beam-related or not) that may cause interference during the bunch train. Storage of a tiny signal charge in a buried channel potential well has been shown to be extremely robust against pickup which would disrupt sensitive analogue electronics associated with charge-tovoltage conversion and beyond. Regarding this issue, efforts will of course be made during ILC commissioning to reduce sources of pickup to an acceptable level, but (as happened at SLC) success cannot be guaranteed, bearing in mind the inevitable time pressure to finish commissioning the machine and permit the first detector to move onto beamline. Once that happens, further diagnosis and amelioration of pickup problems could be extremely difficult. The concept of the ISIS has its origins in commercial devices used for fast-frame optical imaging [5]. The idea for ILC vertexing is to collect signals onto an array of photogates which are biased to deplete several microns of the high-resistivity epitaxial silicon below. The location of the photogates (a slightly trapezoidal array of 20 20 mm2) defines the geometry of the imaging pixels. All the circuitry in the active area is shielded by a deep p implant, other than apertures below the photogates. To a first approximation, signal charges (electrons) are trapped in the epilayer by the
Fig. 1. Cross-section of ISIS concept.
C. Damerell et al. / Nuclear Instruments and Methods in Physics Research A 624 (2010) 465–469
Fig. 2. Plan view of ISIS concept. Target dimensions of linear register are 80 5 mm2.
potential steps to the sheets of p + material above and below, so they diffuse transversely till they encounter the depletion edges below the photogates, where they are collected. The cluster size (typically 2 2 or 3 3 with 200e threshold) is determined by the geometry of the photogates, and the extent of the ‘mushroom’ of depleted silicon below them. This steady collection of signal charge by a combination of diffusion and drift continues through the bunch train, while every 50 ms the collected charge under each photogate is shifted on by one element of a 20-element serial register. At the end of the train, the 20 frames of raw signal charge are safely stored in these buried channel registers. Readout during the inter-train period commences by selecting the first row of the array and shifting the signals by one storage element, so the earliest time slice is transferred to a conventional in-pixel readout circuit, consisting of a sensing transistor, a reset transistor and a row-select transistor (Fig. 2). Voltage signals from the selected row are propagated down column lines and sensed at the periphery of the active area, in a column-parallel architecture (i.e. a complete processing chain for each column) on a pitch of 20 mm. Voltage levels immediately before and after charge transfer are sampled by an ADC, and the difference establishes the signal with high precision (standard correlated double sampling or CDS). Since the inter-train gap allows 10 ms readout time per frame, the noise performance can be excellent (few e rms).
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The biggest challenge faced by this concept is to satisfy the physics requirement of 20 mm pixels, set by the hit density of tracks in high energy jets. Since these jets include long-lived Bs which may decay well beyond the beampipe, the requirement of small pixels should not be relaxed in the outer layers of the vertex detector. The required density of photogates (Fig. 2) implies that the linear register plus in-pixel electronics should be restricted to an area of 400 mm2, say 5 80 mm2. So the size of each storage pixel should be approximately 5 3 mm2, leaving a region of 5 20 mm2 for the associated electronics, which is sufficient. The required dimensions of the storage pixels take us beyond the limits of CCD manufacturers for the scientific market. CCDs with few micron pixels are made by some manufacturers of imaging chips for commercial markets, but their facilities are dedicated to large volume production. What is needed is to work within the constraints of foundries supplying CMOS imaging devices, some of which cater for small-volume scientific customers. We identified Jazz Semiconductors as extremely promising, and the results reported here relate to our first prototypes using their 0.18 mm process, which offers a dual gate thickness, 12 nm in the imaging area (with 5 V devices) and 4.1 nm in the periphery (with1.8 V devices). In contrast to CCD technology where overlapping polysilicon gates are used to maximize charge transfer efficiency (CTE), a multi-layer CMOS process requires device planarisation at every step, so one is obliged to fabricate all the gates in a single layer of polysilicon, with gaps to provide electrical isolation between adjacent gates. For the Jazz process, the minimum gap is 0.23 mm, and we processed devices with gaps in the range 0.23–0.30 mm in order to explore the working range. Our simulations indicated that with 1 mm long gates (so 3 mm long 3-phase pixels) such gaps should still yield very good CTE. Note that the CTE does not need to achieve the levels of excellence usually associated with scientific imaging CCDs, due to the much smaller number of storage elements in each register (20 compared with hundreds or thousands in typical CCDs). With 2000e well capacity per mm2, the individual gates of 1 5 mm2 for a 3-phase pixel, should be entirely adequate for a detector of minimum ionizing particles, having a sensitive thickness (epilayer thickness) of 20–30 mm.
3. First results with ISIS-2 ISIS-1 was a prototype made with a CCD process, which was used successfully to establish some of the operating principles. ISIS-2 is the first prototype made with the CMOS process at Jazz Semiconductors. The linear structures satisfy the dimensional limits of 5 80 mm2, but they are arranged on a 10 mm pitch, due to layout issues with this first design. For ISIS-3, it may be possible to restrict the structure between each register to a simple, very compact channel stop, as in a standard CCD array. So we are already close to the design goal in terms of effective size of the imaging pixels of 20 mm2. So far, studies have been focused on various test structures including a short-CCD device (Fig. 3) which is a truncated version of the full array, lacking the storage cells, and comprising photogate (PG), summing gate (SG), output gate (OG) and output node. The purpose is to test all the key elements, since the storage register in the full array comprises no more than 60 additional SG-like structures. Initial attempts to get these test devices to work were unsuccessful till we realized the importance of two effects which are much less significant with CCDs we had used previously, which had pixel sizes typically 30 times larger in area than those in our register. The first of these are short-channel effects, which result in a much reduced ‘tracking factor’ (ratio of change in buried channel potential wrt change in gate potential),
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Fig. 3. Short-CCD layout. PG length is 3 mm, and lengths of IG SG and OG are all 1 mm. Buried channel width under PG and SG is 5 mm, then it funnels down to the output node.
potential is reduced well below the originally expected value of 1 V. Transfer from the photogate produces a premature signal (labeled PG) on the node, unless VOG is reduced below 0 V. We found 0.2 V to give correct operation (PG signal 0), which is still above the minimum of 0.5 V set by the gate protection circuits. Another discovery with these prototypes is related to the polysilicon gates of the register. Due to the short gate length (0.7 mm of polysilicon, excluding the gaps) the standard procedures (doping and/or silicide layers) could not be accommodated within the Jazz process. This was not considered a problem since the resistivity of the undoped polysilicon was assumed to be 106 O cm, implying 1 ns risetime of the signal on the gates. It was found that this risetime was more like 10 ms, so the gate resistance is much higher than expected. This was verified by measurement of chains of undoped polysilicon resistors on the wafers. We subsequently learned that the sheet resistance of undoped polysilicon is much higher than that of pure undoped silicon, due to resistance across grain boundaries. Jazz offer a process variation (doping before patterning) which will overcome this problem, and this will be implemented on ISIS-3. We have so far observed X-ray conversions in the output diode (without clocking) as shown in Fig. 5. This confirms the simulated responsivity of the output circuit of 24 mV/e . Results are stable from 10 1C to room temperature. The observed width of the Mn(Ka) line reflects the complexity of the collection volume (moving from depleted to undepleted material) and cannot be used to infer the noise performance of the system. Subsequent to the workshop, we have observed efficient transfer of 55Fe signals from PG to node in this test structure (Fig. 3) for various PG dimensions (1 5, 3 5 and 6 5 mm2), and also from PG to node via the 20-element storage register of the full array, so the entire chain has now been demonstrated to operate correctly. Jim Janesick has done pioneering work on noise in very small FETs used in CMOS (and now also CCD) imagers [6,7]. A key feature is that the 1/f noise familiar from larger FETs manifests itself in RTS noise in very small FETs made with the deep submicron process, since the gate area is so small that 0, 1 or a few interface states determine the noise behavior. This has important implications for the noise performance of CDS circuits, such as the independence of the noise after CDS on the sampling period. In our devices, the FET sizes are still perhaps too large for this deviation from 1/f noise to be apparent, but it will be interesting to make the measurements. The performance for
Fig. 4. Signal on output node as fn of VOG. PG is premature signal and SG is on-time signal.
namely 0.5 in contrast to 0.9 in CCDs with larger pixels. In addition, there are fringing field effects, which particularly affect the potential in the channel below the output gate, due to its proximity to the output node at 5 V. Fortunately, once these points were appreciated, it was possible to achieve good charge transfer, while still respecting the rather narrow range of operating voltage of these devices, as indicated in Fig. 4, which demonstrates the failure of the output gate to restrain the charge packet from transferring prematurely to the node, unless its
Fig. 5.
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Fe X-ray signal seen on output node.
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Fig. 6. Noise performance (CDS with 800 ns between samples). Standard deviation is 5.5e equivalent charge on node.
relatively fast sampling rates (relevant for our application) is shown in Fig. 6. The excellent noise performance (5.5e rms) is achieved by CDS with a measured signal risetime of 133 ns and a sampling interval of 800 ns. When we increase the bandwidth (risetime 102 ns) the noise increases to 6.1e , consistent with the expectation for a system dominated by white noise—proportional to 1/sqrt(risetime). It will be interesting to explore slower clocking and see what performance can be achieved for slowscan applications. We are in a new regime of noise performance for CCD structures, because of the greatly reduced node capacitance achievable with the CMOS process. Simulations using Silvaco-TCAD are now being run for the complete test structure, and these confirm the importance of the fringing field and short-channel effects. This simulation indicates that the potential below the output gate is raised by approximately 0.7 V due to its proximity to the output diode.
For the next step (ISIS-3), solving the gate resistance problem should allow contact to be made directly to the gates in the active area of the register, eliminating the need for doped tabs which currently swell the width of the register from 5 to 10 mm. This should allow the goal of 20 20 mm2 imaging pixels to be realised. Furthermore, the signal processing (ADCs, CDS, cluster finding and data sparsification) will next be implemented on chip. Given our experience with developing readout chips for column parallel CCDs [8], this should be relatively straightforward, since the operating conditions are greatly relaxed. ISIS-4 should be a full-scale device ( 12.5 2 cm2) to assemble into prototype ladders for evaluation as candidates for an ILC vertex detector. In the light of ongoing developments in the ILC design, it could be that a 50 ms SW may prove to be insufficient even beyond the inner layer. If the ISIS option has demonstrated its advantages in terms of mechanical stability and material budget, how could one proceed? This architecture could be preserved, while evolving to the vertically integrated or 3-D technology [9]. Tier 1 could be used for SWs 1–20, tier 2 for SWs 21–40, and so on. Whether this could be developed in time for ILC startup, or would be a candidate for an upgrade, depends on how close ILC is able to hold to the most optimistic schedule for becoming an approved project, namely 2012. If there are a few years further delay, the 3-D ISIS could be there for startup. References /http://ilcagenda.linearcollider.org/conferenceDisplay.py?confId=2208S. /http://www.linearcollider.org/wiki/doku.php?id=drdp:drdp_homeS. C.J.S. Damerell, Nucl. Instr. and Meth. A 541 (2005) 178. K.D. Stefanov, Nucl. Instr. and Meth. A 569 (2006) 48. T. Goji Etoh, et al., IEEE Trans. ED ED50 (2003) 144. J. Janesick, et al., Proc. SPIE 6276 (2006). J. Janesick, et al., Proc. SPIE 6690 (2007). M. Havranek et al., Readout chip for column parallel CCD, CPR2A, NIM A, submitted for publication. [9] R. Yarema et al., 3D IC pixel electronics—the next challenge, FERMILAB-PUB08-564 (2008). [1] [2] [3] [4] [5] [6] [7] [8]