Flip-flops

1 Flip-flops

1.1. Overview of the different types of flip-flops “Flip-flops” or latches are widely used circuits. There are various applications: for example, delaying the extinction of a signal, pacing the switching on or off of light, dividing the signal frequency, shaping a signal masked by noise, scheduling the operation of a process, processing the signals, etc. The flip-flops of greatest interest can be identified as: – monostable flip-flops; – bistable flip-flops; – the Schmitt flip-flop. Briefly, a monostable flip-flop can be represented by a black box (Figure 1.1). When impulses (so-called trigger pulses) are applied on the input of this device, we will have a signal on output which will alternatively have a quasi-stable and a stable state.

Figure 1.1. Monostable principle

The duration of the quasi-stable state is chosen by the user. At the end of the duration of this quasi-stable state, the circuit returns to its stable state. The quasi-

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stable state is obtained on output only if a pulse trigger is sent at the input of the circuit. It should be noted that there are two types of monostable: retriggerable monostable and non-retriggerable monostable. The most commonly used is the nonretriggerable monostable. On the other hand, a bistable circuit has two stable states: high state and low state. At every trigger pulse applied on the bistable circuit input, the state of the output changes (Figure 1.2).

Figure 1.2. Principle of the bistable circuit

The Schmitt flip-flop or trigger is actually a special case of bistable flip-flops. The Schmitt flip-flop will be addressed separately because of its peculiarity compared to conventional bistable flip-flops. This type of flip-flop is mainly useful for shaping signals. Furthermore, when, for example, a signal of sinusoidal form is applied to the input of a Schmitt flip-flop (Figure 1.3), the output will assume a square shape. The shift from the low state to the high state and vice versa will depend on two specific triggering thresholds inherent to the Schmitt flip-flop. The latter is frequently used for controlling threshold-based devices. Voltages V1 and V2 are the two inherent thresholds of the Schmitt flip-flop.

Figure 1.3. Schmitt flip-flop principle

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1.2. Monostable flip-flops 1.2.1. Monostable transistor flip-flop 1.2.1.1. Principle and operation On output, the monostable circuit will give a quasi-stable level for a welldetermined time T1 when a short pulse is applied on input. An example of a monostable circuit implemented around bipolar transistors is schematized in Figure 1.4. It should be noted that the study of this circuit is very interesting to fully understand the various switching phenomena that may exist. The interest in this circuit is educational rather than practical due to the fact that nowadays, this type of device can be implemented using integrated circuits.

VC1

VC2

Figure 1.4. Bipolar transistor monostable

The functioning of such a circuit is established as follows: – at rest, there is no trigger pulse. Transistor Tr1 is blocked because of the negative polarization applied to its base. The voltage applied to the collector (VC1) of transistor Tr1 is equal to the supply voltage +Vcc: VC1 = Vcc When connecting (powering on), this voltage VC1 changes from a value a priori equal to zero to the value VCC; the capacitor C transmits this variation to the base of transistor Tr2. The latter will go to a saturation state. We then have:

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Tr1 blocked and Tr2 saturated VC1 = VCC; VC2 = vs ≅ 0; VB2 ≅ 0.6 v When a brief negative pulse ve is applied at time t = t0, the capacitor C will instantly transmit the falling edge of this impulse to the base of transistor Tr2. The voltage applied at the base of this transistor will suddenly be negative and the latter will block. As a result, we have: VB2 < 0 VC2 = vs ≅ Vcc The voltage Vcc applied at the level of the collector of transistor Tr2 is partly transmitted to the base of transistor Tr1, which will cause the latter to shift to a saturated state: VC1 ≅ 0. The voltage applied to the collector of transistor Tr1 changes from a value Vcc to a value equal to 0, with a decrease of the order of –VCC. This variation is instantly transmitted by capacitor C towards the base of transistor Tr2, which means that the base of the latter is now at potential: VB2 = –Vcc + 0.6 This reinforces the idea of blocking transistor Tr2 when the short negative pulse is applied. Under these circumstances, we can establish an equivalent diagram of the branch containing capacitor C, as shown in Figure 1.5.

Figure.1.5. Equivalent diagram of the branch containing capacitor C when transistor Tr1 is saturated

Capacitor C will start to charge through resistance R, in order to try to reach the maximum voltage (+VCC) that is applied to it.

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It should be recalled that the initial voltage at the terminals of the capacitor is of the order of (–VCC + 0.6v). This tension is none other than the voltage VB2 applied to the base of transistor Tr2. Once this tension reaches and slightly exceeds the value of 0.6 volts, transistor Tr2 is saturated and transistor Tr1 blocks. The system will maintain this state until a new impulse reaches the collector of transistor Tr1. At this moment, the cycle described above will repeat. It can be observed that duration T1 of the quasi-stable state of the output signal depends on the time constant τ = RC. The signals associated with the operation of the monostable are presented in Figure 1.6.

Figure 1.6. Signals associated with the functioning of the bipolar transistor monostable. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

1.2.1.2. Duration of the quasi-stable state To calculate duration T1 of the quasi-stable state, it should be noted that this duration corresponds to the time the capacitor takes to charge itself with a voltage value equal to 0.6v (≅ 0 volt), starting from an initial voltage equal to: VB2(0) = –Vcc + 0.6v (≅ –Vcc).

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The equation that characterizes the charge of the capacitor C through resistance R is generally defined using the following equation: −t

VB2 = A.e RC + B Constants “A” and “B” will be determined using boundary conditions. Furthermore, it can be written that: For t = 0; VB2 = A + B = –Vcc When t → ∞; VB2 = B = Vcc  A = –2Vcc Under these conditions, the equation that governs the variations of the capacitor charge voltage becomes: −t

VB2 = Vcc (1 − 2.e RC ) At time t = T1, the voltage at the terminals of the capacitor is practically zero. We then have: −T1

VB2 (t = T1 ) = Vcc (1 − 2.e RC ) ≅ 0 From which it can be deduced that: T1 = RC.Ln(2) T1 ≅ 0.69.RC 1.2.2. Operational amplifier monostable flip-flop 1.2.2.1. Principle and operation The structure of the op-amp monostable circuit is schematized in Figure 1.7.

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Figure 1.7. Op-amp monostable circuit

Initially, no voltage is injected on input. The reference voltage Vref is positive. The inverting input of the op-amp is at potential: v e− =

R4 Vref R3 + R4

The op-amp is assembled as a threshold comparator. Since the voltage at the non-inverting terminal is a priori equal to zero, the output of the operational amplifier is in a low saturation state: vs = –Vsat At rest, the output voltage is zero, and it suddenly shifts to the value –Vsat when powering on. Capacitor C transmits this variation to the cathode of diode D. The latter becomes forward-biased and starts conducting. The potential of point “A” is equal to the threshold voltage of the diode: vA ≅ –0.6 V

vB =

R2 VA R1 + R 2

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The value of the voltage vB is close to zero. When a sufficiently negative impulse (ve) is sent to the inverting input, the potential applied to this input will be lower than that applied to the non-inverting input. The output of the operational amplifier will shift to a high saturation state: vs = +Vsat The output voltage abruptly varies from –Vsat to +Vsat. This variation is transferred to the cathode of diode D through condenser C. The diode is in a blocked state. Under these conditions, the equivalent diagram of the op-amp monostable flip-flop is presented in Figure 1.8.

Figure 1.8. Equivalent diagram of the op-amp monostable where diode D is blocking

Capacitor C will start to charge through resistors R1 and R2. Before the negative pulse reaches the inverted input, capacitor C is fully discharged. The voltage variation law at point A can be defined using the relation: v A = Ee

−t (R 1 + R 2 )C

+F

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“E” and “F” are two constants that will be determined using boundary conditions. For this purpose, we have: For t = 0; vA = 2Vsat = (E + F). When t → ∞; vA = F = 0 (the capacitor is fully charged, and the current no longer circulates through resistors R1 and R2): E = 2Vsat −t

v A = 2Vsat .e (R 1 + R 2 )C

The output will keep a high state until the potential (Ve-) of the inverted input will be greater than that of the non-inverted input (vB): −t

R2 vB = 2 Vsat .e ( R1+R 2 )C R 2 + R1 The switching will occur at the time when: vB ≤

R4 Vref R3 + R4

1.2.2.2. Duration of the quasi-stable state The duration of the quasi-stable state of the monostable flip-flop is the time that the voltage vB takes to change from an initial voltage equal to: vB =

2R 2 Vsat R1 + R 2

to a final voltage: vB =

R4 Vref R3 + R 4

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We know that: vB (t = 0) =

2R 2 Vsat ; R1 + R 2

v B ( t = T1 ) =

R4 Vref R3 + R4

Similarly: − T1

R2 v B ( t = T1 ) = 2 Vsat .e ( R1+R 2 )C R 2 + R1 The general expression of the duration T1 is:

 2V R ( R + R 4 )  T1 = (R 1 + R 2 )C.Ln  sat 2 3   Vref .R 4 (R 1 + R 2 )  In the case where we choose: VSAT = VCC (rail-to-rail op-amp) The op-amp voltage drop is zero. We also choose: Vref = Vcc, We will then have the following expression for the duration of the quasi-stable state of the op-amp monostable:  2R ( R + R 4 )  T1 = (R1 + R 2 )C.Ln  2 3   R 4 (R1 + R 2 )  The evolutions of the different signals at the op-amp monostable level are schematized in Figure 1.9

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Figure 1.9. Evolution of the different signals at the level of the op-amp monostable: (a) triggering signal; (b) output signal; (c) signal at point A; (d) signal at point B. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

1.2.3. Logic gate monostable flip-flop 1.2.3.1. Principle and operation

An example of the logic gate monostable is schematized by the circuit shown in Figure 1.10. The gates used in this case are “NAND” gates. It is also possible to use another kind of gate. The technology for implementing the gates is irrelevant. For the case concerning the use of TTL gates, constant voltage generators (+Vcc) can be omitted due to the fact that in this technology, a disconnected terminal is at a potential equal to 5 volts (supply voltage of the gates).

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Figure 1.10. Logic gate monostable

The functioning of this circuit can be established as follows: – in the absence of any triggering signal on input, point “A” is at a potential equal to vA = 0. The state of the output of gate 2 is high: vF = Vcc; Vcc is the supply voltage. The output of the monostable circuit is low: vs = 0. The output of gate 1 is low: vB = 0; – when a sufficiently negative trigger pulse arrives at input “D” of the first gate, the state of its output changes and the potential shifts from a value equal to zero to a value equal to +Vcc. Capacitor C instantly transmits this change to point “A” and then begins to charge through resistance R. The output of the second gate shifts to the low level: vF = 0 and the output is high: vs = VCC. The potential will then tend to decline following an exponential law until it becomes lower than the switching threshold of the “NAND” gate. At that moment, point “F” will be at potential +VCC, and the output will be low. The circuit will maintain this state until a new negative trigger pulse arrives. Signals that summarize the operation of the “NAND” logic gate monostable are schematized in Figure 1.11.

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Figure 1.11. Signal evolution at the logic gate monostable level

1.2.3.2. Duration of the quasi-stable state

To calculate the duration of the quasi-stable state, it is assumed that the trigger voltage of a gate is equal to V0. From the graph shown in Figure 1.11, it can be seen that duration T1 of the quasi-stable state is the time that the voltage at point “A” takes to move from an initial voltage equal to +Vcc to a final value equal to the threshold voltage V0. The variation law of the potential of point “A” is given by: −t

v A = A1e RC + B1

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“A1” and “B1” are two constants that will be determined using boundary conditions At t = 0; vA = VCC = A1+B1; When t → ∞; vA = 0 = B1  A1 = VCC v A = Vcc

−t RC .e

At time t = T1 (duration of the quasi-stable state), the voltage value is equal to the switching threshold V0 of the gate: − T1

v A ( t = T1 ) = Vcc .e RC = V0

From which: V  T1 = RC.Ln  cc   V0  When the switching threshold is equal to (VCC/2), for example, the duration of the quasi-stable state is defined by: T1 = RC.Ln ( 2)

1.2.3.3. “NOR” gate monostable

This type of circuit (Figure 1.12) can be triggered by a positive pulse. The study of this device is similar to what has preceded.

Figure 1.12. NOR gate monostable

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Signals implemented at the “NON OR” monostable level are schematized in Figure 1.13. The switching threshold is equal to (VCC/3).

Figure 1.13. Signals implemented in a NOR gate monostable. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

1.2.4. Timer monostable flip-flop: 555 integrated circuit 1.2.4.1. Principle and operation

The 555 integrated circuit (IC) allows the design of monostable devices, making use of few external components, as shown in Figure 1.14.

Figure 1.14. 555 integrated circuit monostable

Input 2 of the 555 circuit is positively polarized through resistance R1 (virtually all the supply voltage appears at this terminal). At rest, the output potential is zero.

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The charge of capacitor C is maintained equal to zero due to the internal discharge transistor of the 555 circuit. When a sufficiently negative triggering pulse ve is applied to the “threshold” input 2 of the 555 IC, the output state changes, and the magnitude of its potential will be of the order of the supply voltage: vs ≅ VCC The terminal (7) of the 555 IC will be in open position, and capacitor C will start to charge through resistor R2. When the voltage “vC” at the terminals of the capacitor reaches and slightly exceeds the value (2/3 VCC), the output toggles from a high state to a low state: vc ≥

2 Vcc ; vs = 0 3

The internal discharge transistor of the 555 IC will become saturated and bring pin 7 to ground potential. This will result in the capacitor discharging instantly and keeping a potential of zero at its terminals until the next trigger pulse. The signal variations existing at the 555 IC monostable circuit level are schematized in Figure 1.15.

Figure 1.15. Signals at the 555 monostable level

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1.2.4.2. Duration of the quasi-stable state

The time T1 of the quasi-stable state is the time that the capacitor C takes to charge through R2 from an initial value of zero to a final value equal to (2/3)Vcc. The equation that defines the capacitor charge is given by: −t

v c = Vcc (1 − e R 2 C )

At time t = T1, vc = (2/3)VCC − T1

v c ( t = T1 ) = Vcc (1 − e R 2 C ) =

2 Vcc 3

Finally, we obtain the expression of the duration of the quasi-stable state: T1 = R2CLn(3) 1.3. Bistable circuits 1.3.1. Transistor bistable

A transistor bistable has the same structure as a transistor astable except that the capacitors that connect the bases to the collectors of the transistors are replaced by resistances (see Figure 1.16).

Figure 1.16. Bipolar transistor bistable

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The operating principle of a bistable circuit is based on the fact that if one of the transistors (e.g. Tr1) is blocked, the other (Tr2) is necessarily saturated. The difference between a bistable and an astable circuit is that the triggering or shifting from a blocked state to a saturated state and, conversely, of one of the transistors, is no longer achieved by the cumulative charge of capacitors. Therefore, in the bistable case, when it is desirable to shift from one state to another for each one of the transistors, this requires the use of external impulses. The operation of the bistable circuit shown in Figure 1.16 can be established as follows. At the initial moment, it is assumed that one of the transistors (e.g. Tr1) is conducting and the other (Tr2) is blocking. Under these conditions, it can be written that: VC1 = VCE1 ≅ 0



VC2 = VCE2 ≅ VCC 

IC1 is maximum IC2 ≅ 0

The voltage applied to the base of transistor Tr2 is expressed by: VB 2 =

R B2 VC1 ≅ 0 R B2 + R 1

This properly verifies that transistor Tr2 is blocking. The voltage applied to the base of the transistor Tr1 is expressed by: VB1 =

R B1 VC 2 R B1 + R 2

VB1 ≅

R B1 Vcc R B1 + R 2

This thus verifies the conducting state of transistor Tr1. When a negative pulse of sufficiently high amplitude is applied at the base of the transistor (Tr1), this will enable its blocking. It should be noted that before the arrival of this negative pulse, voltage VB1 was positive. When the negative pulse arrives, voltage VB1 becomes negative and Tr1 becomes blocking. The latter will cause the saturation of transistor Tr2.

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In fact, when blocking, transistor Tr1 will transmit from its collector a positive voltage change to the base of Tr2. VC1 shifts from 0 to +VCC VB 2 =

R B2 VC1 R B2 + R 1

VB 2

R B2 Vcc R B2 + R1

≅

The two transistors will maintain this state until the application of a new negative pulse of sufficient amplitude to the collector of Tr1 (or on the base of transistor Tr2). Under these conditions, we will have the blocking of transistor Tr2 and the saturation of Tr1. Indeed, the base of transistor Tr2 was at potential approximately 0.6 volts; the application of a negative pulse at its base will make voltage VB2 negative and therefore allow Tr2 to block. The collector voltage of the latter will change from a value of zero to +VCC. The voltage +VCC is partly transmitted to the base of transistor Tr1. This will ensure its saturation (VB1 > 0). The functioning of this bistable circuit is summarized by the evolution of the different signals shown in Figure 1.17. The output is taken from the collector of transistor Tr1.

Figure 1.17. Evolution of the different signals at the transistor bistable level

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NOTE.– The bistable flip-flop has a memory effect. The flip-flop remembers the previous state at any time. This is a sequential-type circuit. 1.3.2. Improved bipolar transistor bistable

To achieve a bipolar transistor bistable whose performance is improved compared to the one which has been studied, the circuit schematized in Figure 1.18 is used.

Figure 1.18. Improved bipolar transistor bistable circuit

The diodes D1 and D2 make it possible to isolate the bistable circuit of the triggering circuit in the absence of command impulses. The capacitors C1 and C2 ensure faster switching. Furthermore, a capacitor has the ability to instantly transmit any fast transition. With regard to this transition, the capacitor behaves like a short circuit. The implementation of capacitors C1 and C2 will allow triggering even with positive impulses, ensuring their derivation. As a result, a succession of positive and negative pulses will be obtained when applying a sequence of positive impulses for the control.

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1.3.3. Practical example of transistor bistable: the “SR” flip-flop A practical example of a bistable SR flip-flop achieved using bipolar transistors is schematized in Figure 1.19.

Figure 1.19. Bipolar transistor “SR” bistable

To explain the operation of this circuit, it is assumed that initially, we have: vS1 = 0 and vS2 = VCC. At the various positions of switches E1 and E2, the status of the outputs vS1 and vS2 is summarized in Table 1.1. E1 open

E2 open

vS1 0

open

closed

closed

open

Vcc 0

closed

closed

0 or Vcc (indeterminate)

vS2 Vcc 0 Vcc Vcc or 0 (indeterminate)

Table 1.1. Operating states of the transistor “SR” bistable flip-flop

We now establish the following equalities: E1 = R; E2 = S; vS1 = Q; vS2 = Q . Open = 0 and closed = 1

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We finally obtain the truth table (see Table 1.2) relating to the operation of an “SR” flip-flop. R

S

Q

Q

0

0

Q=0

1

0

1

1

0

1

0

0

1

1

1

φ

φ

Table 1.2. Truth table of an “SR” flip-flop

The initial state is chosen to be equivalent at a low state. φ: indeterminate state. 1.3.4. “SR” flip-flop and logic gate derivatives “NAND”-type logic gates can be used (Figure 1.20) to implement “SR” bistable flip-flops.

Figure 1.20. NAND gate “SR” flip-flop

We can also achieve “SR” flip-flops based on “NOR” gates, as shown in Figure 1.21.

Figure 1.21. NOR gate “SR” flip-flops

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From an “SR” flip-flop, it is also possible to implement in a very simple way a “D”-type bistable flip-flop, by placing an inverter between inputs “S” and “R”. The input of the D flip-flop is taken at “S” (Figure 1.22).

Figure 1.22. “NOR” gate D flip-flop

The truth table relating to the “D” flip-flop is presented in Table 1.3. S (D)

Qn

Qn+1

0

0

0

1

0

1

0

1

0

1

1

1

Table 1.3. Truth table of the D flip-flop

1.3.5. Integrated circuit “JK” bistable flip-flop 1.3.5.1. Examples of “JK” bistable integrated circuits

Bistable flip-flops are now fully integrated. Examples of integrated circuits that contain “JK” flip-flops include, among others, “CMOS” circuits of the “4000” family: the “CD 4095” and the “CD 4096”. Each of these integrated circuits is encapsulated in a 14-pin “DIL” case, as shown in Figure 1.23.

Figure 1.23. Bistable circuits: “CD 4095” and “CD 4096”

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We will particularly look into the CD 4095 integrated circuit whose simplified internal diagram is presented in Figure 1.24. The inputs J and K are served by two “AND” gates. One has three J inputs (J1, J2, J3) and the other has three K inputs (K1, K2, K3). SET and RESET inputs enable the operation of the bistable in synchronous or asynchronous mode.

Figure 1.24. Simplified internal diagram of the “CD 4095” bistable integrated circuit

The truth table of this JK bistable flip-flop in synchronous mode is given in Table 1.4. Synchronous operations

SET = 0; RESET = 0

Inputs J and K

Outputs Q and Q (following the rising clock edge)

J

K

Q

Q

0

0

Q

Q

0

1

0

1

1

0

1

0

1

1

Q

Q

Table 1.4. Truth table of the JK bistable flip-flop in synchronous mode

1.3.5.2. Example of the use of the 4095 circuit

Figure 1.25a shows the CD 4095 integrated circuit assembled as a synchronous bistable flip-flop of the type “T flip-flop”. The change in the output state of the

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flip-flop occurs when there is a pulse “clock” rising edge (see the chronogram in Figure 1.25b). It should be noted that the frequency of the output signal (output Q or complementary output Q) is halved with respect to the frequency of the clock signal. The division of the frequency of a signal using flip-flops is a very common application.

Figure 1.25. The 4095 assembled in the T flip-flop (a); chronogram of the functioning of the T flip-flops (b)

1.4. The Schmitt flip-flop 1.4.1. Principle of the Schmitt flip-flop

The Schmitt flip-flop is used in several electronic functions. The most important include: – shaping a square wave (fast rising and descending edges) previously distorted by circuits downstream the Schmitt trigger or masked by noise; – transforming analog signals into almost perfect square form signals; – triggering a circuit when a certain threshold established a priori is crossed. The flip-flop or Schmitt “trigger” is in fact a circuit for comparing signals, which has a hysteresis cycle (two comparison thresholds). It can also be called the threshold flip-flop. The Schmitt trigger is a bistable circuit (two stable states) that internally makes use of a positive reaction. Switching thresholds may be symmetrical or asymmetrical. This depends on the organization of the circuit and its application. One of the interesting applications of the Schmitt trigger is, for example, reshaping a digital signal affected by noise (Figure 1.26).

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Figure 1.26. Application example of the Schmitt trigger: reshaping of a square wave. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

1.4.2. Operation of a Schmitt trigger

When, for example, a sinusoidal signal is applied to the input of a Schmitt flipflop (Figure 1.27), this signal will go through two values of voltages that represent the thresholds specific to the flip-flop. The output signal will assume two states, “a high state and a low state”, that will obviously depend on the switching thresholds e1 and e2 of the Schmitt trigger.

Figure 1.27. Operating principle of the Schmitt trigger

The representation of the transfer function [vs = f(ve)] of the Schmitt trigger shows the existence of a hysteresis cycle (Figure 1.28) limited on the abscissa by the two trigger thresholds and on the ordinate by the high state and low state levels.

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Figure 1.28. Hysteresis cycle of a Schmitt trigger

1.4.3. Transistor Schmitt trigger 1.4.3.1. Schematic diagram

The diagram of a transistor Schmitt trigger is presented in Figure 1.29.

Figure 1.29. Bipolar transistor Schmitt trigger

1.4.3.2. Operation

This type of circuit presents a rather more educational interest for the understanding of circuits and phenomena that govern the operation of a Schmitt trigger.

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There is only little practical interest in it because of the integration of most electronic functions. However, theoretically mastering this type of circuit will allow for easier understanding of the phenomena taking place in integrated Schmitt triggers. We will proceed by steps. Step 1

In the idle state (no signal is applied on the trigger input), transistor Tr1 is blocked. When the base current (IB2) of transistor Tr2 is neglected compared to the one that flows through resistance RA, it can then be written that: VB2 = VRA =

RA Vcc R C1 + R B2 + R A

Voltage VB2 is positive. Resistances RC1, RB2 and RA are chosen such that the transistor Tr2 can be conducting. To this end, we have: VCE2 ≅ 0 VE1 = VE2 ≅ VB2 - 0.6 VE1 = VE2 ≅ VRA - 0.6 To make the transistor Tr1 conducting, it is necessary to increase the value of the input voltage ve starting from the value of zero until the necessary trigger voltage is reached. This trigger voltage should have the value: VB1 = VE1 + 0.6 Hence, the high trigger threshold e2 should have the value: VB1 = VE1 + 0.6 = VE2 + 0.6 =VRA e 2 = VB1 = VRA =

RA Vcc R C1 + R B2 + R A

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Step 2

When the voltage ve becomes slightly greater: e2 =

RA Vcc R C1 + R B2 + R A

Thus, transistor Tr1 becomes conductive. As a result, we will have a significant flow of current through resistance RC1. This current will cause to drop the voltage VC1 (voltage at the collector level of transistor Tr1) and thus the voltage at the terminals of the resistance RA: VRA =

RA VC1 R A + R B2

The decrease in VRA causes the decrease in voltage at the levels of each of the emitters of the two transistors (i.e. with the intention of keeping the operation of transistor Tr2 normally). When the emitter voltage of transistor Tr1 decreases, the conducting state of the latter is reinforced. When the conduction state of transistor Tr1 increases, the current through resistance RC1 also increases, and the voltage at the terminals of resistance RA decreases. This reinforces the blocking state of Tr2 and the saturation state of Tr1: vs = Vcc This level linked to the output voltage will be maintained as long as the input voltage does not fall below the low trigger threshold. Step 3

The input voltage will start decreasing at a certain level. When it reaches a threshold and becomes slightly smaller than e1 (low threshold), transistor Tr1 tends to block and transistor Tr2 becomes saturated: e1 = ? vs = ?

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The idea is to find the value of the low threshold and also the value of the output voltage: ve = e1 = VB1 = VE1 +0.6 VB2 = VRA = VE2 + 0.6 = VE1 +0.6 This is tantamount to finding voltage VRA that will make transistor Tr2 conduct and bring it to saturation. It is known that the voltage applied on input is decreasing. Current through resistance RC1 also tends to decrease; the tension at the level of the collector (VC1) will increase for voltage VB2 until there is switching. Voltage vs changes from high saturation estimated to be VCC to a low state that will be calculated. When switching occurs (voltage ve is slightly smaller than or equal to the switching voltage e1), it can be written that: VC1 = i1(RB2 + RA) ve = e1 = VRA =RAi1 i1 =

ve RA

The current through resistance RC1 is defined by the following relation:

i R C1 = i1 + i R E i R C1 =

v e v e − 0,6 + RA RE

We also have: Vcc = VC1 + RC1.iRC1 Vcc =

ve v v − 0,6 (R B2 + R A ) + R C1 ( e + e ) RA RA RE

Vcc = v e (

R B 2 + R A R C1 R C1 0,6R C1 + + )− RA RA RE RE

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31

From which the low threshold: R C1 RE R C1 R C1 + + RA RE

Vcc + 0,6 e1 = v e =

R B2 + R A RA

It now remains for us to establish the expression of the output voltage. To this end, it should be noted that: ve > e2; the output is in high state; the transistor Tr2 is blocking: vs = Vcc When we have: ve < e1; the output is at low state; transistor Tr2 is saturated. vs = VC2 = Vcc - RC2.iRC2 v s = Vcc − R C 2

VRE RE

1.4.3.3. Practical test of the transistor Schmitt trigger

The circuit under test is schematized in Figure 1.30.

Figure 1.30. Tested bipolar transistor Schmitt trigger

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The calculations give the following values for high and low thresholds as well as for the amplitude of high and low output signal levels: High threshold: e2 = 3.75V High level of the output: vs = VH = +VCC = 10V Low threshold: e1 = 2.9V Low level of the output: vs = VL = 6,9V The representation of the evolution of the output signal of the bipolar transistor Schmitt trigger when a triangular signal is applied on input is given in Figure 1.31. It is clear that the values of the high threshold e2 and the low threshold e1 are consistent with the established calculation. The same occurs for the extreme values of the output voltage.

Figure 1.31. Variation of the output signal corresponding with the signal applied to the input of the bipolar transistor Schmitt trigger. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

1.4.4. Operational amplifier Schmitt trigger 1.4.4.1. Inverting Schmitt trigger

A Schmitt trigger can be implemented in a very simple way using an op-amp (Figure 1.32).

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33

Figure 1.32. Op-amp inverting Schmitt trigger

In an op-amp inverting Schmitt trigger, the attack is carried out on the inverting input. The operating principle of this circuit is established according to the following steps. Step 1

It is initially assumed that the circuit is in the quiescent state, and therefore there is no current flowing through resistor R2. When the input voltage ve is positive, the output is in the low saturation state. Under these conditions, it can be written that: vs = –Vsat The voltage applied to the non-inverting input is expressed by: Ve + = −

R2 Vsat = V1 R1 + R 2

Step 2

When the voltage ve becomes smaller than the voltage V1 applied at the non-inverting input, the output will switch to the high state: vs = +Vsat. The voltage applied to the non-inverting input is expressed by: Ve + =

R2 Vsat = V2 R1 + R 2

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Nonlinear Electronics 2

Step 3

When the input voltage ve exceeds the value V2, the output will switch back to the low state, and we have: vs = –Vsat Ve + = −

R2 Vsat = V1 R1 + R 2

The two switching thresholds of the Schmitt trigger can thus be easily recognized, represented by values V1 (low threshold) and V2 (high threshold). To illustrate the operation of the Schmitt trigger, we assume that a sinusoidal signal of 2 volts of amplitude is applied on input. Resistances R2 and R1 have values 1 KΩ and 10 KΩ respectively. Symmetrical supply voltages are ± VCC = ± 9 volts. The changes in the output signal corresponding to the signal applied on the inputs of the Schmitt trigger are shown in Figure 1.33. The tests were carried out with a “rail-to-rail” op-amp (Vsat = VCC).

Figure 1.33. Evolution of the output signal vS compared to the signal ve applied to the input of an op-amp Schmitt trigger. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

The values of high and low switching thresholds are given by: High threshold: V2 ≅ 0.9V. Low threshold: V1 ≅ –0.9V.

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35

The transfer function (or hysteresis cycle) of this inverting op-amp Schmitt trigger is presented in Figure 1.34.

Figure 1.34. Hysteresis cycle of the op-amp inverting Schmitt trigger

1.4.4.2. Non-inverting trigger

In a non-inverting Schmitt trigger (Figure 1.35), the input signal is injected to the non-inverting input.

Figure 1.35. Op-amp non-inverting Schmitt trigger

The inverting input can be connected to ground or a reference voltage, such as a mechanism for manipulating the switching thresholds of the Schmitt trigger outside the resistors R1 and R2. For the study of the circuit shown in Figure 1.35, it can be noted that this is a positive reaction. We will assume that the voltage ve is initially positive. It is obviously possible to consider a negative input voltage.

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Nonlinear Electronics 2

This assumption is only made for educational purposes for the understanding of the operation of the assembly being studied: ve > 0 vS = +Vsat The expression that defines the voltage applied at the non-inverting input level is given by: Ve + =

R 1vS + R 2 v e R 1Vsat + R 2 v e = R1 + R 2 R1 + R 2

This voltage is positive, which reinforces the assumption that was made at the outset. The definition expression of the input voltage according to the output voltage and the voltage that is found at the non-inverting input level is given by: ve =

− R1Vsat + (R1 + R 2 )Ve+ R2

As long as voltage Ve+ remains positive, the output voltage remains in the high saturation state. As soon as the voltage Ve+ becomes negative, the output voltage shifts to the low saturation state. The evolution of Ve+ is related to voltage ve applied on input: Ve+ > 0



R1Vsat + R 2 ve >0 R1 + R 2

As a result, for the voltage applied on input, we get: ve > −

R1Vsat = V1 R2

Therefore, for the high saturation state to be present on output, it would be necessary that the voltage ve applied on input be greater than voltage V1. Voltage V1 is the switching threshold from the high state to the low state.

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37

It is known that the voltage ve applied on input is a variable voltage. The switch from the high state to the low state occurs when the voltage Ve+ becomes negative: Ve+ < 0 vS = –Vsat Ve+ =

− R 1Vsat + R 2 v e R1 + R 2

Ve+ < 0



−R 1Vsat + R 2 v e <0 R1 + R 2

The expression that will allow the switching threshold to be deduced is obtained as follows: ve <

R 1Vsat = V2 R2

V2 is the output switching threshold from the low state to the high state. The signals involved at the Schmitt trigger level are schematized in Figure 1.36. These signals were obtained experimentally, and the values of the components used for this purpose are R1 = 2 KΩ; R2 = 10KΩ. This will yield the two switching points:

V1 =

−Vsat V ; V2 = sat 5 5

The representation of the evolution of the output voltage according to the input voltage (see Figure 1.37) makes it possible to give the range of the hysteresis loop of the non-inverting Schmitt trigger. The representation of vS = f(ve) allows an interesting amount of information to be deduced. The Schmitt trigger possesses two switching points. These two threshold values provide indications about the width of the hysteresis loop. If the amplitude of the input voltage is below switching thresholds, the trigger will not operate as expected and the output voltage will be frozen to a constant value equal to about the saturation voltage Vsat.

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Nonlinear Electronics 2

Figure 1.36. Signals involved at the non-inverting Schmitt trigger level. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

The evolution of the output voltage according to the input voltage (see Figure 1.37) makes it possible to give a representation of the hysteresis cycle of the non-inverting Schmitt trigger.

Figure 1.37. Representation of the evolution of the output voltage vS according to the voltage ve applied on input

The non-inverting Schmitt trigger has two symmetrical switching thresholds, a high threshold (V2) and a low threshold (V1): V1 =

−R1Vsat R2

V2 =

R1Vsat : R2

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39

NOTE.– In most cases, op-amps present a dropout voltage. This explains why the high or low saturation voltage does not have an amplitude equal to the supply voltage. The saturation voltage is generally less than the supply voltage. However, there are some operational amplifiers that do no present any dropout voltage or possess a negligible dropout voltage; these are “Rail-to-Rail” op-amps. Switching thresholds are determined by the values of the high and low saturation voltages of the operational amplifiers as well as the values of the resistors that ensure the positive reaction. It is of paramount importance to ensure that the signal applied on input to be shaped has sufficient amplitude so that there is a switch on output from the high level to the low level and vice versa. Otherwise, the Schmitt trigger will not be able to perform the function for which it was designed. 1.4.4.3. Inverting trigger with variable threshold

In order to adjust switching thresholds, we can, for example, make use of the circuit shown in Figure 1.38. The reference voltage (Vref) can be adjusted in order to adjust switching thresholds.

Figure 1.38. Inverting Schmitt trigger with variable thresholds

The voltage applied on the inverting input can be variable in the sense of varying the threshold values. The voltage applied to the non-inverting input is expressed using the relation: VA = Ve+ =

v S .R 1 + Vref .R 2 R1 + R 2

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Nonlinear Electronics 2

The output will depend on the position or the value of the voltage Ve+ compared to the value of the voltage Ve-. When Ve+ is greater than Ve-, the output is in high saturation Ve+ > Vevs = +Vsat Ve- = ve Ve+ =

ve <

vS .R 1 + Vref .R 2 > ve R1 + R 2

Vsat .R 1 + Vref .R 2 R1 + R 2

This relation allows us to define the high switching threshold as being V2, with: Vsat .R 1 + Vref .R 2 R1 + R 2

V2 =

When the high threshold (V2) is exceeded by ve by higher values, the output will switch from the high to the low state (Figure 1.38). The same process will be used to find the low switching threshold. When the output voltage is in low saturation, the voltage applied to the inverting input is higher than the voltage applied to the non-inverting input: Ve+ < Vevs = -Vsat Ve+ =

vS .R 1 + Vref .R 2 < ve R1 + R 2

It can then be deduced that: ve >

− Vsat .R 1 + Vref .R 2 R1 + R 2

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41

The low threshold V1 can now be defined as: V1 =

−Vsat .R 1 + Vref .R 2 R1 + R 2

When the voltage ve is lower than the switching threshold V1, the output will switch from the low to the high state. To trace the signal variations related to the operation of the Schmitt trigger with varying thresholds, the following data have been set: R1 = R2 = 20 KΩ; VCC = 12V (dropout voltage = 2V), Vref = -2V. For the high (V2) and low (V1) thresholds, we respectively find: V2 =

Vsat .R 1 + Vref .R 2 10 − 2 = = 4V R1 + R 2 2

V1 =

− Vsat .R 1 + Vref .R 2 −10 − 2 = = −6V R1 + R 2 2

Voltage Ve+ is directly related to the output voltage vs. It will have the same shape as the latter (see Figure 1.39).

Figure 1.39. Signals involved in a Schmitt trigger with adjustable thresholds. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

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Nonlinear Electronics 2

To study the variation of the switching thresholds and the different characteristics of the Schmitt trigger with variable thresholds, it proves interesting to trace the evolution of these thresholds based on the reference voltage (see Figure 1.40).

Figure 1.40. Evolution of switching thresholds based on the reference voltage Vref. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

NOTE.– The difference between the two high and low thresholds, respectively V2 and V1, is constant and equals to: ΔV = V2 − V1 =

2VCC .R1 R1 + R 2

When we have R1 = R2 ΔV = VCC When the reference voltage is zero, we again find the thresholds that have been previously calculated for the inverting Schmitt trigger (section 1.4.4.1): V1 = −

R2 Vcc R1 + R 2

and

V2 =

R2 Vcc R1 + R 2

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43

1.4.5. The 555 Schmitt trigger

It is also possible to implement Schmitt triggers from the 555 integrated circuit previously described. An example is presented in Figure 1.41.

Figure 1.41. 555 IC Schmitt trigger

The operation of this trigger refers to the internal schema of the 555 integrated circuit (or timer). It can be established as follows. When the voltage ve applied on input is positive but nevertheless remains lower than the value (2/3)VCC, the output of the trigger is in a high state. As soon as the voltage ve slightly exceeds this threshold voltage that is (2/3)VCC, the output of the Schmitt trigger changes to the low state. When the voltage ve decreases from a value above the threshold (2/3)VCC, the output voltage will keep its low state to the point where ve reaches and becomes slightly lower than the other switching voltage (1/3)VCC specific to the 555 circuit. To test the operation of the 555 timer-based Schmitt trigger, it is assumed that a unilateral triangular signal of amplitude equal to 8 volts is applied on input. The supply voltage VCC of the 555 circuit chosen is equal to 9 volts. The evolution of the output signal and that of the input signal are presented in Figure 1.42.

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Figure 1.42. Evolution of the output signal according to the signal applied to the input of a Schmitt trigger designed around the 555 circuit. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

Figure 1.43 shows the hysteresis cycle relative to the Schmitt trigger designed around the timer 555.

Figure 1.43. Hysteresis cycle of the Schmitt trigger based on the 555 circuit

The high and low thresholds of the Schmitt trigger based on a timer (555 integrated circuit) are established by the supply voltage and the internal structure of

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45

the integrated circuit under consideration. For the case under study (VCC = 9 volts), the high and low thresholds are given by: High threshold: V2 = (2/3)Vcc = 6 volts Low threshold: V1 = (1/3)Vcc = 3 volts 1.4.6. Schmitt trigger based on logic integrated circuits

Two examples of digital integrated circuits will be addressed: the most widely known and most used to implement Schmitt triggers. One is implemented in TTL (Transistor–Transistor Logic) technology and the other is realized in CMOS (Complementary Metal Oxide Semiconductor) technology. There are of course a multitude of integrated circuits which are able to perform the function of a Schmitt trigger. 1.4.6.1. Schmitt trigger based on TTL logic integrated circuits

The TTL integrated logic IC that is intended to implement the function of a Schmitt trigger is the 7414 circuit. The 7414 IC is a 14-pin “DIL” (Dual In-Line) case. It consists of six inverting gates operating as a Schmitt trigger, as shown in Figure 1.44. Each Schmitt trigger has an input and an output. The power supply is connected to pin 14 and ground to pin 7 of the integrated circuit.

Figure 1.44. Structure of the 7414 IC

One of the inverting gates (e.g. the first gate) of this circuit can be used to operate as a Schmitt trigger.

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Nonlinear Electronics 2

This simply requires that the circuit shown in Figure 1.45 be implemented and performing its subsequent testing. It is obviously necessary to supply power to the circuit. (1) ve

(2) vS

Figure 1.45. Schmitt trigger using one of the gates of the 7414 IC

The testing of this circuit by injecting a unilateral triangular signal enables the tracing of the evolution of the output signal, as schematized in Figure 1.46. The circuit is powered by a voltage equal to VCC = 5 volts.

Figure 1.46. Evolution of the output signal according to the signal applied to the input Schmitt trigger based on the 7414 IC. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

The analysis of Figure 1.45 enables us to infer the two switching thresholds: the high and the low thresholds. It can indeed be observed that there exists a high threshold V2 (the output voltage shifts from the high state to the low state) and a low threshold V1 (the output voltage shifts from the low state to the high state). These two thresholds are respectively: V2 = 1.6V V1= 0.8V

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47

These two values are consistent with the data of the manufacturer. Based on the evolution of the output voltage according to the signal applied to the input, the hysteresis cycle (see Figure 1.47) of this type of Schmitt trigger can be deduced.

Figure 1.47. Hysteresis cycle of the Schmitt trigger based on the 7414 circuit. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

1.4.6.2. Schmitt trigger with CMOS logic integrated circuits

The CMOS logic circuit presented is the 4093 circuit. This is a DIL case with two rows of seven pins each. It includes four NAND Schmitt trigger circuits (see Figure 1.48).

Figure 1.48. Structure of the CMOS 4093 logic circuit

Each Schmitt trigger circuit works independently. To illustrate the operation of one of the Schmitt triggers of the 4093 circuit, we use the circuit that is schematized in Figure 1.49.

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Nonlinear Electronics 2

Figure 1.49. Schmitt trigger based on the 4093 integrated circuit (1/4)

The switching points are denoted by V1 (low threshold) and V2 (high threshold). The difference between the values of the thresholds V2 and V1 defines the width of the hysteresis loop VH (Figure 1.50) of the Schmitt trigger.

Figure 1.50. Hysteresis cycle of the built-in Schmitt trigger of the 4093 circuit. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

The supply voltage of the CMOS 4093 circuit can vary from 3 volts up to about 18 volts. It is applied to pin 14. The common ground of the four built-in Schmitt triggers connects to pin 7 of the 4093 integrated circuit. The values of these trigger points will depend on the supply voltage applied to pin 14 of the 4093 IC, as shown in Figure 1.51. For example, when the supply voltage is equal to VDD = 5 volts, the switching points are approximately equal to: V2 = 2.7V; V1 = 1.8V

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49

Figure 1.51. Evolution of the switching thresholds with the supply voltage (source: datasheet Texas Instruments). For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

The width of the hysteresis loop is equal to ΔV = V2 –V1 = VH = 0.9V When the supply voltage VDD = 10V, it can be seen that the values of the switching thresholds change: V2 = 6.1V; V1 = 3.7V The width of the hysteresis loop is equal to ΔV = V2 –V1 = VH = 2.3V 1.5. Exercises on flip-flops EXERCISE 1

The circuit under study is presented in Figure E1.1(a). Input and output signals are shown in Figure E1.1(b).

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Figure E1.1. (a) Monostable circuit and (b) signals involved. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

1) Give the duration of the trigger pulse and the duration of the quasi-stable state. 2) Is this a retriggerable or non-retriggerable monostable? Justify the answer. SOLUTIONS TO EXERCISE 1

1) Duration of the trigger pulse and duration of the quasi-stable state: – the duration of the trigger pulse is τ1; – the duration of the quasi-stable state is T1. 2) Nature of the monostable: It cannot be said whether the monostable is retriggerable or non-retriggerable, because the trigger pulse does not arrive during the quasi-stable state to see the reaction of the monostable. EXERCISE 2

Given the circuit of Figure E2.1(a) composed of NAND gates.

(a)

(b)

Figure E2.1. (a) Circuit under study and (b) pulse applied on input. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

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51

It is assumed that initially, voltage = VCC. 1) Give the expressions of vA, vB and vS and their value when the NAND gates used are in TTL technology. 2) A pulse is applied on the input as schematized in Figure E2.1(b). Explain the operation of the circuit. Give the expressions of voltages vA, vB and vS during the quasi-stable state and the steady state. 3) Give the representations based on the time of voltages vA, vB and vS. What is the function provided by this circuit? 4) Give the expression of the duration of the quasi-steady state, knowing that the switching threshold of the gates is equal to 1/3.VCC. SOLUTIONS TO EXERCISE 2

1) Expressions of vA, vB and vS and their value when the NAND gates used are in TTL technology: vS = VCC; vA = 0 and VB = 0 vS = 5 V; vA = 0 and VB = 0. 2) Operation of the circuit. Expressions of voltages vA, vB and vS during the quasi-stable state and the stable state: 2.1) Quasi-stable state: Shifting from the stable state to the quasi-stable state is obtained by applying on the input a pulse ve that will trigger the device on a falling edge. As a result, we will have (see Figure E2.2) the output voltage that will shift from one stable state to a quasi-stable state for a duration equal to T1. The voltage vA will abruptly shift from 0 to VCC: vA = VCC vS = 0

Figure E2.2. Quasi-stable state of the circuit. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

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This variation of vA is instantly transmitted by capacitor C to point B. At this time, we thus have vB = VCC. Voltage vB will then evolve at the pace of the charge of the capacitor. The capacitor charges through the resistance R according to the exponential law: –t

vC = (vA - vB )=AeRC +B Constants A and B are determined using the boundary conditions. For t = 0, vC = 0; A + B = 0; A = -B When t → ∞, vC = VCC; B = VCC and A= -VCC –t

vC = VCC (1- eRC ) Finally, the voltage at the point is inferred as follows: –t

vB = (vA -vC ) = VCC .eRC Voltage vB decreases until this voltage becomes slightly smaller than the gate switching threshold V0, which will then follow that: vS = VCC; vA = 0; vB = V0-VCC After a while, the system returns to its stable state. 2.2) Stable state: Expressions of the stable state voltage are as follows: vA = 0; vS = VCC; vB = 0; 3) Representation according to the time of voltages vA, vB and vS and function provided by the circuit: The representation according to the time of voltages vA, vB and vS is given in Figure E2.3.

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53

Figure E2.3. Representation over the time of voltages vA, vB and vS. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

The circuit provides the monostable function. 4) Expression of the duration of the quasi-stable state: The gate switching threshold is equal to VCC/3. The quasi-stable state is the time T1 that voltage vB takes to switch from a value equal to VCC to a value equal to the NAND gate switching threshold (Vthreshold = VCC/3). It should be recalled that: –t

vB =VCC .eRC For t = 0, we again find that vB = VCC. When t = T1, vB = V0 =VCC/3: –T1

vB (T1 ) = VCC .e RC = We finally obtain: T1 =RCLn(3)

VCC 3

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EXERCISE 3

The system under study is a monostable circuit based on “No Or” (NOR) MOS-technology circuits (see Figure E3.1). The gate switching threshold is defined as (VCC/2).

Figure E3.1. Monostable circuit under study

1) Give the truth table of a NOR gate. 2) During the stable state, give the values of voltage vA, vB, vR, vC and vS, as well as the value of the currents that flow through the resistance R and the capacitor C. 3) What action should be triggered on the input to shift from the stable state to the quasi-stable state? Explain. 4) In the example of the application of a voltage ve adequate to shift from a stable state to a quasi-stable state, give the expressions of voltages vA, vB, vR, vC and vS, as well as their representation during the quasi-stable state and the stable state. 5) Determine the duration of the quasi-stable state according to the parameters of the monostable circuit. SOLUTIONS TO EXERCISE 3

1) The NOR gate truth table is given in Table E3.1:

Flip-flops

a

b

s=(a+b)

0

0

1

0

1

0

1

0

0

1

1

0

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Table E3.1. NOR gate truth table

2) Values of voltages vA, vB, vR, vC and vS as well as the value of the currents that flow through resistance R and the capacitor C during the stable state: There is no flow of current through the resistance R. The capacitor C is fully discharged. The supply voltage is directly transferred to point B. For the different voltages involved at the level of the circuit under study during the stable state, we then have: vB = VCC vS = 0 vA = VCC v C = vA - v B = 0 vR = VCC – vB = 0 The values of the currents that flow through the resistance R (IR) and the capacitor C (IC) are: IR = 0 IC = 0 3) Action to be triggered on the input to switch from the stable state to the quasistable state: In order to switch the output from the stable state to a quasi-stable state, a rising edge needs to be simply applied on the input (see Figure E3.2).

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Figure E3.2. Switching of the stable state to the quasi-stable state. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

When a rising edge arrives on the input ve, the output vA of the first NOR gate toggles from the value +VCC to value 0. This sudden change is transferred to point B by the capacitor C. We then have: vA = 0; vB = 0 and vS = +VCC Voltage vB will change at the pace of the charge of the capacitor through resistance R and strive to reach the value of VCC according to the law: -t

vC =vB - vA = vA = A1 eRC +B1 Constants A1 and B1 are determined using the initial and final conditions: Initial condition: t = 0; vC = 0 = A1 + B1; A1 = -B1 Final condition: t → ∞; vC = VCC; A1 = VCC and B1 = -VCC -t

vC =vB =VCC (1-eRC ) The voltage at the capacitor terminals (or voltage vB) will never reach the final value +VCC, and the switching will occur once voltage vB reaches and slightly exceeds the switching threshold voltage of NOR gates.

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57

Here, we will have the output voltage that will switch from the value +VCC to 0 V. Similarly, the voltage at point A will switch from 0 V to the value +VCC. This variation (+VCC) of voltage vA is instantly transmitted to point B through the capacitor C. At the switching time, we thus have: vS = 0; vA = +VCC; vB = VCC+Vthreshold = (3VCC/2) The capacitor will tend to reduce to zero the current in the mesh formed by R, C and +VCC. Voltage vB will start to decrease, starting from an initial voltage equal to VCC + Vthreshold to reach the stability value: vB = VCC. 4) Expression and representation according to the time of voltages, vA, vB, vR, vC and vS during the presence of the quasi-stable state until the stable state is reached: As described in the solution to question 3, when applying a rising edge, the output shifts from a stable state (vS = 0) to a quasi-stable state (vS = VCC) of duration T1. The expressions of the different voltages involved during the quasi-stable state in the circuit are given as follows: -t

vA = 0; vC = vB -vA = vB = VCC (1-eRC ); -t

vR = vB - VCC =VCC .eRC vS = VCC The details of the calculation are provided in the solution to question 3. The representation of the different voltages is given in Figure E3.3.

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Figure E3.3. Representation of voltages vA, vB, vR, vC and vS. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

5) Determination of duration T1 of the quasi-stable state according to the parameters of the monostable circuit: The time T1 of the quasi-stable state (see Figure E3.3) is the time it takes for voltage vB to shift from a value zero to a value equal to (VCC/2). We remember that the expression of voltage vB (or vC) for the duration of the quasi-stable state is given by: -t

vC = vB = VCC (1-eRC ) At time t = 0, we find vC = vB = 0.

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59

When t = T1, we have vB = vC = (VCC/2): vB (T1 ) =

-T1 VCC = VCC (1-eRC ) 2

Finally: T1 =RCLn(2) EXERCISE 4

We propose to study the monostable based on the timer presented in Figure E4.1.

Figure E4.1. Monostable under study

1) The circuit is in its stable state. Determine the values of the voltage at points A, B and on the output. 2) We press the push button at time t = 0. Explain the operation of the circuit from this time onwards and represent the voltage changes at points A, B and on the output. 3) Determine time T1 of the quasi-stable state. What is the function of resistance R1? 4) Study the variations in the duration of the quasi-stable state according to R, knowing that the value of capacitance C is equal to 0.2, 0.1, 0.05 and 0.002 µf. 5) Give the individual pairs of values using the graph in the solution to question 4 to obtain a duration T1 of the quasi-stable state equal to 2 ms.

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SOLUTIONS TO EXERCISE 4

1) Determination of voltage values at points A, B and on the output during the stable state. No current flows through resistance R1. The supply voltage VCC appears in its entirety at point A: vA = VCC. Because vA= VCC, the output can only be zero: vS = 0. Under these conditions, points 7 and 6 of the 555 integrated circuit will be at zero potential (vB = 0). 2) Explanation of the operation of the circuit and representation of the evolution of the voltages at points A, B and on the output when pressing the push button: 2.1) Explanation of the operation: As soon as the push button is depressed, point A is suddenly found at zero potential. The output of the monostable shifts to the high state. The output at point 7 (collector of the internal transistor of the 555 IC) is open. At the initial switching time (t = 0), the capacitor is discharged and the voltage at point B is (VCC/2). Voltage vB will then increase following the pace of the charge of capacitor C from the initial voltage (VCC/2) to try to reach the supply voltage VCC. As soon as voltage vB reaches and slightly exceeds the value (2VCC/3), the output switches from the high state to the low state. Terminal 7 of the 555 IC will change to a zero -t

potential. Therefore, when vs = VCC, voltage vB changes such that: vB =De2RC +E. The parameters D and E are two constants that are determined using the boundary conditions. The capacitor charges through the two resistances R assembled in series with a time constant equal to: τ = 2RC. When t = 0, vB = (VCC/2): A+B = (VCC/2); For t → ∞, vB → VCC: B = VCC, A = (-VCC/2). -t

1 2RC vB =VCC (1- e ) 2

2.2) Representation of the evolution of the voltages at points A, B and on the output when the monostable is triggered:

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Figure E4.2. Evolution of voltages vA, vB and vS. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

3) Determination of the duration of the quasi-stable state and the role of the resistance R1: 3.1) Duration of the quasi-stable state: The duration T1 of the steady state is the time that the voltage vB takes to reach the value (2VCC/3) starting from an initial tension equal to (VCC/3): -t

-T1

1 2RC 1 2RC 2VCC vB =VCC (1- e ); vB (T1 )=VCC (1- e )= 2 3 2

Finally: 3 T1 =2RCLn( ) 2 3.2) Function of resistance R1: The resistance R1 polarizes point A at +VCC to maintain the circuit in a stable state (vS = 0). When the push button is depressed, this resistance protects the power supply against a short circuit at the triggering time. 4) Study of the variations in the duration of the quasi-stable state according to R: The variations in the duration T1 of the quasi-stable state according to the value of resistance R and for different values of capacitance C are shown in Figure E4.3.

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Figure E4.3. Evolution of the duration of the quasi-stable state according to R. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

5) The various pairs of values of R and C to obtain a duration T1 of the quasistable state equal to 2 ms: For this purpose, it is necessary to draw the line T1 = 2 ms in Figure E4.3, and to identify the different pairs that make it possible to get the duration of the quasistable state. It should be noted that with a capacity of 20 nF, the desirable duration cannot be obtained with a resistance R less than or equal to 100 KΩ. For other capacity values, we will have the following pairs that meet the desired set point: R ≅ 51 kΩ and C = 50 nF; R ≅ 25 kΩ and C = 100 nF; R ≅ 12.5 kΩ and C = 200 nF. EXERCISE 5

The objective is to study the operational amplifier monostable circuit presented in Figure E5.1. To simplify things, diode D is considered to be ideal (the threshold voltage and the resistance in the direct direction are equal to zero, and the reverse resistance is infinite).

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Figure E5.1. Monostable circuit

1) What is the role of diode D? Give the expressions of voltages vA, vB and vS in the absence of an input voltage. 2) The button is pressed for a very short time. Explain the operation of the circuit following the injection of a negative pulse on the inverting input of the op-amp. What is the role played by resistance R? 3) Give the expressions of voltages vA, vB and vS during the quasi-stable state and the beginning of the stable state immediately following the quasi-stable state. Application: it is assumed that when R1 = R2 = R, the operational amplifier has no dropout voltage (Vsat = VCC) and that V0 is 2 V. 4) Represent voltage changes: ve, vA, vB and vS. 5) Determine the expression of the duration of the quasi-stable state. Numerical application: R1 = R2, = R = 10 kΩ, C = 1 µf, Vsat = VCC and V0 = 2 V. 6) When the output abruptly returns to zero, how will the voltage change at point B? Explain. 7) Estimate the recovery time associated with the return to the stable state where we have R1 = R2 = R =10 kΩ, C = 1 µF, Vsat = VCC = 10 V and V0=2 V. How can this recovery time be reduced? SOLUTIONS TO EXERCISE 5

1) Role of diode D and expressions of voltages vA, vB and vS in the absence of an input voltage: 1.1) Diode function:

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Since it has been assumed that the diode is ideal, when the op-amp enters low saturation (vS = -Vsat), the output voltage is clipped (conductive diode) and will be equal to zero. However, the diode plays no role when the output is in a high state (vS = +Vsat), the diode is blocking and acts as an open circuit. 1.2) Expressions of voltages vA, vB and vS in the absence of an input voltage: It should be noted that voltage -V0 applied to the non-inverting input of the op-amp is negative, and that the voltage applied to the inverting input is zero. The output of the op-amp is in low saturation. Due to the presence of diode D which will be conducting, we will have on the output: vs = 0, The capacitor is initially discharged. The simplified schematic of the circuit is shown in Figure E5.2.

Figure E5.2. Equivalent circuit of the monostable in the idle position

The capacitor C will charge through resistors R1 and R2 to reach voltage -V0 which is applied thereto. We thus have: vB = -V0 (negative voltage); vA = 0 and vS = 0 (for the reasons already mentioned). 2) Explanation of the operation of the circuit following the injection of a negative pulse at the inverting input of the op-amp and the role played by resistance R: 2.1) Explanation of the operation: On injecting a falling edge (negative pulse), the inverting input will be at a smaller potential than that of the non-inverting input (VCC > V0). The output of the op-amp will be in high saturation: vs = +Vsat

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When the op-amp has no dropout voltage, we have: vs = +VCC Before sending the negative pulse to the input, it should be recalled that vB = -V0. The variation of the output voltage from a low to a high level is instantly transmitted by the capacitor to point B. It thus follows that: vB = Vsat - V0. = VCC - V0 Voltage VB will start to decrease from an initial voltage equal to VCC - V0 in order to reach -V0. The presence of the capacitor C in the mesh C, R1, R2 and -V0 causes this one to seek to cancel off the current in the mesh being considered. The tension at point A is related to the voltage at point B: vA =

R1 vB -R2 V0 R1 +R2

As soon as the voltage reaches at point A and very slightly exceeds with a smaller value, the value zero, the output voltage switches from a high state (quasistable state) to a low state (stable state). We will have as switching threshold: vA = 0  vB =

R2 V0 R1

The fact that the output shifts from a value equal to +VCC to a value of zero, causes this variation (-VCC) to be instantly transmitted to point B. We thus have: vB =

R2 V0 - VCC R1

Voltage vB will increase exponentially to reach the steady state relative to the stable state of the monostable. 2.2) Role played by resistance R: The resistance R protects the op-amp from destruction. There is a risk of a strong current at the input of the op-amp during the injection of the trigger pulse. This current cannot be supported by the op-amp. Large part of the excitation current is derived towards resistance R. In the absence of the trigger pulse, resistance R makes it possible to have the zero reference for the switching from the quasi-stable state to the stable state.

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3) Expressions of voltages vA, vB and vS during the quasi-stable state and at the beginning of the steady state immediately following the quasi-stable state. Application when we assume that R1 = R2 = R, vsat = VCC and V0 = 2: 3.1) The quasi-stable state: We have: vS = +Vsat -t

vB =Ae(R1+R2)C +B Constants A and B are determined using the boundary conditions. When t = 0, we have vB = -V0 + Vsat. When t →∞, vB → -V0 A +B = -V0 + Vsat. B = -V0 and A = Vsat. We finally obtain: -t

vB =Vsat .e(R1+R2)C - V0 -t

R1 vB -R2 V0 R1 (Vsat .e(R1+R2)C - V0 ) - R2 V0 vA = = R1 +R2 R1 +R2 3.2) The stable state: vS = 0 -t

vB =A1 e(R1+R2)C +B1 vA =

R1 vB -R2 V0 R1 +R2

Constants A1 and B1 are determined using the boundary conditions. For t = 0,

vB (t=0) =

When t →∞, vB → -V0

R2 V0 R1

- Vsat

A1 + B1 =

R2 V0 R1

- Vsat

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B1 = -V0 ; A1 = V0 + vB = (V0 + vA =

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R2 V0 - Vsat R1

-t R2 V0 - Vsat )e(R1+R2)C - V0 R1

R1 vB -R2 V0 R1 +R2

3.3) Application: It is assumed that R1 = R2, Vsat = VCC and V0 = 2 V. The expressions of the various voltages can be simplified. Quasi-stable state: vS = VCC -t

vB =VCC .e2RC - V0 -t

(VCC .e2RC - 2V0 ) vA = 2 Stable state: vS = 0 -t

vB = (2V0 - VCC )e2RC - V0 -t

(2V0 - VCC )e(R1+R2)C - 2V0 vA = 2 4) Representation of the evolutions of voltages ve, vS, vB and vA (see Figure E5.3): 5) Determination of the expression of the duration of the quasi-stable state and numerical application: By analyzing the graph in Figure E5.3, it can be observed that the duration T1 of the quasi-stable state is the time that voltage vB takes to change from an initial value (vB = VCC –V0) to a final value equal to (vB = R2V0/R1) following an exponential law: -t

vB =Vsat .e(R1+R2)C - V0 -T1

vB (T1 )=Vsat .e(R1+R2)C - V0 =

R2 V R1 0

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Figure E5.3. Evolution in time of the signals ve, vS, vB and vA. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

Finally, we get: T1 =(R1 +R2 )C.Ln(

R1 Vsat ) (R1 +R2 )V0

Numerical application: R1 = R2, = R = 10 kΩ, C = 1 µf, Vsat = VCC =10 V and V0 = 2 V: T1 =2R.C.Ln(

VCC ) 2V0

T1 =18.3 ms 6) When the output abruptly returns to zero. Evolution of the voltage at point B and explanation: When the output switches from the high state (quasi-stable state) to the low state (stable state), voltage vB can reach its permanent stable state only after some time.

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It is remembered that the expression of vB immediately after the switch of the output to the stable state is given by: vB = (V0 +

-t R2 V0 - Vsat )e(R1+R2)C - V0 R1

It can be seen that voltage vB changes exponentially with a time constant τ = (R1+R2)C to reach the voltage -V0 relatively to the permanent stable state. It would take some time to reach the value of (-V0 = - 2 V). This is the recovery time TR. The monostable can only be retriggered at the end of this recovery time. Otherwise, the duration of the quasi-stable state will be erroneous (see Figure E5.4). In fact, it should be noted that when the monostable is triggered after some time which is greater than the recovery time TR, the duration of the quasi-stable state can be found from the calculation given in the solution to question 5. On the other hand, when the monostable is triggered before the end of the recovery time, it can be seen that the duration of the quasi-stable state is equal to T2 and T2 < T1.

Figure E5.4. Effect of the recovery time on the monostable operation. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

7) Estimate of the recovery time TR and reduction of this time: It is assumed that R1 = R2 = R =10 kΩ, C = 1 µF, Vsat = VCC = 10 V and V0=2 V.

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Under these conditions, we have: -t

-t

vB = (2V0 - VCC )e2RC - V0 = −6e2RC − 2 At the end of time TR: -

6e2RC → 0 It can be estimated that after a time TR equal to five times the time constant, we practically have: vB ≅ -2 V. As a result, the estimate of the recovery time gives: TR ≅ 5(R1+R2)C = 10.RC =100 ms This recovery time is not very troublesome in some applications, but it may be in others. The best thing to do is to reduce this recovery time by adding a diode to the circuit under study, as shown in Figure E5.5.

Figure E5.5. Insertion of diode D1 to decrease the recovery time. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

The result is very interesting. As shown in Figure E5.6, in the absence of diode D1, the recovery time is quite significant; however, in the presence of diode D1, the recovery time is virtually zero.

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Figure E5.6. Effect of the diode on the recovery time. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

EXERCISE 6

The monostable circuit under study is schematically presented in Figure E6.1. The diode has a threshold voltage equal to 0.6 V, a negligible dynamic resistance and a very large inverse resistance.

Figure E6.1. Circuit under study

1) What is the use of voltage V0 = 0.6 V inserted in series with diode D? 2) Express the output state and give the expression of voltage vB for a situation where the switch K is open in the following two cases: (a) V1 < 0 and (b) V1 > 0. 3) Switch K is closed for a very short time. Give the voltage expressions at points S, A and at the terminals of capacitor C in the following two cases: (a) V1 < 0 and (b) V1 > 0.

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4) Represent the evolution over time of the voltages at points B, S, A and at the terminals of capacitor C for V1 > 0. 5) Give the expression of time T1 of the quasi-stable state. Study the variations of T1 according to V1 for R = 10 kΩ and C = 1 µF, Vsat = 10 V. Graphically determine time T1 for V1 = 1 V and for V1 = 6 V. What conclusion can be drawn from it? SOLUTIONS TO EXERCISE 6

1) Usefulness of voltage V0 = 0.6 V inserted in series with diode D: The diode presents a threshold that is equal to about 0.6 V; the presence of voltage V0 = 0.6 V will compensate for this threshold. In the case of low saturation of the op-amp, the presence of diode D in series with V0 will make it possible to have a voltage approximately equal to zero on the output. However, if there is high saturation, the diode will be blocking and will virtually act as an open circuit. In this case, it has no effect on the output voltage. 2) Output state when switch K is open: 2.1) V1 < 0: When voltage V1 is negative, the voltage at the non-inverting terminal is zero and larger than voltage V1 applied at the inverting input. The op-amp is fitted with a positive reaction. The output is in a high state: vS = +Vsat; vB = V1. 2.2) V1 > 0: When voltage V1 is positive, the voltage at the non-inverting input is zero and smaller than voltage V1 applied to the inverting input. The output is in a low saturation state. Due to the presence of the diode and the compensation voltage V0, we have: vS = 0; vB = V1. 3) Voltage expressions at points S, A and at the terminals of capacitor C (switch K is closed for a very short time): 3.1) V1 < 0:

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When a negative pulse is applied to the inverting input by switching off switch K for a short moment, the level of negative voltage is reinforced on this input. The non-inverting input is at potential zero. As a result, we have: vS = +Vsat; vA = 0 vC = vS - vA = +Vsat The circuit will remain indefinitely in this state. Consequently, the presence of a voltage V1 < is not an interesting case for study. 3.2) V1 > 0: When switch K is switched off for a short time, a negative pulse of amplitude -VCC is generated, which starts from an initial value equal to V1. The inverting input of the op-amp will change to a potential less than that applied to the non-inverting input. The output of the op-amp is in a high state for a while: vs = -Vsat The sudden change at the time of the output transition from zero to the value +Vsat is instantly transmitted by capacitor C to point A: vs = -Vsat The voltage vA will change according to an exponential form at the pace of the variation of the voltage at the terminals of capacitor C. It should be noted that a capacitor inserted in a mesh will seek to cancel the current in this mesh: -t

vA =AeRC +B Constants A and B are determined using the boundary conditions. At the initial moment (transition of vS from zero to the voltage +Vsat), as explained above, we have: vA = +Vsat. When t → ∞, vA → 0 We thus have: B = 0 and A = +Vsat -t

vA =Vsat eRC

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The expression of the voltage at the terminals of capacitor C remains to be found: v C = vS - v A -t

vC =Vsat (1- eRC ) 4) Representation of the changes over time of the voltages at points B, S, A and at the terminals of capacitor C for V1 > 0: The representation of the different voltages is given in Figure E6.2. It can be observed that as soon as a negative pulse is applied on the input (switching off switch K for a very short time), the output switches from the low state (vS = 0) to the high state (vS = + Vsat). Voltage vA will change according to the form: -t

vA =Vsat eRC As soon as voltage vA reaches and exceeds V1 by small values, the output voltage will shift from the quasi-stable state (vS = + Vsat) to the stable state (vS = 0) until the next application of a negative pulse.

Figure E6.2. Representation of the evolution over time of the signals at points B, S, A and at the terminals of capacitor C for V1 > 0. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

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5) Expression of time T1 of the quasi-stable state and the study of the variation of T1 according to V1 for R = 10 kΩ and C = 1 µF and Vsat = 10 V, plus determination of the values of T1 for V1 = 1 V and V1 = 6 V and conclusion: 5.1) Expression of time T1 of the quasi-stable state: By analyzing the variations of voltage vA, it can be observed that the time T1 of the quasi-stable state is the time that this voltage vA takes to shift from an initial voltage equal to Vsat to the value vA= V1. For this case, we recall that the expression of voltage vA during the quasi-stable state is given by: -t

vA =Vsat eRC For t = T1, we have: -T1

vA (T1 )=Vsat e RC =V1 We finally obtain: T1 =RC.Ln(

Vsat ) V1

5.2) Study of the variation of T1 according to V1. R = 10 kΩ and C = 1 µF and Vsat = 10 V (see Figure E6.3):

Figure E6.3. Evolution of the duration of the quasi-stable state according to voltage V1. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

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5.3) Calculations of the values of T1 for V1 = 1 V and V1 = 6 V: To graphically determine the values of the duration T1 of the quasi-stable state, we use the graph shown in Figure E6.3. a) For V1 = 1 V, we graphically find that: T1 ≅ 23 ms The direct calculation gives T1 =23,02 ms. b) For V1 = 6 V, we graphically find that: T1 ≅ 5 ms The direct calculation gives T1 =5,1 ms. 5.4) Conclusion: It can be seen that the circuit can only operate as a monostable when voltage V1 is positive. The duration of the quasi-stable state is a logarithmic function of voltage V1. This is a voltage applied to the inverting input of the op-amp. The duration of the quasi-stable state increases when voltage V1 decreases. Very significant periods of the quasi-stable state can be obtained when voltage V1 is close to zero with positive values. Voltage V1 must be positive. The graphical approach will allow us to very quickly determine the duration of the quasi-stable state. EXERCISE 7

The objective is to study the device based on the “555 timer” that is schematically presented in Figure E7.1(a). Signals ve1 and ve2 applied to the inputs of this circuit are presented in Figure E7.1(b). 1) Voltages ve1 and ve2 are respectively injected at terminals 2 and 6 of the 555 timer. Explain the operation of the circuit and give the representation of the evolution of the output voltage vs with respect to voltages ve1 and ve2. 2) Calculate the duration of the high state of the output pulse of the quasi-stable state according to the period of one of the signals applied on the input.

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Figure E7.1. (a) Circuit under study and (b) signals applied on the inputs. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

3) Terminals “2” and “6” are now taken together and we simultaneously apply voltages ve = ve2. Give the evolution of vS over time. Plot vS= f(ve). What is the function achieved by this circuit? 4) We now use the circuit shown in Figure E7.2. A voltage of sinusoidal shape ve = Vmsin(2πft) +Vm is applied on the input. Voltage Vm is the peak value of the input signal. Let Vm = VCC/2. Trace the evolution of vs(t) according to ve(t).

Figure E7.2. Circuit under study

SOLUTIONS TO EXERCISE 7

1) Explanation of the circuit operation and representation of the evolution of the output voltage vs according to the voltages ve1 and ve2: 1.1) Explanation:

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Voltages ve1 and ve2 are applied to inputs 2 and 6 respectively. Initially, the output vS is in a high state: vS = VCC. Voltages ve1 and ve2 change in a linear fashion. When ve1 exceeds the value (VCC/3), voltage ve2 exceeds the value (2VCC/3). As a result, voltage vs will switch from the high state to the low state (at the switching time of ve1 by VCC/3 and ve2 by 2VCC/3): vS = 0 The two voltages will continue to increase and then begin to decrease until voltage ve1 becomes slightly less than (VCC/3) and voltage ve2 becomes slightly less than (2VCC/3). At this time, the output voltage will switch from the low state to the high state: vS = VCC The cycle repeats itself indefinitely as long as ve1 and ve2 are present and the circuit is in working condition. TO SUMMARIZE.– ve1 < VCC/3 and ve2 < 2VCC/3 vs = VCC. ve1 > VCC/3 and ve2 > 2VCC/3 vs = 0.

1.2) Representation: The representation of the evolution of the output voltage vs according to the voltages ve1 and ve2 is given in Figure E7.3.

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Figure E7.3. Representation of the evolution of the output voltage according to ve1 and ve2. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

2) Calculation of the duration of the high state of the output pulse according to the period of one of the signals applied on the input: The two signals ve1 and ve2 have the same period (see Figure E7.3). The duration of the high state of the output signal is denoted by T1. The relation between T1 and T is given by: T1 =

2T 3

3) Evolution of the output voltage vS over time, plot of vs = f(ve) and function performed by the circuit when terminals “2” and “6” are joined together and a voltage ve = ve2 is simultaneously applied to them: 3.1) Evolution of vS in time (see Figure E7.4):

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Figure E7.4. Evolution of the output voltage vS according to time. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

3.2) Plot of vs = f(ve): The plot of the variations of vs according to ve is given in Figure E7.5.

Figure E7.5. Evolution of the output voltage vS according to time. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

3.3) Function performed by the circuit: The circuit achieves the function of a Schmitt trigger (or flip-flop), which has two switching thresholds: a low threshold that is equal to (VCC/3) and a high threshold (2VCC/3). 4) Plot of the evolution of vs(t) according to ve(t). The circuit under test is schematically presented in Figure E7.2. The signal applied to the input is sinusoidal: The voltage applied to the input is of the form: ve = ((VCC/2).(sin(2πft) +1). The output state will depend on the voltages applied to inputs 2 and 6 of the 555 timer IC.

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When the voltage applied at terminal 2 of the 555 circuit falls below (VCC/3) and the voltage applied at terminal 6 is lower than (2VCC/3), the output of the circuit presented in Figure E7.2 is in a high state. On the other hand, when the voltage applied at terminal 2 is greater than (VCC/3) and the voltage applied at terminal 6 is greater than (2VCC/3), the output is in the low state. The voltage v6 applied at input 6 (terminal 6) is equal to ve. Nonetheless, voltage v2 that is applied to input 2 (terminal 2) is equal to: v2 =

R 1 ve = ve R+R 2

Voltage v2 at the level of terminal 2 will follow voltage v6 at the level of terminal 6, as shown in Figure E7.6. The output voltage is a rectangular signal. Switching from a low level to a high level and vice versa depends on high and low switching thresholds. These high and low switching thresholds are respectively equal to (2VCC/3) and (VCC/3).

Figure E7.6. Evolution of the output voltage vs with respect to time. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

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EXERCISE 8

The circuit under study is schematically presented in Figure E8.1. The op-amp is considered to be ideal and has no dropout voltage. 1) What is the expression of the output signal in the absence of a signal at the circuit input? 2) A sufficiently high-amplitude sinusoidal signal is applied on the input. Determine the high and low switching thresholds V1 and V2.

Figure E8.1. Circuit under study

3) Represent the evolution of V1 and V2 according to the variations of voltage V0 when R1 = R2. Voltage V0 varies from –VCC to +VCC (-VCC < V0 < VCC). 4) Represent the changes in the output voltage vs(t) according to voltage ve applied on the input for the following cases: V0 = -VCC, V0 = 0, V0 = (VCC/2), V0 = (-VCC/2) when R1 = R2 and ve =VCC.sin(2πft). SOLUTIONS TO EXERCISE 8

1) Expression of the output signal in the absence of a signal on the circuit input: The output signal expression depends on the sign of voltage V0. Therefore, two cases can arise: Case 1. V0 is positive: vS = +VCC; Case 2. V0 is negative: vS = -VCC.

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2) Determination of thresholds when a sinusoidal signal of high amplitude is applied on the input: It is initially assumed that when voltage V0 is positive, we have: vS = VCC et VA =

R2 V0 +R1 VCC =V1 R1 +R2

Voltage ve will start to increase as soon as voltage ve reaches and slightly exceeds the switching threshold V1 (high threshold), the output voltage vs will switch from the high state to the low state. We then have the following expressions: vS =-VCC and VA =

R2 V0 - R1 VCC =V2 R1 + R2

When R1 = R2, we get: For the high threshold: V1 =

V0 + VCC 2

For the low threshold: V 2 =

V0 - VCC 2

3) Representation of the evolution of the thresholds according to V0: The evolution of the high and low switching thresholds with the external voltage V0 is presented in Figure E8.2. 4) Variations in the output voltage vs(t) according to the input voltage ve for the following cases: V0 = -VCC, V0 = 0, V0 = (+VCC/2), V0 = (-VCC/2) and R1 = R2 and ve = VCC.sin(2πft). 4.1) V0 = VCC and V0 = 0:

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For V0 = VCC, the high and low switching thresholds are respectively equal to (V1 = VCC and V2 = 0). For V0 = 0, these thresholds are respectively equal to (V1 = -V2 = (VCC /2)).

Figure E8.2. Evolution of the switching thresholds according to V0. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

The representation of the variations in vs(t) for the cases V0 = -VCC and V0 = 0 are given in Figure E8.3. The supply voltage VCC is set at 10 V.

Figure E8.3. Representation of vs(t): (a) V0 = VCC and (b) V0 = 0. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

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4.2) V0 = (VCC/2) and V0 = (-VCC/2): For V0 = VCC, the high and low switching thresholds are respectively equal to (VCC = V1 and V2 = 0). For V0 = (-VCC/2), these thresholds are respectively V1= (VCC/4) and V2 = (-3VCC/4). The representation of vS(t) according to ve(t) for the values of voltage V0 = (±VCC/2) is given in Figure E8.4.

(a)

(b)

Figure E8.4. Representation of vs(t): (a) V0 = VCC/2 and (b) V0 =(-VCC/2). For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

NOTE.– When V0 = VCC, the high and low switching thresholds are respectively equal to VCC and zero. Similarly, when V0 = 0, the high and low thresholds are symmetrical. This is all the more consistent with the results presented in Figure E8.2. When V0 = +VCC/2, the high switching threshold is equal to V1 = 3VCC/4. The low threshold V2 is equal to -VCC/4. When the polarities of voltage V0 are inverted, (V0 =-VCC/2), we obtain V1 = VCC/4 for the high threshold and V2 = -3VCC/4 for the low threshold. We should also note a certain symmetry with respect to the switching thresholds obtained for V0 = VCC/2. EXERCISE 9

The circuit under study is schematically presented in Figure E9.1. The op-amp is considered to be ideal (infinite differential input resistance, zero output resistance and infinite open-loop gain).

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Figure E9.1. Circuit under study

1) It is assumed that voltage VX is positive and there is no input voltage. It is also assumed that the op-amp has no dropout voltage (rail-to-rail op-amp). Give the expression of the output voltage. 2) A sinusoidal signal ve of frequency f and amplitude Vm, ve = Vm.sin(2πft) is applied on the input. Study the circuit operation starting from the initial state t = 0. 3) For this case, we have VX = VCC = 10 V, R1 = 10 kΩ and R2 = 20 kΩ. Study the evolution of the switching threshold voltages of the circuit according to RX. What conclusion can be drawn from it? Determine the limit values of Rx in order to have switching on the output. 4) Two values of resistances are imposed, RX = 10 kΩ and RX = 20 kΩ. The other parameters maintain their values as given in question 3. Graphically and analytically determine the values of switching thresholds for each value of RX and plot the evolution of the output voltage over time according to the input voltage, knowing that: ve = 7.sin(2πft). 5) Plot the evolution of vS = f(ve) for the two values of RX (RX = 10 kΩ and RX = 20 kΩ). How can we reduce the hysteresis cycle? 6) Here, it is imposed that R1 = R2 = RX, VCC = 10 and VX is a variable (0 ≤ VX ≤ VCC). Study the evolution of switching thresholds based on voltage VX. What conclusion can be drawn from it?

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7) Graphically determine the switching thresholds and plot the evolution of the output voltage according to time and input voltage vS = f(ve) for VX = 0 and VX = VCC. SOLUTIONS TO EXERCISE 9

1) Expression of the output voltage: It is initially assumed that the output voltage is zero. At the non-inverting input of the op-amp, we find a voltage: ve+ =

R1 V R1 +RX X

Voltage VX is positive. Voltage ve+ is also positive. The amplifier is assembled with a positive feedback, and the output is saturated. It is in a high state: vs = +VCC 2) Study of the operation of the circuit: At time t = 0, the input voltage ve is zero. The output voltage is: vs = VCC. The input voltage will increase and will be at all times compared to the voltage that can be found at the non-inverting input Ve+. When the amplifier output is in a high state, the expression of voltage Ve+ is given by: Ve+ =

R1 Rx VCC +R1 R2 VX = V1 R1 R2 +R1 RX +R2 RX

The threshold voltage V1 is called the high threshold. This voltage has a positive value. When the input voltage ve reaches and exceeds the threshold voltage Ve+= V1, the output voltage vs switches from the high state to the low state: vs = -VCC.

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The voltage that is applied to the non-inverting input immediately after the switching is given by: Ve+ =

-R1 Rx VCC +R1 R2 VX R1 R2 +R1 RX +R2 RX

=V2

The input voltage can continue to increase, and no phenomenon is observed. At some point, the input voltage will start to decrease until it reaches and exceeds the second threshold voltage V2 with a lower value. At this time, the output voltage switches from the low state to the high state: vs = VCC. The cycle thus described will repeat indefinitely as long as the circuit is operating. Voltage V2 is the low switching threshold. Its sign cannot be known because we do not have for now the values of the various voltages and resistances implemented in the circuit under study. 3) Study of the evolution of switching threshold voltages according to RX, conclusion that can be drawn from it and limit values of RX in order to have switching on output: 3.1) Evolution of the high switching threshold V1 according to RX and conclusion: We have VX = VCC = 10 V, R1 = 10 kΩ and R2 = 20 kΩ. Under these conditions, we define the switching thresholds as follows: High threshold: V1 =

10(Rx +20) (Rx +20)VCC = 20+3RX 20+3RX

Low threshold: V2 =

10(-Rx +20) (-Rx +20)VCC = 20+3RX 20+3RX

In these relations, RX is expressed in kΩ. The evolution of V1 according to resistance RX is presented in Figure E9.2.

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Figure E9.2. Evolution of the high switching threshold according to RX. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

It can be seen that the high switching threshold cannot fall below a certain value. The lower limit value of the high switching threshold V1 is given by the relation: V1min =

VCC 3

This means that the amplitude of the input signal must be necessarily higher than (VCC/3) for the circuit to perform the function for which it was designed. It should also be noted that if the value of RX is too low, the upper switching threshold may be too high (see Figure E9.1). The circuit under study cannot be used for formatting low-amplitude signals. If the signal on the input has a low amplitude, the output will permanently remain in a high state. In fact, the non-inverting input will be at all times at a higher potential than the one that is applied to the inverting input.

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3.2) Evolution of the low switching threshold V2 according to RX and conclusion: The representation of the evolution of the low switching threshold according to the changes of resistance RX is given in Figure E9.3.

Figure E9.3. Evolution of the low switching threshold according to RX. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

It can be observed that the minimum value of the switching threshold is negative and tends towards the value: V2min =

-VCC 3

The maximal value of the switching threshold can reach the supply voltage if resistance RX is too low. 3.3) Limit values of RX in order to have transitions on the output: The calculation of the high and low switching thresholds for the case in which we have: VX = VCC, R1 = 10 kΩ and R2 = 20 kΩ yields the following expressions:

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High threshold: V1 =

(Rx +20)VCC 20+3RX

Low threshold: V2 =

(-Rx +20)VCC 20+3RX

It should be noted that the input voltage is expressed as: ve = 7.sin(2πft). In order to have transitions at the output level, the following conditions must be present: V1 =

(Rx +20)VCC
RX >

20(VCC -Vm ) ; RX is expressed in kΩ 3Vm-VCC

Similarly, it would be necessary that: V2 =

(-Rx +20)VCC >-Vm 20+3RX

RX >

−20(VCC +Vm ) ; RX is expressed in kΩ 3VM -VCC

This relation is always verified for the particular case under consideration. Numerical application: Vm = 7 V and VCC = 10 V R >

60 KΩ 11

4) Graphical and analytical determination of switching thresholds and plot of the evolution of the output voltage according to the input voltage: 4.1) RX = 10 kΩ: 4.1.1) Graphical determination of the switching thresholds (see Figure E9.4):

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(a)

(b)

Figure E9.4. Graphical determination of the switching thresholds for RX = 10 kΩ: (a) high threshold and (b) low threshold. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

The analysis of the curves shown in Figure E9.4 allows us to deduct the high threshold (V1 = 6 V) and the low threshold (V2 = 2 V). 4.1.2) Analytical determination: To analytically find the values of the switching thresholds V1 and V2, we have to simply make use of the two relations that have already been defined for this purpose and to replace RX by its value (RX = 10 kΩ): high threshold: V1 =

(Rx +20)VCC (-R +20)VCC = 6 V; low threshold: V2 = x = 2 V 20+3RX 20+3RX

4.1.3) Plot of the evolution of the output voltage vs(t) according to the input voltage (see Figure E9.5):

Figure E9.5. Evolution of the output voltage with respect to time according to the input voltage. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

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4.2) RX = 20 kΩ: 4.2.1) Graphical determination of switching thresholds: We have to mainly see the correspondence between the value RX = 20 kΩ and voltages V1 and V2 based on the curves shown in Figure E9.6.

(a)

(b)

Figure E9.6. Graphical determination of switching thresholds for RX = 20 kΩ: (a) high threshold and (b) low threshold. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

Based on the curves shown in in Figure E9.6, we determine the switching thresholds: High threshold: V1 = 5 V; Low threshold: V2 = 0 V. 4.2.2) Analytical determination: For this purpose, we can use the definition relations of the two switching thresholds: High threshold: V1 =

(Rx +20)VCC =5V 20+3RX

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Low threshold: V2 =

(-Rx +20)VCC =0V 20+3RX

4.2.3) Plot of the output voltage vs(t) according to the input voltage (see Figure E9.7):

Figure E9.7. Evolution of the output voltage with respect to time. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

5) Plot of the evolution of vS = f(ve) for RX = 10 kΩ and RX = 20 kΩ: 5.1) For RX = 10 kΩ: The plot of the evolution of the output voltage according to the input voltage for the case of RX = 10 kΩ is schematically presented in Figure E9.8.

Figure E9.8. Evolution of vs = f(ve) for RX = 10 kΩ. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

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5.2) For RX = 20 kΩ: The plot of the evolution of the output voltage according to the input voltage for the case of RX = 20 kΩ is schematically presented in Figure E9.9.

Figure E9.9. Evolution of vs = f(ve) for RX = 20 kΩ. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

6) Study of the evolution of switching thresholds according to the evolution of voltage VX and conclusion: High and low switching thresholds are defined as: High threshold: V1 =

R1 Rx VCC +R1 R2 VX R1 R2 +R1 RX +R2 RX

Low threshold: V2 =

-R1 Rx VCC +R1 R2 VX R1 R2 +R1 RX +R2 RX

When R1 = R2 = RX, VCC = 10 and VX is a variable ((0 ≤ VX ≤ VCC). The expressions that define the switching thresholds are: High threshold: V1 =

VCC +VX 3

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Low threshold: V2 =

-VCC +VX 3

Representation of the high threshold V1 and low threshold V2 according to VX is given in Figure E9.10. Conclusion: – the switching thresholds linearly evolve with voltage VX; – the high threshold V1 is always positive (3.33 V < V1 < 6.66 V); – the low threshold V2 is still negative (-3.33 V < V1 < 0 V). We can also observe the symmetry between the switching thresholds. This means that independently of the value of VX, the hysteresis cycle will always have the same width. Only the triggering thresholds will offset.

Figure E9.10. Evolution of the high threshold V1 and the low threshold V2 according to voltage VX. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

7) Graphical determination of switching thresholds and plot of vS = f(ve) for VX = 0 and VX = VCC: 7.1) Graphic determination of switching thresholds:

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The graph shown in Figure E9.10 allows us to easily determine the switching thresholds for VX = 0 and VX = VCC: VX = 0: V1 = 3.33 V and V2 =-3.33 V VX = VCC =10 V: V1 = 6.66 V and V2 = 0 V 7.2) Plot of vs(t) for VX = 0 and VX = VCC (see Figure E9.11):

Figure E9.11. Plot of vs(t): (a) VX = 0 V and (b) VX = VCC =10 V. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip

7.3) Plot of vS = f(ve) for VX = 0 and VX = VCC (see Figure E9.12):

(a)

(b)

Figure E9.12. Plot of vs = f(ve): (a) VX = 0 V and (b) VX = VCC =10 V. For a color version of this figure, see www.iste.co.uk/haraoubia/nonlinear2.zip