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Forensic characterization of thin film resistor degradation
Microelectronics Reliability 48 (2008) 958–964
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Forensic characterization of thin film resistor degradation William J. Roesch * TriQuint Semiconductor Inc., 2300 N.E. Brookwood Parkway, Hillsboro, OR 97124-5300, United States
a r t i c l e
i n f o
Article history: Received 20 December 2007 Received in revised form 1 February 2008 Available online 22 April 2008
a b s t r a c t Experienced reliability engineers and failure analysts often rely on visual aspects of degradation and destruction to reconstruct events leading up to failure of semiconductor circuit elements. Often, the resulting theories about failure causes are tested by duplication experiments. These re-creations are typically evaluated and compared using those same visual attributes. This study is intended to establish the historical basis for visual comparison of nichrome resistor failures (a Rogues gallery of broken resistors) and then debunk correlation theories with simulations and empirical failure duplication results. The results will show that various visual failure characteristics can be reproduced by an unexpectedly wide range of applied stimulus. The final appearance of a ‘‘dead” resistor does not always portray how the part was ‘‘killed”. Ó 2008 Elsevier Ltd. All rights reserved.
1. Introduction One of the most valuable techniques of root cause failure analysis is to perform a good visual inspection of a circuit and compare anomalies to previous experiences with degradation. Often, a good ‘‘look” is the key to a diagnosis. Over time, these experiences accumulate into a mental catalog. Eventually, some relationships between cause and effect are developed into theories. However, the relationships may be only a loose association of anecdotes or stories which grow into expectations. The accumulation of historical data and experiences build evidence to support a theory, but if the hypotheses are not tested scientifically, then they are nothing more than lore, myths, and legends. Engineers and scientists become technical myth-busters when they apply scientific methods to decide the validity of a hypothesis. Essentially, they become forensic failure analysts. Previous work on degradation of nichrome resistors utilized within compound semiconductor integrated circuits has built an experienced-based expectation of cause and effect between applied stresses and resulting appearance of resistor elements. This work investigates various stress conditions and provides additional data on the physical appearance of degraded resistors. This investigation compares an original observed relationship using a failure analysis technique called ‘‘duplication”. Discrete resistors are subjected to various stresses in order to duplicate the physical and electrical damage which was previously discov-
Abbreviations: NiCr, nickel chrome = ‘‘nichrome”; RF, radio frequency; ESD, electrostatic discharge; EOS, electrical overstress; HBM, human body model; DC, direct current; BCB, divinylsiloxane bis-BenzoCycloButene. * Tel.: +1 503 615 9292; fax: +1 503 615 8903. E-mail address: [email protected] 0026-2714/$ - see front matter Ó 2008 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2008.02.002
ered in a customer’s application. Without the effort to duplicate the appearance, the damage could not be explained by the historical relationship. Subsequent experiments and measurements eventually show that the original hypothesized relationship did not exist after-all. 2. Lifetesting history of thin film resistors Thin film resistors are common elements in analog and high frequency circuits. In compound semiconductors, the resistors can be constructed from nickel chrome, tantalum nitride, silicon chrome, or other elements. This investigation is a look at nickel chrome or ‘‘nichrome” resistors. During initial characterization, the nichrome resistors were studied as individual circuit elements. Independent temperature and current density tests were performed on populations of 70 nichrome resistors. Biased resistor temperatures were measured using an infrared thermal imager. Drift testing was performed using temperature and DC current density variables. Three temperature conditions lasting 24 h and three current densities conditions lasting 24 h were conducted. The resistors changed less than 0.4% during any of the five independent stress conditions. Drift testing resulted in very little change in resistance in reasonable lifetimes. Acceleration factor testing resulted in similar data to the drift results. Full lifetesting has been performed on nichrome resistors at 125 °C, 150 °C, 175 °C, and 200 °C at a bias inducing the maximum rated current density and also without any electrical bias. Electrical results of the latest lifetest are shown in Fig. 1 [1]. No failures could be generated after 6000 h of aging under maximum rated current density at temperatures up to 200 °C. The resistance increase degradation appears to be logarithmic with
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Resistance Change (Percent)
W.J. Roesch / Microelectronics Reliability 48 (2008) 958–964
1.0% 0.9% 0.8% 0.7% 0.6%
200ºC
0.5%
175ºC
0.4%
150ºC
0.3%
125ºC
0.2% 0.1% 0.0% 1000
2000
3000
4000
5000
6000
Lifetest Duration (Hours) Fig. 1. Electrical degradation results of accelerated lifetesting on nichrome resistors. These tests were conducted at the temperatures shown, and under maximum rated current density.
time. Projection of the median life is based on this 6000 h trend results in an activation energy of 1.0 eV. The failure mechanism is expected to be electromigration. Extended biased lifetests of individual resistors were subsequently performed at temperatures up to 290 °C. Physical degradation resulted in a very thin line of damage located in the very center of the resistor, bridging from side-to-side and severing resistance from end-to-end. 3. Electrostatic discharge testing history of thin film resistors Several sizes of nichrome resistors were subjected to ESD (Electrostatic Discharge) pulses generated from a HBM (Human Body Model) simulator. This size of resistors varied from 125 lm2 to 6875 lm2. Resistance changes of 4% and greater were considered failures. A total of 24 resistors were pulsed with increasing voltages until failure. The ESD susceptibility was consistently dependent of the width of the resistor. See Table 1. As an example, for
Table 1 Instantaneous current required to cause failure in nichrome resistors Nichrome width (lm)
Pulse voltage (V)
Resistance (X)
Pulse current* (Amps)
Current per lm (mA/lm)
5 5 5 5 5 5 5 5 25 25 25 25 25 25 25 25 25 25 25 25 45 45 45
220 220 220 220 230 230 240 250 950 950 1000 1040 1100 1100 1150 1150 1175 1175 1200 1200 1700 1725 1800
246.4 241.2 241.6 240.6 246.4 246.6 241.0 243.0 51.2 51.7 51.7 151.5 152.7 152.9 239.6 239.6 454.3 457.9 458.9 240.2 50.4 51.0 51.0
0.126 0.126 0.126 0.126 0.132 0.132 0.138 0.143 0.612 0.612 0.644 0.630 0.666 0.665 0.661 0.661 0.601 0.600 0.613 0.690 1.096 1.112 1.161
25.2 25.3 25.3 25.3 24.6 24.6 27.6 28.6 24.5 24.5 25.8 25.2 26.6 26.6 26.4 26.4 24.0 24.0 24.5 27.6 24.4 24.7 25.8
See below the table for a definition of the pulse current calculation. voltageðVÞ Pulse current ¼ SRðXÞ þPulse . SR = Simulator resistance = 1500 X. Nichrome resistanceðXÞ
*
Fig. 2. Scanning electron micrograph of a nichrome resistor failure after ESD pulsing. Note that the damage involves about 1/4 of the resistor body length. 5 lm 25 lm resistor blown at 229 V using a HBM pulse.
each micron of resistor width, the nichrome could withstand between 24 and 29 mA of instantaneous discharge current. ESD testing of nichrome resistors has produced entirely different-looking type of damage from long term lifetesting. The resulting physical degradation occurred at the contact metal interfaces or in the center of the resistors. The damage involved considerable areas of the resistor body from 20% to 90% of the element undergoing an appearance change. At the respective electrical threshold, the entire resistor body is often melted, and in some cases cratered. See Fig. 2 for an example of the style of damage observed after ESD pulsing [2]. 4. Definition of the appearance model The evolution of the relationship between applied stress and resulting appearance arose from two types of stress: lifetesting and ESD characterization. Lifetesting nichrome resistors involves controlled current density and temperature, whereas ESD testing involves stored charge on a capacitor which is rapidly discharged through the sample of interest. The two stresses resulted in very different appearances of the degraded devices – and thus the relationship was initiated. See Fig. 3.
Large
Area
Damage Appearance
0
Pulse
Line Small
Lifetest Long
Short
Stress Duration Fig. 3. Original hypothesis on the relationship between stress and resulting physical appearance of nichrome resistors.
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W.J. Roesch / Microelectronics Reliability 48 (2008) 958–964
5. Thin film resistors in circuits Based upon several biased circuit lifetests at temperatures up to 290 °C, the nichrome degradation matched elemental findings and resulted in a very thin line of damage located in the very center of the resistor, bridging from side-to-side and severing resistance from end-to-end. Subsequent lifetests of compound semiconductor integrated circuits, have occasionally involved nichrome resistors that are the highest thermally stressed elements in the circuit. Naturally, after lifetest, these highly stressed resistors have shown similar degradation [3]. See Fig. 4. On the other hand, ESD and EOS (Electrical OverStress) testing of circuits including of nichrome resistors has produced entirely different-looking type of damage. At the respective electrical threshold, large areas of the resistor body is often degraded, with an obvious change in appearance. Fig. 5 is an example of an individual resistor degraded under EOS conditions. These examples provide the basis of modeling the physical damage compared to different stress durations. For example, ESD and EOS, which are both short duration stresses resulted in damage to significant portions of the resistor. On the other hand, long term lifetesting of discrete resistors and integrated circuits have resulted in very long duration degradation which resulted in small area damage – usually a very distinct line bisecting the resistor body. Various circuit results accumulated over a 20 year span have continuously supported the model hypothesized in Fig. 3.
Fig. 6. Photomicrograph of an actual failure. This is a 3 lm 4.8 lm resistor for investigation. Note the similarity in appearance even though this resistor is 30 times smaller than the one in Fig. 4. For reference, the resistor damaged in this photo is identified as RB.
6. The challenge: new data that does not match the prevailing hypothesis During analysis of a routine device failure, a ‘‘line” type of appearance was detected. Upon subsequent investigation, the circuit was found to operate under normal conditions for a brief lifetime when the resistor degradation was noted. See Fig. 6. The history of this nichrome failure did not match the model shown in Fig. 3. In this case, the resistor failed with the appearance of a long duration stress, but the degradation was known to occur early in the lifetime under nominal use conditions. Based upon the challenge above, there could be several explanations: 1. The hypothesis for the long-standing model is wrong. 2. The device history is wrong. 3. There is an entirely different form of nichrome resistor degradation that does not match with the historical hypothesis. Fig. 4. Photomicrograph of a nichrome resistor failure after lifetesting in an integrated circuit. Note that the damage is confined to a thin line at the very center of the resistor. 1986 circuit design.
7. Preliminary simulation of the circuit in operation
Fig. 5. Optical photomicrograph of a nichrome resistor failure after rapid degradation. Note that the damage involves more than half the resistor body length. 5 lm 25 lm resistor blown by overstress.
For reference, the failing resistor is an 80 X element in the integrated circuit and is designated as RB. This resistor connects to the main circuit bias voltage on the first stage bias network. RB supplies current to the emitter follower output that feeds the base of the first stage RF transistor. As RB degrades, its resistance increases. In the actual circuit failures, the resistance had increased by more than 10 times the nominal value. An increase in RB resistance causes a decrease in the first stage output, which will lead to a decrease in the overall output of the circuit. The reduced power output is the failure mode that is reported. RB is constructed from a 3 lm wide nichrome resistor and has a current rating of 3 mA. The resistor RB is not connected in a manner that is susceptible to external stimulus to the device. In other words, the application of ESD pulses on the circuit eventually cause damage to other elements and RB is unaffected during ESD thresh-
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W.J. Roesch / Microelectronics Reliability 48 (2008) 958–964
1.6
m5
m4
1.4
I_RB (mA)
1.2
1.0
0.8
0.6 10
12
14
16
18
20
22
24
26
28
30
32
34
Pout (dB) Fig. 7. Simulation #1of current through nichrome resistor RB under nominal and maximum rated voltage conditions. For reference, the maximum rated current for this size resistor is 3 mA and the maximum power is limited at 28 dBm.
150Ω
the circuit, the design team confirmed that operation in the circuit itself could not possibly cause damage to the resistor. According to the design team, the resistor was adequately sized for all potential scenarios of circuit operation. For example, the current through RB was simulated at two operating conditions designated as m4 and m5. The m4 condition was at a nominal supply voltage (Vcc) of 3.4 V and the m5 condition was at a maximum rated supply voltage (Vcc) of 4.5 V. The simulation of current through RB during the m4 and m5 conditions is shown in Fig. 7. At a maximum power output of 28 dBm, the RB current simulation demonstrates the current will not exceed 1.0 mA. One milliamp is one-third of the rated current for RB.
150Ω
8. Circuit application data
old testing. The RB resistor is effectively ‘‘buried” within the circuit schematic to be shielded from external spikes or external overstress. The first step in analysis was to consult the circuit design team and verify the bias expectations. After various attempts to simulate Power Supply (-1.0V DC)
Curve Tracer (0 to +4.5V AC)
Vcc2
Vcc1
open
SP3T manual toggle
150Ω
Vreg
Power Supply (+2.65V DC)
DUT
18
gnd
16
Ven
17
Vmode
All other pins open
Fig. 8. Block diagram of bench test setup. This arrangement was used initially to duplicate the application conditions leading to device fallout. Toggling Ven was found to have a similar damaging effect as toggling Vreg.
This is where the duplication part of failure analysis comes in to play. First, the customer was consulted for clues as to sources of possible overstress. No new ideas were forthcoming. Being unable to simulate or understand any possible source of overstress, an application engineer was sent to visit the customer and measure all the applicable waveforms. During this interaction, the first clues were collected.
Current, mA
50 45 40 35 30 25 20 15 10 5 0 -5 0
2
1
3
time, usec Fig. 9. Simulation #2 for ‘‘out-of-sequence” bias condition. DC transient current prediction through 3 lm 4.8 lm (RB) resistor with Vcc = 4.4 V, Vreg = 2.85 V and toggle of Ven ‘‘on” with a 50 ns rise time.
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W.J. Roesch / Microelectronics Reliability 48 (2008) 958–964
While measuring the timing of control stimulus, it was determined that an unexpected sequence of signals was applied externally to the device. In general, RF input was being applied to, and detected from, the circuit while it was disabled. Specifically, the
device enable pin (Ven) was pulled low at some circumstances while RF stimulus was also being applied to the device. This stimulus was classified as an ‘‘out-of-sequence” bias condition. 9. Duplication experiments 9.1. Experiment #1. Circuit power on sequencing In order to duplicate the experience observed at the customer’s production test, a socket, two DC power supplies, and a curve tracer were assembled into a DC bench configuration. The basic bench configuration is shown in Fig. 8. Samples of the circuit were exercised under various stimuli to the three DUT control pins (VregVenVrmode) shown in Fig. 8. The damage was eventually duplicated simply by toggling the Vreg pin with RF applied. Armed with the knowledge that the damage could be duplicated by toggling a control pin with RF applied,
Fig. 10. Photomicrograph of the physical appearance of 3 lm 4.8 lm (RB) resistor damaged with enable pin (Ven) toggled on with nominal Vcc and Vreg voltage preexisting. Note this is an ‘‘out-of-sequence” logic condition. Compare this appearance to the actual fallout damage appearance in Fig. 6.
Table 2 Thin film resistor characteristics Resistor type
Size (W L)
Value
Cover layers
Lifetest element ESD elements Lifetest circuit RB (Actual fallout) Surrogate RB
5 lm 25 lm 7 Various 100 lm 150 lm 3 lm 4.8 lm 2 lm 2 lm
250 X Various 75 X 80 X 50 X
Nitride Nitride Nitride Nitride + BCB Nitride + BCB
Fig. 11. Photomicrograph of 2 lm 2 lm surrogate test structure used to evaluate damage stress relationship. Note the tiny resistor in the very center is already completely damaged in this sample.
BCB = divinylsiloxane bis-BenzoCycloButene.
2.50E-02
Current (A)
2.00E-02
1.50E-02
1.00E-02
5.00E-03
00 1. 03 0E +
00 1. 02 5E +
00 1. 02 0E +
00 1. 01 5E +
00 1. 01 0E +
00 1. 00 5E +
00 1. 00 0E +
9. 95 0E -
01
0.00E+00
Voltage (V) Fig. 12. Current and voltage characteristics of a 2 lm 2 lm surrogate resistor under ‘‘backed-off” DC bias conditions when degradation occurs.
W.J. Roesch / Microelectronics Reliability 48 (2008) 958–964
963
the design team was able to simulate the damage over a wide range of bias. While this was classified as an ‘‘out-of-sequence” bias condition, the sequence of pulling the enable control pin (Ven) low during RF bias was specifically modeled and found to produce between 23 and 43 mA of pulsed current across the test resistor for a time of less than 1.5 ls. See Fig. 9 for the simulated current through RB for the Ven ‘‘out-of-sequence” bias condition. Additional trials were able to reproduce the field failure (electrically and physically) with just a toggle of the Ven pin with nominal power supply voltage and a single bias pin enabled. An example of the physical damage to resistor RB is shown in Fig. 10. The physical appearance of the damage under these applied duplication conditions is nearly identical to the actual failure shown in Fig. 6.
Fig. 13. Photomicrograph showing the physical appearance of 2 lm 2 lm surrogate resistor damaged with ‘‘backed-off” ramp conditions under a 50% duty cycle.
Fig. 16. Example pulse shape to cause increase in resistance in a 2 lm 2 lm surrogate resistor damaged with 50 X impedance terminations. Note this pulse is much shorter and lower voltage than Fig. 14.
Fig. 14. Example pulse shape to cause increase in resistance of a 2 lm 2 lm surrogate resistor damaged with 1 MX impedance terminations. Note this is more than 10 V for approximately 1 ls.
Fig. 15. Photomicrograph of the physical appearance of 2 lm 2 lm surrogate resistor damaged with pulses applied under 1 MX impedance terminations. More than half of the resistor area is physically damaged.
Fig. 17. Photomicrograph of the physical appearance of 2 2 lm surrogate resistor damaged with 5 V, 150 ns pulses applied under 50 X impedance terminations. This Photomicrograph was digitally enhanced using a post-processing edge sharpening filter. Note: this damage appearance matches the style originally seen with longer duration aging.
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W.J. Roesch / Microelectronics Reliability 48 (2008) 958–964
Table 3 Various experimental results on the 50 X surrogate resistor using 50 X terminations ID
Pulse width (ns)
Peak voltage (V)
Aging duration
Final resistance
Appearance
1 2 3 4 5 6 7 8
120 130 140 150 150 150 150 150
2.2 2.5 2.8 3.0 3.0 3.0 3.0 5.0
2 min 25 s 20 s 5s 3 manual pulses 1 manual pulse 2 pulses 1 pulse
1 KX 2.5 KX 9.8 KX >10 KX 594 X No change 1900 X >1 KX
Damage starts at scope side Damage starts at scope side Damage starts at scope side Damage started in center of Blown at center No visible damage Blown at center Blown at center
of resistor of resistor of resistor resistor
9.2. Preliminary duplication background
9.6. Experiment #5: matched impedance pulsing
Samples of discrete resistors were obtained for experimentation. These surrogate samples are slightly different in size compared to the RB resistor, but the surrogates were very similar in size and construction. Comparisons of all the resistor types is shown in Table 2. To evaluate the degradation empirically, several experiments were conducted to investigate various types of stimulus and damage. A square wave with variable pulse width and duty cycle was used as the basic waveform. Applied Voltage levels, termination impedance of the instrumentation, applied pulse width, and duty cycle were investigated, as well as, single manual ‘‘square” pulses. The surrogate RB test structure is shown in Fig. 11.
Using a 50 X impedance terminations, smaller and shorter pulses were found to induce the desired damage. After tuning the pulse width and amplitude, a single pulse was discovered which could cause damage that duplicated the resistance increase and appearance of the original failure. See Fig. 16 for an example of a pulse that results in the desired resistance and appearance. Fig. 17 shows the surrogate resistor’s appearance after a 5 V, 150 ns pulse having the characteristics shown in Fig. 16. Several different resistor damage types were produced using different bias techniques. Some of the data collected is summarized in Table 3. Almost any type of physical damage could be produced just by minor variations in pulse and voltage characteristics.
9.3. Experiment #2: DC conditions By simply ramping voltage, it was determined that the resistor could instantaneously be damaged by current flow between 27 and 30 mA. In all trials at these conditions, the resistor was badly damaged and involved a complete darkening of the entire resistor body. These results matched the expectations of the model in Fig. 3. An abrupt event resulted in extreme physical damage and more than a 10x resistance increase with no exceptions. 9.4. Experiment #3: backed-off DC By carefully applying voltage, the surrogate 2 lm 2 lm resistor could be electrically degraded without significant visual damage. The resistor was slowly ramped from 0.9995 V to 1.025 V. In this voltage range, the resistor drew a peak current of 23.1 mA. With a 50% duty cycle ramp of 50 ms on, 50 ms off, over approximately 500 cycles (about 4 min) the resistor could be degraded. The resistance increased from approximately 45 X to about 2.35 KX. (See Fig. 12) Visual inspection discovered that the physical damage was quite similar to long term degradation and the failure of interest. (See Fig. 13) In other words, the damage was a faint narrow line bisecting the center of the resistor. This result did not match the model in Fig. 3 because it only took 4 min to produce the long stress type of appearance. These results were the first indication that experiments applying short term bias could produce damage appearance identical to damage seen under very long lifetest conditions. 9.5. Experiment #4: resistor pulsing with mis-matched impedance A wide variety of pulse shapes and pulse voltages were applied to surrogate resistors. A range of duty cycles were attempted, from 50% duty down to individual single pulses. Eventually, a series of pulses were able to induce an increase in resistance using the high impedance match. See Fig. 14. The appearance of the original failure was harder to achieve. Fig. 15 shows an example of the visual result.
10. Conclusions Using empirical trial and error, it was possible to produce damage appearances and resistance increases with a 150 ns pulse that looked just like long term degradation produced under high DC current, 6000 h, lifetest conditions. The range of physical damage observed on nichrome resistors is not directly related to the duration of the applied stress. It has been shown that all types of damage appearances can be produced with a few very short pulses. The original stress appearance hypothesis shown in Fig. 3 is false! This work reinforces the importance of using duplication as an analysis technique to recreate failures under controlled stress conditions. Even though historical generalizations are sometimes debunked, the cooperative efforts of applications, design, reliability, and failure analysis folks with the customer have resulted in discovery of the true root cause. Acknowledgements The author would like to thank Dorothy Hamada for performing ramp-to-failure and backed-off experiments for this investigation, Ray Pavio and Andy Forbes for their help in simulating and bench testing the resistor in an actual product, Sam Hammond for visiting the customer factory and providing applications support, and the TriQuint Reliability Group for accumulating historical data on nichrome resistor elements. Finally, the author would like to thank Steve Brockett and Tony Rubalcava for their helpful insights, assistance in performing accurate measurements, and advice in duplicating the failure. References [1] Bill Roesch, Douglas Stunkard. Proving GaAs reliability with IC element testing. In: Mantech conference; 1988. p. 91–5. [2] Anthony L. Rubalcava, Douglas Stunkard, Bill Roesch. Electrostatic discharge effects on GaAs ICs. In: EOS/ESD symposium, Las Vegas, NV; 1986. [3] Mike Peters, Bill Roesch. Studying lifetimes and failure rates of GaAs MMICs. Microwaves RF 1988.
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Forensic characterization of thin film resistor degradation William J. Roesch * TriQuint Semiconductor Inc., 2300 N.E. Brookwood Parkway, Hillsboro, OR 97124-5300, United States
a r t i c l e
i n f o
Article history: Received 20 December 2007 Received in revised form 1 February 2008 Available online 22 April 2008
a b s t r a c t Experienced reliability engineers and failure analysts often rely on visual aspects of degradation and destruction to reconstruct events leading up to failure of semiconductor circuit elements. Often, the resulting theories about failure causes are tested by duplication experiments. These re-creations are typically evaluated and compared using those same visual attributes. This study is intended to establish the historical basis for visual comparison of nichrome resistor failures (a Rogues gallery of broken resistors) and then debunk correlation theories with simulations and empirical failure duplication results. The results will show that various visual failure characteristics can be reproduced by an unexpectedly wide range of applied stimulus. The final appearance of a ‘‘dead” resistor does not always portray how the part was ‘‘killed”. Ó 2008 Elsevier Ltd. All rights reserved.
1. Introduction One of the most valuable techniques of root cause failure analysis is to perform a good visual inspection of a circuit and compare anomalies to previous experiences with degradation. Often, a good ‘‘look” is the key to a diagnosis. Over time, these experiences accumulate into a mental catalog. Eventually, some relationships between cause and effect are developed into theories. However, the relationships may be only a loose association of anecdotes or stories which grow into expectations. The accumulation of historical data and experiences build evidence to support a theory, but if the hypotheses are not tested scientifically, then they are nothing more than lore, myths, and legends. Engineers and scientists become technical myth-busters when they apply scientific methods to decide the validity of a hypothesis. Essentially, they become forensic failure analysts. Previous work on degradation of nichrome resistors utilized within compound semiconductor integrated circuits has built an experienced-based expectation of cause and effect between applied stresses and resulting appearance of resistor elements. This work investigates various stress conditions and provides additional data on the physical appearance of degraded resistors. This investigation compares an original observed relationship using a failure analysis technique called ‘‘duplication”. Discrete resistors are subjected to various stresses in order to duplicate the physical and electrical damage which was previously discov-
Abbreviations: NiCr, nickel chrome = ‘‘nichrome”; RF, radio frequency; ESD, electrostatic discharge; EOS, electrical overstress; HBM, human body model; DC, direct current; BCB, divinylsiloxane bis-BenzoCycloButene. * Tel.: +1 503 615 9292; fax: +1 503 615 8903. E-mail address: [email protected] 0026-2714/$ - see front matter Ó 2008 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2008.02.002
ered in a customer’s application. Without the effort to duplicate the appearance, the damage could not be explained by the historical relationship. Subsequent experiments and measurements eventually show that the original hypothesized relationship did not exist after-all. 2. Lifetesting history of thin film resistors Thin film resistors are common elements in analog and high frequency circuits. In compound semiconductors, the resistors can be constructed from nickel chrome, tantalum nitride, silicon chrome, or other elements. This investigation is a look at nickel chrome or ‘‘nichrome” resistors. During initial characterization, the nichrome resistors were studied as individual circuit elements. Independent temperature and current density tests were performed on populations of 70 nichrome resistors. Biased resistor temperatures were measured using an infrared thermal imager. Drift testing was performed using temperature and DC current density variables. Three temperature conditions lasting 24 h and three current densities conditions lasting 24 h were conducted. The resistors changed less than 0.4% during any of the five independent stress conditions. Drift testing resulted in very little change in resistance in reasonable lifetimes. Acceleration factor testing resulted in similar data to the drift results. Full lifetesting has been performed on nichrome resistors at 125 °C, 150 °C, 175 °C, and 200 °C at a bias inducing the maximum rated current density and also without any electrical bias. Electrical results of the latest lifetest are shown in Fig. 1 [1]. No failures could be generated after 6000 h of aging under maximum rated current density at temperatures up to 200 °C. The resistance increase degradation appears to be logarithmic with
959
Resistance Change (Percent)
W.J. Roesch / Microelectronics Reliability 48 (2008) 958–964
1.0% 0.9% 0.8% 0.7% 0.6%
200ºC
0.5%
175ºC
0.4%
150ºC
0.3%
125ºC
0.2% 0.1% 0.0% 1000
2000
3000
4000
5000
6000
Lifetest Duration (Hours) Fig. 1. Electrical degradation results of accelerated lifetesting on nichrome resistors. These tests were conducted at the temperatures shown, and under maximum rated current density.
time. Projection of the median life is based on this 6000 h trend results in an activation energy of 1.0 eV. The failure mechanism is expected to be electromigration. Extended biased lifetests of individual resistors were subsequently performed at temperatures up to 290 °C. Physical degradation resulted in a very thin line of damage located in the very center of the resistor, bridging from side-to-side and severing resistance from end-to-end. 3. Electrostatic discharge testing history of thin film resistors Several sizes of nichrome resistors were subjected to ESD (Electrostatic Discharge) pulses generated from a HBM (Human Body Model) simulator. This size of resistors varied from 125 lm2 to 6875 lm2. Resistance changes of 4% and greater were considered failures. A total of 24 resistors were pulsed with increasing voltages until failure. The ESD susceptibility was consistently dependent of the width of the resistor. See Table 1. As an example, for
Table 1 Instantaneous current required to cause failure in nichrome resistors Nichrome width (lm)
Pulse voltage (V)
Resistance (X)
Pulse current* (Amps)
Current per lm (mA/lm)
5 5 5 5 5 5 5 5 25 25 25 25 25 25 25 25 25 25 25 25 45 45 45
220 220 220 220 230 230 240 250 950 950 1000 1040 1100 1100 1150 1150 1175 1175 1200 1200 1700 1725 1800
246.4 241.2 241.6 240.6 246.4 246.6 241.0 243.0 51.2 51.7 51.7 151.5 152.7 152.9 239.6 239.6 454.3 457.9 458.9 240.2 50.4 51.0 51.0
0.126 0.126 0.126 0.126 0.132 0.132 0.138 0.143 0.612 0.612 0.644 0.630 0.666 0.665 0.661 0.661 0.601 0.600 0.613 0.690 1.096 1.112 1.161
25.2 25.3 25.3 25.3 24.6 24.6 27.6 28.6 24.5 24.5 25.8 25.2 26.6 26.6 26.4 26.4 24.0 24.0 24.5 27.6 24.4 24.7 25.8
See below the table for a definition of the pulse current calculation. voltageðVÞ Pulse current ¼ SRðXÞ þPulse . SR = Simulator resistance = 1500 X. Nichrome resistanceðXÞ
*
Fig. 2. Scanning electron micrograph of a nichrome resistor failure after ESD pulsing. Note that the damage involves about 1/4 of the resistor body length. 5 lm 25 lm resistor blown at 229 V using a HBM pulse.
each micron of resistor width, the nichrome could withstand between 24 and 29 mA of instantaneous discharge current. ESD testing of nichrome resistors has produced entirely different-looking type of damage from long term lifetesting. The resulting physical degradation occurred at the contact metal interfaces or in the center of the resistors. The damage involved considerable areas of the resistor body from 20% to 90% of the element undergoing an appearance change. At the respective electrical threshold, the entire resistor body is often melted, and in some cases cratered. See Fig. 2 for an example of the style of damage observed after ESD pulsing [2]. 4. Definition of the appearance model The evolution of the relationship between applied stress and resulting appearance arose from two types of stress: lifetesting and ESD characterization. Lifetesting nichrome resistors involves controlled current density and temperature, whereas ESD testing involves stored charge on a capacitor which is rapidly discharged through the sample of interest. The two stresses resulted in very different appearances of the degraded devices – and thus the relationship was initiated. See Fig. 3.
Large
Area
Damage Appearance
0
Pulse
Line Small
Lifetest Long
Short
Stress Duration Fig. 3. Original hypothesis on the relationship between stress and resulting physical appearance of nichrome resistors.
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5. Thin film resistors in circuits Based upon several biased circuit lifetests at temperatures up to 290 °C, the nichrome degradation matched elemental findings and resulted in a very thin line of damage located in the very center of the resistor, bridging from side-to-side and severing resistance from end-to-end. Subsequent lifetests of compound semiconductor integrated circuits, have occasionally involved nichrome resistors that are the highest thermally stressed elements in the circuit. Naturally, after lifetest, these highly stressed resistors have shown similar degradation [3]. See Fig. 4. On the other hand, ESD and EOS (Electrical OverStress) testing of circuits including of nichrome resistors has produced entirely different-looking type of damage. At the respective electrical threshold, large areas of the resistor body is often degraded, with an obvious change in appearance. Fig. 5 is an example of an individual resistor degraded under EOS conditions. These examples provide the basis of modeling the physical damage compared to different stress durations. For example, ESD and EOS, which are both short duration stresses resulted in damage to significant portions of the resistor. On the other hand, long term lifetesting of discrete resistors and integrated circuits have resulted in very long duration degradation which resulted in small area damage – usually a very distinct line bisecting the resistor body. Various circuit results accumulated over a 20 year span have continuously supported the model hypothesized in Fig. 3.
Fig. 6. Photomicrograph of an actual failure. This is a 3 lm 4.8 lm resistor for investigation. Note the similarity in appearance even though this resistor is 30 times smaller than the one in Fig. 4. For reference, the resistor damaged in this photo is identified as RB.
6. The challenge: new data that does not match the prevailing hypothesis During analysis of a routine device failure, a ‘‘line” type of appearance was detected. Upon subsequent investigation, the circuit was found to operate under normal conditions for a brief lifetime when the resistor degradation was noted. See Fig. 6. The history of this nichrome failure did not match the model shown in Fig. 3. In this case, the resistor failed with the appearance of a long duration stress, but the degradation was known to occur early in the lifetime under nominal use conditions. Based upon the challenge above, there could be several explanations: 1. The hypothesis for the long-standing model is wrong. 2. The device history is wrong. 3. There is an entirely different form of nichrome resistor degradation that does not match with the historical hypothesis. Fig. 4. Photomicrograph of a nichrome resistor failure after lifetesting in an integrated circuit. Note that the damage is confined to a thin line at the very center of the resistor. 1986 circuit design.
7. Preliminary simulation of the circuit in operation
Fig. 5. Optical photomicrograph of a nichrome resistor failure after rapid degradation. Note that the damage involves more than half the resistor body length. 5 lm 25 lm resistor blown by overstress.
For reference, the failing resistor is an 80 X element in the integrated circuit and is designated as RB. This resistor connects to the main circuit bias voltage on the first stage bias network. RB supplies current to the emitter follower output that feeds the base of the first stage RF transistor. As RB degrades, its resistance increases. In the actual circuit failures, the resistance had increased by more than 10 times the nominal value. An increase in RB resistance causes a decrease in the first stage output, which will lead to a decrease in the overall output of the circuit. The reduced power output is the failure mode that is reported. RB is constructed from a 3 lm wide nichrome resistor and has a current rating of 3 mA. The resistor RB is not connected in a manner that is susceptible to external stimulus to the device. In other words, the application of ESD pulses on the circuit eventually cause damage to other elements and RB is unaffected during ESD thresh-
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1.6
m5
m4
1.4
I_RB (mA)
1.2
1.0
0.8
0.6 10
12
14
16
18
20
22
24
26
28
30
32
34
Pout (dB) Fig. 7. Simulation #1of current through nichrome resistor RB under nominal and maximum rated voltage conditions. For reference, the maximum rated current for this size resistor is 3 mA and the maximum power is limited at 28 dBm.
150Ω
the circuit, the design team confirmed that operation in the circuit itself could not possibly cause damage to the resistor. According to the design team, the resistor was adequately sized for all potential scenarios of circuit operation. For example, the current through RB was simulated at two operating conditions designated as m4 and m5. The m4 condition was at a nominal supply voltage (Vcc) of 3.4 V and the m5 condition was at a maximum rated supply voltage (Vcc) of 4.5 V. The simulation of current through RB during the m4 and m5 conditions is shown in Fig. 7. At a maximum power output of 28 dBm, the RB current simulation demonstrates the current will not exceed 1.0 mA. One milliamp is one-third of the rated current for RB.
150Ω
8. Circuit application data
old testing. The RB resistor is effectively ‘‘buried” within the circuit schematic to be shielded from external spikes or external overstress. The first step in analysis was to consult the circuit design team and verify the bias expectations. After various attempts to simulate Power Supply (-1.0V DC)
Curve Tracer (0 to +4.5V AC)
Vcc2
Vcc1
open
SP3T manual toggle
150Ω
Vreg
Power Supply (+2.65V DC)
DUT
18
gnd
16
Ven
17
Vmode
All other pins open
Fig. 8. Block diagram of bench test setup. This arrangement was used initially to duplicate the application conditions leading to device fallout. Toggling Ven was found to have a similar damaging effect as toggling Vreg.
This is where the duplication part of failure analysis comes in to play. First, the customer was consulted for clues as to sources of possible overstress. No new ideas were forthcoming. Being unable to simulate or understand any possible source of overstress, an application engineer was sent to visit the customer and measure all the applicable waveforms. During this interaction, the first clues were collected.
Current, mA
50 45 40 35 30 25 20 15 10 5 0 -5 0
2
1
3
time, usec Fig. 9. Simulation #2 for ‘‘out-of-sequence” bias condition. DC transient current prediction through 3 lm 4.8 lm (RB) resistor with Vcc = 4.4 V, Vreg = 2.85 V and toggle of Ven ‘‘on” with a 50 ns rise time.
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While measuring the timing of control stimulus, it was determined that an unexpected sequence of signals was applied externally to the device. In general, RF input was being applied to, and detected from, the circuit while it was disabled. Specifically, the
device enable pin (Ven) was pulled low at some circumstances while RF stimulus was also being applied to the device. This stimulus was classified as an ‘‘out-of-sequence” bias condition. 9. Duplication experiments 9.1. Experiment #1. Circuit power on sequencing In order to duplicate the experience observed at the customer’s production test, a socket, two DC power supplies, and a curve tracer were assembled into a DC bench configuration. The basic bench configuration is shown in Fig. 8. Samples of the circuit were exercised under various stimuli to the three DUT control pins (VregVenVrmode) shown in Fig. 8. The damage was eventually duplicated simply by toggling the Vreg pin with RF applied. Armed with the knowledge that the damage could be duplicated by toggling a control pin with RF applied,
Fig. 10. Photomicrograph of the physical appearance of 3 lm 4.8 lm (RB) resistor damaged with enable pin (Ven) toggled on with nominal Vcc and Vreg voltage preexisting. Note this is an ‘‘out-of-sequence” logic condition. Compare this appearance to the actual fallout damage appearance in Fig. 6.
Table 2 Thin film resistor characteristics Resistor type
Size (W L)
Value
Cover layers
Lifetest element ESD elements Lifetest circuit RB (Actual fallout) Surrogate RB
5 lm 25 lm 7 Various 100 lm 150 lm 3 lm 4.8 lm 2 lm 2 lm
250 X Various 75 X 80 X 50 X
Nitride Nitride Nitride Nitride + BCB Nitride + BCB
Fig. 11. Photomicrograph of 2 lm 2 lm surrogate test structure used to evaluate damage stress relationship. Note the tiny resistor in the very center is already completely damaged in this sample.
BCB = divinylsiloxane bis-BenzoCycloButene.
2.50E-02
Current (A)
2.00E-02
1.50E-02
1.00E-02
5.00E-03
00 1. 03 0E +
00 1. 02 5E +
00 1. 02 0E +
00 1. 01 5E +
00 1. 01 0E +
00 1. 00 5E +
00 1. 00 0E +
9. 95 0E -
01
0.00E+00
Voltage (V) Fig. 12. Current and voltage characteristics of a 2 lm 2 lm surrogate resistor under ‘‘backed-off” DC bias conditions when degradation occurs.
W.J. Roesch / Microelectronics Reliability 48 (2008) 958–964
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the design team was able to simulate the damage over a wide range of bias. While this was classified as an ‘‘out-of-sequence” bias condition, the sequence of pulling the enable control pin (Ven) low during RF bias was specifically modeled and found to produce between 23 and 43 mA of pulsed current across the test resistor for a time of less than 1.5 ls. See Fig. 9 for the simulated current through RB for the Ven ‘‘out-of-sequence” bias condition. Additional trials were able to reproduce the field failure (electrically and physically) with just a toggle of the Ven pin with nominal power supply voltage and a single bias pin enabled. An example of the physical damage to resistor RB is shown in Fig. 10. The physical appearance of the damage under these applied duplication conditions is nearly identical to the actual failure shown in Fig. 6.
Fig. 13. Photomicrograph showing the physical appearance of 2 lm 2 lm surrogate resistor damaged with ‘‘backed-off” ramp conditions under a 50% duty cycle.
Fig. 16. Example pulse shape to cause increase in resistance in a 2 lm 2 lm surrogate resistor damaged with 50 X impedance terminations. Note this pulse is much shorter and lower voltage than Fig. 14.
Fig. 14. Example pulse shape to cause increase in resistance of a 2 lm 2 lm surrogate resistor damaged with 1 MX impedance terminations. Note this is more than 10 V for approximately 1 ls.
Fig. 15. Photomicrograph of the physical appearance of 2 lm 2 lm surrogate resistor damaged with pulses applied under 1 MX impedance terminations. More than half of the resistor area is physically damaged.
Fig. 17. Photomicrograph of the physical appearance of 2 2 lm surrogate resistor damaged with 5 V, 150 ns pulses applied under 50 X impedance terminations. This Photomicrograph was digitally enhanced using a post-processing edge sharpening filter. Note: this damage appearance matches the style originally seen with longer duration aging.
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Table 3 Various experimental results on the 50 X surrogate resistor using 50 X terminations ID
Pulse width (ns)
Peak voltage (V)
Aging duration
Final resistance
Appearance
1 2 3 4 5 6 7 8
120 130 140 150 150 150 150 150
2.2 2.5 2.8 3.0 3.0 3.0 3.0 5.0
2 min 25 s 20 s 5s 3 manual pulses 1 manual pulse 2 pulses 1 pulse
1 KX 2.5 KX 9.8 KX >10 KX 594 X No change 1900 X >1 KX
Damage starts at scope side Damage starts at scope side Damage starts at scope side Damage started in center of Blown at center No visible damage Blown at center Blown at center
of resistor of resistor of resistor resistor
9.2. Preliminary duplication background
9.6. Experiment #5: matched impedance pulsing
Samples of discrete resistors were obtained for experimentation. These surrogate samples are slightly different in size compared to the RB resistor, but the surrogates were very similar in size and construction. Comparisons of all the resistor types is shown in Table 2. To evaluate the degradation empirically, several experiments were conducted to investigate various types of stimulus and damage. A square wave with variable pulse width and duty cycle was used as the basic waveform. Applied Voltage levels, termination impedance of the instrumentation, applied pulse width, and duty cycle were investigated, as well as, single manual ‘‘square” pulses. The surrogate RB test structure is shown in Fig. 11.
Using a 50 X impedance terminations, smaller and shorter pulses were found to induce the desired damage. After tuning the pulse width and amplitude, a single pulse was discovered which could cause damage that duplicated the resistance increase and appearance of the original failure. See Fig. 16 for an example of a pulse that results in the desired resistance and appearance. Fig. 17 shows the surrogate resistor’s appearance after a 5 V, 150 ns pulse having the characteristics shown in Fig. 16. Several different resistor damage types were produced using different bias techniques. Some of the data collected is summarized in Table 3. Almost any type of physical damage could be produced just by minor variations in pulse and voltage characteristics.
9.3. Experiment #2: DC conditions By simply ramping voltage, it was determined that the resistor could instantaneously be damaged by current flow between 27 and 30 mA. In all trials at these conditions, the resistor was badly damaged and involved a complete darkening of the entire resistor body. These results matched the expectations of the model in Fig. 3. An abrupt event resulted in extreme physical damage and more than a 10x resistance increase with no exceptions. 9.4. Experiment #3: backed-off DC By carefully applying voltage, the surrogate 2 lm 2 lm resistor could be electrically degraded without significant visual damage. The resistor was slowly ramped from 0.9995 V to 1.025 V. In this voltage range, the resistor drew a peak current of 23.1 mA. With a 50% duty cycle ramp of 50 ms on, 50 ms off, over approximately 500 cycles (about 4 min) the resistor could be degraded. The resistance increased from approximately 45 X to about 2.35 KX. (See Fig. 12) Visual inspection discovered that the physical damage was quite similar to long term degradation and the failure of interest. (See Fig. 13) In other words, the damage was a faint narrow line bisecting the center of the resistor. This result did not match the model in Fig. 3 because it only took 4 min to produce the long stress type of appearance. These results were the first indication that experiments applying short term bias could produce damage appearance identical to damage seen under very long lifetest conditions. 9.5. Experiment #4: resistor pulsing with mis-matched impedance A wide variety of pulse shapes and pulse voltages were applied to surrogate resistors. A range of duty cycles were attempted, from 50% duty down to individual single pulses. Eventually, a series of pulses were able to induce an increase in resistance using the high impedance match. See Fig. 14. The appearance of the original failure was harder to achieve. Fig. 15 shows an example of the visual result.
10. Conclusions Using empirical trial and error, it was possible to produce damage appearances and resistance increases with a 150 ns pulse that looked just like long term degradation produced under high DC current, 6000 h, lifetest conditions. The range of physical damage observed on nichrome resistors is not directly related to the duration of the applied stress. It has been shown that all types of damage appearances can be produced with a few very short pulses. The original stress appearance hypothesis shown in Fig. 3 is false! This work reinforces the importance of using duplication as an analysis technique to recreate failures under controlled stress conditions. Even though historical generalizations are sometimes debunked, the cooperative efforts of applications, design, reliability, and failure analysis folks with the customer have resulted in discovery of the true root cause. Acknowledgements The author would like to thank Dorothy Hamada for performing ramp-to-failure and backed-off experiments for this investigation, Ray Pavio and Andy Forbes for their help in simulating and bench testing the resistor in an actual product, Sam Hammond for visiting the customer factory and providing applications support, and the TriQuint Reliability Group for accumulating historical data on nichrome resistor elements. Finally, the author would like to thank Steve Brockett and Tony Rubalcava for their helpful insights, assistance in performing accurate measurements, and advice in duplicating the failure. References [1] Bill Roesch, Douglas Stunkard. Proving GaAs reliability with IC element testing. In: Mantech conference; 1988. p. 91–5. [2] Anthony L. Rubalcava, Douglas Stunkard, Bill Roesch. Electrostatic discharge effects on GaAs ICs. In: EOS/ESD symposium, Las Vegas, NV; 1986. [3] Mike Peters, Bill Roesch. Studying lifetimes and failure rates of GaAs MMICs. Microwaves RF 1988.