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Formation and assembly of carbon nanotube bumps for interconnection applications
Diamond & Related Materials 18 (2009) 1109–1113
Contents lists available at ScienceDirect
Diamond & Related Materials j o u r n a l h o m e p a g e : w w w. e l s ev i e r. c o m / l o c a t e / d i a m o n d
Formation and assembly of carbon nanotube bumps for interconnection applications K.P. Yung a,b,⁎, J. Wei a, B.K. Tay b a b
Singapore Institute of Manufacturing Technology, 71 Nanyang Drive, Singapore 638075, Singapore School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798, Singapore
a r t i c l e
i n f o
Article history: Received 7 October 2008 Received in revised form 4 January 2009 Accepted 9 February 2009 Available online 24 February 2009 Keywords: Carbon Nanotubes Flip Chip Interconnects Joining
a b s t r a c t A simple assembly process of carbon nanotube (CNT) bumps which could be used for flip chip interconnects was proposed and investigated. Firstly, high density aligned CNT bumps were grown on both top and bottom substrates. By employing typical flip chip bonding technique, the CNT bumps on the flipped top substrate were aligned with those on the bottom substrate. Applying a downward force on the die, the CNT bumps on the top substrate were pressed and inserted into the CNT bumps on the bottom substrate. After CNT insertion, the CNTs were held together with van der Waals force and the CNT interconnection bumps were formed. The electrical conductivity of the CNT interconnection bumps was measured and compared to conductive silver adhesive. The conductivity of CNT interconnection bump was found to be of many magnitudes higher than that of silver adhesive. It was demonstrated that the CNT bumps have a much superior electrical properties over the typical metallic bumps. © 2009 Elsevier B.V. All rights reserved.
1. Introduction Lead-content found in common solder poses various problems for interconnect application. Although the use of lead can maximize material strength, and increase resistance to creep [1], toxicity of lead [2] is not eco-friendly [3,4]. Lead free alternatives, such as conductive adhesive [5], tin–silver–copper [6,7] and tin–copper [8], were developed to replace tin–lead solder interconnection materials [9,10]. Nevertheless, lead-free solder has disadvantages such as higher melting temperature and low metal surface wettability. Performance wise, lead-free solder properties are close to that of typical solder, with similar electrical, thermal and mechanical characteristics. In the quest for product miniaturization, integrated circuit (IC) size reduction is inversely proportional to device density [11–13]. As circuit density increases, the number of input/output (I/O) pins on IC packaging increases exponentially with significant drop in pin pitch [14,15]. According to International Technology Roadmap for Semiconductors (ITRS) [16], the number of packaged pins per chip will continue to increase at approximately 10% each year and will approach as high as 5000 pins for high performance ICs in the coming decade. The peripheral I/O flip chip direct chip attach is predicted to scale down to b20 µm pitch and area array flip chip packaging is expected to reach 100 µm pitch by the year of 2014. At this scale, current interconnection technology will become an obstacle to provide reliable high speed connections for smaller devices. To address these problems, metal wire-bumped and metal adhesive flip chip connec⁎ Corresponding author. Singapore Institute of Manufacturing Technology, 71 Nanyang Drive, Singapore 638075, Singapore. Tel.: +65 90037083; fax: +65 67933318. E-mail address: [email protected] (K.P. Yung). 0925-9635/$ – see front matter © 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.diamond.2009.02.022
tions [17,18] were developed. Metal or metal adhesive bumps [5,19] were formed using conventional flip chip bonding equipment as packaging interconnects. Those techniques offer application simplicity because they enable direct bumping and only require equipment that are widely available. In addition, metal also has a much higher electrical and thermal conductivity compared to solder. However, as interconnect miniaturization continues, electromigration and reliability issue will be more apparent when current density in metal interconnection surges. Carbon nanotubes (CNTs) are one dimensional nanowire with superior electrical, thermal and mechanical properties. CNTs are also non-toxic [20]. For these reasons, they have been considered as future building block materials for many active and passive components within electronic devices [21–24]. In particular, with CNT nano feature size and high resistance to electromigration, they are an ideal material for fabricating sub-micro or nano flip chip interconnects with outstanding performance. 2. Experimental detail Fig. 1 illustrates the fabrication process sequence of CNT interconnection bumps. Aligned carbon nanotube (ACNT) film is deposited onto two identical Ni coated Cr/Al electrode surfaces, with p-type silicon b100N wafer with 500 nm thermal oxide used as the top and bottom substrates. A 30 nm thick of Ni catalyst layer is applied for growing CNT forest with a desired density of 6 tubes/µm2 [25]. The 100 nm/1 µm thick of Cr/Al electrode layer and 30 nm thick of nickel catalyst layer are pre-deposited onto the top and bottom substrates by magnetron sputtering at room temperature. A plasma enhanced chemical vapor deposition (PECVD) system is used to synthesize the
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K.P. Yung et al. / Diamond & Related Materials 18 (2009) 1109–1113
3. Results and discussion
Fig. 1. Illustration of CNT insertion process sequence (a–c), top view of the assembled sample (d), and cross-sectional view of the assembled sample (e).
CNTs. Once the base pressure of 2E− 2 mbar is achieved in the PECVD chamber, ammonia is introduced at a flow rate of 240 sccm. The pressure inside the plasma chamber is maintained at 2.9 mbar. All samples are heated to 800 °C and annealed for 2 min. Subsequently, acetylene is allowed into the chamber at a flow rate of 60 sccm to initiate ACNT growth and a 500 V of biased voltage is applied for vertically aligning the CNTs. The chamber pressure is kept constant at 8.2 mbar, throughout the 60 min CNT growth process. To assemble CNT bumps, the sample surfaces with the ACNTs are faced each other in angular alignment, as observed with a low power microscope. Different insertion lengths of the contacted CNT between the top and bottom substrates are accomplished by placing different amounts of weight onto the top substrate. This weight is then removed from the structure. Once interlocking has taken place, the top substrate is supported by the bottom substrate and the two substrates are considered “joined”. The minimum load applied for interlocking is 0.03 g which is benefited from the top substrate's weight and the maximum load used is 3.00003 kg. The cross sectional images of the assembled samples are observed using a high-resolution scanning electron microscope (SEM, JEOL JSM5910LV) for determining the length of CNT penetration region. Electrical properties of the “inserted” structure are measured by four point probe technique using Keithly 230 programmable voltage source and Keithly 590 CV analyzer. A current is applied across the “inserted” CNTs through probes 1 and 2, which are connected to one side of the top and bottom CNT substrates, respectively. The voltage drop of the CNTs is then measured between probes 3 and 4, which are connected to the other end of the top and bottom substrates, respectively. An illustration of the measurement set up is shown in Fig. 2 and the applied current ranges from 50 mA to − 50 mA with a 10 mA interval. Reference sample was prepared using silver adhesive as the interconnect material with similar set up. This sample is used as benchmark and the electrical performance is compared to that of the “inserted” CNT structure. Repeated cycles of measurements were performed for all samples to check the consistency of the data.
The morphology of vertically grown primary ACNTs that are prepared for the assembly process is presented in Fig. 3a. The ACNTs have a uniform diameter of around 200 nm and a uniform length of around 15 µm. During the initial stage of the CNT assembly process, an axial compression force is applied, which caused the hollow graphene body of CNTs to undergo structural deformation and buckling [26,27]. Such deformations enable the tubes to be squeezed into the air space within the other CNT bump and allowing penetration to occur. When the compress force is released, all deformed CNTs would expand, attempting to regain their original shape. However, there is not enough air space for the spontaneous “regaining” action of the tubes and they can only take up the shape of the available space between them and their neighboring tubes. With the nanotubes from both bumps fitted tightly to each other, the CNT bumps are mechanically interlocked. For interconnect application, the adhesion strength of the assembled structure needs to be strong mechanically and this strength can be obtained from interlocked CNT formed under the following conditions. First, the volume ratio of CNTs to air space on both side of the CNT bumps needs to be at most 1:1. This will ensure minimal air space between the penetrated CNT structures. The larger the CNT diameter is, the lower the CNT density is needed. Next, the ideal length of the CNT bump should be N10 µm, which would provide enough interaction length for interlocking the CNTs. Fig. 3b–e illustrates the interpenetrated and interlocked CNT bumps from top and bottom substrates. Predictably, the degree of interpenetration of the CNT bumps has shown to be consistent with the amount of the assembly force applied. The corresponding “penetration” length to the amount of assembly force is shown in Table 1. SEM results in Fig. 3b show the penetration of CNT in test vehicle 1, under no additional loading condition. In this condition with only the weight of the substrate at 0.03 g acting on it, the CNT penetration length is measured to be around 3.5 µm (~ 23% of the CNTs length). Whereas for test vehicle 4, shown in Fig. 3e, the largest assembly weight of 3.00003 kg has enabled full interpenetration length of 15 µm. The CNT bump that has went through 50 cycles of interpenetration and detach process is presented in Fig. 3f. The SEM image shows that the interpenetration action does not cause any damage to the CNT bump structure. The process is considered reworkable and it allows easy readjustment and replacement of components if used as interconnects for flip chip packaging. For interconnection applications, the desired contact resistance between the interconnect bump and bond pad or electrode should be
Fig. 2. A schematic of the four-point-probe measurement set-up. The current is applied through probes 1 and 2 and the voltages measured between probes 3 and 4.
K.P. Yung et al. / Diamond & Related Materials 18 (2009) 1109–1113
1111
Fig. 3. SEM images, with scale-bar of 2 µm, of the as grown CNT bump (a), the cross sectional views, with scale-bar of 5 µm, of the CNT structures after their assembly process: test vehicle 1 (b), test vehicle 2 (c), test vehicle 3 (d) and test vehicle 4 (e), and the images with scale-bar of 2 µm of the CNT bump that has went through 50 cycles of interpenetration and detachment processes (f).
as low as possible. Conventional way of joining CNT bumps by metallic adhesive [28] may provide reasonable mechanical adhesion, however, problems such as high contact resistance often arises. The unique electronic structure of nanotubes gives rise to high contact resistance, which is caused by weak electronic coupling at the Fermi surface between the weakly bonded metal to the tip CNTs [29–31]. Improved electron transport is feasible using the penetration method, as the weak metal–CNT contacts are replaced by the CNT–CNT contacts. The electrical behavior of CNT–CNT contacts is predicated to resemble directional graphene–graphene stacking. A simple four point probe measurement set up for measuring the current to voltage (I–V) Table 1 The corresponding “penetration” length of CNTs versus the assembly force. Test vehicle
1
2
3
4
Force (kg) Penetration length (µm)
0.00003 3.6
1.00003 7.3
2.00003 11.1
3.00003 15
characteristic of CNT test vehicles is shown in Fig. 2. The measured voltages are presented in Fig. 4, with applied current varying from 50 mA to −50 mA. The measured resistance value is composed of the probe-to-electrode contact resistances, the electrode-to-CNT contact resistances, and the intrinsic resistance of the CNT bump. Hence, the obtained results are analyzed by comparing to that of a test vehicle with silver adhesive as interconnect material. The linear I–V curve in Fig. 4b indicates the metallic characteristic of the as-grown multiwalled CNTs as well as the ohmic contacts between the CNTs. The resistance of the CNT test vehicle is found to be magnitudes lower than that of test vehicle with silver adhesive as presented in Fig. 4a. The experimental measurements above show that the CNT bumps have a much lower intrinsic resistance than typical metal. The total contact resistance presented in the CNT system is much lower to that of the other test vehicle using silver adhesive contact. The resistance of the inserted CNT structure is also found to decrease with the increase in the penetration depth as presented in Fig. 4. The linear decrease in resistance with increase in penetration depth proves that CNT–CNT
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contacts are having metallic behavior and are ohmic. The lower resistance measured from the interpenetrated CNT structure has demonstrated the advantage of our approach in creating low contact resistance, CNT-based interconnects. In addition, the contact length dependent conductance of the “inserted” CNT structure would be useful for various microsystems. The reattachable laminating properties created with this technique are also applicable to fastening nano devices similar to that of typical Velcro®. 4. Proposed CNT flip chip interconnect formation process The CNT ‘insertion” technique can be used as interconnection bump for flip chip packaging system. A schematic of the proposed CNT interconnect formation is depicted in Fig. 5a–c. For fabricating CNT flip chip interconnection, metallization layers followed by catalyst layer on IC die and its carrier are first deposited. Lithography technique is used for patterning the metallization layers and catalyst layer as presented in Fig. 5a. Upon removal of the mask and the formation of patterned metallization layers and catalyst layer, ACNTs are grown on the patterned IC and carrier (Fig. 5b). Subsequently, the IC can be flipped and aligned with its carrier for bonding (Fig. 5c). With an appropriate force applied onto the substrate, the CNT bumps will be inserted and joined as shown in Fig. 5d. 5. Conclusions Simple insertion assembly technique for CNT bumps leads to the formation of highly electrical conductive structure for flip chip
Fig. 5. Proposed CNT insertion process for flip chip application. Deposition of under CNT metallization and catalyst layer (a), deposition of CNTs (b), align die to its carrier (c), and assembly of die to its carrier with downward force (d).
interconnects application. The CNT bumps from top and bottom substrates have shown to adhere well to each other and exhibit low contact resistance. The measured total resistance is lower than that of silver adhesive, thus illustrating the feasibility of low resistance CNTbased interconnects. Acknowledgements The authors would like to thank SIMTech colleagues and research students from Ion Beam Processing Lab at Nanyang Technological University for their valuable assistance. This project is funded by A⁎STAR (Agency for Science, Technology, & Research). References
Fig. 4. I–V measurement of test vehicle 4 with inserted CNT bump and silver adhesive (a) and test vehicles 1 to 4 (b).
[1] R.K. Singh, D.-G. Lee, J. Electron. Mater. 25 (1996) 137; C.M. Chuang, T.S. Lui, L.H. Chen, J. Mat. Res. 16 (2001) 2644. [2] A.D. Merriman, Met. Treat. Drop Forg. 22 (1955) 127. [3] D.W. Zachmann, R. Block, Water Air Soil Pollut. 78 (1994) 317. [4] N. Itsubo, J. Noh, A. Inaba, Mater. Trans. 45 (2004) 3194. [5] S.K. Lohokare, L. Zhaolin, C.A. Schuetz, D.W. Prather, IEEE Trans. Adv. Packaging 29 (2006) 542. [6] M. Kitajim, T. Shono, M. Noguchi, Fuji 51 (2000) 341. [7] M.E. Loomans, M.E. Fine, Metall. Mater. Trans., A Phys. Metall. Mater. Sci. 31 (2000) 1155. [8] P. Biocca, Glob. SMT Packag. 6 (2006) 23. [9] X.J. Wu, Y.G. Tong, Electr. Weld. Mach. 38 (2008) 77. [10] Y. Tsuyoshi, T. Ken-Ichiro, Fuji Sci. Tech. Jpn. 43 (2007) 50. [11] C. Edwards, IET Electr. Syst. Softw. 5 (2007) 8. [12] S. Mil'shtein, Microelectron. J. 39 (2008) 669. [13] S. Naffziger, B. Stackhouse, T. Grutkowski, D. Josephson, J. Desai, E. Alon, M. Horowitz, IEEE J. Solid-State Circuits 41 (2006) 197. [14] D.G. Morrison, Electr. Des. 50 (2002) 51. [15] Y. Alcobi, Circuits Assem. 17 (2006) 46. [16] B. Bottoms, http://public.itrs.net2007.
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L.S. Roth, V. McTaggart, Adv. Packag. 14 (2005) 31. M. Allen, Adv. Packag. 12 (2003) 26. D.F. Baldwin, Adv. Packag. 15 (2006) 44. A. Garcia, I. Bustero, R. Munoz, L. Goikotxea, I. Obieta, Phys. Status Solidi, A Appl. Mater. 203 (2006) 1117. [21] M. Ahlskog, P. Hakonen, M. Paalanen, L. Roschier, R. Tarkiainen, J. Low Temp. Phys. 124 (2001) 335. [22] Y.F. Li, R. Hatakeyama, J. Shishido, T. Kato, T. Kaneko, Appl. Phys. Lett. 90 (2007) 173127. [23] D. Tsuya, M. Suzuki, Y. Aoyagi, K. Ishibashi, Appl. Phys. Lett. 287 (2005) 153101.
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[24] S. Selvarasah, P. Makaram, C.L. Chen, H. Pan, A. Busnaina, M.R. Dokmeci, IEEE Conf. on Nanotech. (NANO) 8th, 2008, p. 18. [25] K.P. Yung, J. Wei, B.K. Tay, Z.F. Wang, Mater. Res. Innov. 10 (2006) 84. [26] K.M. Liew, C.H. Wong, M.J. Tan, P.D. Chuang, Solid State Phenom. 121 (2007) 1415. [27] K.M. Liew, C.H. Wong, M.J. Tan, Acta Mater. 54 (2006) 225. [28] T. Iwai, Y. Awano, Fuji Sci. Tech. Jpn. 43 (2007) 508. [29] B.Q. Wei, R. Vajtai, P.M. Ajayan, Appl. Phys. Lett. 79 (2001) 1172. [30] J. Tersoff, Appl. Phys. Lett. 74 (1999) 2122. [31] Y. Tzeng, Y. Chen, C. Liu, Diamond Relat. Mater. 12 (2003) 774.
Contents lists available at ScienceDirect
Diamond & Related Materials j o u r n a l h o m e p a g e : w w w. e l s ev i e r. c o m / l o c a t e / d i a m o n d
Formation and assembly of carbon nanotube bumps for interconnection applications K.P. Yung a,b,⁎, J. Wei a, B.K. Tay b a b
Singapore Institute of Manufacturing Technology, 71 Nanyang Drive, Singapore 638075, Singapore School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798, Singapore
a r t i c l e
i n f o
Article history: Received 7 October 2008 Received in revised form 4 January 2009 Accepted 9 February 2009 Available online 24 February 2009 Keywords: Carbon Nanotubes Flip Chip Interconnects Joining
a b s t r a c t A simple assembly process of carbon nanotube (CNT) bumps which could be used for flip chip interconnects was proposed and investigated. Firstly, high density aligned CNT bumps were grown on both top and bottom substrates. By employing typical flip chip bonding technique, the CNT bumps on the flipped top substrate were aligned with those on the bottom substrate. Applying a downward force on the die, the CNT bumps on the top substrate were pressed and inserted into the CNT bumps on the bottom substrate. After CNT insertion, the CNTs were held together with van der Waals force and the CNT interconnection bumps were formed. The electrical conductivity of the CNT interconnection bumps was measured and compared to conductive silver adhesive. The conductivity of CNT interconnection bump was found to be of many magnitudes higher than that of silver adhesive. It was demonstrated that the CNT bumps have a much superior electrical properties over the typical metallic bumps. © 2009 Elsevier B.V. All rights reserved.
1. Introduction Lead-content found in common solder poses various problems for interconnect application. Although the use of lead can maximize material strength, and increase resistance to creep [1], toxicity of lead [2] is not eco-friendly [3,4]. Lead free alternatives, such as conductive adhesive [5], tin–silver–copper [6,7] and tin–copper [8], were developed to replace tin–lead solder interconnection materials [9,10]. Nevertheless, lead-free solder has disadvantages such as higher melting temperature and low metal surface wettability. Performance wise, lead-free solder properties are close to that of typical solder, with similar electrical, thermal and mechanical characteristics. In the quest for product miniaturization, integrated circuit (IC) size reduction is inversely proportional to device density [11–13]. As circuit density increases, the number of input/output (I/O) pins on IC packaging increases exponentially with significant drop in pin pitch [14,15]. According to International Technology Roadmap for Semiconductors (ITRS) [16], the number of packaged pins per chip will continue to increase at approximately 10% each year and will approach as high as 5000 pins for high performance ICs in the coming decade. The peripheral I/O flip chip direct chip attach is predicted to scale down to b20 µm pitch and area array flip chip packaging is expected to reach 100 µm pitch by the year of 2014. At this scale, current interconnection technology will become an obstacle to provide reliable high speed connections for smaller devices. To address these problems, metal wire-bumped and metal adhesive flip chip connec⁎ Corresponding author. Singapore Institute of Manufacturing Technology, 71 Nanyang Drive, Singapore 638075, Singapore. Tel.: +65 90037083; fax: +65 67933318. E-mail address: [email protected] (K.P. Yung). 0925-9635/$ – see front matter © 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.diamond.2009.02.022
tions [17,18] were developed. Metal or metal adhesive bumps [5,19] were formed using conventional flip chip bonding equipment as packaging interconnects. Those techniques offer application simplicity because they enable direct bumping and only require equipment that are widely available. In addition, metal also has a much higher electrical and thermal conductivity compared to solder. However, as interconnect miniaturization continues, electromigration and reliability issue will be more apparent when current density in metal interconnection surges. Carbon nanotubes (CNTs) are one dimensional nanowire with superior electrical, thermal and mechanical properties. CNTs are also non-toxic [20]. For these reasons, they have been considered as future building block materials for many active and passive components within electronic devices [21–24]. In particular, with CNT nano feature size and high resistance to electromigration, they are an ideal material for fabricating sub-micro or nano flip chip interconnects with outstanding performance. 2. Experimental detail Fig. 1 illustrates the fabrication process sequence of CNT interconnection bumps. Aligned carbon nanotube (ACNT) film is deposited onto two identical Ni coated Cr/Al electrode surfaces, with p-type silicon b100N wafer with 500 nm thermal oxide used as the top and bottom substrates. A 30 nm thick of Ni catalyst layer is applied for growing CNT forest with a desired density of 6 tubes/µm2 [25]. The 100 nm/1 µm thick of Cr/Al electrode layer and 30 nm thick of nickel catalyst layer are pre-deposited onto the top and bottom substrates by magnetron sputtering at room temperature. A plasma enhanced chemical vapor deposition (PECVD) system is used to synthesize the
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K.P. Yung et al. / Diamond & Related Materials 18 (2009) 1109–1113
3. Results and discussion
Fig. 1. Illustration of CNT insertion process sequence (a–c), top view of the assembled sample (d), and cross-sectional view of the assembled sample (e).
CNTs. Once the base pressure of 2E− 2 mbar is achieved in the PECVD chamber, ammonia is introduced at a flow rate of 240 sccm. The pressure inside the plasma chamber is maintained at 2.9 mbar. All samples are heated to 800 °C and annealed for 2 min. Subsequently, acetylene is allowed into the chamber at a flow rate of 60 sccm to initiate ACNT growth and a 500 V of biased voltage is applied for vertically aligning the CNTs. The chamber pressure is kept constant at 8.2 mbar, throughout the 60 min CNT growth process. To assemble CNT bumps, the sample surfaces with the ACNTs are faced each other in angular alignment, as observed with a low power microscope. Different insertion lengths of the contacted CNT between the top and bottom substrates are accomplished by placing different amounts of weight onto the top substrate. This weight is then removed from the structure. Once interlocking has taken place, the top substrate is supported by the bottom substrate and the two substrates are considered “joined”. The minimum load applied for interlocking is 0.03 g which is benefited from the top substrate's weight and the maximum load used is 3.00003 kg. The cross sectional images of the assembled samples are observed using a high-resolution scanning electron microscope (SEM, JEOL JSM5910LV) for determining the length of CNT penetration region. Electrical properties of the “inserted” structure are measured by four point probe technique using Keithly 230 programmable voltage source and Keithly 590 CV analyzer. A current is applied across the “inserted” CNTs through probes 1 and 2, which are connected to one side of the top and bottom CNT substrates, respectively. The voltage drop of the CNTs is then measured between probes 3 and 4, which are connected to the other end of the top and bottom substrates, respectively. An illustration of the measurement set up is shown in Fig. 2 and the applied current ranges from 50 mA to − 50 mA with a 10 mA interval. Reference sample was prepared using silver adhesive as the interconnect material with similar set up. This sample is used as benchmark and the electrical performance is compared to that of the “inserted” CNT structure. Repeated cycles of measurements were performed for all samples to check the consistency of the data.
The morphology of vertically grown primary ACNTs that are prepared for the assembly process is presented in Fig. 3a. The ACNTs have a uniform diameter of around 200 nm and a uniform length of around 15 µm. During the initial stage of the CNT assembly process, an axial compression force is applied, which caused the hollow graphene body of CNTs to undergo structural deformation and buckling [26,27]. Such deformations enable the tubes to be squeezed into the air space within the other CNT bump and allowing penetration to occur. When the compress force is released, all deformed CNTs would expand, attempting to regain their original shape. However, there is not enough air space for the spontaneous “regaining” action of the tubes and they can only take up the shape of the available space between them and their neighboring tubes. With the nanotubes from both bumps fitted tightly to each other, the CNT bumps are mechanically interlocked. For interconnect application, the adhesion strength of the assembled structure needs to be strong mechanically and this strength can be obtained from interlocked CNT formed under the following conditions. First, the volume ratio of CNTs to air space on both side of the CNT bumps needs to be at most 1:1. This will ensure minimal air space between the penetrated CNT structures. The larger the CNT diameter is, the lower the CNT density is needed. Next, the ideal length of the CNT bump should be N10 µm, which would provide enough interaction length for interlocking the CNTs. Fig. 3b–e illustrates the interpenetrated and interlocked CNT bumps from top and bottom substrates. Predictably, the degree of interpenetration of the CNT bumps has shown to be consistent with the amount of the assembly force applied. The corresponding “penetration” length to the amount of assembly force is shown in Table 1. SEM results in Fig. 3b show the penetration of CNT in test vehicle 1, under no additional loading condition. In this condition with only the weight of the substrate at 0.03 g acting on it, the CNT penetration length is measured to be around 3.5 µm (~ 23% of the CNTs length). Whereas for test vehicle 4, shown in Fig. 3e, the largest assembly weight of 3.00003 kg has enabled full interpenetration length of 15 µm. The CNT bump that has went through 50 cycles of interpenetration and detach process is presented in Fig. 3f. The SEM image shows that the interpenetration action does not cause any damage to the CNT bump structure. The process is considered reworkable and it allows easy readjustment and replacement of components if used as interconnects for flip chip packaging. For interconnection applications, the desired contact resistance between the interconnect bump and bond pad or electrode should be
Fig. 2. A schematic of the four-point-probe measurement set-up. The current is applied through probes 1 and 2 and the voltages measured between probes 3 and 4.
K.P. Yung et al. / Diamond & Related Materials 18 (2009) 1109–1113
1111
Fig. 3. SEM images, with scale-bar of 2 µm, of the as grown CNT bump (a), the cross sectional views, with scale-bar of 5 µm, of the CNT structures after their assembly process: test vehicle 1 (b), test vehicle 2 (c), test vehicle 3 (d) and test vehicle 4 (e), and the images with scale-bar of 2 µm of the CNT bump that has went through 50 cycles of interpenetration and detachment processes (f).
as low as possible. Conventional way of joining CNT bumps by metallic adhesive [28] may provide reasonable mechanical adhesion, however, problems such as high contact resistance often arises. The unique electronic structure of nanotubes gives rise to high contact resistance, which is caused by weak electronic coupling at the Fermi surface between the weakly bonded metal to the tip CNTs [29–31]. Improved electron transport is feasible using the penetration method, as the weak metal–CNT contacts are replaced by the CNT–CNT contacts. The electrical behavior of CNT–CNT contacts is predicated to resemble directional graphene–graphene stacking. A simple four point probe measurement set up for measuring the current to voltage (I–V) Table 1 The corresponding “penetration” length of CNTs versus the assembly force. Test vehicle
1
2
3
4
Force (kg) Penetration length (µm)
0.00003 3.6
1.00003 7.3
2.00003 11.1
3.00003 15
characteristic of CNT test vehicles is shown in Fig. 2. The measured voltages are presented in Fig. 4, with applied current varying from 50 mA to −50 mA. The measured resistance value is composed of the probe-to-electrode contact resistances, the electrode-to-CNT contact resistances, and the intrinsic resistance of the CNT bump. Hence, the obtained results are analyzed by comparing to that of a test vehicle with silver adhesive as interconnect material. The linear I–V curve in Fig. 4b indicates the metallic characteristic of the as-grown multiwalled CNTs as well as the ohmic contacts between the CNTs. The resistance of the CNT test vehicle is found to be magnitudes lower than that of test vehicle with silver adhesive as presented in Fig. 4a. The experimental measurements above show that the CNT bumps have a much lower intrinsic resistance than typical metal. The total contact resistance presented in the CNT system is much lower to that of the other test vehicle using silver adhesive contact. The resistance of the inserted CNT structure is also found to decrease with the increase in the penetration depth as presented in Fig. 4. The linear decrease in resistance with increase in penetration depth proves that CNT–CNT
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K.P. Yung et al. / Diamond & Related Materials 18 (2009) 1109–1113
contacts are having metallic behavior and are ohmic. The lower resistance measured from the interpenetrated CNT structure has demonstrated the advantage of our approach in creating low contact resistance, CNT-based interconnects. In addition, the contact length dependent conductance of the “inserted” CNT structure would be useful for various microsystems. The reattachable laminating properties created with this technique are also applicable to fastening nano devices similar to that of typical Velcro®. 4. Proposed CNT flip chip interconnect formation process The CNT ‘insertion” technique can be used as interconnection bump for flip chip packaging system. A schematic of the proposed CNT interconnect formation is depicted in Fig. 5a–c. For fabricating CNT flip chip interconnection, metallization layers followed by catalyst layer on IC die and its carrier are first deposited. Lithography technique is used for patterning the metallization layers and catalyst layer as presented in Fig. 5a. Upon removal of the mask and the formation of patterned metallization layers and catalyst layer, ACNTs are grown on the patterned IC and carrier (Fig. 5b). Subsequently, the IC can be flipped and aligned with its carrier for bonding (Fig. 5c). With an appropriate force applied onto the substrate, the CNT bumps will be inserted and joined as shown in Fig. 5d. 5. Conclusions Simple insertion assembly technique for CNT bumps leads to the formation of highly electrical conductive structure for flip chip
Fig. 5. Proposed CNT insertion process for flip chip application. Deposition of under CNT metallization and catalyst layer (a), deposition of CNTs (b), align die to its carrier (c), and assembly of die to its carrier with downward force (d).
interconnects application. The CNT bumps from top and bottom substrates have shown to adhere well to each other and exhibit low contact resistance. The measured total resistance is lower than that of silver adhesive, thus illustrating the feasibility of low resistance CNTbased interconnects. Acknowledgements The authors would like to thank SIMTech colleagues and research students from Ion Beam Processing Lab at Nanyang Technological University for their valuable assistance. This project is funded by A⁎STAR (Agency for Science, Technology, & Research). References
Fig. 4. I–V measurement of test vehicle 4 with inserted CNT bump and silver adhesive (a) and test vehicles 1 to 4 (b).
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