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n-Si Schottky barrier diodes with and without SnO2 insulator layer
Physica B 406 (2011) 4119–4123
Contents lists available at ScienceDirect
Physica B journal homepage: www.elsevier.com/locate/physb
Forward and reverse bias current–voltage characteristics of Au/n-Si Schottky barrier diodes with and without SnO2 insulator layer ¨ - en a,n, S- . Altındal b, M. Karaman c,d, U. Aydemir b M. Gokc a
Department of Physics, Faculty of Arts and Sciences, D¨ uzce University, 81620 D¨ uzce, Turkey Department of Physics, Faculty of Sciences, Gazi University, 06500 Ankara, Turkey c ¨ Center For Solar Energy Research and Application (GUNAM), Department of Physics, Faculty of Sciences, Middle East Technical University, 06800 Ankara, Turkey d Physics Group, Faculty of Engineering, Atılım University, 06836 Ankara, Turkey b
a r t i c l e i n f o
abstract
Article history: Received 8 July 2011 Received in revised form 1 August 2011 Accepted 2 August 2011 Available online 7 August 2011
The effects of interfacial insulator layer, interface states (Nss) and series resistance (Rs) on the electrical characteristics of Au/n-Si structures have been investigated using forward and reverse bias current– voltage (I–V) characteristics at room temperature. Therefore, Au/n-Si Schottky barrier diodes (SBDs) were fabricated as SBDs with and without insulator SnO2 layer to explain the effect of insulator layer on main electrical parameters. The values of ideality factor (n), Rs and barrier height (FBo) were calculated from ln(I) vs. V plots and Cheung methods. The energy density distribution profile of the interface states was obtained from the forward bias I–V data by taking bias dependence of ideality factor, effective barrier height (Fe) and Rs into account for MS and MIS SBDs. It was found that Nss values increase from at about mid-gap energy of Si to bottom of conductance band edge of both SBDs and the MIS SBD’s Nss values are 5–10 times lower than those of MS SBD’s. An apparent exponential increase from the midgap towards the bottom of conductance band is observed for both SBDs’ (MS and MIS) interface states obtained without taking Rs into account. & 2011 Elsevier B.V. All rights reserved.
Keywords: Au/n-Si Insulator layer effects Series resistance I–V characteristic Interface states
1. Introduction For a rectifying contact in order to form a SBD, there are lots of negative effects in the metal–semiconductor (M/S) interface such as high leakage current, high temperature dispersion, and high defect trapped charges. An insulator layer is used between metal and semiconductor to prevent these negative effects; thus, these metal–semiconductor (MS) structures convert into metal– insulator–semiconductor (MIS) structures. Such interfacial insulator layer not only prevents inter-diffusion between metal and semiconductor, but also alleviates the electric field reduction in MIS SBDs. Electronic properties of a SBD are characterized by its main electrical parameters such as leakage current, barrier height (FB) formation at M/S interface, ideality factor (n), series resistance (Rs) and interface states (Nss). These electrical parameters are affected strongly by the existence of an insulator layer, because, insulator layer increases the FB, intercept voltage, n and Rs while it leads to a decrease in reverse leakage current and Nss [1]. Recently, especially Si3N4, SnO2, TiO2, etc. are used as interfacial insulator layer instead of SiO2. Because of its potential applications such as transparent conducting electrodes, varistors, gas sensors and lithium ion batteries, SnO2 is an attractive interfacial insulator layer material for SBDs [2–7].
n
Corresponding author. Tel.: þ90 380 541 24 04; fax: þ90 380 541 24 03. ¨ -en). E-mail address: [email protected] (M. Gokc
0921-4526/$ - see front matter & 2011 Elsevier B.V. All rights reserved. doi:10.1016/j.physb.2011.08.006
The performance of an MS or MIS SBD depends on various factors such as presence of the localized interface states at the M/S or insulator/semiconductor interface, metal to semiconductor barrier height and Rs of SBD. Rs and interfacial layer are very important parameters of MS and MIS SBDs, because when a voltage is applied to an MS or MIS Schottky diode, the total voltage is shared by M/S interfacial layer, depletion layer and Rs of the SBD. The magnitude of this shared voltage depends on the thickness of interfacial insulator layer and the structure’s Rs [6]. Therefore, the performance and reliability of these devices are especially dependent on the interfacial layer quality and Rs. For an accurate and reliable determination of the electrical characteristics, the Rs should be taken into account. Hence, in this study, the effect of interfacial insulator layer’s existence (SnO2) and Rs on the electrical characteristics of Au/n-Si structures has been investigated by using forward and reverse current–voltage (I–V) measurements at room temperature.
2. Experimental procedures The studied Au/n-Si/Ag and Au/SnO2/n-Si/Ag structures were fabricated using n-type (P-doped) single crystals silicon wafer with /1 1 0S surface orientation, 280 mm thick, 3 in diameter and 4.45 O.cm resistivity. In the first step of cleaning, the wafer was ultrasonically cleaned by acetone, propanol and de-ionized water for 10 min at each step. Following the first step, the piranha
M. G¨ okc- en et al. / Physica B 406 (2011) 4119–4123
solution of 3H2SO4:1H2O2 was prepared for cleaning the organic residues and then the wafer was immersed into the solution for 15 min. In the last step, the wafer was dipped into the solution of 20% HF to get rid of the oxide layer formed in the previous step. After each cleaning step, the wafer was rinsed thoroughly with de-ionized water of 18 MO cm resistivity. Immediately after surface cleaning, high purity Ag metal (99.999%) with thickness of 2500 A˚ was thermally evaporated from the tungsten filament onto the whole back surface of the wafer in liquid nitrogen trapped vacuum system at the pressure of 1 10 6 Torr. In order to achieve a good ohmic contact, the evaporated Ag was annealed at 500 1C for 30 min. The front side of the wafer was cleaned with 20% HF solution to remove the thin oxide layer, which is formed during annealing. Then, in order to form the interfacial insulator layer in the MIS structure, the sample was loaded to sputtering chamber for SnO2 deposition. First, the chamber was evacuated to 2 10–6 Torr and 4 sccm Ar was provided into the chamber to maintain the deposition pressure at 5 10 3 Torr. As a source material 2 in of SnO2 target was used by applying 30 W of DC power. Deposition was held under room temperature as the temperature and the rotation of substrate was supplied for better homogeneity. After sputtering process, circular dots of 2 mm in diameter and 2500 A˚ thick Au rectifying contacts were deposited onto the SnO2 (MIS) and front side of n-Si (MS) surfaces of the wafer through a metal shadow mask by thermal evaporator vacuum system with the pressure of 1 10 6 Torr. The thickness of metal layer and deposition rates were both monitored with the help of a digital quartz ˚ crystal thickness monitor. The deposition rates were about 1–3 A/s. The interfacial oxide layer thickness was estimated to be about 40 A˚ from measurement of the oxide capacitance in the strong accumulation region for MIS structure. The current–voltage (I–V) measurements of MS and MIS SBDs were performed using Keithley 2400 source-meter at room temperature.
1.0E-03
1.0E-04
I (A)
4120
1.0E-05
1.0E-06
1.0E-07
1.0E-08 MS MIS
1.0E-09
-5.0
-4.0
-3.0
-2.0
1.0E-10 -1.0 0.0 V (V)
1.0
where q is the electronic charge, An is the Richardson constant and is equal to 112 A cm 2 K 2 for n-type Si, A is the diode area, k is the Boltzmann constant, T is the absolute temperature in K, FBo is the zero bias barrier height and n is the ideality factor. The ideality factor values of MS and MIS SBDs were calculated from the slope of the linear region of the forward bias ln(I)–V
4.0
5.0
Table 1 Various parameters determined by various methods from forward bias I–V characteristics of MS and MIS type SBDs.
I0 (A)
3. Results and discussion
where Io is the reverse saturation current derived from the straight-line intercept of lnI at zero bias, and is given by [9–11] qFBo ð2Þ I0 ¼ AAn T 2 exp kT
3.0
Fig. 1. Current–voltage characteristics of the Au/n-Si (MS) and Au/SnO2/n-Si (MIS) SBDs at room temperature.
ln(I) V
The semi-logarithmic forward and reverse bias I–V plots of the Au/n-Si SBDs with and without SnO2 interfacial insulator layer are given in Fig. 1. As can be seen in Fig. 1, both MS and MIS types SBDs show a good rectifying behavior and especially MIS SBD has higher rectifying ratio with low leakage current compared to MS SBD. The interfacial insulator layer SnO2 in MIS SBD not only prevents leakage current but also raises the rectifying ratio up such that it decreases the leakage current 25 times and increases rectifying ratio 4 times. This situation is attributed to the image force lowering of schottky barrier height [1,8–9] and the presence of the interfacial insulator layer passivating semiconductor surface. The current through an SBD with series resistance, according to thermionic emission (TE) theory, is given by the following relationship [9–11]: h i q I ¼ I0 exp ðVIRs Þ ð1Þ nkT
2.0
MS (without SnO2) MIS (with SnO2)
H(I) I n
8.40E 08 1.69 7.62E 10 4.91
plots through the relation q dV n¼ kT d ln I
dV/dln(I) I
(eV)
Rs (kX)
0.71 0.84
6.60 0.59 130.30 0.80
UB0
UB0
Rs (kX)
(eV) 6.70 129.60
ð3Þ
The values of FBo are determined from the extrapolated I0 and given by the relation: n 2 kT AA T ln FBo ¼ ð4Þ q I0 The values of I0, n, and FBo of MS and MIS type SBDs shown in Table 1 are derived from straight-line intercept of ln(I) at zero bias or from the slope of the linear region of the forward bias ln(I)–V plots through the relations above. As can be seen in the table, I0 value of MIS SBD is smaller than that of MS SBD, whereas n and FBo values of MIS SBD are higher compared to those of MS SBD. These high values of n for MS and MIS type SBDs can be attributed to the existence of nonlinearly deposited insulator layer, interface states, image force lowering and the formation of barrier height at M/S interface. The double-logarithmic I–V plots of MS and MIS SBDs were drawn and given in Fig. 2, respectively, in order to achieve better understanding of the current conduction mechanism in detail. The double-logarithmic I–V plot has two distinct linear regions for
M. G¨ okc- en et al. / Physica B 406 (2011) 4119–4123
1.0E-03
especially depend on this interfacial layer quality and Rs. The resistance of SBDs (Ri) can be named as shunt resistance (Rsh) in reverse bias region and series resistance (Rs) in forward bias region. The Rsh and Rs were determined from the Ri( ¼dVi/dIi) vs. applied bias voltage (Vi) plot, which are given in Fig. 3 determined from the I–V characteristics. It can be seen in Fig. 3 that at sufficiently high reverse and forward bias voltages, the Rsh and Rs of MS SBD have a constant value while the MIS SBD’s Rsh and Rs values decrease in two bias voltage regions. The values of Rs were found as 4.92 kO and 22.36 kO for MS and MIS SBDs, respectively. The values of Rsh were found as 1.57 MO and 728.68 MO for MS and MIS SBDs, respectively. It is clear that both the values of Rsh and Rs were found to strongly depend on the applied bias voltage and interfacial insulator layer. In addition, the values of the Rs of these MS and MIS Schottky diodes were evaluated from the forward bias I–V data using the methods developed by Cheung and Cheung [13]. The forward bias current–voltage characteristics due to the thermionic emission of Schottky diodes with the series resistance can be expressed as [9–11,13] Cheung’s functions:
1.0E-04
1.0E-06
1.0E-07 MS MIS
1.0 V (V)
0.1
10.0
Fig. 2. Double-logarithmic I–V plots of the Au/n-Si (MS) and Au/SnO2/n-Si (MIS) SBDs at room temperature.
HðIÞ ¼ Vn
1.0E+08
ð6Þ
MS
1.5
1.0E+06
MS MIS
dV/dLn (I) H (I)
(V)
H (I) = 6602.9I + 1.0038
1.0E+05
1.0
dV/dLn (I) = 6707.3I + 0.1226
0.5
1.0E+04
2E -0 4 1.
04 E1. 1
04 E1. 0
9. 0
E-
05
0E -0 5 8.
0E -0 5
I (A)
Fig. 3. Resistance of the Au/n-Si (MS) and Au/SnO2/n-Si (MIS) SBDs at room temperature.
MIS
5.0 4.0 (V)
H (I) = 130274I + 3.9145
3.0
dV/dLn (I) H (I)
2.0 1.0
dV/dLn (I) = 129647I + 0.1738
-0 6 3. 5E
3. 0E -0 6
06 5E 2.
06
06 0E 2.
0E -
07
0.0
5.
MS SBD, while three distinct linear regions for MIS SBD. This discrepancy can be attributed to the existence of interfacial layer at the M/S interface. A detailed analysis of these plots emerged that the charge transport is mainly governed by space charge limited current (SCLC) process rather than the other current conduction process. According to the SCLC theory, when applied voltage is increased, the injection of electrons from electrode to the films increases accordingly [12]. The series resistance is a very important parameter of MS and MIS Schottky diodes, because when a voltage is applied to an MS or an MIS Schottky diode, the total voltage is shared by interfacial layer between metal and semiconductor, depletion layer and series resistance of the structure. The magnitude of this shared voltage depends on the interfacial insulator layer and Rs [6]. Therefore, the performance and the reliability of these devices
7.
8.0
1. 5E -
6.0
0E -0 5
4.0
E06
2.0 V (V)
0E -0 5
0.0
5.
-4.0
kT I ln ¼ IRS þ n fB0 q AAn T 2
2.0
1.0E+07
1.0E+03 -2.0 0.0
ð5Þ
For both equations, dV/dln(I) and H(I) vs. I plots should give a straight-line for the data of downward curvature region in the forward bias I–V characteristics. Thus, slopes of dV/dln(I) and H(I) vs. I will give Rs of these MS and MIS Schottky diodes. Fig. 4 shows the
1.0E+09
R (Ω )
dV kT ¼ IRs þ n dlnðIÞ q
6.
1.0E-09
1. 0
I (A)
1.0E-05
1.0E-08
4121
I (A) Fig. 4. Experimental dV/dln(I) and H(I) vs. I plots of the Au/n-Si (MS) and Au/SnO2/n-Si (MIS) SBDs at room temperature.
M. G¨ okc- en et al. / Physica B 406 (2011) 4119–4123
where b is the voltage coefficient of the effective barrier height Fe, used in the place of the barrier height, and it is a parameter that combines the effects of interface states and Rs [1,11,15–18]. For non-ideal MS and MIS type SBDs, the voltage and series resistance dependences of ideality factor n(V) due to Nss can be written with the following Equations:[1,11] q ðVIRs Þ d es ¼ 1þ þ qNss ðVÞ ð8Þ nðVÞ ¼ kT lnðI=I0 Þ ei WD where d is the thickness of interfacial insulator layer, WD is the width of the space charge region, es ¼11, 8 eo and ei ¼7eo are the permittivities of the interfacial insulator layer and the semiconductor, respectively. The expression for the interface state density is deduced as follows [1,9,11,17]: 1 ei es NSS ðVÞ ¼ ðnðVÞ1Þ ð9Þ q d WD The interfacial insulator layer (SnO2) thickness for the MIS SBD, d, was obtained as about 40 A˚ from C–V characteristics using the equation for insulator layer capacitance (Cox ¼ eieoA/d), where ei ¼ 7eo and eo is the permittivity of free space [11,17]. Furthermore, in n-type semiconductors, the energy of Nss with respect to the bottom of conductance band at the surface of the semiconductor is given by [1,11,17] Ec Ess ¼ q½Fe ðVIRs Þ
ð10Þ
Fig. 5 shows the energy distribution profiles of the Nss with and without taking Rs obtained from forward bias I–V characteristics of MS and MIS SBDs at room temperature into account. The energy density distribution of Nss profile of MS and MIS type SBDs obtained without taking Rs into account has an apparent exponential increase from mid gap towards the bottom of the conductance band of Si as can be seen in Fig. 5. In addition, the results indicate that Nss values increase with the increasing bias voltage values. This confirms that the density of interface states changes with bias and each of the applied biases corresponds to a position inside the Si gap. MIS SBD’s Nss values are 5–10 times lower than those of MS SBD’s whether Rs is taken into account or not. The purpose of the SnO2 insulator layer is to prevent the reaction and inter-diffusion between the Au metal contact and semiconductor as well as to passivate active dangling bonds at semiconductor surface and reduce the high gate-leakage current [19]. This reduction in the leakage current in the MIS SBD is caused by the thin interfacial insulator layer and is due to a combination of increased barrier height at metal/semiconductor
1.8E+14
MS
1.5E+14 Nss (eV-1cm-2)
experimental dV/dln(I) and H(I) vs. I plots of MS and MIS Schottky diodes. Also, using n and kT/q values in Eqs. 5 and 6, the values of FBo are derived from the plots in Fig. 4. As can be seen from Fig. 4 and Table 1, the Rs values, which are derived using two methods (dV/dln(I) and H(I) vs. I), are in good agreement with each other for both MS and MIS SBDs for Rs. In the literature, Au/SnO2/n-Si SBDs were fabricated by different techniques and obtained about similar results for most of these diodes parameters [4,14,15]. For rectifying ratio and I0, more suitable values were obtained at our current study according to higher shunt resistance. The nonlinearity of the I–V characteristics of the SBDs at high bias voltages indicates a continuum of Nss, which is at equilibrium with the semiconductor and Rs. In addition, when the interfacial layer is sufficiently thick, the transmission probability between the metal and the interface states is very small. The effective barrier height Fe is assumed to be bias-dependent due to the presence of an interfacial insulator layer and series resistance, and it is given as [11,15–18] 1 ðVIRs Þ Fe ¼ FBo þ bðVÞ ¼ FBo þ 1 ð7Þ nðVÞ
1.2E+14 9.0E+13 6.0E+13
Without Rs With Rs
3.0E+13
0.0E+00 0.50 0.52 0.54 0.56 0.58 0.60 0.62 0.64 0.66 0.68 Ec-Ess (eV) 1.8E+13
MIS
1.5E+13 Nss (eV-1cm-2)
4122
1.2E+13 9.0E+12
Without Rs With Rs
6.0E+12 3.0E+12 0.60 0.62 0.64 0.66 0.68 0.70 0.72 0.74 0.76 0.78 0.80 0.82 Ec-Ess (eV) Fig. 5. Density of interface states (Nss) as a function of Ec–Ess with and without Rs effect for Au/n-Si (MS) and Au/SnO2/n-Si (MIS) SBDs at room temperature.
interface and reduced velocity of charge carriers. These combined effects cause important outcomes such as 25 times and 5–10 times decrease in the leakage current and Nss, respectively, when the MS SBD is converted into MIS SBD. Therefore, we can say that Nss is affected strongly by the existence and the thickness of the interfacial insulator layer at M/S interface and Rs. There are a lot of studies in the literature showing that the forward bias current– voltage characteristics at sufficiently large voltages have been affected from series resistance and the existence and the thickness of the interfacial layer [1,11,12,20].
4. Conclusions The effects of interfacial insulator layer and series resistance on the forward and reverse bias current–voltage (I–V) characteristics of the SBDs have been studied at room temperature. The non-ideal forward bias I–V behavior observed in both MS and MIS SBDs is attributed to a change in the metal/semiconductor barrier height due to the interface states, interfacial insulator layer and series resistance. The values of n, Rs and FBo, which were calculated from ln(I) vs. V plots and Cheung methods for MS SBD, are lower than those for MIS SBD. Regarding the interface states of both SBDs obtained without taking Rs into account, an apparent exponential increase from mid gap towards the bottom of the conductance band is observed. Nss values increase with the increasing bias voltage values. MIS SBD’s Nss values are 5–10 times lower than those of MS SBD’s whether Rs is taken into account or not. Hence, we can say that the interface state density,
M. G¨ okc- en et al. / Physica B 406 (2011) 4119–4123
leakage current, series resistance and barrier height depend on the existence of the interfacial insulator layer between metal and semiconductor. Also, we can conclude that the series resistance should be taken into account in order to obtain accurate and reliable results of the interface states density as above. In conclusion, in our study, interfacial insulator layer has some positive effects such as higher rectifying ratio and low leakage current.
Acknowledgments ¨ This work is supported by Duzce University Scientific Research Project (Project no. 2010.05.02.056). References ¨ zc- elik, H. Shtrikman, Vacuum 83 (2009) 1060. [1] H. Altuntas- , S- . Altındal, S. O [2] Z. Pan, Z. Dai, Z.L. Wang, Science 291 (2001) 1947.
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Contents lists available at ScienceDirect
Physica B journal homepage: www.elsevier.com/locate/physb
Forward and reverse bias current–voltage characteristics of Au/n-Si Schottky barrier diodes with and without SnO2 insulator layer ¨ - en a,n, S- . Altındal b, M. Karaman c,d, U. Aydemir b M. Gokc a
Department of Physics, Faculty of Arts and Sciences, D¨ uzce University, 81620 D¨ uzce, Turkey Department of Physics, Faculty of Sciences, Gazi University, 06500 Ankara, Turkey c ¨ Center For Solar Energy Research and Application (GUNAM), Department of Physics, Faculty of Sciences, Middle East Technical University, 06800 Ankara, Turkey d Physics Group, Faculty of Engineering, Atılım University, 06836 Ankara, Turkey b
a r t i c l e i n f o
abstract
Article history: Received 8 July 2011 Received in revised form 1 August 2011 Accepted 2 August 2011 Available online 7 August 2011
The effects of interfacial insulator layer, interface states (Nss) and series resistance (Rs) on the electrical characteristics of Au/n-Si structures have been investigated using forward and reverse bias current– voltage (I–V) characteristics at room temperature. Therefore, Au/n-Si Schottky barrier diodes (SBDs) were fabricated as SBDs with and without insulator SnO2 layer to explain the effect of insulator layer on main electrical parameters. The values of ideality factor (n), Rs and barrier height (FBo) were calculated from ln(I) vs. V plots and Cheung methods. The energy density distribution profile of the interface states was obtained from the forward bias I–V data by taking bias dependence of ideality factor, effective barrier height (Fe) and Rs into account for MS and MIS SBDs. It was found that Nss values increase from at about mid-gap energy of Si to bottom of conductance band edge of both SBDs and the MIS SBD’s Nss values are 5–10 times lower than those of MS SBD’s. An apparent exponential increase from the midgap towards the bottom of conductance band is observed for both SBDs’ (MS and MIS) interface states obtained without taking Rs into account. & 2011 Elsevier B.V. All rights reserved.
Keywords: Au/n-Si Insulator layer effects Series resistance I–V characteristic Interface states
1. Introduction For a rectifying contact in order to form a SBD, there are lots of negative effects in the metal–semiconductor (M/S) interface such as high leakage current, high temperature dispersion, and high defect trapped charges. An insulator layer is used between metal and semiconductor to prevent these negative effects; thus, these metal–semiconductor (MS) structures convert into metal– insulator–semiconductor (MIS) structures. Such interfacial insulator layer not only prevents inter-diffusion between metal and semiconductor, but also alleviates the electric field reduction in MIS SBDs. Electronic properties of a SBD are characterized by its main electrical parameters such as leakage current, barrier height (FB) formation at M/S interface, ideality factor (n), series resistance (Rs) and interface states (Nss). These electrical parameters are affected strongly by the existence of an insulator layer, because, insulator layer increases the FB, intercept voltage, n and Rs while it leads to a decrease in reverse leakage current and Nss [1]. Recently, especially Si3N4, SnO2, TiO2, etc. are used as interfacial insulator layer instead of SiO2. Because of its potential applications such as transparent conducting electrodes, varistors, gas sensors and lithium ion batteries, SnO2 is an attractive interfacial insulator layer material for SBDs [2–7].
n
Corresponding author. Tel.: þ90 380 541 24 04; fax: þ90 380 541 24 03. ¨ -en). E-mail address: [email protected] (M. Gokc
0921-4526/$ - see front matter & 2011 Elsevier B.V. All rights reserved. doi:10.1016/j.physb.2011.08.006
The performance of an MS or MIS SBD depends on various factors such as presence of the localized interface states at the M/S or insulator/semiconductor interface, metal to semiconductor barrier height and Rs of SBD. Rs and interfacial layer are very important parameters of MS and MIS SBDs, because when a voltage is applied to an MS or MIS Schottky diode, the total voltage is shared by M/S interfacial layer, depletion layer and Rs of the SBD. The magnitude of this shared voltage depends on the thickness of interfacial insulator layer and the structure’s Rs [6]. Therefore, the performance and reliability of these devices are especially dependent on the interfacial layer quality and Rs. For an accurate and reliable determination of the electrical characteristics, the Rs should be taken into account. Hence, in this study, the effect of interfacial insulator layer’s existence (SnO2) and Rs on the electrical characteristics of Au/n-Si structures has been investigated by using forward and reverse current–voltage (I–V) measurements at room temperature.
2. Experimental procedures The studied Au/n-Si/Ag and Au/SnO2/n-Si/Ag structures were fabricated using n-type (P-doped) single crystals silicon wafer with /1 1 0S surface orientation, 280 mm thick, 3 in diameter and 4.45 O.cm resistivity. In the first step of cleaning, the wafer was ultrasonically cleaned by acetone, propanol and de-ionized water for 10 min at each step. Following the first step, the piranha
M. G¨ okc- en et al. / Physica B 406 (2011) 4119–4123
solution of 3H2SO4:1H2O2 was prepared for cleaning the organic residues and then the wafer was immersed into the solution for 15 min. In the last step, the wafer was dipped into the solution of 20% HF to get rid of the oxide layer formed in the previous step. After each cleaning step, the wafer was rinsed thoroughly with de-ionized water of 18 MO cm resistivity. Immediately after surface cleaning, high purity Ag metal (99.999%) with thickness of 2500 A˚ was thermally evaporated from the tungsten filament onto the whole back surface of the wafer in liquid nitrogen trapped vacuum system at the pressure of 1 10 6 Torr. In order to achieve a good ohmic contact, the evaporated Ag was annealed at 500 1C for 30 min. The front side of the wafer was cleaned with 20% HF solution to remove the thin oxide layer, which is formed during annealing. Then, in order to form the interfacial insulator layer in the MIS structure, the sample was loaded to sputtering chamber for SnO2 deposition. First, the chamber was evacuated to 2 10–6 Torr and 4 sccm Ar was provided into the chamber to maintain the deposition pressure at 5 10 3 Torr. As a source material 2 in of SnO2 target was used by applying 30 W of DC power. Deposition was held under room temperature as the temperature and the rotation of substrate was supplied for better homogeneity. After sputtering process, circular dots of 2 mm in diameter and 2500 A˚ thick Au rectifying contacts were deposited onto the SnO2 (MIS) and front side of n-Si (MS) surfaces of the wafer through a metal shadow mask by thermal evaporator vacuum system with the pressure of 1 10 6 Torr. The thickness of metal layer and deposition rates were both monitored with the help of a digital quartz ˚ crystal thickness monitor. The deposition rates were about 1–3 A/s. The interfacial oxide layer thickness was estimated to be about 40 A˚ from measurement of the oxide capacitance in the strong accumulation region for MIS structure. The current–voltage (I–V) measurements of MS and MIS SBDs were performed using Keithley 2400 source-meter at room temperature.
1.0E-03
1.0E-04
I (A)
4120
1.0E-05
1.0E-06
1.0E-07
1.0E-08 MS MIS
1.0E-09
-5.0
-4.0
-3.0
-2.0
1.0E-10 -1.0 0.0 V (V)
1.0
where q is the electronic charge, An is the Richardson constant and is equal to 112 A cm 2 K 2 for n-type Si, A is the diode area, k is the Boltzmann constant, T is the absolute temperature in K, FBo is the zero bias barrier height and n is the ideality factor. The ideality factor values of MS and MIS SBDs were calculated from the slope of the linear region of the forward bias ln(I)–V
4.0
5.0
Table 1 Various parameters determined by various methods from forward bias I–V characteristics of MS and MIS type SBDs.
I0 (A)
3. Results and discussion
where Io is the reverse saturation current derived from the straight-line intercept of lnI at zero bias, and is given by [9–11] qFBo ð2Þ I0 ¼ AAn T 2 exp kT
3.0
Fig. 1. Current–voltage characteristics of the Au/n-Si (MS) and Au/SnO2/n-Si (MIS) SBDs at room temperature.
ln(I) V
The semi-logarithmic forward and reverse bias I–V plots of the Au/n-Si SBDs with and without SnO2 interfacial insulator layer are given in Fig. 1. As can be seen in Fig. 1, both MS and MIS types SBDs show a good rectifying behavior and especially MIS SBD has higher rectifying ratio with low leakage current compared to MS SBD. The interfacial insulator layer SnO2 in MIS SBD not only prevents leakage current but also raises the rectifying ratio up such that it decreases the leakage current 25 times and increases rectifying ratio 4 times. This situation is attributed to the image force lowering of schottky barrier height [1,8–9] and the presence of the interfacial insulator layer passivating semiconductor surface. The current through an SBD with series resistance, according to thermionic emission (TE) theory, is given by the following relationship [9–11]: h i q I ¼ I0 exp ðVIRs Þ ð1Þ nkT
2.0
MS (without SnO2) MIS (with SnO2)
H(I) I n
8.40E 08 1.69 7.62E 10 4.91
plots through the relation q dV n¼ kT d ln I
dV/dln(I) I
(eV)
Rs (kX)
0.71 0.84
6.60 0.59 130.30 0.80
UB0
UB0
Rs (kX)
(eV) 6.70 129.60
ð3Þ
The values of FBo are determined from the extrapolated I0 and given by the relation: n 2 kT AA T ln FBo ¼ ð4Þ q I0 The values of I0, n, and FBo of MS and MIS type SBDs shown in Table 1 are derived from straight-line intercept of ln(I) at zero bias or from the slope of the linear region of the forward bias ln(I)–V plots through the relations above. As can be seen in the table, I0 value of MIS SBD is smaller than that of MS SBD, whereas n and FBo values of MIS SBD are higher compared to those of MS SBD. These high values of n for MS and MIS type SBDs can be attributed to the existence of nonlinearly deposited insulator layer, interface states, image force lowering and the formation of barrier height at M/S interface. The double-logarithmic I–V plots of MS and MIS SBDs were drawn and given in Fig. 2, respectively, in order to achieve better understanding of the current conduction mechanism in detail. The double-logarithmic I–V plot has two distinct linear regions for
M. G¨ okc- en et al. / Physica B 406 (2011) 4119–4123
1.0E-03
especially depend on this interfacial layer quality and Rs. The resistance of SBDs (Ri) can be named as shunt resistance (Rsh) in reverse bias region and series resistance (Rs) in forward bias region. The Rsh and Rs were determined from the Ri( ¼dVi/dIi) vs. applied bias voltage (Vi) plot, which are given in Fig. 3 determined from the I–V characteristics. It can be seen in Fig. 3 that at sufficiently high reverse and forward bias voltages, the Rsh and Rs of MS SBD have a constant value while the MIS SBD’s Rsh and Rs values decrease in two bias voltage regions. The values of Rs were found as 4.92 kO and 22.36 kO for MS and MIS SBDs, respectively. The values of Rsh were found as 1.57 MO and 728.68 MO for MS and MIS SBDs, respectively. It is clear that both the values of Rsh and Rs were found to strongly depend on the applied bias voltage and interfacial insulator layer. In addition, the values of the Rs of these MS and MIS Schottky diodes were evaluated from the forward bias I–V data using the methods developed by Cheung and Cheung [13]. The forward bias current–voltage characteristics due to the thermionic emission of Schottky diodes with the series resistance can be expressed as [9–11,13] Cheung’s functions:
1.0E-04
1.0E-06
1.0E-07 MS MIS
1.0 V (V)
0.1
10.0
Fig. 2. Double-logarithmic I–V plots of the Au/n-Si (MS) and Au/SnO2/n-Si (MIS) SBDs at room temperature.
HðIÞ ¼ Vn
1.0E+08
ð6Þ
MS
1.5
1.0E+06
MS MIS
dV/dLn (I) H (I)
(V)
H (I) = 6602.9I + 1.0038
1.0E+05
1.0
dV/dLn (I) = 6707.3I + 0.1226
0.5
1.0E+04
2E -0 4 1.
04 E1. 1
04 E1. 0
9. 0
E-
05
0E -0 5 8.
0E -0 5
I (A)
Fig. 3. Resistance of the Au/n-Si (MS) and Au/SnO2/n-Si (MIS) SBDs at room temperature.
MIS
5.0 4.0 (V)
H (I) = 130274I + 3.9145
3.0
dV/dLn (I) H (I)
2.0 1.0
dV/dLn (I) = 129647I + 0.1738
-0 6 3. 5E
3. 0E -0 6
06 5E 2.
06
06 0E 2.
0E -
07
0.0
5.
MS SBD, while three distinct linear regions for MIS SBD. This discrepancy can be attributed to the existence of interfacial layer at the M/S interface. A detailed analysis of these plots emerged that the charge transport is mainly governed by space charge limited current (SCLC) process rather than the other current conduction process. According to the SCLC theory, when applied voltage is increased, the injection of electrons from electrode to the films increases accordingly [12]. The series resistance is a very important parameter of MS and MIS Schottky diodes, because when a voltage is applied to an MS or an MIS Schottky diode, the total voltage is shared by interfacial layer between metal and semiconductor, depletion layer and series resistance of the structure. The magnitude of this shared voltage depends on the interfacial insulator layer and Rs [6]. Therefore, the performance and the reliability of these devices
7.
8.0
1. 5E -
6.0
0E -0 5
4.0
E06
2.0 V (V)
0E -0 5
0.0
5.
-4.0
kT I ln ¼ IRS þ n fB0 q AAn T 2
2.0
1.0E+07
1.0E+03 -2.0 0.0
ð5Þ
For both equations, dV/dln(I) and H(I) vs. I plots should give a straight-line for the data of downward curvature region in the forward bias I–V characteristics. Thus, slopes of dV/dln(I) and H(I) vs. I will give Rs of these MS and MIS Schottky diodes. Fig. 4 shows the
1.0E+09
R (Ω )
dV kT ¼ IRs þ n dlnðIÞ q
6.
1.0E-09
1. 0
I (A)
1.0E-05
1.0E-08
4121
I (A) Fig. 4. Experimental dV/dln(I) and H(I) vs. I plots of the Au/n-Si (MS) and Au/SnO2/n-Si (MIS) SBDs at room temperature.
M. G¨ okc- en et al. / Physica B 406 (2011) 4119–4123
where b is the voltage coefficient of the effective barrier height Fe, used in the place of the barrier height, and it is a parameter that combines the effects of interface states and Rs [1,11,15–18]. For non-ideal MS and MIS type SBDs, the voltage and series resistance dependences of ideality factor n(V) due to Nss can be written with the following Equations:[1,11] q ðVIRs Þ d es ¼ 1þ þ qNss ðVÞ ð8Þ nðVÞ ¼ kT lnðI=I0 Þ ei WD where d is the thickness of interfacial insulator layer, WD is the width of the space charge region, es ¼11, 8 eo and ei ¼7eo are the permittivities of the interfacial insulator layer and the semiconductor, respectively. The expression for the interface state density is deduced as follows [1,9,11,17]: 1 ei es NSS ðVÞ ¼ ðnðVÞ1Þ ð9Þ q d WD The interfacial insulator layer (SnO2) thickness for the MIS SBD, d, was obtained as about 40 A˚ from C–V characteristics using the equation for insulator layer capacitance (Cox ¼ eieoA/d), where ei ¼ 7eo and eo is the permittivity of free space [11,17]. Furthermore, in n-type semiconductors, the energy of Nss with respect to the bottom of conductance band at the surface of the semiconductor is given by [1,11,17] Ec Ess ¼ q½Fe ðVIRs Þ
ð10Þ
Fig. 5 shows the energy distribution profiles of the Nss with and without taking Rs obtained from forward bias I–V characteristics of MS and MIS SBDs at room temperature into account. The energy density distribution of Nss profile of MS and MIS type SBDs obtained without taking Rs into account has an apparent exponential increase from mid gap towards the bottom of the conductance band of Si as can be seen in Fig. 5. In addition, the results indicate that Nss values increase with the increasing bias voltage values. This confirms that the density of interface states changes with bias and each of the applied biases corresponds to a position inside the Si gap. MIS SBD’s Nss values are 5–10 times lower than those of MS SBD’s whether Rs is taken into account or not. The purpose of the SnO2 insulator layer is to prevent the reaction and inter-diffusion between the Au metal contact and semiconductor as well as to passivate active dangling bonds at semiconductor surface and reduce the high gate-leakage current [19]. This reduction in the leakage current in the MIS SBD is caused by the thin interfacial insulator layer and is due to a combination of increased barrier height at metal/semiconductor
1.8E+14
MS
1.5E+14 Nss (eV-1cm-2)
experimental dV/dln(I) and H(I) vs. I plots of MS and MIS Schottky diodes. Also, using n and kT/q values in Eqs. 5 and 6, the values of FBo are derived from the plots in Fig. 4. As can be seen from Fig. 4 and Table 1, the Rs values, which are derived using two methods (dV/dln(I) and H(I) vs. I), are in good agreement with each other for both MS and MIS SBDs for Rs. In the literature, Au/SnO2/n-Si SBDs were fabricated by different techniques and obtained about similar results for most of these diodes parameters [4,14,15]. For rectifying ratio and I0, more suitable values were obtained at our current study according to higher shunt resistance. The nonlinearity of the I–V characteristics of the SBDs at high bias voltages indicates a continuum of Nss, which is at equilibrium with the semiconductor and Rs. In addition, when the interfacial layer is sufficiently thick, the transmission probability between the metal and the interface states is very small. The effective barrier height Fe is assumed to be bias-dependent due to the presence of an interfacial insulator layer and series resistance, and it is given as [11,15–18] 1 ðVIRs Þ Fe ¼ FBo þ bðVÞ ¼ FBo þ 1 ð7Þ nðVÞ
1.2E+14 9.0E+13 6.0E+13
Without Rs With Rs
3.0E+13
0.0E+00 0.50 0.52 0.54 0.56 0.58 0.60 0.62 0.64 0.66 0.68 Ec-Ess (eV) 1.8E+13
MIS
1.5E+13 Nss (eV-1cm-2)
4122
1.2E+13 9.0E+12
Without Rs With Rs
6.0E+12 3.0E+12 0.60 0.62 0.64 0.66 0.68 0.70 0.72 0.74 0.76 0.78 0.80 0.82 Ec-Ess (eV) Fig. 5. Density of interface states (Nss) as a function of Ec–Ess with and without Rs effect for Au/n-Si (MS) and Au/SnO2/n-Si (MIS) SBDs at room temperature.
interface and reduced velocity of charge carriers. These combined effects cause important outcomes such as 25 times and 5–10 times decrease in the leakage current and Nss, respectively, when the MS SBD is converted into MIS SBD. Therefore, we can say that Nss is affected strongly by the existence and the thickness of the interfacial insulator layer at M/S interface and Rs. There are a lot of studies in the literature showing that the forward bias current– voltage characteristics at sufficiently large voltages have been affected from series resistance and the existence and the thickness of the interfacial layer [1,11,12,20].
4. Conclusions The effects of interfacial insulator layer and series resistance on the forward and reverse bias current–voltage (I–V) characteristics of the SBDs have been studied at room temperature. The non-ideal forward bias I–V behavior observed in both MS and MIS SBDs is attributed to a change in the metal/semiconductor barrier height due to the interface states, interfacial insulator layer and series resistance. The values of n, Rs and FBo, which were calculated from ln(I) vs. V plots and Cheung methods for MS SBD, are lower than those for MIS SBD. Regarding the interface states of both SBDs obtained without taking Rs into account, an apparent exponential increase from mid gap towards the bottom of the conductance band is observed. Nss values increase with the increasing bias voltage values. MIS SBD’s Nss values are 5–10 times lower than those of MS SBD’s whether Rs is taken into account or not. Hence, we can say that the interface state density,
M. G¨ okc- en et al. / Physica B 406 (2011) 4119–4123
leakage current, series resistance and barrier height depend on the existence of the interfacial insulator layer between metal and semiconductor. Also, we can conclude that the series resistance should be taken into account in order to obtain accurate and reliable results of the interface states density as above. In conclusion, in our study, interfacial insulator layer has some positive effects such as higher rectifying ratio and low leakage current.
Acknowledgments ¨ This work is supported by Duzce University Scientific Research Project (Project no. 2010.05.02.056). References ¨ zc- elik, H. Shtrikman, Vacuum 83 (2009) 1060. [1] H. Altuntas- , S- . Altındal, S. O [2] Z. Pan, Z. Dai, Z.L. Wang, Science 291 (2001) 1947.
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