- Email: [email protected]
SoH estimators
Microelectronics Reliability 84 (2018) 66–74
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
FPGA-based design of advanced BMS implementing SoC/SoH estimators a,⁎
b
Bijender Kumar , Neeta Khare , P.K. Chaturvedi a b c
T
c
Electronics Engineering Department, Banasthali University, Banasthali, Rajasthan 304022, India Leclanche'SA, Av. des Sports, 1400 Yverdon-les-Bains, Switzerland Electronics & Communication Engineering, SRM University, Ghaziabad, U.P., India
A R T I C LE I N FO
A B S T R A C T
Keywords: EVs HEVs SoC SoH ANN MATLAB BMS FPGA HDL RTL
Energy storage system, usually a battery, become essential part for all electric drive vehicles such as hybrid electric vehicle (HEV), plug-in hybrid electric vehicle (PHEV) and electric vehicle (EV) in the coming decades. These energy storage systems include Li-ion batteries, Ni-MH batteries, lead-acid batteries and ultra-capacitors. An accurate Battery Management System (BMS) is highly demanded integrated system in all electric derive vehicles to ensure the optimum use of an energy storage system. The battery's state monitoring & evaluation, charge control and cell balancing are the important features of any BMS. However, due to unavailability of inaccurate battery's state-of-charge (SoC)/state-of-health (SoH) estimators and uncertainty of battery's performance, new approaches of BMS design are under development to control batteries optimally and hence, the vehicle performance. In addition, most of the existing BMSs either do not provide SoH at all or provide it as a function of capacity degradation over the battery usage. This research paper presents the field-programmable gate array (FPGA) - based Advanced BMS design using MATLAB-to-FPGA design flow. The Advanced BMS design provides the combined estimation of both SoC and SoH of a rechargeable battery. This research paper also summarizes the Neuro-Fuzzy & statistical models implemented in Advanced BMS for accurate estimation of battery's SoC & SoH respectively. Further, this research paper presents the selection of suitable FPGA and its hardware realization implementing Advanced BMS. Finally, the experimental results are confirmed by simulation and synthesis of its register transfer level (RTL) design. FPGA-based Advanced BMS would provide the best chip solution for a generalized BMS with benefits of low Non-recurring engineering (NRE) cost, low power consumption, high speed of operation, large reconfigurable logic and large data storage capacity.
1. Introduction As the automotive industry moves through the second decade of the 21st century, especially transportation industries have now convinced themselves to electrify their vehicles and to produce EVs & HEVs. The driving force towards the electrification of vehicles includes: Government incentives for buying electric and plug-in hybrid vehicles, the economic and political problems related to oil dependency, the effect of oil prices on consumer's car buying habits, carbon dioxide emission and pollution awareness, and the effect of current and upcoming worldwide emissions regulations. Unlike traditional vehicles, EVs require a different value chain and different processes to support them. Moreover, consumer perceptions of the practicality, functionality and the potential advantages of EVs remain largely mixed in such areas as cost, savings, convenience, travel range and charging infrastructure. In recent years, the rechargeable batteries have proven themselves as the primary source of clean energy for various applications such as transportation, grid storage & mobile systems. The evolution of ⁎
Corresponding author. E-mail address: [email protected] (B. Kumar).
https://doi.org/10.1016/j.microrel.2018.03.015 Received 4 October 2017; Received in revised form 14 March 2018; Accepted 15 March 2018 Available online 19 March 2018 0026-2714/ © 2018 Elsevier Ltd. All rights reserved.
electricity storage technologies ensures the appearance of more efficient batteries and the launch of electric cars with ranges comparable to that of fossil fuel car. Due to the relative maturity of the batteries, much effort by academia and industry is devoted to making batteries reliable and affordable for the electrification of vehicles. In case of transportation, the detection of in-time battery failures, monitoring and determination of the battery state is still a challenge for researchers to monitor accurate battery's SoC & SoH. Battery Monitoring means keeping a check on the key operational parameters during charging and discharging such as voltage, current, battery internal resistance, ambient temperature and charging/discharging cycles [1]. In addition to the development of new batteries with better capacity and power capability, BMS - an independent system addressing the battery monitoring is also required to better utilize the capacity of the batteries and to provide diagnostic information for the benefit of the driver. An efficient BMS ensures the optimum use of the battery and provides the accurate monitoring of SoC & SoH of a rechargeable battery. In recent example of Boeing 787 and Samsung galaxy 7 smart phones, the fire
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implemented in Statistical model to address SoH of the battery. These SoC and SoH estimators are also tested and validated here on the collected data set of lead-acid battery. For ease of FPGA implementation; the Simulink model of Advanced BMS implementing the SoC and SoH algorithms of the battery is developed in step 3 using MATLAB/ Simulink [3]. In step 4, the Simulink model of Advanced BMS is then converted into register transfer level (RTL) model. RTL model details the design abstraction to the Advanced BMS model in terms of the flow of digital signals (data) between the hardware registers, and the operations performed on those signals. The VHDL codes describing the RTL model of Advanced BMS are finalized using HDL Coder Toolbox of MATLAB. In addition, design validation is also performed using functional or behavioral simulation in this step of design flow [4]. In step 5, we have performed logic synthesis to achieve a netlist of gates/blocks specified in the targeted FPGA device and also performed mapping to get target FPGA architecture. Placement is followed by mapping to select the optimal position for each block. The basic goals of placement in FPGA design flow is to locate functional blocks and interconnects those are required to route the signals between blocks. A good placement is extremely important for FPGA system to reduce the design cost and power loss. Placement directly affects the routability and the performance of FPGA design. Routing is the last step in the design methodology prior to generating the bit file required to program the FPGA. Lastly, timing simulation is performed to validate the logical correctness of the design considering the time response of the FPGA device. In this FPGA design methodology, it takes the mapped, placed and routed design as input and generates the necessary bit stream to program the logic and interconnects to implement the intended logic design and layout of Advanced BMS on the target FPGA device.
and explosion of a battery can cause the fatal accidents. Obviously, detecting in-time battery failures and determination of the battery state become necessary for system and user safety. And, the efficient BMS must be the parts of all electric derive vehicles to notify the user with the state of the safety, usage, performance, and longevity of the battery. However, many different commercialised BMS products for various application platforms and few chip sets for battery management exist in markets today which are still in premature stage. Neither the standard definition of SoC and SoH exist, nor do BMS designs follow any common standard safety, charging methodology and communication protocols. Even if state-of-the-art algorithms and monitoring methods were developed and applied in EVs and HEVs, the reliability of BMS would still make end users suspicious. The scope of this research paper covers the FPGA-based design of Advanced BMS for combined and accurate estimation of SoC & SoH of the rechargeable battery. The presented research work is primarily focused on the Excide make MF40sv 12 V lead-acid battery which is used for cranking of the engine and slow electric discharge in non-electric automotive. The Advanced BMS is designed and tested on the experimental data collected for lead-acid battery at Excide Industry Ltd. INDIA. The Advanced BMS design can be easily extended to other battery technologies also by changing the training and testing data sets of the model. The presented research work is important because it creates an option for a BMS system to have a separate high computational power chip to execute accurate BMS algorithms with low capacity master controller. The development process of FPGA-based Advanced BMS is described in Section 2. The intelligent battery monitoring techniques used as SoC & SoH estimators are discussed in Section 3. Section 4 explains the process of FPGA selection and the suitable FPGA implementing the Advanced BMS. The FPGA design implementation of Advanced BMS is explained in Section 5. The experimental results of simulation and synthesis are analyzed in Section 6, followed by the conclusion remarks in Section 7.
3. Intelligent battery monitoring techniques Please note, as a case study for FPGA-based Advanced BMS chip implementation, we have used our previous work models: Neuro-Fuzzy & Statistical model for SoC & SoH estimation respectively [5].
2. Development process – MATLAB-to-FPGA design flow Today, there are various methodologies involved in the development of digital systems. These methodologies generally include the processes for tuning, validating and verifying systems. In this research paper, the chip based solution of an Advanced BMS providing the combined estimation of both SoC and SoH of a rechargeable battery is developed using MATLAB-to-FPGA design flow. The MATLAB-to-FPGA design flow used to develop the FPGA-based Advanced BMS is shown in Fig. 1. The initial step 1 in the adopted design methodology is the parameters selection and data collection activity. The selection of input parameters affecting the battery's state and health is always a challenge in any kind of BMS design. In our previous research work [2] where, our colleagues have collected and analyzed the data set at Exide Industries Ltd, R&D Lab, Kolkata, INDIA. The following five electrical parameters of a 12 V lead-acid battery MF40sv are selected for estimating SoC and SoH of a battery: - 1) consumption time, 2) current drawn, 3) terminal voltage, 4) temperature, and 5) internal resistance. The impact of these parameters on specific gravity (SG) of the battery's electrolyte for different charged condition of battery (100%, 75% & 50%) at different temperature (40 °C, 27 °C & 0 °C) for different age of battery (fresh, one year and two year old) in both slow discharge & real cranking operation of a car, was also analyzed in their data collection activity. In step 2 of the design flow, the Neuro-Fuzzy algorithm and the regression formula are developed to address the SoC and SoH of a rechargeable battery. The neural network is first used to model the electrochemical behavior of the lead-acid battery and to measure the SG of battery's electrolyte. Then the fuzzy logic is deployed to map the SG and temperature onto SoC of the battery. The regression formula is
3.1. Neuro-fuzzy model – SoC estimators Artificial Neural Networks (ANN) is well known for simulating nonlinear physical processes. ANN coupled with fuzzy logic provides a powerful mechanism to linguistically translate the behavior of a complex physical process. The nonlinear adoptive-learning capability of ANN is used here to simulate the discharging process of a battery which is translated linguistically using fuzzy logic to indicate the SoC of the battery in user friendly terms [5]. A schematic diagram of Neuro-Fuzzy model for SoC determination is shown in Fig. 2 [6,7]. Author has used ANN to simulate the discharge process of a battery by mapping of five online parameters of battery such as voltage, current, internal resistance, discharge duration and temperature onto the SG of electrolyte. The SG of battery electrolyte has been known as accurate measures of SoC. The SG and temperature are then mapped onto SoC of battery using Fuzzifier to represent results in linguistic terms such as Fully Charged, > Half Charged, Half Charged, < Half Charged and Flat Charged. In the Fig. 2, the parameters 1–5 are the real-time inputs to the ANN to generate output in terms of SoC indications. These inputs are 1) consumption time, 2) current drawn, 3) terminal voltage, 4) temperature, and 5) internal resistance. These parameters are directly measurable. ANN model implemented in Neural Network Toolbox of MATLAB consists of the input layer (containing five inputs neurons), two hidden layers (containing eleven neurons each) and output layer (containing one neuron). The ANN is trained using combined sets of data for slow discharge and real cranking operations for different battery ages at various environment temperatures for various initial SoC 67
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Fig. 1. MATLAB to FPGA design flow.
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Fig. 2. A schematic diagram of Neuro-Fuzzy model for SoC determination.
Table 1 Fuzzy rule base for linguistic variables of SoC. Fig. 3. Block diagram of FPGA-based design of advanced BMS.
Temperature Specific Gravity VVL
VL
Low
medium high
VH
VVH
Very Low
Flat
Flat
Flat
Flat
Low
Flat
Flat
Flat
< Half
Flat
Half
>Half
Medium
Flat
Flat
Flat
Half
>Half
>Half
>Half
High
Flat
Half
>Half
>Half
Full
Very High
Half
>Half
Full
Full
two parameters that are SG slope and the terminal voltage slope.
4. FPGA selection FPGAs provide a tremendously exciting implementation platform. FPGAs are used to replace Application Specific ICs (ASICs), such as digital receivers, and programmable general purpose processors or DSPs. Even though programmable logic has been around for many years, the latest FPGAs are more powerful and making their way as the right solution for many embedded applications. Each new generation of FPGA devices delivers faster speeds, improved density, larger memory resources and more flexible interfaces. The general block diagram of FPGA-based advanced BMS chip implementation is shown in Fig. 3. The values of the following five parameters of a lead acid battery 1) consumption time, 2) current drawn, 3) terminal voltage, 4) temperature, 5) internal resistance can easily be extracted using the interfacing circuitry. The data set of these inputs is collected using laboratory based circuits-Bitrode battery test system and Agilent impedance measurement system. The details of data collection activity are briefed in Section 2. The real-time test set parameters of selected inputs are applied to input/output ports of FPGA and processed by the digital signal processing (DSP) blocks of FPGA implementing SoC and SoH estimators. Three basic models deployed in estimation of battery's SoC and SoH: a) Artificial Neural Network controller b) Fuzzy Logic controller c) Statistical Controller are implemented using DSP blocks of FPGA. ANN controller computes the neural network algorithm to measure the SG of battery's electrolyte. The SG and battery temperature are then applied to fuzzy logic controller to estimate the SoC of the battery. The combination of ANN controller and Fuzzifier is termed as Neuro-Fuzzy Controller that estimates SoC of a battery. The statistical controller block computes the regression formula to estimate the SoH of the battery. The display of SoC & SoH maintains the past status till input discharge current and time parameters are zero. As soon as discharge current and discharge time appears at input, the algorithm starts executing a new set of parameters to compute new values on display. Clock triggering regulates the process of FPGA based BMS chip implementation. The selecting the right FPGA device for design implementation is very important and can impact the overall success of the design. After targeting many FPGAs for implementation, we have finally chosen the Xilinx Virtex-7 xc7vx485tffg1761-2 FPGA which suits well for Advanced BMS chip implementation. The comparison analysis of different FPGAs targeted for Advanced BMS chip implementation is summarized in Table 2.
conditions. The ANN is retrained in this research paper and generates an accuracy of 99.90% [3]. The output SG of ANN along with the battery temperature is used as input to a Fuzzifier to provide SoC in linguistic terms such as very high, high, half, low and very low. Fuzzifier is implemented in Fuzzy Toolbox of MATLAB. Fuzzy logic and 35 defined rule base are deployed in order to map SG and temperature onto SoC. If-then rules of Fuzzy controller are defined in the Table 1 [3,6] to determine the linguistic term of SoC of the battery. Here, SG is represented in linguistic terms such as VVL, VL, Low, medium, high, VH and VVH. The linguistic terms used for represent the temperature are Very Low, Low, Medium, High and Very High. 3.2. Statistical model – SoH estimators The cause of battery health deterioration is the effect of aging on the grid, electrodes, contacts, corrosion and charging/discharging cycles. The SoH of a lead acid battery is modeled using multivariate linear regression [8] on the aging effect and in-time consumption of the battery. It has been observed that the slopes of parameters like specific gravity, terminal voltage and internal resistance with respect to time (m, m′, m″ respectively) indicate the effect of age. Author has calculated the various slops from the collected data set by testing 12 V-70 Ah lead-acid battery [9]. In the statistical model, a formula is obtained after applying the multiple regression technique:
SoH = 1.0043 + 0.0088(TT × C) + 3.8925 m(SG) + 0.2444m′ (OCV) –0.0863m″ (IR) where TT is the run-time of the battery, C is the discharge rate and IR is the internal resistance. TT × C gives the ampere-hour consumption of the battery and m(SG), m′ (OCV), m”(IR) are slopes refer to aging of the battery. The computed results of statistical model showed that the SoH of lead acid battery for real cranking operation of a car is affected 60% by current consumption, 30% by the IR slope and 10% by the remaining 69
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Table 2 Comparison of different FPGAs resources utilization. FPGA Resources
Logic used (LUTs) Registers used (flip flops) Block arithmetic/DSP slices SLICEL (logic slice) SLICEM (memory slice IO Ports
Spartan-6
Virtex-5
Virtex-6
Virtex-7
Available
Required
Available
Required
Available
Required
Available
Required
27,288 54,576 58 1809 1602 296
16,816 773 62 1115 987 366
81,920 81,920 320 14,160 6320 840
11,800 773 326 2040 911 366
150,720 301,440 768 23,080 14,600 600
5620 773 773 861 545 366
303,600 607,200 2800 43,200 32,700 700
1123 751 1125 160 121 366
“Advanced_BMS” is presented in Fig. 4. The RTL schematic of Advanced BMS for FPGA implementation consists of two major components NFM1 (neuro_fuzzy_model) and SM1 (Statistical_Model) for estimating the SOC/battery_soc_bms_out & SOH/ exp_battery_life_bms_out respectively. The positive symbols on the NFM1 & SM1 modules can be expanded to get the detailed internal circuitry (Gate Level design) of NFM1 & SM1. The inputs and outputs of the Advanced BMS design are mapped to the physical I/O pins of the selected FPGA. The battery parameters required to estimate the SoC & SoH of battery are applied to the input ports of selected FPGA using 64bit format of each input as shown in Fig. 4. In this RTL design, the allocation of pin numbers is automatically performed by the Xilinx implementation tools. The allocation of pin numbers to the I/O pads is shown by the schematic diagram of the Advanced BMS design in Fig. 4. The enable signal makes the Advanced BMS active if it is 1 and deactivate if it is 0. The complete architecture of Advanced BMS is triggered for operation on the rising edge of the clock. Once the Advanced BMS is activated & triggered, the processor runs the SoC & SoH algorithms to estimate the 3-bit output of linguistic SoC/battery_soc_bms_out and 64-bit SoH/exp_battery_life_bms_out output representation respectively. The outputs of Advanced BMS are displayed on the output ports of FPGA in accordance of the applied input parameters. The internal blocks of NFM1 & SM1 modules are also shown in Fig. 5. The block NFM1 is implementing two blocks F1/ANN_controller and F2/rule_base1to estimate SG and SoC respectively. The block SM1 is implementing SoH algorithms/Statistical model using RTL multiplier/adder/subtractor slices in FPGA as shown in Fig. 5. The complete FPGA architecture of Advanced BMS at lowest level of
The Table 2 shows that the resources required to implement the Advanced BMS on FPGA board are exceeded the resources available in Spartan-6, Virtex-5 and Virtex-6 FPGAs. The number of DSP blocks and IO ports in Spartan-6 FPGA are less than the required resources in implementation of Advanced BMS. Similarly, DSP blocks available in Spartan-6, Virtex-5 and Virtex-6 FPGAs are not enough to implement the Advanced BMS. The Virtex-7 FPGA suits well for implementing Advanced BMS as shown in Table 2. Therefore, the Virtex-7 FPGA (xc7vx485tffg1761-2) is selected for implementation of Advanced BMS which is a full-featured, highly-flexible and high-speed serial base platform FPGA. The selected FPGA also includes basic components of hardware, design tools, IP, and pre-verified reference designs for system designs that demand high-performance, serial connectivity and advanced memory interfacing. 5. FPGA design implementation In this research paper, the both Neuro-Fuzzy and Statistical models of SoC and SoH estimation are first designed and incorporated together in a Simulink model known as Advanced BMS. Further, Simulink model of Advanced BMS is converted in RTL model. The RTL model is validated at behavioral/functional level of design abstraction. We also performed synthesis of RTL model of Advanced BMS using Xilinx ISE Design Suite 14.1 for the selected Xilinx FPGA i.e. Virtex-7 FPGA, xc7vx485tffg1761–2. The synthesis is a process by which an abstract form of desired circuit behavior, typically at RTL, is turned into a design implementation in terms of logic gates/circuits. The RTL schematic of Advanced BMS using the logic synthesis of top entity named as
Fig. 4. RTL schematic of FPGA-based Advanced BMS.
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Fig. 5. Detailed RTL schematic of advanced BMS.
RTL model of Advanced BMS. The comparison between the expected battery life (%) estimated using Simulink model and expected battery life (%) using RTL model of Advanced BMS is presented in Table 4. The expected battery life (remaining SoH) is accurately measured by RTL model and found very much similar that of Simulink model. The RTL simulation results in Fig. 6 are representing the values of SoC/battery_soc_bms_out in linguistic terms which are full (86.82%), mthaf (64.09%), full (77.09%), mthaf (67.08%), lthalf (29.12%) and flat (16%). With the defined rule base and fuzzy membership functions defined in Fuzzifier, the percentage SoC are translated into linguistic variables. The both SoC & SoH estimation results simulate at the rising edge of the clock and when enable = 1. In addition, Fig. 6 indicates that Advanced BMS is deactivated before 2.0 μs as enable = 0 and it starts its operation for SoC estimation on the rising edge of clock & enable = 1at 2.0 μs. The SoC output of Advanced BMS changes its linguistic state depending on any change in the input parameters. Fig. 7 indicates that the simulation result for another output of Advanced BMS i.e. SoH/exp_battery_life_bms_out is activated on the rising edge of clock & enable = 1 at 1010.020 ns. The SoH output of Advanced BMS changes its percentage value depending on any change in the input parameters and slops defined in statistical model as shown in Fig. 7. The combined RTL simulation results of SoC/battery_soc_bms_out & SoH/exp_battery_life_bms_out estimation using RTL model of Advanced BMS are presented in Fig. 8. The simulation results of Simulink model and RTL model for SoC in %age and linguistic SoC respectively as presented in Table 3 are traced in Fig. 9. The comparison between expected battery life (remaining SoH) estimated using Simulink Model and RTL model of Advanced BMS is plotted in Fig. 10. In Fig. 10, the SoH simulation results are verified for
Table 3 Comparison of SoC %age and SoC linguistic. Sr. no.
SoC (%) from Simulink model
SoC (%) from RTL model
Linguistic SoC from RTL model
1 2 3 4 5 6 7
86.82% 64.09% 48.06% 77.09% 67.08% 29.12% 10%
86.82% 64.09% 48.06% 77.09% 67.08% 29.12% 10%
Full Mthalf Half Full Mthalf Lthalf Flat
abstraction (more design details) can be displayed by expending the + sign of all building blocks, but not included here because of lack of visibility. 6. Experimental results In this research paper, the FPGA-based chip design of Advanced BMS is developed for estimating the SoC & SoH of the lead-acid battery. Advanced BMS is focused for combined and accurate estimation of battery's SoC & SoH. The battery state monitoring algorithms, Neurofuzzy approach and statistical model for battery SoC and SoH respectively, are implemented in Advanced BMS. Advanced BMS design is tested and validated at every design level of design flow through the software simulation. The training, testing and validation of ANN provide more than 99% accurate results in battery's SG measurements and hence, in SoC measurements [6]. The comparison between SoC (%) estimated from Simulink model and SoC (%) & linguistic values of SoC estimated from RTL model of Advanced BMS are presented in Table 3. The accuracy in SoC measurement is consistent from Simulink model to
Table 4 Comparison between expected battery life estimated using Simulink & VHDL models of advanced BMS. Sr. no.
Charged state of battery
Temperature (°C)
Battery aging
Expected battery life (%) using Simulink model
Expected battery life (%) using RTL model
1 2 3 4 5 6
100%
27 °C
Fresh battery One year old battery Two year old battery Fresh battery One year old battery Two year old battery
91.49% 89.5% 85.81% 89.61% 82.99% 80.89%
91.4936% 89.510% 85.805% 89.608% 82.986% 80.891%
40 °C
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Fig. 6. RTL simulation of linguistic SoC presented at enable ‘high’ and rising clock's edge.
Fig. 7. RTL simulation of SoH (%) presented at enable ‘high’ and rising clock's edge.
timing & power optimization in synthesis/implementation process. The summary of available FPGA resources and utilized in Advanced BMS implementation is also plotted in Fig. 11.
fresh battery, one year old and two years old battery at 27 °C & 40 °C temperature considering 100% charged state of battery. In addition, Fig. 10 also represents that the expected battery life is decreasing as battery being old for 100% charged battery at different constant temperatures 27 °C & 40 °C. The expected battery life also decreases with increase in temperature. Further, a synthesis netlist of gates/blocks/resources utilized in FPGA implementation of Advanced BMS is achieved. The resources utilization summary of selected FPGA implementing the Advanced BMS and its operating parameters are annotated in Table 5. The results of the synthesis/implementation proved, in terms of resources consumption, the entire Advanced BMS system fits well by consuming the maximum 52% of logic hardware in Xilinx Virtex-7 xc7vx485tffg1761-2 FPGA. Once the hardware specifications have been achieved, the netlist is compiled into a bitstream file to be downloaded later in targeted FPGA on board. The desirable maximum clock frequency & reduced power consumption for Advanced BMS design can be targeted later during the
7. Conclusions In this research paper, we presented a FPGA-based chip design of Advanced BMS and discussed its design flow. The Advanced BMS design is focused for combined and accurate estimation of SoC & SoH of leadacid battery. The intelligent battery estimation algorithms, NeuroFuzzy approach and statistical model for SoC and SoH estimation respectively, are also outlined here. The selected Neuro-Fuzzy approach and statistical model have the capabilities to adopt nonlinear electrochemical behavior of battery and map them to accurate SoC & SoH respectively. The selected SoC and SoH estimators are first design and tested using different MATLAB tools (nntool and fuzzy tool). SoC and SoH estimators are iincorporated in Advanced BMS using the Simulink 72
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Fig. 8. RTL simulation of combined estimation of linguistic SoC & SoH (%) of the battery.
Fig. 9. SoC (%) versus SoC (linguistic).
Fig. 10. Expected battery life using Simulink & RTL model of advanced BMS versus battery aging.
tool of MATLAB. The Simulink model of Advanced BMS is tested well on the collected data set of lead-acid battery. Further, this Simulink model is then converted into the RTL model of Advanced BMS using the HDL coder tool of MATLAB. Finally, the RTL model of Advanced BMS is processed through compilation, simulation and synthesis processes to develop a FPGA-based architecture of Advanced BMS. The most of the existing BMS either do not provide SoH at all or provide it as a function of capacity degradation over the battery usage [10,11]. Capacity degradation alone cannot provide accurate battery health because battery health is a complex function of multi parameters. Battery health depends on electrolyte, electrode, separators and SEI (Solid Electrolyte Interface) layer which unfortunately do not often reflect in graceful capacity degradation but a sudden capacity loss. In most cases, after certain age of the battery, chances are huge that capacity degrades
suddenly due to SEI layer damage or electrodes damage. To predict the aging it is essential to reach out to get a model that includes electrochemical parameters or one that can map the electrochemical behavior of the battery. In addition, Most of the existing BMS systems use master controller that includes SoC & SoH algorithms and these estimation algorithms are mainly the parts of the software [12]. Due to limitation of BMS hardware design, the accurate algorithms which require higher computational power could not be used in these master controllers. Our paper focuses the electrochemical behavior modeling of a battery and presents a FPGA-based Advanced BMS to provide accurate and combined estimation of SoC & SoH estimation of the lead-acid battery. The work is important because it creates an option for a BMS system to have a separate high computational power chip to execute accurate BMS algorithms with low capacity master controller. 73
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Off-course, FPGA-based Advanced BMS should be preferred over other existing BMS because of low Non-recurring engineering (NRE) cost, low power consumption, high speed of operation, large reconfigurable logic, large data storage capacity, more flexible interfaces and hence better performance.
Table 5 Resources utilization summary for advanced BMS implementation. FPGA Logic/Resources Utilization
Available
Used
Utilization (%)
Logic used (LUTs) Registers used (flip flops) Block arithmetic/DSP48E1 SLICEL (logic slices) SLICEM (memory slices) IO ports Total CPU time to XST completion Add generic clock buffer (BUFG) Total memory usage Maximum clock frequency for IO_FIFO switching (RDCLK and WRCLK) Maximum frequency for block RAM switching Maximum frequency for DSP48E1 switching Maximum frequency for user clock Switching Maximum toggle frequency for CLB switching
303,600 607,200 2800 43,200 32,700 700 0.19 s 16 181,752 kb 470.37 MHz
1123 751 1125 160 121 366
1% 1% 40% 1% 1% 52%
References [1] Joan Lowy, Lithium batteries central to Boeing's 787 woes (Update), Phys.org Internet News Portal, 17 January 2013. [2] N. Khare, Intelligent Battery Monitoring, Ph.D. Thesis Banasthali University, Rajasthan, India, 2006. [3] Bijender kumar, Neeta Khare, P.K. Chaturvedi, Advanced battery management system using MATLAB/Simulink, International Telecommunications Energy Conference (INTELEC) Osaka, Japan, IEEE, 2015. [4] Bijender kumar, Neeta Khare, P.K. Chaturvedi, A vhdl implementation of advanced battery management system targeting FPGAs, International Multidisciplinary Scientific GeoConferences & EXPO - SGEM, 2015 Bulgaria. [5] Neeta Khare, Rekha Govil, and Surendra Kumar Mittal, “A Process of determining State of Charge and State of Health of a Battery”, Indian Patent, 813/KOL/2005. [6] Neeta Khare, Rekha Govil, A battery storage system for fault tolerance, International Telecommunications Energy Conference (INTELEC) Rome, Italy, IEEE, 2007. [7] Raj Kumar, Neeta Khare, Smart instrument for automotive battery application, Fourth International Conference on Computational Intelligence and Communication Networks, Mathura India, 2012. [8] N.R. Draper, H. Smith, Applied Regression Analysis, 3rd edition, John Wiley & Sons, 1998. [9] Neeta Khare, Shalini Chandra, Rekha Govil, Statistical modeling of SoH of an automotive battery for online indication, International Telecommunications Energy Conference (INTELEC) San Diego, CA, USA, IEEE, 2008. [10] X. Tian, B. Jeppesen, T. Ikushima, Accelerating state-of-charge estimation in FPGAbased battery management systems, 6th Hybrid and Electric Vehicles Conference (HEVC 2016), London, UK, March 2017. [11] Dennis Babu, Anirudh Kumar, Joydeb Roy Chowdhury, FPGA based battery management system for battery powered electric cars, The 9th International Conference on Intelligent Unmanned Systems, Jaipur, India, 2013. [12] M. Rezal, A.R. Zulaikha, M. Sabri, Orion battery management system (BMS) for lithium-ion battery pack, Colloquium of Education, Engineering & Technology (COLEET 2014) at Universiti Kuala Lumpur Malaysian Spanish Institute, Kulim HiTech Park, Kulim, Kedah, 2014.
543.77 MHz 650.20 MHz 412.50 MHz 1818 MHz
Fig. 11. Summary of FPGA Virtex-7 resources implementing Advanced BMS.
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Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
FPGA-based design of advanced BMS implementing SoC/SoH estimators a,⁎
b
Bijender Kumar , Neeta Khare , P.K. Chaturvedi a b c
T
c
Electronics Engineering Department, Banasthali University, Banasthali, Rajasthan 304022, India Leclanche'SA, Av. des Sports, 1400 Yverdon-les-Bains, Switzerland Electronics & Communication Engineering, SRM University, Ghaziabad, U.P., India
A R T I C LE I N FO
A B S T R A C T
Keywords: EVs HEVs SoC SoH ANN MATLAB BMS FPGA HDL RTL
Energy storage system, usually a battery, become essential part for all electric drive vehicles such as hybrid electric vehicle (HEV), plug-in hybrid electric vehicle (PHEV) and electric vehicle (EV) in the coming decades. These energy storage systems include Li-ion batteries, Ni-MH batteries, lead-acid batteries and ultra-capacitors. An accurate Battery Management System (BMS) is highly demanded integrated system in all electric derive vehicles to ensure the optimum use of an energy storage system. The battery's state monitoring & evaluation, charge control and cell balancing are the important features of any BMS. However, due to unavailability of inaccurate battery's state-of-charge (SoC)/state-of-health (SoH) estimators and uncertainty of battery's performance, new approaches of BMS design are under development to control batteries optimally and hence, the vehicle performance. In addition, most of the existing BMSs either do not provide SoH at all or provide it as a function of capacity degradation over the battery usage. This research paper presents the field-programmable gate array (FPGA) - based Advanced BMS design using MATLAB-to-FPGA design flow. The Advanced BMS design provides the combined estimation of both SoC and SoH of a rechargeable battery. This research paper also summarizes the Neuro-Fuzzy & statistical models implemented in Advanced BMS for accurate estimation of battery's SoC & SoH respectively. Further, this research paper presents the selection of suitable FPGA and its hardware realization implementing Advanced BMS. Finally, the experimental results are confirmed by simulation and synthesis of its register transfer level (RTL) design. FPGA-based Advanced BMS would provide the best chip solution for a generalized BMS with benefits of low Non-recurring engineering (NRE) cost, low power consumption, high speed of operation, large reconfigurable logic and large data storage capacity.
1. Introduction As the automotive industry moves through the second decade of the 21st century, especially transportation industries have now convinced themselves to electrify their vehicles and to produce EVs & HEVs. The driving force towards the electrification of vehicles includes: Government incentives for buying electric and plug-in hybrid vehicles, the economic and political problems related to oil dependency, the effect of oil prices on consumer's car buying habits, carbon dioxide emission and pollution awareness, and the effect of current and upcoming worldwide emissions regulations. Unlike traditional vehicles, EVs require a different value chain and different processes to support them. Moreover, consumer perceptions of the practicality, functionality and the potential advantages of EVs remain largely mixed in such areas as cost, savings, convenience, travel range and charging infrastructure. In recent years, the rechargeable batteries have proven themselves as the primary source of clean energy for various applications such as transportation, grid storage & mobile systems. The evolution of ⁎
Corresponding author. E-mail address: [email protected] (B. Kumar).
https://doi.org/10.1016/j.microrel.2018.03.015 Received 4 October 2017; Received in revised form 14 March 2018; Accepted 15 March 2018 Available online 19 March 2018 0026-2714/ © 2018 Elsevier Ltd. All rights reserved.
electricity storage technologies ensures the appearance of more efficient batteries and the launch of electric cars with ranges comparable to that of fossil fuel car. Due to the relative maturity of the batteries, much effort by academia and industry is devoted to making batteries reliable and affordable for the electrification of vehicles. In case of transportation, the detection of in-time battery failures, monitoring and determination of the battery state is still a challenge for researchers to monitor accurate battery's SoC & SoH. Battery Monitoring means keeping a check on the key operational parameters during charging and discharging such as voltage, current, battery internal resistance, ambient temperature and charging/discharging cycles [1]. In addition to the development of new batteries with better capacity and power capability, BMS - an independent system addressing the battery monitoring is also required to better utilize the capacity of the batteries and to provide diagnostic information for the benefit of the driver. An efficient BMS ensures the optimum use of the battery and provides the accurate monitoring of SoC & SoH of a rechargeable battery. In recent example of Boeing 787 and Samsung galaxy 7 smart phones, the fire
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implemented in Statistical model to address SoH of the battery. These SoC and SoH estimators are also tested and validated here on the collected data set of lead-acid battery. For ease of FPGA implementation; the Simulink model of Advanced BMS implementing the SoC and SoH algorithms of the battery is developed in step 3 using MATLAB/ Simulink [3]. In step 4, the Simulink model of Advanced BMS is then converted into register transfer level (RTL) model. RTL model details the design abstraction to the Advanced BMS model in terms of the flow of digital signals (data) between the hardware registers, and the operations performed on those signals. The VHDL codes describing the RTL model of Advanced BMS are finalized using HDL Coder Toolbox of MATLAB. In addition, design validation is also performed using functional or behavioral simulation in this step of design flow [4]. In step 5, we have performed logic synthesis to achieve a netlist of gates/blocks specified in the targeted FPGA device and also performed mapping to get target FPGA architecture. Placement is followed by mapping to select the optimal position for each block. The basic goals of placement in FPGA design flow is to locate functional blocks and interconnects those are required to route the signals between blocks. A good placement is extremely important for FPGA system to reduce the design cost and power loss. Placement directly affects the routability and the performance of FPGA design. Routing is the last step in the design methodology prior to generating the bit file required to program the FPGA. Lastly, timing simulation is performed to validate the logical correctness of the design considering the time response of the FPGA device. In this FPGA design methodology, it takes the mapped, placed and routed design as input and generates the necessary bit stream to program the logic and interconnects to implement the intended logic design and layout of Advanced BMS on the target FPGA device.
and explosion of a battery can cause the fatal accidents. Obviously, detecting in-time battery failures and determination of the battery state become necessary for system and user safety. And, the efficient BMS must be the parts of all electric derive vehicles to notify the user with the state of the safety, usage, performance, and longevity of the battery. However, many different commercialised BMS products for various application platforms and few chip sets for battery management exist in markets today which are still in premature stage. Neither the standard definition of SoC and SoH exist, nor do BMS designs follow any common standard safety, charging methodology and communication protocols. Even if state-of-the-art algorithms and monitoring methods were developed and applied in EVs and HEVs, the reliability of BMS would still make end users suspicious. The scope of this research paper covers the FPGA-based design of Advanced BMS for combined and accurate estimation of SoC & SoH of the rechargeable battery. The presented research work is primarily focused on the Excide make MF40sv 12 V lead-acid battery which is used for cranking of the engine and slow electric discharge in non-electric automotive. The Advanced BMS is designed and tested on the experimental data collected for lead-acid battery at Excide Industry Ltd. INDIA. The Advanced BMS design can be easily extended to other battery technologies also by changing the training and testing data sets of the model. The presented research work is important because it creates an option for a BMS system to have a separate high computational power chip to execute accurate BMS algorithms with low capacity master controller. The development process of FPGA-based Advanced BMS is described in Section 2. The intelligent battery monitoring techniques used as SoC & SoH estimators are discussed in Section 3. Section 4 explains the process of FPGA selection and the suitable FPGA implementing the Advanced BMS. The FPGA design implementation of Advanced BMS is explained in Section 5. The experimental results of simulation and synthesis are analyzed in Section 6, followed by the conclusion remarks in Section 7.
3. Intelligent battery monitoring techniques Please note, as a case study for FPGA-based Advanced BMS chip implementation, we have used our previous work models: Neuro-Fuzzy & Statistical model for SoC & SoH estimation respectively [5].
2. Development process – MATLAB-to-FPGA design flow Today, there are various methodologies involved in the development of digital systems. These methodologies generally include the processes for tuning, validating and verifying systems. In this research paper, the chip based solution of an Advanced BMS providing the combined estimation of both SoC and SoH of a rechargeable battery is developed using MATLAB-to-FPGA design flow. The MATLAB-to-FPGA design flow used to develop the FPGA-based Advanced BMS is shown in Fig. 1. The initial step 1 in the adopted design methodology is the parameters selection and data collection activity. The selection of input parameters affecting the battery's state and health is always a challenge in any kind of BMS design. In our previous research work [2] where, our colleagues have collected and analyzed the data set at Exide Industries Ltd, R&D Lab, Kolkata, INDIA. The following five electrical parameters of a 12 V lead-acid battery MF40sv are selected for estimating SoC and SoH of a battery: - 1) consumption time, 2) current drawn, 3) terminal voltage, 4) temperature, and 5) internal resistance. The impact of these parameters on specific gravity (SG) of the battery's electrolyte for different charged condition of battery (100%, 75% & 50%) at different temperature (40 °C, 27 °C & 0 °C) for different age of battery (fresh, one year and two year old) in both slow discharge & real cranking operation of a car, was also analyzed in their data collection activity. In step 2 of the design flow, the Neuro-Fuzzy algorithm and the regression formula are developed to address the SoC and SoH of a rechargeable battery. The neural network is first used to model the electrochemical behavior of the lead-acid battery and to measure the SG of battery's electrolyte. Then the fuzzy logic is deployed to map the SG and temperature onto SoC of the battery. The regression formula is
3.1. Neuro-fuzzy model – SoC estimators Artificial Neural Networks (ANN) is well known for simulating nonlinear physical processes. ANN coupled with fuzzy logic provides a powerful mechanism to linguistically translate the behavior of a complex physical process. The nonlinear adoptive-learning capability of ANN is used here to simulate the discharging process of a battery which is translated linguistically using fuzzy logic to indicate the SoC of the battery in user friendly terms [5]. A schematic diagram of Neuro-Fuzzy model for SoC determination is shown in Fig. 2 [6,7]. Author has used ANN to simulate the discharge process of a battery by mapping of five online parameters of battery such as voltage, current, internal resistance, discharge duration and temperature onto the SG of electrolyte. The SG of battery electrolyte has been known as accurate measures of SoC. The SG and temperature are then mapped onto SoC of battery using Fuzzifier to represent results in linguistic terms such as Fully Charged, > Half Charged, Half Charged, < Half Charged and Flat Charged. In the Fig. 2, the parameters 1–5 are the real-time inputs to the ANN to generate output in terms of SoC indications. These inputs are 1) consumption time, 2) current drawn, 3) terminal voltage, 4) temperature, and 5) internal resistance. These parameters are directly measurable. ANN model implemented in Neural Network Toolbox of MATLAB consists of the input layer (containing five inputs neurons), two hidden layers (containing eleven neurons each) and output layer (containing one neuron). The ANN is trained using combined sets of data for slow discharge and real cranking operations for different battery ages at various environment temperatures for various initial SoC 67
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Fig. 1. MATLAB to FPGA design flow.
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Fig. 2. A schematic diagram of Neuro-Fuzzy model for SoC determination.
Table 1 Fuzzy rule base for linguistic variables of SoC. Fig. 3. Block diagram of FPGA-based design of advanced BMS.
Temperature Specific Gravity VVL
VL
Low
medium high
VH
VVH
Very Low
Flat
Flat
Flat
Flat
Low
Flat
Flat
Flat
< Half
Flat
Half
>Half
Medium
Flat
Flat
Flat
Half
>Half
>Half
>Half
High
Flat
Half
>Half
>Half
Full
Very High
Half
>Half
Full
Full
two parameters that are SG slope and the terminal voltage slope.
4. FPGA selection FPGAs provide a tremendously exciting implementation platform. FPGAs are used to replace Application Specific ICs (ASICs), such as digital receivers, and programmable general purpose processors or DSPs. Even though programmable logic has been around for many years, the latest FPGAs are more powerful and making their way as the right solution for many embedded applications. Each new generation of FPGA devices delivers faster speeds, improved density, larger memory resources and more flexible interfaces. The general block diagram of FPGA-based advanced BMS chip implementation is shown in Fig. 3. The values of the following five parameters of a lead acid battery 1) consumption time, 2) current drawn, 3) terminal voltage, 4) temperature, 5) internal resistance can easily be extracted using the interfacing circuitry. The data set of these inputs is collected using laboratory based circuits-Bitrode battery test system and Agilent impedance measurement system. The details of data collection activity are briefed in Section 2. The real-time test set parameters of selected inputs are applied to input/output ports of FPGA and processed by the digital signal processing (DSP) blocks of FPGA implementing SoC and SoH estimators. Three basic models deployed in estimation of battery's SoC and SoH: a) Artificial Neural Network controller b) Fuzzy Logic controller c) Statistical Controller are implemented using DSP blocks of FPGA. ANN controller computes the neural network algorithm to measure the SG of battery's electrolyte. The SG and battery temperature are then applied to fuzzy logic controller to estimate the SoC of the battery. The combination of ANN controller and Fuzzifier is termed as Neuro-Fuzzy Controller that estimates SoC of a battery. The statistical controller block computes the regression formula to estimate the SoH of the battery. The display of SoC & SoH maintains the past status till input discharge current and time parameters are zero. As soon as discharge current and discharge time appears at input, the algorithm starts executing a new set of parameters to compute new values on display. Clock triggering regulates the process of FPGA based BMS chip implementation. The selecting the right FPGA device for design implementation is very important and can impact the overall success of the design. After targeting many FPGAs for implementation, we have finally chosen the Xilinx Virtex-7 xc7vx485tffg1761-2 FPGA which suits well for Advanced BMS chip implementation. The comparison analysis of different FPGAs targeted for Advanced BMS chip implementation is summarized in Table 2.
conditions. The ANN is retrained in this research paper and generates an accuracy of 99.90% [3]. The output SG of ANN along with the battery temperature is used as input to a Fuzzifier to provide SoC in linguistic terms such as very high, high, half, low and very low. Fuzzifier is implemented in Fuzzy Toolbox of MATLAB. Fuzzy logic and 35 defined rule base are deployed in order to map SG and temperature onto SoC. If-then rules of Fuzzy controller are defined in the Table 1 [3,6] to determine the linguistic term of SoC of the battery. Here, SG is represented in linguistic terms such as VVL, VL, Low, medium, high, VH and VVH. The linguistic terms used for represent the temperature are Very Low, Low, Medium, High and Very High. 3.2. Statistical model – SoH estimators The cause of battery health deterioration is the effect of aging on the grid, electrodes, contacts, corrosion and charging/discharging cycles. The SoH of a lead acid battery is modeled using multivariate linear regression [8] on the aging effect and in-time consumption of the battery. It has been observed that the slopes of parameters like specific gravity, terminal voltage and internal resistance with respect to time (m, m′, m″ respectively) indicate the effect of age. Author has calculated the various slops from the collected data set by testing 12 V-70 Ah lead-acid battery [9]. In the statistical model, a formula is obtained after applying the multiple regression technique:
SoH = 1.0043 + 0.0088(TT × C) + 3.8925 m(SG) + 0.2444m′ (OCV) –0.0863m″ (IR) where TT is the run-time of the battery, C is the discharge rate and IR is the internal resistance. TT × C gives the ampere-hour consumption of the battery and m(SG), m′ (OCV), m”(IR) are slopes refer to aging of the battery. The computed results of statistical model showed that the SoH of lead acid battery for real cranking operation of a car is affected 60% by current consumption, 30% by the IR slope and 10% by the remaining 69
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Table 2 Comparison of different FPGAs resources utilization. FPGA Resources
Logic used (LUTs) Registers used (flip flops) Block arithmetic/DSP slices SLICEL (logic slice) SLICEM (memory slice IO Ports
Spartan-6
Virtex-5
Virtex-6
Virtex-7
Available
Required
Available
Required
Available
Required
Available
Required
27,288 54,576 58 1809 1602 296
16,816 773 62 1115 987 366
81,920 81,920 320 14,160 6320 840
11,800 773 326 2040 911 366
150,720 301,440 768 23,080 14,600 600
5620 773 773 861 545 366
303,600 607,200 2800 43,200 32,700 700
1123 751 1125 160 121 366
“Advanced_BMS” is presented in Fig. 4. The RTL schematic of Advanced BMS for FPGA implementation consists of two major components NFM1 (neuro_fuzzy_model) and SM1 (Statistical_Model) for estimating the SOC/battery_soc_bms_out & SOH/ exp_battery_life_bms_out respectively. The positive symbols on the NFM1 & SM1 modules can be expanded to get the detailed internal circuitry (Gate Level design) of NFM1 & SM1. The inputs and outputs of the Advanced BMS design are mapped to the physical I/O pins of the selected FPGA. The battery parameters required to estimate the SoC & SoH of battery are applied to the input ports of selected FPGA using 64bit format of each input as shown in Fig. 4. In this RTL design, the allocation of pin numbers is automatically performed by the Xilinx implementation tools. The allocation of pin numbers to the I/O pads is shown by the schematic diagram of the Advanced BMS design in Fig. 4. The enable signal makes the Advanced BMS active if it is 1 and deactivate if it is 0. The complete architecture of Advanced BMS is triggered for operation on the rising edge of the clock. Once the Advanced BMS is activated & triggered, the processor runs the SoC & SoH algorithms to estimate the 3-bit output of linguistic SoC/battery_soc_bms_out and 64-bit SoH/exp_battery_life_bms_out output representation respectively. The outputs of Advanced BMS are displayed on the output ports of FPGA in accordance of the applied input parameters. The internal blocks of NFM1 & SM1 modules are also shown in Fig. 5. The block NFM1 is implementing two blocks F1/ANN_controller and F2/rule_base1to estimate SG and SoC respectively. The block SM1 is implementing SoH algorithms/Statistical model using RTL multiplier/adder/subtractor slices in FPGA as shown in Fig. 5. The complete FPGA architecture of Advanced BMS at lowest level of
The Table 2 shows that the resources required to implement the Advanced BMS on FPGA board are exceeded the resources available in Spartan-6, Virtex-5 and Virtex-6 FPGAs. The number of DSP blocks and IO ports in Spartan-6 FPGA are less than the required resources in implementation of Advanced BMS. Similarly, DSP blocks available in Spartan-6, Virtex-5 and Virtex-6 FPGAs are not enough to implement the Advanced BMS. The Virtex-7 FPGA suits well for implementing Advanced BMS as shown in Table 2. Therefore, the Virtex-7 FPGA (xc7vx485tffg1761-2) is selected for implementation of Advanced BMS which is a full-featured, highly-flexible and high-speed serial base platform FPGA. The selected FPGA also includes basic components of hardware, design tools, IP, and pre-verified reference designs for system designs that demand high-performance, serial connectivity and advanced memory interfacing. 5. FPGA design implementation In this research paper, the both Neuro-Fuzzy and Statistical models of SoC and SoH estimation are first designed and incorporated together in a Simulink model known as Advanced BMS. Further, Simulink model of Advanced BMS is converted in RTL model. The RTL model is validated at behavioral/functional level of design abstraction. We also performed synthesis of RTL model of Advanced BMS using Xilinx ISE Design Suite 14.1 for the selected Xilinx FPGA i.e. Virtex-7 FPGA, xc7vx485tffg1761–2. The synthesis is a process by which an abstract form of desired circuit behavior, typically at RTL, is turned into a design implementation in terms of logic gates/circuits. The RTL schematic of Advanced BMS using the logic synthesis of top entity named as
Fig. 4. RTL schematic of FPGA-based Advanced BMS.
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Fig. 5. Detailed RTL schematic of advanced BMS.
RTL model of Advanced BMS. The comparison between the expected battery life (%) estimated using Simulink model and expected battery life (%) using RTL model of Advanced BMS is presented in Table 4. The expected battery life (remaining SoH) is accurately measured by RTL model and found very much similar that of Simulink model. The RTL simulation results in Fig. 6 are representing the values of SoC/battery_soc_bms_out in linguistic terms which are full (86.82%), mthaf (64.09%), full (77.09%), mthaf (67.08%), lthalf (29.12%) and flat (16%). With the defined rule base and fuzzy membership functions defined in Fuzzifier, the percentage SoC are translated into linguistic variables. The both SoC & SoH estimation results simulate at the rising edge of the clock and when enable = 1. In addition, Fig. 6 indicates that Advanced BMS is deactivated before 2.0 μs as enable = 0 and it starts its operation for SoC estimation on the rising edge of clock & enable = 1at 2.0 μs. The SoC output of Advanced BMS changes its linguistic state depending on any change in the input parameters. Fig. 7 indicates that the simulation result for another output of Advanced BMS i.e. SoH/exp_battery_life_bms_out is activated on the rising edge of clock & enable = 1 at 1010.020 ns. The SoH output of Advanced BMS changes its percentage value depending on any change in the input parameters and slops defined in statistical model as shown in Fig. 7. The combined RTL simulation results of SoC/battery_soc_bms_out & SoH/exp_battery_life_bms_out estimation using RTL model of Advanced BMS are presented in Fig. 8. The simulation results of Simulink model and RTL model for SoC in %age and linguistic SoC respectively as presented in Table 3 are traced in Fig. 9. The comparison between expected battery life (remaining SoH) estimated using Simulink Model and RTL model of Advanced BMS is plotted in Fig. 10. In Fig. 10, the SoH simulation results are verified for
Table 3 Comparison of SoC %age and SoC linguistic. Sr. no.
SoC (%) from Simulink model
SoC (%) from RTL model
Linguistic SoC from RTL model
1 2 3 4 5 6 7
86.82% 64.09% 48.06% 77.09% 67.08% 29.12% 10%
86.82% 64.09% 48.06% 77.09% 67.08% 29.12% 10%
Full Mthalf Half Full Mthalf Lthalf Flat
abstraction (more design details) can be displayed by expending the + sign of all building blocks, but not included here because of lack of visibility. 6. Experimental results In this research paper, the FPGA-based chip design of Advanced BMS is developed for estimating the SoC & SoH of the lead-acid battery. Advanced BMS is focused for combined and accurate estimation of battery's SoC & SoH. The battery state monitoring algorithms, Neurofuzzy approach and statistical model for battery SoC and SoH respectively, are implemented in Advanced BMS. Advanced BMS design is tested and validated at every design level of design flow through the software simulation. The training, testing and validation of ANN provide more than 99% accurate results in battery's SG measurements and hence, in SoC measurements [6]. The comparison between SoC (%) estimated from Simulink model and SoC (%) & linguistic values of SoC estimated from RTL model of Advanced BMS are presented in Table 3. The accuracy in SoC measurement is consistent from Simulink model to
Table 4 Comparison between expected battery life estimated using Simulink & VHDL models of advanced BMS. Sr. no.
Charged state of battery
Temperature (°C)
Battery aging
Expected battery life (%) using Simulink model
Expected battery life (%) using RTL model
1 2 3 4 5 6
100%
27 °C
Fresh battery One year old battery Two year old battery Fresh battery One year old battery Two year old battery
91.49% 89.5% 85.81% 89.61% 82.99% 80.89%
91.4936% 89.510% 85.805% 89.608% 82.986% 80.891%
40 °C
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Fig. 6. RTL simulation of linguistic SoC presented at enable ‘high’ and rising clock's edge.
Fig. 7. RTL simulation of SoH (%) presented at enable ‘high’ and rising clock's edge.
timing & power optimization in synthesis/implementation process. The summary of available FPGA resources and utilized in Advanced BMS implementation is also plotted in Fig. 11.
fresh battery, one year old and two years old battery at 27 °C & 40 °C temperature considering 100% charged state of battery. In addition, Fig. 10 also represents that the expected battery life is decreasing as battery being old for 100% charged battery at different constant temperatures 27 °C & 40 °C. The expected battery life also decreases with increase in temperature. Further, a synthesis netlist of gates/blocks/resources utilized in FPGA implementation of Advanced BMS is achieved. The resources utilization summary of selected FPGA implementing the Advanced BMS and its operating parameters are annotated in Table 5. The results of the synthesis/implementation proved, in terms of resources consumption, the entire Advanced BMS system fits well by consuming the maximum 52% of logic hardware in Xilinx Virtex-7 xc7vx485tffg1761-2 FPGA. Once the hardware specifications have been achieved, the netlist is compiled into a bitstream file to be downloaded later in targeted FPGA on board. The desirable maximum clock frequency & reduced power consumption for Advanced BMS design can be targeted later during the
7. Conclusions In this research paper, we presented a FPGA-based chip design of Advanced BMS and discussed its design flow. The Advanced BMS design is focused for combined and accurate estimation of SoC & SoH of leadacid battery. The intelligent battery estimation algorithms, NeuroFuzzy approach and statistical model for SoC and SoH estimation respectively, are also outlined here. The selected Neuro-Fuzzy approach and statistical model have the capabilities to adopt nonlinear electrochemical behavior of battery and map them to accurate SoC & SoH respectively. The selected SoC and SoH estimators are first design and tested using different MATLAB tools (nntool and fuzzy tool). SoC and SoH estimators are iincorporated in Advanced BMS using the Simulink 72
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Fig. 8. RTL simulation of combined estimation of linguistic SoC & SoH (%) of the battery.
Fig. 9. SoC (%) versus SoC (linguistic).
Fig. 10. Expected battery life using Simulink & RTL model of advanced BMS versus battery aging.
tool of MATLAB. The Simulink model of Advanced BMS is tested well on the collected data set of lead-acid battery. Further, this Simulink model is then converted into the RTL model of Advanced BMS using the HDL coder tool of MATLAB. Finally, the RTL model of Advanced BMS is processed through compilation, simulation and synthesis processes to develop a FPGA-based architecture of Advanced BMS. The most of the existing BMS either do not provide SoH at all or provide it as a function of capacity degradation over the battery usage [10,11]. Capacity degradation alone cannot provide accurate battery health because battery health is a complex function of multi parameters. Battery health depends on electrolyte, electrode, separators and SEI (Solid Electrolyte Interface) layer which unfortunately do not often reflect in graceful capacity degradation but a sudden capacity loss. In most cases, after certain age of the battery, chances are huge that capacity degrades
suddenly due to SEI layer damage or electrodes damage. To predict the aging it is essential to reach out to get a model that includes electrochemical parameters or one that can map the electrochemical behavior of the battery. In addition, Most of the existing BMS systems use master controller that includes SoC & SoH algorithms and these estimation algorithms are mainly the parts of the software [12]. Due to limitation of BMS hardware design, the accurate algorithms which require higher computational power could not be used in these master controllers. Our paper focuses the electrochemical behavior modeling of a battery and presents a FPGA-based Advanced BMS to provide accurate and combined estimation of SoC & SoH estimation of the lead-acid battery. The work is important because it creates an option for a BMS system to have a separate high computational power chip to execute accurate BMS algorithms with low capacity master controller. 73
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Off-course, FPGA-based Advanced BMS should be preferred over other existing BMS because of low Non-recurring engineering (NRE) cost, low power consumption, high speed of operation, large reconfigurable logic, large data storage capacity, more flexible interfaces and hence better performance.
Table 5 Resources utilization summary for advanced BMS implementation. FPGA Logic/Resources Utilization
Available
Used
Utilization (%)
Logic used (LUTs) Registers used (flip flops) Block arithmetic/DSP48E1 SLICEL (logic slices) SLICEM (memory slices) IO ports Total CPU time to XST completion Add generic clock buffer (BUFG) Total memory usage Maximum clock frequency for IO_FIFO switching (RDCLK and WRCLK) Maximum frequency for block RAM switching Maximum frequency for DSP48E1 switching Maximum frequency for user clock Switching Maximum toggle frequency for CLB switching
303,600 607,200 2800 43,200 32,700 700 0.19 s 16 181,752 kb 470.37 MHz
1123 751 1125 160 121 366
1% 1% 40% 1% 1% 52%
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543.77 MHz 650.20 MHz 412.50 MHz 1818 MHz
Fig. 11. Summary of FPGA Virtex-7 resources implementing Advanced BMS.
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