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FPGA-based reconfigurable computing
Microprocessors and Microsystems 30 (2006) 281–282 www.elsevier.com/locate/micpro
Editorial
FPGA-based reconfigurable computing
This ‘‘Special Issue on FPGA-based Reconfigurable Computing’’ presents a collection of high-quality papers from the FPGA research community. The 23 accepted papers were selected from the 74 submissions received from 14 countries. The paper topics reflect the continuing evolution of this discipline with a growing emphasis on imaging processing and computing/networking security. Submissions were judged on novelty, generality, significance, clarity, and support criteria. The distribution of 74 submissions is from the following countries with parenthesized number of submissions: Australia (1), Brazil (2), Canada (2), United States (33), Spain (5), France (6), Greece (3), Italy (2), Japan (2), Mexico (6), Egypt (1), Singapore (2), Taiwan (4), and United Kingdom (5). All 74 submissions went through rigorous review process. There were total 208 reviews generated by 123 reviewers. It is not possible to conclude the review process of such large number of submissions within 9 weeks without the support from our reviewers. We wish to thank all the reviewers for their dedicated work. The 23 accepted papers are arranged to be published in three issues. In the first issue of the three-issue series, we have selected eight papers that cover a spectrum of FPGA-based reconfigurable computing. The topics covered in the papers are related to the issues of framework or infrastructure in reconfigurable computing. The authors have done an excellent job of presenting the material. We are sure this issue will be very informative for all the readers who are engaged in FPGA-based reconfigurable computing. The title of our first paper is ‘‘HIDE: A Hardware Intelligent Description Environment,’’ by K. Benkrid, S. Belkacemi, and A. Benkrid. This paper presents a logic-based structural hardware design environment. The proposed design environment allows hardware designers to describe and assemble highly efficient circuits from high level geometrical descriptions based on Signal Flow Graphs. Then, the system generates optimized hardware in EDIF format or VHDL. The performance, in terms of speed and area, of their proposed system is compared to some commercial tools.
0141-9331/$ - see front matter Ó 2006 Published by Elsevier B.V. doi:10.1016/j.micpro.2006.04.003
The second paper, entitled ‘‘Stochastic Spatial Routing for Reconfigurable Networks,’’ by A. DeHon, R. Huang, and J. Wawrzynek presents a stochastic search scheme in hardware-assisted routing. This route scheme can achieve comparable route quality to software-based routers. The area overhead of proposed scheme is also investigated in this paper. The title of our third paper is ‘‘Online Architectures: A Theoretical Formulation and Experimental Prototype,’’ by R. Sass, B. Greskamp, B, Leonard, J. Young, and S. Beeravolu. This paper suggests an online algorithm to make run-time reconfiguration decisions. The challenge in the online architectures is how to balance the overhead against expected performance gains. This paper provides a theoretical formulation of the problem and a report based on a prototype and simulations. The forth paper, entitled ‘‘Stream Computations Organized for Reconfigurable Execution,’’ by A. DeHon, Y. Markovsky, E. Caspi, M. Chu, R. Huang, S. Perissakis, L. Pozzi, J. Yeh, and J. Wawrzynek, presents a stream-oriented compute model, system architecture, and execution patterns that can capture and exploit the parallelism of spatial computations. The conventional register-transfer-level (RTL) hardware models are lacing of the flexibility to scale to exploit newer, larger, and faster hardware platform in reconfigurable systems. This paper describes hardware and software techniques to allow late-bound platform mapping. The title of our fifth paper is ‘‘Rapid Generation of Custom Instructions Using Predefined Dataflow Structures,’’ by S.K. Lam and T. Srikanthan. This paper proposes a methodology for rapid instruction set customization on RISPs (Reconfigurable Instruction Set Processors). The proposed system uses predefined sets of dataflow structures that are based on templates and reusable structures. The generated custom instructions were implemented in FPGA. The performance, in terms of area saving with comparable performance, of the proposed scheme is also compared to conventional implementation approaches. The sixth paper ‘‘EPICURE: A Partitioning and CoDesign Framework For Reconfigurable Computing,’’ by J. Diguet, G. Gogniat, and J. Phillippe presents a design
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Editorial / Microprocessors and Microsystems 30 (2006) 281–282
methodology to work between an abstraction specification and a heterogeneous reconfigurable architecture. This methodology includes graph extraction from a mixed Safe State Machine/C specification, system and architectural exploration and estimation and hardware/software partitioning. A video supervision application and a part of JPEG 2000 decoder are used to illustrate the proposed design paradigm. The seventh paper, ‘‘Dynamic Clock-Frequencies for FPGAs’’ by J.A. Bower W. Luk O. Mencer, M.J. Flynn, and M. Morf, deals with clocking strategy in FPGA. It argues that fixed clock frequency cannot take advantage of the full potential of an application running on a specific device. The paper proposes a scheme to allow dynamic clock-frequencies in FPGA. A framework that can explore the dynamic behavior of FPGA applications is presented. The proposed system can add circuitry to arbitrary FPGA designs to adjust clock-frequency to a safe limit under current operating conditions. A speed improvement as a result of the proposed scheme is also presented. The last but not least important paper in this issue, ‘‘Application Specific SIMD Synthesis for Reconfigurable Architectures,’’ by M. Cheema, and O. Hammami, aims to bring SIMD extensions to FPGA platform for embedded applications. This paper proposes a SIMD based synthesis flow for application specific instruction set extensions. This research used imaging processing applications as case study that employed AltiVec (a floating point and integer SIMD instruction set designed by Apple, IBM and Motorola) based SIMD unit and PowerPC embedded processor. The compatibility and customization issues in the synthesis flow are addressed. We hope that these research papers will help to give a better insight into the latest trend of works on the critical issues of FPGA-based reconfigurable computing. We take this
opportunity to thank all the authors who have submitted their papers for this special issue and also the reviewers who spend their valuable time in reviewing the papers and providing constructive comments. Without their participation, it would have been difficult for us to meet the deadlines. J. Morris Chang* C. Dan Lo Iowa State University, Department of Electrical and Computer Engineering, Ames, IA 50011, USA E-mail addresses: [email protected], [email protected] Available online 11 May 2006 J. Morris Chang is an associate professor in the Department of Electrical and Computer Engineering, Iowa State University. He received a PhD degree in Computer Engineering from North Caroline State University. Dr. Chang’s research interests include FPGA-based computing, Managed Run-time Environment and Wireless Networks.
Chia-Tien Dan Lo is an assistant professor in the Department of Computer Science, University of Texas at San Antonio. He received a PhD degree in Computer Science from Illinois Institute of Technology. Dr. Lo’s research interests include Reconfigurable Computing, Network Intrusion Detection, and High Performance Embedded Systems.
*
Corresponding author. Tel.: +1 515 294 7618; fax: +1 515 294 8432.
Editorial
FPGA-based reconfigurable computing
This ‘‘Special Issue on FPGA-based Reconfigurable Computing’’ presents a collection of high-quality papers from the FPGA research community. The 23 accepted papers were selected from the 74 submissions received from 14 countries. The paper topics reflect the continuing evolution of this discipline with a growing emphasis on imaging processing and computing/networking security. Submissions were judged on novelty, generality, significance, clarity, and support criteria. The distribution of 74 submissions is from the following countries with parenthesized number of submissions: Australia (1), Brazil (2), Canada (2), United States (33), Spain (5), France (6), Greece (3), Italy (2), Japan (2), Mexico (6), Egypt (1), Singapore (2), Taiwan (4), and United Kingdom (5). All 74 submissions went through rigorous review process. There were total 208 reviews generated by 123 reviewers. It is not possible to conclude the review process of such large number of submissions within 9 weeks without the support from our reviewers. We wish to thank all the reviewers for their dedicated work. The 23 accepted papers are arranged to be published in three issues. In the first issue of the three-issue series, we have selected eight papers that cover a spectrum of FPGA-based reconfigurable computing. The topics covered in the papers are related to the issues of framework or infrastructure in reconfigurable computing. The authors have done an excellent job of presenting the material. We are sure this issue will be very informative for all the readers who are engaged in FPGA-based reconfigurable computing. The title of our first paper is ‘‘HIDE: A Hardware Intelligent Description Environment,’’ by K. Benkrid, S. Belkacemi, and A. Benkrid. This paper presents a logic-based structural hardware design environment. The proposed design environment allows hardware designers to describe and assemble highly efficient circuits from high level geometrical descriptions based on Signal Flow Graphs. Then, the system generates optimized hardware in EDIF format or VHDL. The performance, in terms of speed and area, of their proposed system is compared to some commercial tools.
0141-9331/$ - see front matter Ó 2006 Published by Elsevier B.V. doi:10.1016/j.micpro.2006.04.003
The second paper, entitled ‘‘Stochastic Spatial Routing for Reconfigurable Networks,’’ by A. DeHon, R. Huang, and J. Wawrzynek presents a stochastic search scheme in hardware-assisted routing. This route scheme can achieve comparable route quality to software-based routers. The area overhead of proposed scheme is also investigated in this paper. The title of our third paper is ‘‘Online Architectures: A Theoretical Formulation and Experimental Prototype,’’ by R. Sass, B. Greskamp, B, Leonard, J. Young, and S. Beeravolu. This paper suggests an online algorithm to make run-time reconfiguration decisions. The challenge in the online architectures is how to balance the overhead against expected performance gains. This paper provides a theoretical formulation of the problem and a report based on a prototype and simulations. The forth paper, entitled ‘‘Stream Computations Organized for Reconfigurable Execution,’’ by A. DeHon, Y. Markovsky, E. Caspi, M. Chu, R. Huang, S. Perissakis, L. Pozzi, J. Yeh, and J. Wawrzynek, presents a stream-oriented compute model, system architecture, and execution patterns that can capture and exploit the parallelism of spatial computations. The conventional register-transfer-level (RTL) hardware models are lacing of the flexibility to scale to exploit newer, larger, and faster hardware platform in reconfigurable systems. This paper describes hardware and software techniques to allow late-bound platform mapping. The title of our fifth paper is ‘‘Rapid Generation of Custom Instructions Using Predefined Dataflow Structures,’’ by S.K. Lam and T. Srikanthan. This paper proposes a methodology for rapid instruction set customization on RISPs (Reconfigurable Instruction Set Processors). The proposed system uses predefined sets of dataflow structures that are based on templates and reusable structures. The generated custom instructions were implemented in FPGA. The performance, in terms of area saving with comparable performance, of the proposed scheme is also compared to conventional implementation approaches. The sixth paper ‘‘EPICURE: A Partitioning and CoDesign Framework For Reconfigurable Computing,’’ by J. Diguet, G. Gogniat, and J. Phillippe presents a design
282
Editorial / Microprocessors and Microsystems 30 (2006) 281–282
methodology to work between an abstraction specification and a heterogeneous reconfigurable architecture. This methodology includes graph extraction from a mixed Safe State Machine/C specification, system and architectural exploration and estimation and hardware/software partitioning. A video supervision application and a part of JPEG 2000 decoder are used to illustrate the proposed design paradigm. The seventh paper, ‘‘Dynamic Clock-Frequencies for FPGAs’’ by J.A. Bower W. Luk O. Mencer, M.J. Flynn, and M. Morf, deals with clocking strategy in FPGA. It argues that fixed clock frequency cannot take advantage of the full potential of an application running on a specific device. The paper proposes a scheme to allow dynamic clock-frequencies in FPGA. A framework that can explore the dynamic behavior of FPGA applications is presented. The proposed system can add circuitry to arbitrary FPGA designs to adjust clock-frequency to a safe limit under current operating conditions. A speed improvement as a result of the proposed scheme is also presented. The last but not least important paper in this issue, ‘‘Application Specific SIMD Synthesis for Reconfigurable Architectures,’’ by M. Cheema, and O. Hammami, aims to bring SIMD extensions to FPGA platform for embedded applications. This paper proposes a SIMD based synthesis flow for application specific instruction set extensions. This research used imaging processing applications as case study that employed AltiVec (a floating point and integer SIMD instruction set designed by Apple, IBM and Motorola) based SIMD unit and PowerPC embedded processor. The compatibility and customization issues in the synthesis flow are addressed. We hope that these research papers will help to give a better insight into the latest trend of works on the critical issues of FPGA-based reconfigurable computing. We take this
opportunity to thank all the authors who have submitted their papers for this special issue and also the reviewers who spend their valuable time in reviewing the papers and providing constructive comments. Without their participation, it would have been difficult for us to meet the deadlines. J. Morris Chang* C. Dan Lo Iowa State University, Department of Electrical and Computer Engineering, Ames, IA 50011, USA E-mail addresses: [email protected], [email protected] Available online 11 May 2006 J. Morris Chang is an associate professor in the Department of Electrical and Computer Engineering, Iowa State University. He received a PhD degree in Computer Engineering from North Caroline State University. Dr. Chang’s research interests include FPGA-based computing, Managed Run-time Environment and Wireless Networks.
Chia-Tien Dan Lo is an assistant professor in the Department of Computer Science, University of Texas at San Antonio. He received a PhD degree in Computer Science from Illinois Institute of Technology. Dr. Lo’s research interests include Reconfigurable Computing, Network Intrusion Detection, and High Performance Embedded Systems.
*
Corresponding author. Tel.: +1 515 294 7618; fax: +1 515 294 8432.