FPGA implementation of two fractional order chaotic systems

Int. J. Electron. Commun. (AEÜ) 78 (2017) 162–172

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International Journal of Electronics and Communications (AEÜ) journal homepage: www.elsevier.com/locate/aeue

Regular paper

FPGA implementation of two fractional order chaotic systems Mohammed F. Tolba a, Amr M. AbdelAty b, Nancy S. Soliman a, Lobna A. Said a,⇑, Ahmed H. Madian a,c, Ahmad Taher Azar a,d, Ahmed G. Radwan a,e a

NISC Research Center, Nile University, Cairo, Egypt Dept. of Engineering Mathematics and Physics, Fayoum University, Egypt c Radiation Engineering Dept., NCRRT, Egyptian Atomic Energy, Authority, Egypt d Faculty of Computers and Information, Benha University, Egypt e Dept. of Engineering Mathematics and Physics, Cairo University, Egypt b

a r t i c l e

i n f o

Article history: Received 14 February 2017 Accepted 24 April 2017

Keywords: Chaotic systems FPGA Fractional order Liu system Multi-scroll V-Shape

a b s t r a c t This paper discusses the FPGA implementation of the fractional-order derivative as well as two fractional-order chaotic systems where one of them has controllable multi-scroll attractors. The complete hardware architecture of the Grünwald-Letnikov (GL) differ-integral is realized with different memory window sizes. As an application of the proposed circuit, a complete fractional-order FPGA implementation of Liu chaotic system is introduced with different fractional-orders. Moreover, a fractional-order controllable heart and V-shape multi-scrolls chaotic systems are verified in the case of symmetric and asymmetric cases. Different interesting attractors are realized under various parametric changes with distinct step sizes for different fractional-orders. To verify the chaotic behavior of many generating attractors, the Maximum Lyapunov Exponent (MLE) is calculated for such systems. The designs have been simulated using Xilinx ISE 14.5 and realized on Xilinx FPGA Virtex 5 XC5VLX50T. The achieved throughputs are: 4.4 Gbit/s for GL, 1.986 Gbit/s for Liu system, and 2.921 Gbit/s for V-Shape multi-scroll attractor. Ó 2017 Elsevier GmbH. All rights reserved.

1. Introduction In 1960s, Lorenz has described the chaos phenomenon by introducing the butterfly attractor which is highly sensitive to initial conditions [1]. A small change in the system parameters leads to a huge difference in its behavior. Inspired by Lorenz attractor, many researchers developed different chaotic attractors and implemented simple circuits for exhibiting these nonlinear dynamical phenomena [2,3]. Chaos emerges in many applications such as signal generators [4], synchronization [5], random number generator [6,7], communication security [8] and others [9,10]. Nowadays, there is a great need to have secure data especially in IOT related applications which inspired the researchers to develop more complicated chaotic systems [8]. Multi-scrolls attractor [11,12] is considered one of these complicated systems. Also, more complexity is achieved by generalizing the conventional integerorder systems into the fractional-order domain [13]. One of the advantages of fractional-order chaotic systems is the added parameters that can be used to extend the encryption key.

⇑ Corresponding author. E-mail address: [email protected] (L.A. Said). http://dx.doi.org/10.1016/j.aeue.2017.04.028 1434-8411/Ó 2017 Elsevier GmbH. All rights reserved.

Before fractional calculus was introduced, system modeling was confined to the integer order domain. This restriction often caused either imprecise models of low order or extremely complex higher order ones. However, these exact systems could now be described with higher accuracy and fewer number of parameters. Also, the non-locality property of most fractional calculus operators allowed modeling of systems exhibiting memory dependency more accurately. Moreover, variable order fractional operators add more degrees of freedom to model systems with changing models in time, space or both. All these interesting features inspired researcher to utilize this new tool in many areas such as: control [14,15], bioengineering [16,17], PV modeling [18], analog filters [19–23], oscillators [24–26], stability analysis [27], Smith chart [28], chaotic systems [29], super-capacitor modeling [30] and viscoelasticity [31]. Fractional-order systems are complicated to translate into hardware due to their memory dependency that requires the use of high-order integer order systems. Field Programmable Gate Array (FPGA) technology is suitable for implementing complex systems. That is why hardware implementation of fractionalorder differentiators and integrators requires careful consideration of some issues such as system quality, hardware cost and speed. Recent approaches in technology have made digital hardware

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M.F. Tolba et al. / Int. J. Electron. Commun. (AEÜ) 78 (2017) 162–172 =0.7

1

=0.9

1 0.5

)

)

0.5 0

-0.5 -1

0

w(j

w(j

implementations less expensive, faster, and easier to design. The FPGA is an efficient platform to implement high quality, high throughput approximations to fractional order systems that are low in cost and require only short design times [32]. There have been several trials in the literature to implement fractional order operators on FPGAs [32–36]. A high order Finite Impulse Response (FIR) filter or a sum of first-order Infinite Impulse Response (IIR) sections were used to implement the fractional order operator in [32–34]. In [35], LabVIEW was used for the implementation of fractional order integrator/differentiator on FPGA. The design based on LabVIEW does not optimize the hardware resources on FPGA. Another FPGA implementation was introduced in [36] based on the short memory principle by Podlubny [37]. The aim of this work is to provide a more compact hardware implementation of the Grünwald-Letnikov’s (GL) fractional order differ-integral operator and then use it as a building block to simulate systems of fractional order chaotic differential equations efficiently on FPGAs. The paper also aims to investigate the effect of the fractional order, memory window length and other parameters on the MLE of the implemented systems. These systems are established on Xilinx FPGA Virtex 5 XC5VLX50T. The proposed design utilizes the parallel structure and the flexibility of FPGAs to produce high-performance and yet low-cost implementations with faster delay times than the ones reported in literature. This paper is organized as follows, Section 2 presents a summary of the GL fractional order operator and its FPGA implementation. Liu system discussion and hardware implementation are introduced in Section 3. Controllable V-shape multi-scroll system discussion and the circuit are illustrated in Section 4, and finally Section 5 concludes the work.

-0.5 0

5

k

10

-1

15

0

5

(a)

k

10

15

(b)

Fig. 1. The value of the binomial coefficient weights at (a) a ¼ 0:7 and (b) a ¼ 0:9.

Dq1 x ¼Pðx; y; z; tÞ;

ð5aÞ

Dq2 y ¼Q ðx; y; z; tÞ;

ð5bÞ

Dq3 z ¼Rðx; y; z; tÞ:

ð5cÞ

To simulate this system based on GL definition, the following set of equations are used [13]: q

xtk ¼Pðxðt k1 Þ; yðt k1 Þ; zðt k1 ÞÞh 1 

m X

ðq1 Þ

wj

xðtkj Þ;

ð6aÞ

j¼1 q

ytk ¼Q ðxðt k1 Þ; yðtk1 Þ; zðtk1 ÞÞh 2 

m X ðq Þ wj 2 yðt kj Þ;

ð6bÞ

j¼1 q

ztk ¼Rðxðt k1 Þ; yðtk1 Þ; zðtk1 ÞÞh 3 

m X ðq Þ wj 3 zðt kj Þ;

ð6cÞ

j¼1

where m ¼ L for the approximated window variation of GL operator and m ¼ k when the entire state memory is used in calculations. This approach is quite similar to Euler method for integer order DEs.

2. Implementation of fractional order derivative

2.2. Grünwald-Letnikov’s FPGA implementation

2.1. Grünwald-Letnikov’s theoretical analysis

GL equation consists of two parts, the first is the binomial coefficients in (2), which is implemented by using look up table (LUT) to store the coefficients. The second part depicted in Fig. 2 is the dot product of the row and column vectors presented by (3). From Fig. 2, each input is multiplied by all the binomial coefficients. The implementation of the proposed GL design is explained through the flowchart depicted in Fig. 3. Two LUTs are required, the first one stores the binomial coefficients w0 to wn , and the second one stores the output of the addition from V in w1 þ d1 to V in wn þ dn . The input signal is multiplied with all the binomial coefficients that are stored in the first LUT then the output is added to the data previously stored in the second LUT. The first results of the addition, ðV in w0 þ d0 Þ is not stored and directly taken as an output. The rest

The GL definition of the fractional order derivative is [37]: GL a

bðtaÞ=hc 1 X ðaÞ wj f ðt  jhÞ; a h!0 h j¼0

Dat f ðtÞ ¼ lim ðaÞ

where wj ðaÞ

w0 ¼ 1;

ð1Þ

are the binomial coefficients, calculated recursively as: ðaÞ

wj

¼

  a þ 1 ðaÞ wj1 ; 1 j

j ¼ 1; 2; 3; . . . :

ð2Þ

In order to implement this operator on the FPGA, an approximate FIR version of length L is given by: GL tL

Dat f ðtÞ ¼

L 1X ðaÞ w f ðt  jhÞ; a h j¼0 j

ð3Þ

where h is the step size, L is the window size. According to the short memory principle, the error in calculating this approximated derivative is bounded by [37]:

DðtÞ ¼ ja GL Dat f ðtÞ  tL GL Dat f ðtÞj 6

MLa ; jCð1  aÞj

ð4Þ

where ða þ L < t < bÞ and jf ðtÞj < M when a < t < b. So, it can be inferred that the error is reduced by increasing the window size. ðaÞ

Fig. 1 shows how the magnitude of the wj

decreases with increas-

ing j. It can be seen that the dependency on past values of the function decreases as the order a approaches the integer value. The general form of a fractional order system of three differential equations is given as:

Fig. 2. Row and column vector dot products output.

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Start

LUT to store the binomial coefficients

Input data Vin

data 0

data

1

Data_out

0 1

n

n-1 n

LUT to store the addition results

Fig. 3. GL derivative design flow chart.

of the addition operations is stored in the second LUT with zero in the last position. Fig. 4 illustrates the hardware implementation of the proposed GL. Multipliers and adders are required to accumulate the output of the GL design. Initially, the data at the second LUT is zero according to the rst signal, then it is updated at each clock. The latency of the design is one cycle. Fixed-point operations have been widely used for hardware implementations to save costs and increase speed. The data stored in the first LUT is 22-bit fixed point, 6b for integer part and 16b for the fractional part. The input is defined as an 8b integer part and

24b for fractional part, the result in 54b fixed point. The data stored in the first LUT block are calculated according to the coefficient in (2). 2.3. GL results The proposed architecture for GL definitions is implemented on Xilinx FPGA Virtex 5 XC5VLX50T. Table 1 illustrates the GL fractional order derivative of f ðtÞ ¼ sinðtÞ for different a; L, with step size h ¼ 0:01. The error in the FPGA implemented GL derivative

X Coefficients

LUT

0

Fig. 4. The hardware architecture of GL derivatives.

Table 1 GL FPGA implemented derivative of sinðtÞ.

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M.F. Tolba et al. / Int. J. Electron. Commun. (AEÜ) 78 (2017) 162–172 Table 2 FPGA implementation results for GL. Logic utilization

Total No. slices

Total No. slice LUT

Total No. slice registers

Max. Freq. ‘‘MHz”

DSP Multi.

Power ‘‘mW”

Throughput Gbit/s

L ¼ 30

806 11%

3079 10%

1630 5%

137:561

30

573

4.4

Used Utilization

is calculated by comparing with the theoretical one computed using MATLAB when a ¼ 0:95 with different L. At L ¼ 40, the maximum error achieved is 0:09 and at L ¼ 20, the maximum error is 0:2. In accordance with the short memory principle, the more window size is increased, the less error is achieved. Table 2 shows the FPGA implementation results for GL derivatives. In [35], a 14 RAMB16s, and 2852 slices were used, on the other hand the proposed architecture uses no RAMs and only 806 slices. All the derivatives waveforms are obtained by applying the input on Xilinx FPGA then saving results as an excel file before plotting it with MATLAB.

For commensurate order systems where q1 ¼ q2 ¼ q3 ¼ q, the eigenvalues of the Jacobian matrix evaluated at E1 (the origin) are k ¼ 1; 5; 2:5 which makes it a saddle point. At the other two equilibrium points, the eigenvalues are k ¼ 4:388; 0:44388  3:346j which makes them a saddle focus of index two as they have two unstable eigenvalues. Saddle points of index two are responsible for generating scroll attractors [38]. This system does not show chaotic behaviour for q < 0:91 [13]. For an incommensurate order Liu system of orders q1 ¼ 1:0; q2 ¼ 0:9 and q3 ¼ 0:8, the characteristic equation of the linearized system given by [13]:

3. Liu system implementation

k27 þ 5k19  2:5k18 þ k17 þ 5k9 þ 2:5k8 þ 50 ¼ 0;

has two unstable roots k ¼ 1:1224  0:177j because jargðkÞj < p=20. The authors in [38] reported that minimum total orders of 2:76 and 2:6 are required for chaotic behavior of the commensurate and incommensurate order systems respectively.

3.1. Liu system theoretical analysis The fractional order Liu system is given by [38,13]: q1

D x ¼  ax  ey2 ;

ð7aÞ

Dq2 y ¼by  kxz; Dq3 z ¼  cz þ mxy;

ð7bÞ ð7cÞ

Thus, according to (6); the numerical solution of (7) is represented as following: k X   q ðq Þ xtk ¼ axðt k1 Þ  ey2 ðt k1 Þ h 1  wj 1 xðt kj Þ;

ð8aÞ

j¼1 q

ytk ¼ðbyðtk1 Þ  kxðtk1 Þzðt k1 ÞÞh 2 

k X ðq Þ wj 2 yðtkj Þ;

ð8bÞ

j¼1 q

ztk ¼ðczðtk1 Þ þ mxðt k1 Þyðt k1 ÞÞh 3 

k X ðq Þ wj 3 zðt kj Þ;

ð8cÞ

j¼1

where q1 ; q2 ; q3 are the fractional orders, a ¼ e ¼ 1; b ¼ 2:5; k ¼ m ¼ 4 and c ¼ 5. The integer order version of the system was first introduced in 2009 by Liu and the fractional order generalization was introduced a year later by Gejji [38,39]. The system has five equilibrium points, two of them are complex and three real ones given as: E1 ¼ ð0; 0; 0Þ, E2 = (0.88388, 0.940150, 0.664786) and E3 ¼ ð0:88388; 0:940150; 0:664786Þ. The Jacobian matrix at equilibrium point is given by [13]:

2

a

6  J ¼ 4 kz 

my

2ey b 

mx

0

3

7 kx 5: c

ð9Þ

Numerical Soluon of

X

ð10Þ

Numerical Soluon of

Y

3.2. Liu system FPGA implementation Chaos generators can be implemented by analog integrators, which require a large capacitor to store the system state. Analog chaotic generators are sensitive to process variations and temperature. On the other hand, the digital design does not demand any capacitors; only registers are used to store the state with a small area and better performance [40]. The proposed system is implemented digitally by realizing its numerical solution as in (8). Fig. 5 presents the general design for any third-order differential-based digital chaotic generator. Three registers are used to store the state variables x; y, and z. A combinational circuit is used to implement the numerical solution for x; y, and z. The hardware implementations of the Liu fractional order system is illustrated in Fig. 6. Three registers are used for x; y and z with 40-bit fixed point, 16b for integer part and 24b for the fractional part. Proposed design requires eleven multipliers, seven adders, squarer, and three GL block to compute the numerical solution for x; y and z. The squarer is used to compute y2 . The quantities q q q h 1 ; h 2 and h 3 are constants in the proposed design, which are calculated with step size h, and the fractional order q1 , q2 and q3 . GL1; GL2, and GL3 blocks are used based on GL in Section 2.2 which are used to evaluate the dot products operation in (8). The output of each multiplier and GL blocks are truncated to get 40b for x; y, and z. The carry in of each adder is one to perform the two’s complement along with the inverter for the subtraction operations.

Numerical Soluon of

Z

Fig. 5. The general architecture of the digital implementation for any third-order differential-based digital chaotic generator.

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X X

X

X

GL 1

X

X

X

X

X

X

X

GL 2

GL 3

Fig. 6. Hardware architecture of Liu fractional order chaotic system.

Table 3 FPGA simulation results for Liu fractional order chaotic system. Used parameter a ¼ e ¼ 1; b ¼ 2:5; k ¼ m ¼ 4, and c ¼ 5.

The performance and area can be improved by using a shift wire in case of the parameters a; b; c; e; k, and m, instead of multiplication. To use the shifted wire the value of a; b; c; e; k, and m must be a power of two. This improvement saves six multipliers where five multipliers are used instead of eleven multipliers. The value of a ¼ e ¼ 1, and b ¼ 2:5 which represented as ð2 þ 21 Þ; k ¼ m ¼ 4, and c ¼ 5 which defined as ð20 þ 22 Þ. 3.3. Results and discussion The proposed design for fractional order Liu system was written in Verilog HDL with the simulation of Xilinx ISE 14:5 and implemented on Xilinx FPGA Virtex 5 XC5VLX50T by using Chip-Scope. The proposed design was synthesized using Xilinx ISE 14:5. Table 3 shows the FPGA simulation results for Liu fractional order chaotic system, with parameters a ¼ e ¼ 1; b ¼ 2:5; k ¼ m ¼ 4, and c ¼ 5. Summary of FPGA implementations results is presented in Table 4. Throughputs of 1:554 Gbit=s and 1:986 Gbit=s are achieved for the design without and with shifted wire respectively.

4. Controllable V-shape multi-scroll system and circuit 4.1. V-shape multi-scroll theoretical analysis The essence of multi-scroll chaotic systems is a nonlinear function such as Piecewise-Linear (PWL) function. One of the relevant systems is the V-shape multi-scroll described in [40]. It was derived essentially from the Lorenz chaotic system and it can be described as follows:

x_ ¼y  x;

ð11aÞ

y_ ¼signðxÞ½1  mz þ GðzÞ;

ð11bÞ

z_ ¼jxj  rz;

ð11cÞ

8 0 > > > > < d1 GðzÞ ¼ . > .. > > > : dN1

z < s0 s0 < z < s1

;

ð11dÞ

z < sN1

Table 4 FPGA implementation results for Liu fractional order chaotic system. Logic utilization Liu fractional order

Without shift wired With shift wired

Total No. slices

Total No. slice registers

Max. Freq. ‘‘MHz”

DSP Multi.

Power ‘‘mW”

Throughput Gbit/s

5688 4847

4962 4938

38:874 49:658

99 93

588 589

1:554 1:986

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M.F. Tolba et al. / Int. J. Electron. Commun. (AEÜ) 78 (2017) 162–172

where m; r are constants and GðzÞ is the system staircase nonlinear function. It allows to control the number of scrolls through the parameter N and control the size by the parameter s and d. Vshape can be symmetric or asymmetric according to the staircase function. It is done by the generalized HðzÞ function to be symmetric or asymmetric shape as follows:

 Hðx; zÞ ¼

GðzÞ

x60

þ

x>0

GðzÞ

ð12Þ

q1 0 Dt x q2 0 Dt y q3 0 Dt z

¼y  x;

ð13aÞ

¼signðxÞ½1  mz þ GðzÞ

ð13bÞ

¼jxj  rz:

ð13cÞ

Thus, according to (6); the numerical solution of (13) is represented as following: q

xtk ¼ðxðt k1 Þ  yðt k1 ÞÞh 1 

k X ðq Þ wj 1 xðt kj Þ;

ð14aÞ

j¼1

If GðzÞþ and GðzÞ are similar it will be symmetric, else it will be asymmetric. The fractional order provides extra degree of freedom, hence, increasing the system complexity. That’s why, generalizing the Vshape to fractional order has a memorable impact on enhancing the system accuracy. Numerical solution of the fractional differential equations of V-shape based on GL definition can be represented as following:

Table 5 Maximum Lyapunov Exponent for different multiscrolls. Number of scrolls

Integer order MLE

Fractional order MLE

1 3 5 7

0:0241 0:125 0:1406 0:1393

0:4060 0:5007 0:7184 0:6773

q

ytk ¼ðsignðxðtk1 ÞÞ½1  mzðt k1 Þ þ Gðzðtk1 ÞÞÞh 2 

Table 5 shows a comparison between the integer and fractional order systems with respective to MLE. It shows that the fractional order has larger MLE value than the integer order. Thus, it is a robust indicator on increasing the complexity. 4.2. V-shape multi-scroll system and circuit FPGA implementation The hardware architecture of proposed V-Shape multi-scroll attractor is shown in Fig. 7. A 40b fixed point is used for x; y, and z; 16b for integer part and 24b for the fractional part. The numerical

2’s Comp

Sign

X

X GL 3

Fig. 7. Hardware implementation of the proposed multi-scroll generator.

Comparator

Comparator

)

)

(a)

ð14cÞ

j¼1

GL 2

Comparator

yðt kj Þ; ð14bÞ

k X q ðq Þ wj 3 zðt kj Þ; ztk ¼ðjxðt k1 Þj  rzðt k1 ÞÞh 3 

Mag

GL 1

ðq2 Þ

wj

j¼1

G(Z)

X

k X

(b)

Fig. 8. Block diagram of two implementations of the non-linear function, (a) GðzÞ, (b) HðzÞ.

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M.F. Tolba et al. / Int. J. Electron. Commun. (AEÜ) 78 (2017) 162–172

solutions described by (14) for x; y, and z are computed in the combinational circuits based on the following blocks: Pk q1 GL3 blocks compute j¼1 wj xðt kj Þ; P q2 q3 k j¼1 wj yðt kj Þ, and j¼1 wj zðt kj Þ in (14) respectively, which it

 GL1, Pk    

GL2,

and

is based on GL in Section 2.2. The sign block can be implemented by select the MSB of x. 2’s comp block is used to obtain the negative number. Mag block compute the absolute value of x. The inverter and the carry in compute the 2’s complement to apply the subtraction operations.

 The expressionð1  mzðtk1 Þ þ Gðzðt k1 ÞÞ is implemented as the output of GðzÞ is added to the inverted shifted z then added to ‘‘1”.  The output of the sign block derives the selector of the multiplexer to evaluate ðsignðxðt k ÞÞ½1  mzðt k1 Þ þ Gðzðt k1 ÞÞÞ. q  The output of the multiplexer is multiplied with h 2 then added with the output of GL2 to get the solution for y.

GðzÞ is the nonlinear function which produces the multi-scroll. Fig. 8(a) shows the design of symmetric V-Shape attractor GðzÞ . It has a comparator used to compare between z and parameters fs0 ; . . . sn g. An encoder is used to encode the output of the comparator to derive selectors of the multiplexer. The multiplexer select between fd0 ; d1 ; . . . ; dn g. Fig. 8(b) presents asymmetric V-Shape attractor by realizing the non-linear function Hðx; zÞ. It is implemented by adding another comparator to compare x with zero, then the outputs of the comparator are encoded to derive the selectors of the multiplexer to get HðzÞ. The combinational circuits of x is worked as follows: q

 The expression ðyðt k1 Þ  xðt k1 ÞÞh 1 is implemented by adding q the inverted x with y then multiply the output with h 1 .  The solution of x is computed by adding the output of the last expression and GL1 block. The combinational circuits of y is worked as follows:

Fig. 9. x–z plane of the heart shape attractor for parameters q1 ¼ q3 ¼ 1:25 ,and q2 ¼ 1. s0 ¼ 0:865; s1 ¼ 2:53; m ¼ 2; d1 ¼ 2 and d2 ¼ 8.

Table 6 FPGA implementation results for V-shape multi-scroll system.

Table 7 FPGA implementation results for V-shape multi-scroll system. Logic utilization

Total No. slices

Total No. slice registers

Max. Freq. ‘‘MHz”

DSP Multi.

Power ‘‘mW”

Throughput Gbit/s

Without shift wired

with GðzÞ with HðzÞ

2659 2712

3360 3360

46.241 40.104

59 59

584 585

1.849 1.604

With shift wired

With GðzÞ With HðzÞ

2522 2599

3360 3360

73.049 60.250

56 56

582 584

2.921 2.41

M.F. Tolba et al. / Int. J. Electron. Commun. (AEÜ) 78 (2017) 162–172

The combinational circuits of z is worked as follows:  The numerical solution for z is implemented by adder which computes the expression jxðtk1 Þj  rzðt k1 Þ. q  The output of the adder is multiplied with h 3 then added to the output of the inverted GL3 block to compute the solutions for z. The output of the proposed design requires only one clock cycle. An improvement could be implemented by replacing the multiplier

Fig. 10. 3D view of chaotic response for q1 ¼ q3 ¼ 0:9 ,and s0 ¼ 0:865; s1 ¼ 2:53; m ¼ 2; d1 ¼ 2 and d2 ¼ 8; r ¼ 0:2 and L ¼ 30.

q2 ¼ 1.

169

at each part of the combinational circuits by shifted wire. The q q q parameters h 1 ; h 2 and h 3 are inputs, where h ¼ 0:25 and q q1 ¼ q3 ¼ 1:25 and q2 ¼ 1. For h ¼ 0:0625 the input h is presented as 2ð41:25Þ ¼ 25 and for q2 ¼ 22 . This modification improves the performance, power consumption, and area. 4.3. Results and discussion Verilog HDL, Xilinx ISE 14:5, and Xilinx FPGA Virtex 5 XC5VLX50T are used for the design and implementation of proposed multi-scroll V-shape attractor. Table 6 illustrates different FPGA simulation results for multi-scroll V-Shape attractor in x-z and y-z plan, with parameters q1 ¼ q3 ¼ 1:25 ,and q2 ¼ 1; s0 = 1.56, s1 = 2.71, s2 = 3.86, s3 = 5.01, s4 = 6.16, m = 1, d1 ¼ 1:15; d2 ¼ 2:3; d3 ¼ 3:45; d4 ¼ 4:6; d5 ¼ 5:75. Table 7 presents the FPGA implementation results for the proposed V-Shape multi-scroll attractor for GðzÞ and HðzÞ. Symmetrical and asymmetrical V-shape are observed as in integer order Domain. Fig. 9 presents an x-z plane of the heart-Shape attractor for parameters q1 ¼ q3 ¼ 1:25 and q2 ¼ 1. s0 ¼ 0:865; s1 ¼ 2:53; m ¼ 2; d1 ¼ 2 and d2 ¼ 8. Fig. 10 presents a 3D of the chaotic response for the same parameters of heart shape with different fractional orders and different values of the r parameter. It is observed that small change in parameter can lead to have a different attractor behavior. 4.3.1. Comparisons and applications Tables 8–12, show different chaotic responses by changing the parameters L; r and h under different fractional-order cases. Table 8 shows various attractors for r ¼ 0:5; q1 ¼ 1:25; q2 ¼ 1; q3 ¼ 1:25

Table 8 FPGA implementation results for V-shape multi-scroll system, where r ¼ 0:5, q1 ¼ 1:25, q2 ¼ 1, q3 ¼ 1:25.

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M.F. Tolba et al. / Int. J. Electron. Commun. (AEÜ) 78 (2017) 162–172 Table 9 FPGA implementation results for V-shape multi-scroll system, where r ¼ 0:4, q1 ¼ 0:9, q2 ¼ 1, q3 ¼ 1:25.

Table 10 FPGA implementation results for V-shape multi-scroll system, where q1 ¼ 0:9, q2 ¼ 1, q3 ¼ 0:9, h ¼ 24 and L ¼ 30.

Table 11 FPGA implementation results for V-shape multi-scroll system, where q1 ¼ 0:9, q2 ¼ 1, q3 ¼ 1:25, h ¼ 24 and L ¼ 30.

where the dynamics of multi-scrolls attractor decrease as h decreases under fixed L. In addition, when L is small enough, as h decrease the chaotic behavior will be disappeared. For fixed step size h, the chaotic behavior increase as L increases which is logic due to the span of more signal history of the fractional-order operator. For q1 ¼ 0:9; q2 ¼ 1; q3 ¼ 1:25; r ¼ 0:6 and different L; h different chaotic responses are obtained as shown in Table 9 specially with lower values of L and h. For example, when ðL; hÞ ¼ ð30; 25 Þ

the (6 left, 6 right) V-shape multi-scrolls attractor has been reduced into ð1; 1Þ attractor. The effect the parameter r with fixed L ¼ 30 and h ¼ 24 is presented in Tables 10–12, for different fractional-order cases ðq1 ; q2 ; q3 Þ ¼ ð0:9; 1:0; 0:9Þ; ð0:9; 1:0; 1:25Þ and ð1:25; 1:0; 1:25Þ respectively. It is clear from these tables that as the orders increases, the range of parameter r for chaotic range increases. Moreover, unexpected strange attractors have been obtained in these tables which illustrate the power of fractional-

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M.F. Tolba et al. / Int. J. Electron. Commun. (AEÜ) 78 (2017) 162–172 Table 12 FPGA implementation results for V-shape multi-scroll system, where q1 ¼ 1:25, q2 ¼ 1, q3 ¼ 1:25, h ¼ 24 and L ¼ 30.

Table 13 MLE for different h and L. 1

2

3

q1 ¼ 1:25 q2 ¼ 1:0 q3 ¼ 1:25

L ¼ 60 r ¼ 0:5

h

q1 ¼ 0:9 q2 ¼ 1:0 q3 ¼ 1:25

L ¼ 60 r ¼ 0:6

h

q1 ¼ 0:9 q2 ¼ 1:0 q3 ¼ 1:25

L ¼ 30 r ¼ 0:4

h

26 0:0887

25 0:1849

24 0:3386

26 0.0837

25 0.2433

24 0.2555

h ¼ 23

MLE L MLE

25 0:0362 30 0.3796

24 0:043 60 0.3809

23 0:3796 120 0.4093

r ¼ 0:4

MLE

MLE

4

q1 ¼ 0:9 q2 ¼ 1:0 q3 ¼ 0:9

h ¼ 24 L ¼ 30

r MLE

0 0:0788

0:2 0:0227

0:4 0:0548

5

q1 ¼ 0:9 q2 ¼ 1:0 q3 ¼ 1:25

h ¼ 24 L ¼ 30

r MLE

0.1 1.1776

0.3 0.1294

0.6 0.1395

6

q1 ¼ 1:25 q2 ¼ 1:0 q3 ¼ 1:25

h ¼ 24 L ¼ 30

r MLE

0:2 0:2332

0:6 0:1849

0:8 0:2186

order parameters as well as the conventional systems parameters on the output response. Table 13 investigates the MLE values for various chaotic cases shown in the previous Tables 9–12 which confirm the chaotic behavior. For fixed fractional orders, it is clear when L and r are fixed, the MLE value increase as h increases. Moreover; in cases 4 and 5; under fixed L and h, the MLE increase as r decreases. 5. Conclusion A new FPGA implementation of fractional order derivative based Grünwald-Letnikov definition was designed. The design was tested for various input signals to ensure its validity. The methodology resulted in an accurate and high-speed fixed-point implementation of the approximated differ-integral. As an application of this new GL block, two chaotic fractional order systems were realized on FPGA. The first one is the fractional order Liu system in its commensurate and incommensurate order forms. Also, symmetric, and asymmetric V- and heart-Shapes attractor were presented. The MLE results showed that the extra degrees of freedom introduced by the fractional operator and its approximation order can be used together to achieve stronger chaotic behavior. The proposed system realization showed an overall good performance and one cycle latency. This realization is suitable for fractional order based signal processing and communication systems due to its high speed. References [1] Lorenz EN. Deterministic nonperiodic flow. J Atmos Sci 1963;20(2):130–41. [2] Radwan AG, Soliman AM, El-Sedeek AL. An inductorless CMOS realization of chua’s circuit. Chaos Solitons Fractals 2003;18(1):149–58. [3] Radwan A, Soliman A, El-Sedeek A. MOS realization of the modified lorenz chaotic system. Chaos Solitons Fractals 2004;21(3):553–61.

[4] Alligood KT, Sauer TD, Yorke JA. Chaos. Berlin Heidelberg: Springer; 1997. [5] Vaidyanathan S. Generalized projective synchronization of vaidyanathan chaotic system via active and adaptive control. In: Advances and Applications in Nonlinear Control Systems. Springer Nature; 2016. p. 97–116. [6] Howard RM. Principles of Random Signal Analysis and Low Noise Design. Wiley-Blackwell; 2002. [7] Barakat ML. Generalized hardware post-processing technique for chaos-based pseudorandom number generators. ETRI J 2013;35(3):448–58. [8] Alvarez G, Li S. Some basic cryptographic requirements for chaos-based cryptosystems. Int J Bifurcation Chaos 2006;16(08):2129–51. [9] Xu J, Ji Y, Tong Cui B. Synchronization and anti-synchronization of time-delay chaotic system and its application to secure communication. J Comput Appl 2010;30(9):2413–6. [10] Radwan AG, AbdElHaleem SH, Abd-El-Hafiz SK. Symmetric encryption algorithms using chaotic and non-chaotic generators: a review. J Adv Res 2016;7(2):193–208. [11] Barajas-Ramírez J. Chaotification of linear systems: multiscroll attractors. IFAC Proc Vol 2012;45(12):105–10. [12] Radwan A, Soliman AM, Elwakil AS. 1-D digitally-controlled multiscroll chaos generator. Int J Bifurcation Chaos 2007;17(01):227–42. [13] Petráš I. Fractional-Order Nonlinear Systems. Nonlinear Physical Science. Berlin Heidelberg: Springer; 2011, ISBN 978-3-642-18100-9. [14] Yakoub Z, Amairi M, Chetoui M, Saidi B, Aoun M. Model-free adaptive fractional order control of stable linear time-varying systems. ISA Trans 2017:1–15. [15] Dimeas I, Petras I, Psychalinos C. New analog implementation technique for fractional-order controller: a DC motor control. AEU Int J Electron Commun 2017. [16] Freeborn TJ. A survey of fractional-order circuit models for biology and biomedicine. Emerg Sel Top Circuits Syst IEEE J 2013;3(3):416–24. [17] Vastarouchas C, Tsirimokou G, Freeborn TJ, Psychalinos C. Emulation of an electrical-analogue of a fractional-order human respiratory mechanical impedance model using OTA topologies. AEU Int J Electron Commun 2017. [18] AbdelAty AM, Radwan AG, Elwakil A, Psychalinos C. A fractional-order dynamic PV model. In: 39th International Conference on Telecommunications and Signal Processing (TSP). Institute of Electrical and Electronics Engineers (IEEE); 2016. [19] Ali AS, Radwan AG, Soliman AM. Fractional order butterworth filter: active and passive realizations. IEEE J Emerg Sel Top Circuits Syst 2013;3(3):346–54. [20] Radwan AG, Elwakil AS, Soliman AM. On the generalization of second-order filters to the fractional-order domain. J Circuits Syst Comput 2009;18 (02):361–86. _ [21] Kawala-Janik A, Bauer W, Zołubak M, Baranowski J. Early-stage pilot study on using fractional-order calculus-based filtering for the purpose of analysis of

172

[22]

[23]

[24]

[25]

[26] [27] [28]

[29]

[30]

M.F. Tolba et al. / Int. J. Electron. Commun. (AEÜ) 78 (2017) 162–172 electroencephalography signals. Stud Logic Gramm Rhetor 2016;47 (1):103–11. Sotner R, Jerabek J, Herencsar N, Petrzela J, Dostal T, Vrba K. First-order adjustable transfer sections for synthesis suitable for special purposes in constant phase block approximation. AEU Int J Electron Commun 2015;69 (9):1334–45. Baderia K, Kumar A, Singh GK. Design of quadrature mirror filter bank using polyphase components based on optimal fractional derivative constraints. AEU Int J Electron Commun 2015;69(9):1254–64. Said LA, Radwan AG, Madian AH, Soliman AM. Fractional order oscillators based on operational transresistance amplifiers. AEU Int J Electron Commun 2015;1:1–16. Said LA, Radwan AG, Madian AH, Soliman AM. Three fractional-ordercapacitors-based oscillators with controllable phase and frequency. J Circuits Syst Comput 2017;5:1750160. Elwakil A, Allagui A, Maundy B, Psychalinos C. A low frequency oscillator using a super-capacitor. AEU Int J Electron Commun 2016;70(7):970–3. Radwan AG, Soliman A, Elwakil AS, Sedeek A. On the stability of linear systems with fractional-order elements. Chaos Solitons Fractals 2009;40(5):2317–28. Radwan AG, Shamim A, Salama KN. Theory of fractional order elements based impedance matching networks. IEEE Microwave Wirel Compon Lett 2011;21 (3):120–2. Gu W, Yu Y, Hu W. Artificial bee colony algorithmbased parameter estimation of fractional-order chaotic system with time delay. IEEE/CAA J Autom Sin 2017;4(1):107–13. Elwakil AS, Allagui A, Freeborn T, Maundy B. Further experimental evidence of the fractional-order energy equation in supercapacitors. AEU Int J Electron Commun 2017.

[31] Colinas-Armijo N, Cutrona S, Di Paola M, Pirrotta A. Fractional viscoelastic beam under torsion. Commun Nonlinear Sci Numer Simul 2017;48:278–87. [32] Jiang CX, Carletta JE, Hartley TT. Implementation of fractional-order operators on field programmable gate arrays. In: Adv. Fract. Calc. Dordrecht. Netherlands: Springer; 2007. p. 333–46. [33] Jiang C, Adams J, Carletta J, Hartley T. Hardware implementation of fractionalorder systems as infinite impulse response filters. IFAC Proc 2006;39 (11):408–13. [34] Jiang CX, Carletta JE, Hartley TT, Veillette RJ. A systematic approach for implementing fractional-order operators and systems. IEEE J Emerg Sel Top Circuits Syst 2013;3(3):301–12. [35] Rana K, Kumar V, Mittra N, Pramanik N. Implementation of fractional order integrator/differentiator on field programmable gate array. Alexandria Eng J 2016;55(2):1765–73. [36] Caponetto R, Dongola G, Gallo A. Fractional integrative operator and its FPGA implementation. In: Volume 4: 7th International Conference on Multibody Systems, Nonlinear Dynamics, and Control, Parts A, B and C. ASME International; 2009. [37] Podlubny I. Fractional Differential Equations: An Introduction to Fractional Derivatives, Fractional Differential Equations, to Methods of their Solution and some of their Applications. Academic Press; 1999. [38] Daftardar-Gejji V, Bhalekar S. Chaos in fractional ordered Liu system. Comput Math with Appl 2010;59(3):1117–27. [39] Liu C, Liu L, Liu T. A novel three dimensional autonomous chaos system. Chaos Solitons Fractals 2009;39(4):1950–8. [40] Zidan MA, Radwan AG, Salama KN. Controllable v-shape multiscroll butterfly attractor: system and circuit implementation. Int J Bifurcation Chaos 2012;22 (06):1250143.