- Email: [email protected]
Front-end electronics and data acquisition system for a multi-wire 3D gas tracker
Author’s Accepted Manuscript Front-end electronics and data acquisition system for a multi-wire 3D gas tracker K. Łojek, D. Rozpȩdzik, K. Bodek, M. Perkowski, N. Severijns www.elsevier.com
PII: DOI: Reference:
S0168-9002(15)01022-0 http://dx.doi.org/10.1016/j.nima.2015.08.058 NIMA57991
To appear in: Nuclear Inst. and Methods in Physics Research, A Received date: 15 April 2015 Revised date: 10 August 2015 Accepted date: 27 August 2015 Cite this article as: K. Łojek, D. Rozpȩdzik, K. Bodek, M. Perkowski and N. Severijns, Front-end electronics and data acquisition system for a multi-wire 3D gas tracker, Nuclear Inst. and Methods in Physics Research, A, http://dx.doi.org/10.1016/j.nima.2015.08.058 This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting galley proof before it is published in its final citable form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.
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Front-end electronics and data acquisition system for a multi-wire 3D gas tracker
3
K. Lojeka , D. Rozp¸edzika,∗, K. Bodeka,∗, M. Perkowskia,b,∗, N. Severijnsb,∗
1
4 5
6
a Institute b Instituut
of Physics, Jagiellonian University, 30348 Cracow, Poland voor Kern-en Stralingsfysica, University of Leuven, 3001 Leuven, Belgium
Abstract This paper presents the design and implementation of the front-end electronics and the data acquisition (DAQ) system for readout of multi-wire drift chambers (MWDC). Apart of the conventional drift time measurement the system delivers the hit position along the wire utilizing the charge division technique. The system consists of preamplifiers, and analog and digital boards sending data to a back-end computer via an Ethernet interface. The data logging software formats the received data and enables an easy access to the data analysis software. The use of specially designed preamplifiers and peak detectors allows the chargedivision readout of the low resistance signal wire. The implication of the chargedivision circuitry onto the drift time measurement was studied and the overall performance of the electronic system was evaluated in dedicated off-line tests.
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Keywords: data acquisition system, hardware, data logging software
8
PACS: 29.85.Ca; 29.40.Gx; 23.40.Bw
9
1. Introduction
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Precision measurements in neutron and nuclear decay offer a sensitive win-
11
dow to search for new physics beyond the standard electroweak model and allow
12
also the determination of the fundamental weak vector coupling. Recent anal-
13
yses based on the effective field theory performed in e.g. [1, 2] show that in
14
processes involving the lightest quarks the neutron and nuclear decay will com-
15
pete with experiments at highest energy accelerators. For instance, data taken ∗ Corresponding
author Email address: [email protected] (D. Rozp¸edzik) Preprint submitted to Nuclear Instruments and Methods in Physics Research ASeptember 2, 2015
16
at the LHC is currently probing these interactions at the 10−2 level (relative
17
to the standard weak interactions), with the potential to reach the ' 10−3
18
level. In some of the β decay correlation measurements there are prospects to
19
reach experimental sensitivities between 10−3 and 10−4 making these observ-
20
ables interesting probes for searches of new physics originating at TeV scale.
21
The most direct access to the exotic tensor interaction in β decay is to measure
22
the Fierz term (coefficient b) or the beta-neutrino correlation coefficient a in a
23
pure Gamow-Teller transition [3]. The b coefficient shows up as a tiny energy
24
dependent (1/E) departure of the β spectrum from its V-A (standard model)
25
shape. The smallness of the potential b contribution requires that other cor-
26
rections to the spectrum shape of the same order are included in the analysis.
27
Indeed, according to [4, 5] the recoil terms also affect the spectrum shape with
28
their main contribution being proportional to E. In order to disentangle these
29
effects the detector efficiency for β particle as a function of energy must be
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known with the precision better than 10−3 [6]. The dominating contribution
31
in the systematic uncertainty comes from back-scattering and out-scattering of
32
electrons from the detector. Monte Carlo simulation of this effect is helpful,
33
however, it introduces its own uncertainty as the input parameters are known
34
with limited accuracy. Monte Carlo simulation would reflect the real situation
35
better after it is adjusted to real experimental data of a particular measurement
36
setup.
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The described in this article electronics was designed for a spectrometer
38
capable of direct registration of the back-scattering events, thus providing ref-
39
erence data for the Monte Carlo calculation of the detector efficiency. The
40
spectrometer itself is still in an R&D phase undergoing detailed tests and tun-
41
ing. It will be a subject of a separate paper together with the performance
42
benchmark [7]. In this paper, its concept will be described only in a minimum
43
extent at the beginning of Section 2 to explain the requirements imposed onto
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the front-end electronics and DAQ. The rest of Section 2 is devoted to the elec-
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tronic system architecture. The test results were obtained with a help of a signal
46
generator and are presented in Section 3. Therein the resulting time spectrum 2
47
and the charge asymmetry distribution representing the typical performance
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are shown. The asymmetry spectra were obtained using a dedicated tester to
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simulate the hit position on the wire with adjustable resistance division (poten-
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tiometer). Conducting the electronic benchmark tests without a detector was
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chosen by purpose. The detector itself is still not fully understood. Therefore it
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was important to assess the purely electronic contribution to the performance
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parameters of the spectrometer. The paper ends with a short summary and
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outlook for the future experiment.
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2. System architecture
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In order to facilitate the identification of the electrons impinging onto and
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scattered from the energy detector (e.g. Si detector, scintillator) a low-Z and
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low-mass tracker must be applied. One of the attractive options is a low pressure
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multi-wire drift chamber with minimum number of necessary wires in order to
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maximize the detector transparency. This condition can be fulfilled by a hexag-
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onal wire geometry and the charge division technique allowing for a 3D track
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reconstruction without major distortion of the electron energy measurement.
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The hexagonal wire geometry is not the only one considered in the project. The
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rectangular (planar) wire configuration is the next suitable alternative. The
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multi-wire drift chamber is based on the small prototype described in Ref. [8]
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and will be operated with He/Isobutan gas mixture (ranging from 70%/30% to
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90%/10%) at lowered pressure (down to 300 mbar). It consists of 10 sense wire
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planes (8 wires for each plane) separated with 24 field wire planes forming the
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double F-F-S-F-F-S-F-F-S-F-F-S-F-F-S-F-F structure (F- denotes a field wire
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plane, S- denotes a signal wire plane). The distance between neighboring signal
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planes is 15 mm, with wires within a plane being separated by 17.32 mm. This
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wire plane structure leads to the hexagonal cell geometry as shown in Fig. 1.
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Each cell consists of a very thin anode wire (NiCr alloy, 25 µm diameter) with
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resistance of about 20 ohms/cm surrounded by 6 cathode field wires forming a
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hexagonal cuboid. All wires are soldered to pads of the printed circuit board
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F F S F F S F F S F F S F F S F F
Fig. 1: (color on-line) Fragment of the hexagonal wire structure. The blue (solid) circles denote the field wires and the red circles (crossed) correspond to signal wires. The field and signal wire planes are indicated with F and S, respectively. The shaded areas ilustrate the responding cells after an electron passed along the black solid line.
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(PCB) frames. The chamber is equipped with a two-dimensional positioning
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system for a beta source installed in the central region of the detector, between
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both parts of the MWDC structure. In the initial configuration, the electrons
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detected in two plastic scintillators installed at both sides of the MWDC pro-
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vide the time reference signal for the drift time measurement. The PMT signals
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are also used as a trigger for the MWDC and electron energy detector read-
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out. Acquiring the drift time and the pulse height asymmetry at both ends of
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the responding signal wire one can establish the electron path across the cham-
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ber cell. The system provides charge-division position sensing in the direction
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parallel to the wires as well as precise drift time measurement. The expected
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position resolution across wires is limited by angular straggling of primary elec-
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trons travelling in the gas and accounts to about 450 µm as shown in Ref. [8].
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In this situation, the precision of the drift time measurement of about 200 ps is
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more than needed as it corresponds to about 50 µm for the operating conditions
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in view. The MWDC will be operated in homogenous magnetic field oriented
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parallel to wires providing a rough electron transverse momentum filter. The
4
LAN Top5 Preamplifiers
Analog Card
MWDC
Digital Card
Analog Card
Bottom5 Preamplifiers
Slow5Control (RS485)
Fig. 2: Schematic of the data acquisition architecture.
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position information along the wires will be used for the identification of the
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sequence of the cells passed by the electrons and for distinguishing between the
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electrons impinging onto and scattered from the energy detector. This is why
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the modest position resolution of a few mm is sufficient for that direction.
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Crucial in the design is the analog part of the system. In principle, com-
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mercial digitizers (TDC, ADC) could be applied at the end of the acquisition
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chain. However, it has been decided to equip the data channels with custom
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digital boards with adjusted specifications such that the whole system is handy,
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cost effective and scalable. The applied on board processing (FPGA) allows for
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acquiring up to 15 000 triggered events per second which gives a comfortable
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factor of 10 reserve as compared to the application in view.
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The described modular electronic system consists of three main parts: (i)
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preamplifiers, (ii) analog cards containing the peak detector and constant frac-
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tion discriminator (CFD), and (iii) the digital boards containing analog to digital
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converters, ADC and TDC. The data logging software on the PC constitutes
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the data receiver. The signal from each signal plane is processed by means
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of one electronics module, which consists of two analog cards and one digital
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board providing 16 ADC and 8 TDC channels. A corresponding block diagram
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is shown in Fig. 2. The signals from both ends of a signal wire are fed to inputs
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of preamplifiers located directly on the detector frames (see Fig. 3) in order to
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Fig. 3: (color on-line) Small piggyback preamplifier PCB cards plugged into the wire frames.
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minimize the input noise and protect the signal from EM interferences. The
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signals from the preamplifiers are received by the analog cards which drive the
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ADC inputs and produce the TDC STOP signals. The digital data is transmit-
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ted via a LAN port to the back-end computer where the process of receiving,
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sorting and formatting to a complete physical event is accomplished by the
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data logging software. The card configuration settings and control is done via a
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RS485 port. Detailed description of each part of the system is presented in the
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following sections.
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2.1. Preamplifiers
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Signal readout from both ends of the relatively low resistance wire requires
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application of dedicated preamplifiers. Low resistance wires force the use of fast
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preamplifiers with low input impedance since the change of signal amplitudes
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and thus position resolution depends on the input impedance. The lower the
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input impedance, the higher the voltage difference that is registered at the wire
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ends. The preamplifiers work in current-mode with the input impedance below
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5 ohms and the input stage bandwidth exceeding 300 MHz. The preamplifier
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circuit is shown in Fig. 4. The first stage of the preamplifier is a current-voltage
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converter with two fast bipolar transistors. The voltage pulse is fed to the
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high-pass filter which cuts off the DC bias and the slow varying components of
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the signal. The first filter is followed by a low-pass filter integrating the pulse
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C1
C2
10nF R1
100nF
B
2k2
+5V
R3 10
C
IN
C7 100nF
C11 100nF
R9 10
Q2 BFR93
C
D1
R2 2k2 Q1 BFR93
E
1N4148 C3 10nF
C5 10nF R4 2k2
C4
R7 330
U2
R8 50
R6 1k
3 2
C9 100p
C10
R5 1k
10
R11 2k2
E
B
R13
100nF
7
4
8 6 5
8 R14 249
U1 AD8099
R12 10
C12 1p
R16 249
C13 100nF
100nF
C6
C8
10nF
100nF
R17 51
AD8139 5
3
2 1
OUT R15 499
4 6
R18 10
R19 499
R20 51 OUT −5V
R10 10
Fig. 4: Electronic circuit of the preamplifier. The system uses 160 dedicated preamplifiers to the drift chamber signals with charge division.
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with 100 ns time constant. The signal is then amplified and transmitted to
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the differential amplifier used to drive the transmission line. Differential sig-
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nal transmission increases the external noise immunity when unshielded twisted
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pair ribbon cables are used to connect the preamplifier outputs to the inputs of
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the analog module. An example of input and output signals from a preamplifier
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is shown in Fig. 5. The input current signal was reproduced with the help of
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Qucs package [9]. Using bipolar transistors increases the preamplifier immunity
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to possible discharges in the gas chamber. Adding more robust input protection
140
(e.g. a series resistor and protection diodes) was abandoned as it would increase
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the input noise and impedance thus worsening the charge division resolution.
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However, accidental discharges cannot be avoided completely and the need for
143
replacement of damaged preamplifiers was taken into account in the design. The
144
individual preamplifiers are arranged as small piggyback PCB cards mounted
145
directly on the wire frames (Fig. 3). They can be replaced easily without un-
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plugging cables or any other major intervention in the setup. Additionally, such
147
a solution minimizes the length of the unshielded connection between the wire
148
end and the preamplifier input.
149
2.2. Analog cards
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The block diagram of the analog circuit is presented in Fig. 6.
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Differential signals from the preamplifiers are processed by the analog circuit.
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The signals from both wire ends are split into two branches. In the first branch, 7
4 2 0
I [ uA]
-2 -4 -6 -8 - 10 - 12 - 14
0
100
200 300 Ti m e [ ns]
0. 2
400
500
0. 15
Am pl i t ude [ V]
0. 1 0. 05 0 - 0. 05 - 0. 1 - 0. 15 - 0. 2 - 200
0
200
400 600 Ti m e [ ns]
800
1000
1200
Fig. 5: (color on-line) Upper panel: Preamplifier input current signal reproduced with the help of Qucs package. Lower panel: Measured output signal from the preamplifier. Blue and red lines denote positive and negative output signals.
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signals from both ends are added and fed to the CFD which produces a TTL
154
pulse for the time-to-digital converter (TDC). A delay correction prior to the
155
summing is not needed unless it is of the order of 1 ns (corresponding to about
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20 cm cable length) significantly less than the rise time of real signals from the
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MWDC. Care is taken to assure the equal length of the connecting cables. If the
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sum of the analog signals is higher than the set value of the CFD threshold, the
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STOP signal for the TDC is generated. The schematic of the CFD is presented
160
in Fig. 7.
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In the second branch, both signals are transmitted to the fast peak-hold
162
detectors, which are responsible for detection of the pulse amplitudes in a given 8
TopSInput
+
Peak Detector
Differential Amplifiers BottomSInput
ADCn ADC Drivers
+
+
Peak Detector
-
ADCn+1
CFD Trigger Input
TDCn
GATE
Gate Generator
DISCHARGE
DAC
Slow Control
Controller
Fig. 6: Block diagram of the analog board.
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gate time. Peak-hold detectors are used to stretch the pulse to the length
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acceptable for the ADC converters. The schematic of the peak-hold detector is
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shown in Fig. 8.
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The gate and hold signals are produced by a programmable timing circuit
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located on the analog board which uses the TDC START signal (external trig-
168
ger) as a time reference. The analog boards hosting the analog signal processing
169
circuits are equipped with built-in controllers for setting the thresholds of the
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CFD as well as the gate and the hold timing. The set values are fed to the
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controller over a slow-control bus (RS485).
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2.3. Digital cards
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The block diagram of the digital circuit is presented in Fig. 9. The digital
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board consists of 16 channels of 14-bit ADCs (AD8099 chips made by Analog
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Devices) and a 8 channel TDC (TDC-GPX chip made by Acam Messelectronic
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Gmbh). Using 14-bit ADCs was dictated by the large dynamic range of the am-
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plitudes of the signals from a gas detector operated in the proportional mode.
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The high bit ADC resolution increases the overall performance of the charge
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division method. The time resolution of the used TDC chip is significantly bet-
9
+ 5V R207 10
1
C200 10n
+5V
R200 10
1
C201 10uF
2
C202 100n
3 2
R201
U201 86 AD8099 5 4 R202470
R216
R206
R209 10
2 D
R210 5k
1
+5V_D
4
100
R204 IN
C203
GND
OUT U200
R211
1p
6
4
1
Q 5 Q
CLR
1
+5V_D
3 CLK
3
1
74F74
Q 13
A 2 B
6
R225 2k2
U206
74123
PRE
+5V
OUT1
47 U205
7474
50ns delay line
4 Q Ce 14
C224
ReCe 15
CLR
220p
74LS123
3 MAX962 U203 220
2
220 C210 C208 10uF
1
R205 10
7 5 MAX962
C215 100n
C212 100n
C209 10n
7
100
8 U203
2 C207 10n
R208 1k
CFD1_IN
1
+5V_D
+5V_D
C206 100n
2
R203 1k
CH1_THR
+ 5V
C204 22uF
100n
C205 -5V 10n
Fig. 7: Schematic of the Constant Fraction Discriminator. +5V
+5V
R108 10
R117 10
+5V
1
1
C112
C109 10uF
C116 10uF
100nF
C125 10uF
2
2
C106
R128 10
1
100nF
C120
INPUT
100nF
R111 51
C
7 8
R121 51
6
5
2
U101 AD8099
4
C
R133 1k
3
C122 1n
U103 AD8099
7 8
E
R126 2k2
C111 10p
E
Q100
B
R124 51
R171 470
OUTPUT
Q101
B
3
2
GATE
6
5
2 4
C127 10p
R130 220
R134 470
R141 1k
2
R115 220 C117 10uF
C121 10p
C128
D100
1
100nF
R127 220
2
C115
C132 10uF 1
100nF R125 10
CLEAR R143 10
−5V
−5V
Fig. 8: Schematic of the peak-hold detector.
180
ter than actually needed (83 ps binning resolution with the typical standard
181
deviation of 77 ps, from the device datasheet). The board measures the delay
182
between the common START (trigger) pulse and the individual STOP signals
183
received from the constant fraction discriminators, as well as the amplitudes of
184
the pulses delivered by the peak-hold detectors. The STOP signals are delayed
185
by a 50 ns delay line in order to compensate for the delays introduced in the
186
analog circuit generating the START signal. The ADCs sample the signals with
187
20 Msps sampling rate. The FPGA chip (Xilinx Spartan XC3S400) receives the
10
ADC1 ADC2 ADC3 ADC4
ADC sAD9252y
ADC5 ADC6 ADC7 ADC8
Ethernet Stack ICosW5100y
FPGA
LAN
ADC9 ADC10 ADC11 ADC12
Controller
ADC sAD9252y
ADC13 ADC14
Slow Control
ADC15 ADC16
TDC1 TDC2 TDC3 TDC4 TDC5 TDC6 TDC7 TDC8
50nso Delay Line
Stop1 Stop2 Stop3 Stop4 Stop5 Stop6 Stop7 Stop8
TDC sTDC-GPXy
Start Trigger
Fig. 9: Block diagram of the digital board. IDLE STATE
IDLE STATE TRIGGER (PMT)
Yes
WAIT_ADC STATE
FIFO EMPTY?
No Yes
ADC_CNV STATE
MTU REACHED?
No 32 ADC conversions
WAIT_TDC STATE
Yes
No TDC EMPTY?
Yes
SEND TIMER?
No
SEND FRAME
FIFO STORE
Data transmission algorithm
Data acquistion algorithm
Fig. 10: Flow diagram of the data acquisition algorithm (left panel) and of the data transmission algorithm (right panel).
11
188
data from the ADCs and the TDC, buffers them, provides zero-suppression and
189
time-stamping, and formats the data frame as described in the next paragraph.
190
The flow diagram of the acquisition algorithm and the data transmission algo-
191
rithm are shown in Fig. 10. The data frame is transmitted to the integrated
192
Ethernet/UDP stack (Wiznet W5100) which is responsible for communication
193
with the back-end PC hosting the acquisition and control software. The digi-
194
tal board is also equipped with a built-in controller providing initialization and
195
configuration of ADC, TDC and Ethernet chips. This controller is accessible
196
via the slow-control bus.
197
2.4. Data formatter
198
The data are transferred to the computer in a form of UDP frames. The
199
data formatter creates a frame for each recorded event. The frame length is
200
a multiple of 96 bytes. The first part of the frame is a fixed header used for
201
synchronization. Next follows the time tag (32 bit unsigned integer value) which
202
allows the time synchronization between multiple modules. The third part of
203
the frame consists of 16 ADC conversion values (16 bit unsigned integer values).
204
The fourth part contains the TDC values - up to eight 24-bit unsigned integer
205
values. Only the non-zero values of the TDC data are transmitted. The time
206
tagging is used because the Ethernet protocol does not ensure the sequence of
207
the data packet delivery. The time-tags are shared between modules and used
208
by the data-logging software to restore the correct data order. Fig. 11 shows
209
the structure of the data frame.
210
2.5. Slow-control bus and interface
211
The slow-control interface allows settings the CFD thresholds and timing
212
configuration parameters of the module. Each board in the module is equipped
213
with its own controller connected to the slow-control bus. Individual addresses
214
of the controllers are set with dip-switches installed on the boards. The con-
215
trollers use a simple ASCII protocol via RS485 interface. In order to connect
216
the bus to the acquisition computer a commercial RS485-USB converter is used.
12
Fig. 11: Data frame structure. The structures with the same time tag belong to one event.
217
An example of the initialization data record necessary for establishing the com-
218
munication over the slow-control bus is presented on Fig. 12. The slow-control
219
parameter set is read back every second and refreshed on a computer display (Fig. 13).
Fig. 12: ASCII command format used for reading and saving values. The command consists of the controller address, the read commands for thresholds (a,b,c,d), analog board timing (t1,t2) and digital board timing (t3,t4), where t1 is the gate width and t2 is the pulse hold time. For the digital board t3 denotes the maximum time for the incoming signal and t4 is the delay for the ADC. The second column presents the commands used for saving values to the controllers. The save commands use the same format but the uppercase option letters. 220
13
Fig. 13: Example of the slow-control display. One panel corresponds to one module consisting of two analog boards (ANB A and ANB B) and one digital board. Backlit represents the edited module data.
Fig. 14: (color on-line) Data flow diagram for ten acquisition modules. The red (green) squares denote the same time tag.
221
2.6. Data logging software
222
The data logging software provides the parallel reception of data frames
223
sent by the modules and the event building i.e. collection of data generated by
224
the system upon a single hardware trigger signal and uniquely identified by a
225
time tag. Each module is identified by its IP address and uses a specific UDP
226
port corresponding to this address. The architecture of the logging software
227
is shown in Fig. 14. The software is multi-threaded and consists of the main
228
thread (the parent) that is responsible for sorting and recording events, and the
14
229
child processes whose task is to receive data from the acquisition modules and to
230
send them via data streams to the main thread. Upon initialization the program
231
reads the configuration file with the addresses of the modules and opens sockets
232
for all modules to communicate with them. The sockets listen to the different
233
UDP ports correlated with the module address. The main loop creates a set of
234
pipes (data streams) and receives the data structures from the child processes.
235
The size of the frame is checked and followed by the pre-selection of cases. If the
236
TDC value is greater than zero, the event is pushed to the FIFO queue of the
237
child process. The event is then read from the FIFO by the parent process in
238
which the data structures from all child processes are sorted (using the quick-sort
239
algorithm) by the time tags and formatted as one complete event. This event
240
will be identified with a particle crossing the chamber planes and directed for
241
physics analysis. The received events are accessible for on-line histogramming
242
analysis by means of a shared memory mechanism and simultaneously saved on
243
a hard disk for later off-line analysis.
244
The cases with empty TDC conversion value (STOP signal below CFD
245
threshold) are used to calculate the baseline offset for the ADC. In this method
246
it is assumed that the lack of the TDC signal in a pair of channels (serving
247
a particular sense wire) means that the cell did not fire so the corresponding
248
ADCs deliver the offset values. This in-flight offset calculation method can be
249
disabled and the fixed offsets can be introduced with the help of the slow-control
250
interface. The baseline offsets subtracted (in flight) from the conversion value
251
are appended to the data structures for each event so that the subtraction is
252
reversible. Finally, the data structure consists of a time tag, module number,
253
channel number, ADC1 value, ADC2 value, TDC value, ADC1 offset and ADC2
254
offset, respectively. It is worth mentioning that the amplitude thresholds which
255
are needed for the histogram building were offset from the ADC baseline values
256
such that only the electronic noise was eliminated. The ultimate adjustment
257
of the thresholds was postponed to the detector efficiency tuning phase. It will
258
depend on the gas mixture composition and pressure as well as on the operation
259
voltage. 15
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J36
2
1
9
2
1
11
2
1
13
2
1
14
2
1
15
2
1
16
2
1 17
J35
2
1
18
J34
2
1
19
J33
2
1
20
J32
2
1
21
J31
2
1
23
J30
2
1
25
J29
J25
1
J24
2
1
J23
2
1
J22
2
1
J21
2
1
J20
2
1
J19
34
32
2
1
J18
2
1
J17
2
1
J16
2
1
2
34
C6 100nF
2
1
J45
C5 100nF
2
1
J44
C2 1nF
PREAMPLIFIER
V+ OUT+ GND OUT− V-
2
1
J43
INPUT
CUTA
2
1
27
C4 100nF
C3 100nF
R3 500
CONA
2
29
R2 68
J15
2
16
J6
1
31
V+ OUT+ GND OUT− V−
17
2
1
18
J5
2
1
19
2
1
20
J4
2
1
21
J3
2
1
23
J2
2
1
25
J1
2
1
27
2
1
29
2
1
31
2
1
33
2
1
33
R1 51
2
1
28
1
INPUT
PREAMPLIFIER
CONN1 INPUT
2
1
30
C1 1nF
2
32
−5V +5V
Fig. 15: Schematic of the dedicated tester for simulation of the signal wire.
260
3. Test results
261
The described DAQ system was tested using a special tester simulating the
262
wire chamber signals. The wire itself is replaced by a potentiometer with the
263
range reflecting the real wire resistance (see Fig. 15). The tester utilizes two
264
preamplifiers and signal cables connected to the selected module. A 400 mV high
265
and 200 ns long simulator input is synchronized with a TTL signal triggering the
266
system. The simulator input was fed by a triangle signal with 10 ns rise time and
267
200 ns fall time adjusted to the expected detector pulse shape obtained from the
268
GARFIELD (Ref. [10]) simulation. The hit position corresponds to a unique
269
potentiometer setting. The corresponding ADC asymmetry distributions are
270
shown in Fig. 16. The zero point defines the middle of the wire. The difference
271
between the individual asymmetry spectra reflects the varying relation between
272
the signal and noise amplitudes. In Fig. 17 sample results from one channel are
273
presented.
274
275
Fig. 18 shows a number of centroids the ADC pulse height asymmetry distributions AADC =
276
VA − VB VA + VB
(1)
acquired at different potentiometer asymmetry settings Apot =
RA − RB RA + RB
16
(2)
Fig. 16: (color on-line) ADC asymmetry spectra taken for 12 different potentiometer settings. The red hashed peak corresponds to Apot = 0.
277
where VA and VB are the ADC1, ADC2 amplitudes and RA , RB are the resis-
278
tances for selected potentiometer settings. The results were obtained for varying
279
resistance division corresponding to the charge collected at both wire ends. The
280
obtained ADC asymmetry is a monotonic function of the resistance asymmetry.
281
The centroids of these distributions are drawn with 1σ error bars in Fig. 18.
282
The polynomial function fitted to the centroids represents the position calibra-
283
tion. Drawing the error band allows the extraction of the position resolution
284
as shown in Fig. 19. The uncertainty of the relative position resolution is con-
285
nected with the interpolation procedure.
286
method determines the position with a resolution between 1.2 and 3.6 mm for
287
a 240 mm long wire. When feeding a given preamplifier pair with the simulator
288
signals the noise distributions on the neighboring channels were acquired as well.
289
Neither a baseline change nor an increase of noise were observed, meaning that
290
the electronic crosstalk is negligible. This does not assure there is no crosstalk
291
when the electronic system is attached to the gas detector. Inductive crosstalk
292
between the wires depends on the configuration and on the operating conditions
293
and is beyond the scope of this paper.
It shows that the charge division
294
In the second test, the response of the TDC measurement was investigated
295
as a function of the input signal asymmetry. Fig. 20 shows a typical example.
17
1000 500
ADC1
Mean 7049 RMS 204.3
Counts
0
ADC2
1000
Mean 7049
500
RMS 201.8
0 1000
A ADC
Mean 2.66e-05 RMS -0.5
1500
0
TDC [ns]
1000
0.02059 0.5
1
Mean 405.2 RMS 0.9561
500 0
9000
5000
500 0 -1
9000
5000
400
420
440
Fig. 17: Sample results for a single channel of one acquisition module. The two top plots present collected ADC values corresponding to both the upper part and the lower part of the wire. The two lower plots show the ADC asymmetry and converted TDC values in nanoseconds.
296
The impact of the charge division on the TDC measurement is found to be less
297
than 1 ns in the entire charge asymmetry range. For the application in view,
298
a 1 ns drift time corresponds to about 250 µm distance (from GARFIELD
299
simulations).
300
The maximum throughput of the system reaches 15 kHz per channel (120
301
kHz per module) and is limited by the transmission time of 60 µs needed for a
302
single event.
18
1 0. 8 0. 6 0. 4 AADC
0. 2 0
0. 3
- 0. 2 - 0. 4
0. 2
- 0. 6 - 0. 8 -1 -1
0. 1 0. 1 - 0. 8 - 0. 6 - 0. 4 - 0. 2
0
0. 2
0. 2 0. 4
0. 3 0. 6
0. 8
1
Apot
Fig. 18: ADC pulse height asymmetry (centroids of the peaks from Fig. 16) as a function of the resistance asymmetry Apot (Eqn. 2). The insert is a zoomed part of the graph showing the error bars equal to ± 1σ of the peak distributions plotted in Fig. 16. Dotted lines interpolate the error bar ends.
303
4. Conclusions and outlook
304
The front-end electronics and DAQ system described here was designed to
305
be used with a special multi-wire drift chamber for tracking low energy electrons
306
from nuclear β decays. It incorporates both the drift time and charge division
307
measurements allowing for efficient 3D determination of the electron tracks with
308
very few and only parallel sense wires. The performed tests show that the
309
electronic contribution to the drift time measurement uncertainty is less than 1
310
ns corresponding to about 250 µm position uncertainty at the expected electron
311
drift velocities. Such result is satisfactory since in the planned experiment the
312
track position resolution will be dominated by the electron angular straggling
313
effects in the gas as shown in Monte Carlo simulations and confirmed in the
314
small prototype test described in Ref. [8]. The necessary spatial resolution of the
315
electron track position determined from the drift time need not to be better than
316
500 µm. The uncertainty of the track position obtained from the charge division
317
measurement varies from 0.5% at wire ends to 1.5% in the center corresponding
318
to 1.2 and 3.6 mm, respectively, for 24 cm long wires (25 µm NiCr). This result
319
is sufficient for the application in view: identification of the cell sequence passed
19
2. 5
ΔL/ L 0 [ % ]
2
1. 5
1
0. 5
0
- 100
- 50
0 L [mm]
50
100
Fig. 19: Position resolution ∆L/L0 expressed in units of length of the wire deduced from Fig. 18. A 500 ohm wire resistance was assumed which corresponds to a 25 µm NiCr wire of L0 = 240 mm length. The uncertainty is connected with the interpolation procedure (see text). 402 401
TDC [ ns]
400 399 398 397 396 395 -1
- 0. 8 - 0. 6 - 0. 4 - 0. 2
0 AADC
0. 2
0. 4
0. 6
0. 8
1
Fig. 20: TDC values as a function of the ADC asymmetry. The error bars correspond to the standard deviation of the TDC histogram.
320
by an electron spiraling in an axial magnetic field and resolving possible double
321
track ambiguities appearing in the 2D projection.
322
323
324
325
[1] T. Bhattacharya, V. Cirigliano, S. D. Cohen, A. Filipuzzi, M. GonzalezAlonso et al., Phys. Rev. D 85, (2012) 054512. [2] O. Naviliat-Cuncic, M. Gonzalez-Alonso, Ann. Phys. (Berlin) 525, No. 89, (2013) 600619.
20
326
[3] J. D. Jackson, S. B. Treiman, H. W. Wyld, Phys. Rev. 106, (1957) 517.
327
[4] B. R. Holstein, Rev. Mod. Phys. 46, (1974) 789.
328
[5] N. Severijns, J. Phys. G., Nucl. Part. Phys. 41, (2014) 114006.
329
[6] F. Wauters, et al. Phys. Rev. C 82 (2010) 055502.
330
[7] to be published; conference posters: G. Soti, The miniBETA spectrometer
331
for the determination of weak magnetism and the Fierz interference term,
332
PSI2013, Switzerland; P. Finlay, miniBETA: A Multiwire Drift Chamber
333
for Beta-spectrum Shape Measurements, ARIS2014, Japan.
334
[8] K. Lojek, K. Bodek, M. Kuzniak, Nucl. Instr. and Meth. A 611 (2009) 284.
335
[9] Qucs - circuit simulator (http://qucs.sourceforge.net/).
336
337
[10] R.
Veenhof,
GARFIELD,
(http://garfield.web.cern.ch/garfield).
21
CERN
program
library
PII: DOI: Reference:
S0168-9002(15)01022-0 http://dx.doi.org/10.1016/j.nima.2015.08.058 NIMA57991
To appear in: Nuclear Inst. and Methods in Physics Research, A Received date: 15 April 2015 Revised date: 10 August 2015 Accepted date: 27 August 2015 Cite this article as: K. Łojek, D. Rozpȩdzik, K. Bodek, M. Perkowski and N. Severijns, Front-end electronics and data acquisition system for a multi-wire 3D gas tracker, Nuclear Inst. and Methods in Physics Research, A, http://dx.doi.org/10.1016/j.nima.2015.08.058 This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting galley proof before it is published in its final citable form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.
2
Front-end electronics and data acquisition system for a multi-wire 3D gas tracker
3
K. Lojeka , D. Rozp¸edzika,∗, K. Bodeka,∗, M. Perkowskia,b,∗, N. Severijnsb,∗
1
4 5
6
a Institute b Instituut
of Physics, Jagiellonian University, 30348 Cracow, Poland voor Kern-en Stralingsfysica, University of Leuven, 3001 Leuven, Belgium
Abstract This paper presents the design and implementation of the front-end electronics and the data acquisition (DAQ) system for readout of multi-wire drift chambers (MWDC). Apart of the conventional drift time measurement the system delivers the hit position along the wire utilizing the charge division technique. The system consists of preamplifiers, and analog and digital boards sending data to a back-end computer via an Ethernet interface. The data logging software formats the received data and enables an easy access to the data analysis software. The use of specially designed preamplifiers and peak detectors allows the chargedivision readout of the low resistance signal wire. The implication of the chargedivision circuitry onto the drift time measurement was studied and the overall performance of the electronic system was evaluated in dedicated off-line tests.
7
Keywords: data acquisition system, hardware, data logging software
8
PACS: 29.85.Ca; 29.40.Gx; 23.40.Bw
9
1. Introduction
10
Precision measurements in neutron and nuclear decay offer a sensitive win-
11
dow to search for new physics beyond the standard electroweak model and allow
12
also the determination of the fundamental weak vector coupling. Recent anal-
13
yses based on the effective field theory performed in e.g. [1, 2] show that in
14
processes involving the lightest quarks the neutron and nuclear decay will com-
15
pete with experiments at highest energy accelerators. For instance, data taken ∗ Corresponding
author Email address: [email protected] (D. Rozp¸edzik) Preprint submitted to Nuclear Instruments and Methods in Physics Research ASeptember 2, 2015
16
at the LHC is currently probing these interactions at the 10−2 level (relative
17
to the standard weak interactions), with the potential to reach the ' 10−3
18
level. In some of the β decay correlation measurements there are prospects to
19
reach experimental sensitivities between 10−3 and 10−4 making these observ-
20
ables interesting probes for searches of new physics originating at TeV scale.
21
The most direct access to the exotic tensor interaction in β decay is to measure
22
the Fierz term (coefficient b) or the beta-neutrino correlation coefficient a in a
23
pure Gamow-Teller transition [3]. The b coefficient shows up as a tiny energy
24
dependent (1/E) departure of the β spectrum from its V-A (standard model)
25
shape. The smallness of the potential b contribution requires that other cor-
26
rections to the spectrum shape of the same order are included in the analysis.
27
Indeed, according to [4, 5] the recoil terms also affect the spectrum shape with
28
their main contribution being proportional to E. In order to disentangle these
29
effects the detector efficiency for β particle as a function of energy must be
30
known with the precision better than 10−3 [6]. The dominating contribution
31
in the systematic uncertainty comes from back-scattering and out-scattering of
32
electrons from the detector. Monte Carlo simulation of this effect is helpful,
33
however, it introduces its own uncertainty as the input parameters are known
34
with limited accuracy. Monte Carlo simulation would reflect the real situation
35
better after it is adjusted to real experimental data of a particular measurement
36
setup.
37
The described in this article electronics was designed for a spectrometer
38
capable of direct registration of the back-scattering events, thus providing ref-
39
erence data for the Monte Carlo calculation of the detector efficiency. The
40
spectrometer itself is still in an R&D phase undergoing detailed tests and tun-
41
ing. It will be a subject of a separate paper together with the performance
42
benchmark [7]. In this paper, its concept will be described only in a minimum
43
extent at the beginning of Section 2 to explain the requirements imposed onto
44
the front-end electronics and DAQ. The rest of Section 2 is devoted to the elec-
45
tronic system architecture. The test results were obtained with a help of a signal
46
generator and are presented in Section 3. Therein the resulting time spectrum 2
47
and the charge asymmetry distribution representing the typical performance
48
are shown. The asymmetry spectra were obtained using a dedicated tester to
49
simulate the hit position on the wire with adjustable resistance division (poten-
50
tiometer). Conducting the electronic benchmark tests without a detector was
51
chosen by purpose. The detector itself is still not fully understood. Therefore it
52
was important to assess the purely electronic contribution to the performance
53
parameters of the spectrometer. The paper ends with a short summary and
54
outlook for the future experiment.
55
2. System architecture
56
In order to facilitate the identification of the electrons impinging onto and
57
scattered from the energy detector (e.g. Si detector, scintillator) a low-Z and
58
low-mass tracker must be applied. One of the attractive options is a low pressure
59
multi-wire drift chamber with minimum number of necessary wires in order to
60
maximize the detector transparency. This condition can be fulfilled by a hexag-
61
onal wire geometry and the charge division technique allowing for a 3D track
62
reconstruction without major distortion of the electron energy measurement.
63
The hexagonal wire geometry is not the only one considered in the project. The
64
rectangular (planar) wire configuration is the next suitable alternative. The
65
multi-wire drift chamber is based on the small prototype described in Ref. [8]
66
and will be operated with He/Isobutan gas mixture (ranging from 70%/30% to
67
90%/10%) at lowered pressure (down to 300 mbar). It consists of 10 sense wire
68
planes (8 wires for each plane) separated with 24 field wire planes forming the
69
double F-F-S-F-F-S-F-F-S-F-F-S-F-F-S-F-F structure (F- denotes a field wire
70
plane, S- denotes a signal wire plane). The distance between neighboring signal
71
planes is 15 mm, with wires within a plane being separated by 17.32 mm. This
72
wire plane structure leads to the hexagonal cell geometry as shown in Fig. 1.
73
Each cell consists of a very thin anode wire (NiCr alloy, 25 µm diameter) with
74
resistance of about 20 ohms/cm surrounded by 6 cathode field wires forming a
75
hexagonal cuboid. All wires are soldered to pads of the printed circuit board
3
F F S F F S F F S F F S F F S F F
Fig. 1: (color on-line) Fragment of the hexagonal wire structure. The blue (solid) circles denote the field wires and the red circles (crossed) correspond to signal wires. The field and signal wire planes are indicated with F and S, respectively. The shaded areas ilustrate the responding cells after an electron passed along the black solid line.
76
(PCB) frames. The chamber is equipped with a two-dimensional positioning
77
system for a beta source installed in the central region of the detector, between
78
both parts of the MWDC structure. In the initial configuration, the electrons
79
detected in two plastic scintillators installed at both sides of the MWDC pro-
80
vide the time reference signal for the drift time measurement. The PMT signals
81
are also used as a trigger for the MWDC and electron energy detector read-
82
out. Acquiring the drift time and the pulse height asymmetry at both ends of
83
the responding signal wire one can establish the electron path across the cham-
84
ber cell. The system provides charge-division position sensing in the direction
85
parallel to the wires as well as precise drift time measurement. The expected
86
position resolution across wires is limited by angular straggling of primary elec-
87
trons travelling in the gas and accounts to about 450 µm as shown in Ref. [8].
88
In this situation, the precision of the drift time measurement of about 200 ps is
89
more than needed as it corresponds to about 50 µm for the operating conditions
90
in view. The MWDC will be operated in homogenous magnetic field oriented
91
parallel to wires providing a rough electron transverse momentum filter. The
4
LAN Top5 Preamplifiers
Analog Card
MWDC
Digital Card
Analog Card
Bottom5 Preamplifiers
Slow5Control (RS485)
Fig. 2: Schematic of the data acquisition architecture.
92
position information along the wires will be used for the identification of the
93
sequence of the cells passed by the electrons and for distinguishing between the
94
electrons impinging onto and scattered from the energy detector. This is why
95
the modest position resolution of a few mm is sufficient for that direction.
96
Crucial in the design is the analog part of the system. In principle, com-
97
mercial digitizers (TDC, ADC) could be applied at the end of the acquisition
98
chain. However, it has been decided to equip the data channels with custom
99
digital boards with adjusted specifications such that the whole system is handy,
100
cost effective and scalable. The applied on board processing (FPGA) allows for
101
acquiring up to 15 000 triggered events per second which gives a comfortable
102
factor of 10 reserve as compared to the application in view.
103
The described modular electronic system consists of three main parts: (i)
104
preamplifiers, (ii) analog cards containing the peak detector and constant frac-
105
tion discriminator (CFD), and (iii) the digital boards containing analog to digital
106
converters, ADC and TDC. The data logging software on the PC constitutes
107
the data receiver. The signal from each signal plane is processed by means
108
of one electronics module, which consists of two analog cards and one digital
109
board providing 16 ADC and 8 TDC channels. A corresponding block diagram
110
is shown in Fig. 2. The signals from both ends of a signal wire are fed to inputs
111
of preamplifiers located directly on the detector frames (see Fig. 3) in order to
5
Fig. 3: (color on-line) Small piggyback preamplifier PCB cards plugged into the wire frames.
112
minimize the input noise and protect the signal from EM interferences. The
113
signals from the preamplifiers are received by the analog cards which drive the
114
ADC inputs and produce the TDC STOP signals. The digital data is transmit-
115
ted via a LAN port to the back-end computer where the process of receiving,
116
sorting and formatting to a complete physical event is accomplished by the
117
data logging software. The card configuration settings and control is done via a
118
RS485 port. Detailed description of each part of the system is presented in the
119
following sections.
120
2.1. Preamplifiers
121
Signal readout from both ends of the relatively low resistance wire requires
122
application of dedicated preamplifiers. Low resistance wires force the use of fast
123
preamplifiers with low input impedance since the change of signal amplitudes
124
and thus position resolution depends on the input impedance. The lower the
125
input impedance, the higher the voltage difference that is registered at the wire
126
ends. The preamplifiers work in current-mode with the input impedance below
127
5 ohms and the input stage bandwidth exceeding 300 MHz. The preamplifier
128
circuit is shown in Fig. 4. The first stage of the preamplifier is a current-voltage
129
converter with two fast bipolar transistors. The voltage pulse is fed to the
130
high-pass filter which cuts off the DC bias and the slow varying components of
131
the signal. The first filter is followed by a low-pass filter integrating the pulse
6
C1
C2
10nF R1
100nF
B
2k2
+5V
R3 10
C
IN
C7 100nF
C11 100nF
R9 10
Q2 BFR93
C
D1
R2 2k2 Q1 BFR93
E
1N4148 C3 10nF
C5 10nF R4 2k2
C4
R7 330
U2
R8 50
R6 1k
3 2
C9 100p
C10
R5 1k
10
R11 2k2
E
B
R13
100nF
7
4
8 6 5
8 R14 249
U1 AD8099
R12 10
C12 1p
R16 249
C13 100nF
100nF
C6
C8
10nF
100nF
R17 51
AD8139 5
3
2 1
OUT R15 499
4 6
R18 10
R19 499
R20 51 OUT −5V
R10 10
Fig. 4: Electronic circuit of the preamplifier. The system uses 160 dedicated preamplifiers to the drift chamber signals with charge division.
132
with 100 ns time constant. The signal is then amplified and transmitted to
133
the differential amplifier used to drive the transmission line. Differential sig-
134
nal transmission increases the external noise immunity when unshielded twisted
135
pair ribbon cables are used to connect the preamplifier outputs to the inputs of
136
the analog module. An example of input and output signals from a preamplifier
137
is shown in Fig. 5. The input current signal was reproduced with the help of
138
Qucs package [9]. Using bipolar transistors increases the preamplifier immunity
139
to possible discharges in the gas chamber. Adding more robust input protection
140
(e.g. a series resistor and protection diodes) was abandoned as it would increase
141
the input noise and impedance thus worsening the charge division resolution.
142
However, accidental discharges cannot be avoided completely and the need for
143
replacement of damaged preamplifiers was taken into account in the design. The
144
individual preamplifiers are arranged as small piggyback PCB cards mounted
145
directly on the wire frames (Fig. 3). They can be replaced easily without un-
146
plugging cables or any other major intervention in the setup. Additionally, such
147
a solution minimizes the length of the unshielded connection between the wire
148
end and the preamplifier input.
149
2.2. Analog cards
150
The block diagram of the analog circuit is presented in Fig. 6.
151
Differential signals from the preamplifiers are processed by the analog circuit.
152
The signals from both wire ends are split into two branches. In the first branch, 7
4 2 0
I [ uA]
-2 -4 -6 -8 - 10 - 12 - 14
0
100
200 300 Ti m e [ ns]
0. 2
400
500
0. 15
Am pl i t ude [ V]
0. 1 0. 05 0 - 0. 05 - 0. 1 - 0. 15 - 0. 2 - 200
0
200
400 600 Ti m e [ ns]
800
1000
1200
Fig. 5: (color on-line) Upper panel: Preamplifier input current signal reproduced with the help of Qucs package. Lower panel: Measured output signal from the preamplifier. Blue and red lines denote positive and negative output signals.
153
signals from both ends are added and fed to the CFD which produces a TTL
154
pulse for the time-to-digital converter (TDC). A delay correction prior to the
155
summing is not needed unless it is of the order of 1 ns (corresponding to about
156
20 cm cable length) significantly less than the rise time of real signals from the
157
MWDC. Care is taken to assure the equal length of the connecting cables. If the
158
sum of the analog signals is higher than the set value of the CFD threshold, the
159
STOP signal for the TDC is generated. The schematic of the CFD is presented
160
in Fig. 7.
161
In the second branch, both signals are transmitted to the fast peak-hold
162
detectors, which are responsible for detection of the pulse amplitudes in a given 8
TopSInput
+
Peak Detector
Differential Amplifiers BottomSInput
ADCn ADC Drivers
+
+
Peak Detector
-
ADCn+1
CFD Trigger Input
TDCn
GATE
Gate Generator
DISCHARGE
DAC
Slow Control
Controller
Fig. 6: Block diagram of the analog board.
163
gate time. Peak-hold detectors are used to stretch the pulse to the length
164
acceptable for the ADC converters. The schematic of the peak-hold detector is
165
shown in Fig. 8.
166
The gate and hold signals are produced by a programmable timing circuit
167
located on the analog board which uses the TDC START signal (external trig-
168
ger) as a time reference. The analog boards hosting the analog signal processing
169
circuits are equipped with built-in controllers for setting the thresholds of the
170
CFD as well as the gate and the hold timing. The set values are fed to the
171
controller over a slow-control bus (RS485).
172
2.3. Digital cards
173
The block diagram of the digital circuit is presented in Fig. 9. The digital
174
board consists of 16 channels of 14-bit ADCs (AD8099 chips made by Analog
175
Devices) and a 8 channel TDC (TDC-GPX chip made by Acam Messelectronic
176
Gmbh). Using 14-bit ADCs was dictated by the large dynamic range of the am-
177
plitudes of the signals from a gas detector operated in the proportional mode.
178
The high bit ADC resolution increases the overall performance of the charge
179
division method. The time resolution of the used TDC chip is significantly bet-
9
+ 5V R207 10
1
C200 10n
+5V
R200 10
1
C201 10uF
2
C202 100n
3 2
R201
U201 86 AD8099 5 4 R202470
R216
R206
R209 10
2 D
R210 5k
1
+5V_D
4
100
R204 IN
C203
GND
OUT U200
R211
1p
6
4
1
Q 5 Q
CLR
1
+5V_D
3 CLK
3
1
74F74
Q 13
A 2 B
6
R225 2k2
U206
74123
PRE
+5V
OUT1
47 U205
7474
50ns delay line
4 Q Ce 14
C224
ReCe 15
CLR
220p
74LS123
3 MAX962 U203 220
2
220 C210 C208 10uF
1
R205 10
7 5 MAX962
C215 100n
C212 100n
C209 10n
7
100
8 U203
2 C207 10n
R208 1k
CFD1_IN
1
+5V_D
+5V_D
C206 100n
2
R203 1k
CH1_THR
+ 5V
C204 22uF
100n
C205 -5V 10n
Fig. 7: Schematic of the Constant Fraction Discriminator. +5V
+5V
R108 10
R117 10
+5V
1
1
C112
C109 10uF
C116 10uF
100nF
C125 10uF
2
2
C106
R128 10
1
100nF
C120
INPUT
100nF
R111 51
C
7 8
R121 51
6
5
2
U101 AD8099
4
C
R133 1k
3
C122 1n
U103 AD8099
7 8
E
R126 2k2
C111 10p
E
Q100
B
R124 51
R171 470
OUTPUT
Q101
B
3
2
GATE
6
5
2 4
C127 10p
R130 220
R134 470
R141 1k
2
R115 220 C117 10uF
C121 10p
C128
D100
1
100nF
R127 220
2
C115
C132 10uF 1
100nF R125 10
CLEAR R143 10
−5V
−5V
Fig. 8: Schematic of the peak-hold detector.
180
ter than actually needed (83 ps binning resolution with the typical standard
181
deviation of 77 ps, from the device datasheet). The board measures the delay
182
between the common START (trigger) pulse and the individual STOP signals
183
received from the constant fraction discriminators, as well as the amplitudes of
184
the pulses delivered by the peak-hold detectors. The STOP signals are delayed
185
by a 50 ns delay line in order to compensate for the delays introduced in the
186
analog circuit generating the START signal. The ADCs sample the signals with
187
20 Msps sampling rate. The FPGA chip (Xilinx Spartan XC3S400) receives the
10
ADC1 ADC2 ADC3 ADC4
ADC sAD9252y
ADC5 ADC6 ADC7 ADC8
Ethernet Stack ICosW5100y
FPGA
LAN
ADC9 ADC10 ADC11 ADC12
Controller
ADC sAD9252y
ADC13 ADC14
Slow Control
ADC15 ADC16
TDC1 TDC2 TDC3 TDC4 TDC5 TDC6 TDC7 TDC8
50nso Delay Line
Stop1 Stop2 Stop3 Stop4 Stop5 Stop6 Stop7 Stop8
TDC sTDC-GPXy
Start Trigger
Fig. 9: Block diagram of the digital board. IDLE STATE
IDLE STATE TRIGGER (PMT)
Yes
WAIT_ADC STATE
FIFO EMPTY?
No Yes
ADC_CNV STATE
MTU REACHED?
No 32 ADC conversions
WAIT_TDC STATE
Yes
No TDC EMPTY?
Yes
SEND TIMER?
No
SEND FRAME
FIFO STORE
Data transmission algorithm
Data acquistion algorithm
Fig. 10: Flow diagram of the data acquisition algorithm (left panel) and of the data transmission algorithm (right panel).
11
188
data from the ADCs and the TDC, buffers them, provides zero-suppression and
189
time-stamping, and formats the data frame as described in the next paragraph.
190
The flow diagram of the acquisition algorithm and the data transmission algo-
191
rithm are shown in Fig. 10. The data frame is transmitted to the integrated
192
Ethernet/UDP stack (Wiznet W5100) which is responsible for communication
193
with the back-end PC hosting the acquisition and control software. The digi-
194
tal board is also equipped with a built-in controller providing initialization and
195
configuration of ADC, TDC and Ethernet chips. This controller is accessible
196
via the slow-control bus.
197
2.4. Data formatter
198
The data are transferred to the computer in a form of UDP frames. The
199
data formatter creates a frame for each recorded event. The frame length is
200
a multiple of 96 bytes. The first part of the frame is a fixed header used for
201
synchronization. Next follows the time tag (32 bit unsigned integer value) which
202
allows the time synchronization between multiple modules. The third part of
203
the frame consists of 16 ADC conversion values (16 bit unsigned integer values).
204
The fourth part contains the TDC values - up to eight 24-bit unsigned integer
205
values. Only the non-zero values of the TDC data are transmitted. The time
206
tagging is used because the Ethernet protocol does not ensure the sequence of
207
the data packet delivery. The time-tags are shared between modules and used
208
by the data-logging software to restore the correct data order. Fig. 11 shows
209
the structure of the data frame.
210
2.5. Slow-control bus and interface
211
The slow-control interface allows settings the CFD thresholds and timing
212
configuration parameters of the module. Each board in the module is equipped
213
with its own controller connected to the slow-control bus. Individual addresses
214
of the controllers are set with dip-switches installed on the boards. The con-
215
trollers use a simple ASCII protocol via RS485 interface. In order to connect
216
the bus to the acquisition computer a commercial RS485-USB converter is used.
12
Fig. 11: Data frame structure. The structures with the same time tag belong to one event.
217
An example of the initialization data record necessary for establishing the com-
218
munication over the slow-control bus is presented on Fig. 12. The slow-control
219
parameter set is read back every second and refreshed on a computer display (Fig. 13).
Fig. 12: ASCII command format used for reading and saving values. The command consists of the controller address, the read commands for thresholds (a,b,c,d), analog board timing (t1,t2) and digital board timing (t3,t4), where t1 is the gate width and t2 is the pulse hold time. For the digital board t3 denotes the maximum time for the incoming signal and t4 is the delay for the ADC. The second column presents the commands used for saving values to the controllers. The save commands use the same format but the uppercase option letters. 220
13
Fig. 13: Example of the slow-control display. One panel corresponds to one module consisting of two analog boards (ANB A and ANB B) and one digital board. Backlit represents the edited module data.
Fig. 14: (color on-line) Data flow diagram for ten acquisition modules. The red (green) squares denote the same time tag.
221
2.6. Data logging software
222
The data logging software provides the parallel reception of data frames
223
sent by the modules and the event building i.e. collection of data generated by
224
the system upon a single hardware trigger signal and uniquely identified by a
225
time tag. Each module is identified by its IP address and uses a specific UDP
226
port corresponding to this address. The architecture of the logging software
227
is shown in Fig. 14. The software is multi-threaded and consists of the main
228
thread (the parent) that is responsible for sorting and recording events, and the
14
229
child processes whose task is to receive data from the acquisition modules and to
230
send them via data streams to the main thread. Upon initialization the program
231
reads the configuration file with the addresses of the modules and opens sockets
232
for all modules to communicate with them. The sockets listen to the different
233
UDP ports correlated with the module address. The main loop creates a set of
234
pipes (data streams) and receives the data structures from the child processes.
235
The size of the frame is checked and followed by the pre-selection of cases. If the
236
TDC value is greater than zero, the event is pushed to the FIFO queue of the
237
child process. The event is then read from the FIFO by the parent process in
238
which the data structures from all child processes are sorted (using the quick-sort
239
algorithm) by the time tags and formatted as one complete event. This event
240
will be identified with a particle crossing the chamber planes and directed for
241
physics analysis. The received events are accessible for on-line histogramming
242
analysis by means of a shared memory mechanism and simultaneously saved on
243
a hard disk for later off-line analysis.
244
The cases with empty TDC conversion value (STOP signal below CFD
245
threshold) are used to calculate the baseline offset for the ADC. In this method
246
it is assumed that the lack of the TDC signal in a pair of channels (serving
247
a particular sense wire) means that the cell did not fire so the corresponding
248
ADCs deliver the offset values. This in-flight offset calculation method can be
249
disabled and the fixed offsets can be introduced with the help of the slow-control
250
interface. The baseline offsets subtracted (in flight) from the conversion value
251
are appended to the data structures for each event so that the subtraction is
252
reversible. Finally, the data structure consists of a time tag, module number,
253
channel number, ADC1 value, ADC2 value, TDC value, ADC1 offset and ADC2
254
offset, respectively. It is worth mentioning that the amplitude thresholds which
255
are needed for the histogram building were offset from the ADC baseline values
256
such that only the electronic noise was eliminated. The ultimate adjustment
257
of the thresholds was postponed to the detector efficiency tuning phase. It will
258
depend on the gas mixture composition and pressure as well as on the operation
259
voltage. 15
J11
J12
J13
J14
2
1
J10
4
3
J9
6
5
J8
7
9
11
13
8
10
12
14
J7
15
22
24
26
28
30
2
1
J42
J28
J41
J27
J40
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
J54
J55
J56
4
2
1
J53
6
2
1
J52
8
3
J39
J26
J38
2
1
J51
10
2
1
J50
12
2
1
J49
22
2
1
J48
CUTB
2
J47
24
CONB
J46
26
5
J37
1
7
J36
2
1
9
2
1
11
2
1
13
2
1
14
2
1
15
2
1
16
2
1 17
J35
2
1
18
J34
2
1
19
J33
2
1
20
J32
2
1
21
J31
2
1
23
J30
2
1
25
J29
J25
1
J24
2
1
J23
2
1
J22
2
1
J21
2
1
J20
2
1
J19
34
32
2
1
J18
2
1
J17
2
1
J16
2
1
2
34
C6 100nF
2
1
J45
C5 100nF
2
1
J44
C2 1nF
PREAMPLIFIER
V+ OUT+ GND OUT− V-
2
1
J43
INPUT
CUTA
2
1
27
C4 100nF
C3 100nF
R3 500
CONA
2
29
R2 68
J15
2
16
J6
1
31
V+ OUT+ GND OUT− V−
17
2
1
18
J5
2
1
19
2
1
20
J4
2
1
21
J3
2
1
23
J2
2
1
25
J1
2
1
27
2
1
29
2
1
31
2
1
33
2
1
33
R1 51
2
1
28
1
INPUT
PREAMPLIFIER
CONN1 INPUT
2
1
30
C1 1nF
2
32
−5V +5V
Fig. 15: Schematic of the dedicated tester for simulation of the signal wire.
260
3. Test results
261
The described DAQ system was tested using a special tester simulating the
262
wire chamber signals. The wire itself is replaced by a potentiometer with the
263
range reflecting the real wire resistance (see Fig. 15). The tester utilizes two
264
preamplifiers and signal cables connected to the selected module. A 400 mV high
265
and 200 ns long simulator input is synchronized with a TTL signal triggering the
266
system. The simulator input was fed by a triangle signal with 10 ns rise time and
267
200 ns fall time adjusted to the expected detector pulse shape obtained from the
268
GARFIELD (Ref. [10]) simulation. The hit position corresponds to a unique
269
potentiometer setting. The corresponding ADC asymmetry distributions are
270
shown in Fig. 16. The zero point defines the middle of the wire. The difference
271
between the individual asymmetry spectra reflects the varying relation between
272
the signal and noise amplitudes. In Fig. 17 sample results from one channel are
273
presented.
274
275
Fig. 18 shows a number of centroids the ADC pulse height asymmetry distributions AADC =
276
VA − VB VA + VB
(1)
acquired at different potentiometer asymmetry settings Apot =
RA − RB RA + RB
16
(2)
Fig. 16: (color on-line) ADC asymmetry spectra taken for 12 different potentiometer settings. The red hashed peak corresponds to Apot = 0.
277
where VA and VB are the ADC1, ADC2 amplitudes and RA , RB are the resis-
278
tances for selected potentiometer settings. The results were obtained for varying
279
resistance division corresponding to the charge collected at both wire ends. The
280
obtained ADC asymmetry is a monotonic function of the resistance asymmetry.
281
The centroids of these distributions are drawn with 1σ error bars in Fig. 18.
282
The polynomial function fitted to the centroids represents the position calibra-
283
tion. Drawing the error band allows the extraction of the position resolution
284
as shown in Fig. 19. The uncertainty of the relative position resolution is con-
285
nected with the interpolation procedure.
286
method determines the position with a resolution between 1.2 and 3.6 mm for
287
a 240 mm long wire. When feeding a given preamplifier pair with the simulator
288
signals the noise distributions on the neighboring channels were acquired as well.
289
Neither a baseline change nor an increase of noise were observed, meaning that
290
the electronic crosstalk is negligible. This does not assure there is no crosstalk
291
when the electronic system is attached to the gas detector. Inductive crosstalk
292
between the wires depends on the configuration and on the operating conditions
293
and is beyond the scope of this paper.
It shows that the charge division
294
In the second test, the response of the TDC measurement was investigated
295
as a function of the input signal asymmetry. Fig. 20 shows a typical example.
17
1000 500
ADC1
Mean 7049 RMS 204.3
Counts
0
ADC2
1000
Mean 7049
500
RMS 201.8
0 1000
A ADC
Mean 2.66e-05 RMS -0.5
1500
0
TDC [ns]
1000
0.02059 0.5
1
Mean 405.2 RMS 0.9561
500 0
9000
5000
500 0 -1
9000
5000
400
420
440
Fig. 17: Sample results for a single channel of one acquisition module. The two top plots present collected ADC values corresponding to both the upper part and the lower part of the wire. The two lower plots show the ADC asymmetry and converted TDC values in nanoseconds.
296
The impact of the charge division on the TDC measurement is found to be less
297
than 1 ns in the entire charge asymmetry range. For the application in view,
298
a 1 ns drift time corresponds to about 250 µm distance (from GARFIELD
299
simulations).
300
The maximum throughput of the system reaches 15 kHz per channel (120
301
kHz per module) and is limited by the transmission time of 60 µs needed for a
302
single event.
18
1 0. 8 0. 6 0. 4 AADC
0. 2 0
0. 3
- 0. 2 - 0. 4
0. 2
- 0. 6 - 0. 8 -1 -1
0. 1 0. 1 - 0. 8 - 0. 6 - 0. 4 - 0. 2
0
0. 2
0. 2 0. 4
0. 3 0. 6
0. 8
1
Apot
Fig. 18: ADC pulse height asymmetry (centroids of the peaks from Fig. 16) as a function of the resistance asymmetry Apot (Eqn. 2). The insert is a zoomed part of the graph showing the error bars equal to ± 1σ of the peak distributions plotted in Fig. 16. Dotted lines interpolate the error bar ends.
303
4. Conclusions and outlook
304
The front-end electronics and DAQ system described here was designed to
305
be used with a special multi-wire drift chamber for tracking low energy electrons
306
from nuclear β decays. It incorporates both the drift time and charge division
307
measurements allowing for efficient 3D determination of the electron tracks with
308
very few and only parallel sense wires. The performed tests show that the
309
electronic contribution to the drift time measurement uncertainty is less than 1
310
ns corresponding to about 250 µm position uncertainty at the expected electron
311
drift velocities. Such result is satisfactory since in the planned experiment the
312
track position resolution will be dominated by the electron angular straggling
313
effects in the gas as shown in Monte Carlo simulations and confirmed in the
314
small prototype test described in Ref. [8]. The necessary spatial resolution of the
315
electron track position determined from the drift time need not to be better than
316
500 µm. The uncertainty of the track position obtained from the charge division
317
measurement varies from 0.5% at wire ends to 1.5% in the center corresponding
318
to 1.2 and 3.6 mm, respectively, for 24 cm long wires (25 µm NiCr). This result
319
is sufficient for the application in view: identification of the cell sequence passed
19
2. 5
ΔL/ L 0 [ % ]
2
1. 5
1
0. 5
0
- 100
- 50
0 L [mm]
50
100
Fig. 19: Position resolution ∆L/L0 expressed in units of length of the wire deduced from Fig. 18. A 500 ohm wire resistance was assumed which corresponds to a 25 µm NiCr wire of L0 = 240 mm length. The uncertainty is connected with the interpolation procedure (see text). 402 401
TDC [ ns]
400 399 398 397 396 395 -1
- 0. 8 - 0. 6 - 0. 4 - 0. 2
0 AADC
0. 2
0. 4
0. 6
0. 8
1
Fig. 20: TDC values as a function of the ADC asymmetry. The error bars correspond to the standard deviation of the TDC histogram.
320
by an electron spiraling in an axial magnetic field and resolving possible double
321
track ambiguities appearing in the 2D projection.
322
323
324
325
[1] T. Bhattacharya, V. Cirigliano, S. D. Cohen, A. Filipuzzi, M. GonzalezAlonso et al., Phys. Rev. D 85, (2012) 054512. [2] O. Naviliat-Cuncic, M. Gonzalez-Alonso, Ann. Phys. (Berlin) 525, No. 89, (2013) 600619.
20
326
[3] J. D. Jackson, S. B. Treiman, H. W. Wyld, Phys. Rev. 106, (1957) 517.
327
[4] B. R. Holstein, Rev. Mod. Phys. 46, (1974) 789.
328
[5] N. Severijns, J. Phys. G., Nucl. Part. Phys. 41, (2014) 114006.
329
[6] F. Wauters, et al. Phys. Rev. C 82 (2010) 055502.
330
[7] to be published; conference posters: G. Soti, The miniBETA spectrometer
331
for the determination of weak magnetism and the Fierz interference term,
332
PSI2013, Switzerland; P. Finlay, miniBETA: A Multiwire Drift Chamber
333
for Beta-spectrum Shape Measurements, ARIS2014, Japan.
334
[8] K. Lojek, K. Bodek, M. Kuzniak, Nucl. Instr. and Meth. A 611 (2009) 284.
335
[9] Qucs - circuit simulator (http://qucs.sourceforge.net/).
336
337
[10] R.
Veenhof,
GARFIELD,
(http://garfield.web.cern.ch/garfield).
21
CERN
program
library