Fully Controlled Semiconductor Devices

10

Fully Controlled Semiconductor Devices 10.0

Introduction

In Chapters 2 and 4 the uncontrolled turn-on and turn-off power diode was presented and analyzed together with the resulting rectifier topologies. Also, in Chapters 3 and 5 the controlled turn-on and uncontrolled turn-off thyristor was presented and analyzed together with the resulting rectifier topologies. In this chapter the fully controlled semiconductor devices, which are also called power semiconductor switches, such as bipolar junction transistors (BJTs), metal-oxide-semiconductor field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), gate turn-off thyristor (GTOs), and MOS-controlled thyristors (MCTs) will be examined. Although, in this chapter the power BJT is also presented, it has to be noted that nowadays it is not used as a semiconductor switch for the implementation of power electronics topologies due to its low current gain. Moreover, the driving and protection circuits of the semiconductor switches will be presented.

10.1

Power Bipolar Junction Transistor (BJT)

The power bipolar junction transistor (BJT) was the first semiconductor switch that was used for the implementation of power electronics switching topologies. There are two types of power transistors, the npn and the pnp, and are shown in Fig. 10.1(a) and (b), respectively. As shown in Fig. 10.1 the transistor is a three layer device and has three terminals: the base (B), the emitter (E), and the collector (C).

10.1.1 BJT Operation Fig. 10.2 shows the construction prototype of an npn transistor which will be used to explain its operation. As can be seen, due to its construction, there are two depletion regions along its surface. The base p region is much smaller than the n region as shown

(a)

C iC

Base B

iB

VBE

Collector -n +p

iE -n E

C

Emitter

(b)

VCE

iC +p E

Base B iB VBE

iE

-n +p +p

E Emitter

Figure 10.1 Power BJT cross section. (a) npn-type, (b) pnp-type. Power Electronics and Motor Drive Systems http://dx.doi.org/10.1016/B978-0-12-811798-9.00010-X Copyright © 2017 Elsevier Inc. All rights reserved.

C

Collector

C

B

B E VCE

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(a) Emitter Base Collector

Emitter Base Collector

(b) iC

n

iE

n V2

iB iC = 0

iC =iB

iE = 0 S1 V 1

S2

(c)

p

n

V2

`

S1 V1

n

`

iE =iB

p

S2

Emitter Base Collector

p p

nn iE

iC

nn

V2

iB

`

S1

V1

S2

Figure 10.2 BJT carriers flow. (a) When baseeemitter junction is forward biased; (b) when baseecollector junction is reverse biased; (c) when the two above biases are simultaneously applied.

in Fig. 10.2. This is necessary because in order for the transistor to operate, the number of the holes of the base must be smaller than the number of the electrons of the emitter and collector (n-type crystals). Generally, during transistor operation, a forward voltage between emitter and base must be applied, while a reverse voltage is applied between collector and base. When only a forward bias is applied between the base and emitter (Fig. 10.2(a)), then the negative terminal of the source V1, which is connected to the emitter, repels the electrons toward nep junction, while at the same time the positive pole of V1 connected to the base, repels the holes toward the same junction (i.e., nep). Therefore, a small number of the free electrons of the emitter recombine with holes of the base, which results in decrease of the barrier potential and, consequently, a small current iB flows through the baseeemitter path. When only a reverse bias is applied between the base and collector of the transistor (Fig. 10.2(b)), the positive terminal of the source V2 attracts electrons from the collector, while the negative terminal attracts holes from the base. Therefore, the electrons and the holes are withdrawn from pen junction, which will result in increase of the junction resistance, causing the interruption of current flow in the collector-base path. However, due to the minority carriers a negligible current will flow through the collectorebase path. In case the two biases described above are simultaneously applied to the transistor (Fig. 10.2(c)), then the negative potential of the emitters repels the free electrons toward the emitterebase nep junction, which as it is forward biased, exhibits low resistance. Therefore, the electrons are

Fully Controlled Semiconductor Devices

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diffused into the base region and recombine with their holes. But as the p-type layer of the base is very thin, possesses a small amount of holes, which results the great majority of the electrons that enter into the base layer to be unable to find a hole to recombine. These continue their flow into the collector region, because they have acquired significant speed and are attracted from the positive pole of V2 source. From the above, it is concluded that from the great number of electrons of the emitter, which are repelled from the negative terminal of the source V1 and diffused into the thin base region, only a small part of them recombine with the holes of the base, while the rest pass in the collector and are attracted from the positive terminal of V2 source. This results to the flow of a small base current and of a much greater in the collector path. Therefore, the emitter current iE consists of the following two components: iE ¼ iB þ iC

(10.1)

The current gain of a transistor is given by the following equation: hfe ¼

iC iB

(10.2)

The base current iB is much smaller than the collector current iC. Usually the gain hfe has a value that varies between 10 and 100. Figs. 10.3 and 10.4 show the input and output characteristics of an npn transistor in common emitter configuration. As can be seen from the output characteristics of Fig. 10.4, a transistor can operate in any of the following three regions: a) Active region: In order for a transistor to operate in this region, the emitterebase region must be forward biased, while the baseecollector region reverse biased. In this region the BJT operates as an amplifier and IC ¼ bIb. This mode of operation is not used in power electronics converters. b) Cut-off region: When both the nep regions are reverse biased, then the currents generated at the terminals of the transistor are very small and, consequently, the BJT operates in the

v BE

VCE2 VCE1

700

500 300

100 0

10

30

50

70

90

iB

Figure 10.3 Input vBEeiB characteristics of an npn power BJT in common emitter configuration.

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Active region IC = h fe I B operates as an amplifier I B5

iC ICMAX Saturation region BJT operates as a closed switch iC =Isaturation

IB4 I B3

SUSTAINING REGION

IB2

Vceo(SUS) Vcer(SUS) Vces(SUS) Vcev(SUS)

IB1

Increasing IB IB = 0 VCE(sat)

Cut − off region BJT operates as an open switch iC = 0

VBces VBvev

vCE

VBcer VBceo

VCE(MAX)

Figure 10.4 Output iCevCE characteristics of an npn power BJT in common emitter configuration. cut-off region. The transistor in this region is considered to be an open switch. When the BJT is in this region, it is considered to be in the so-called off-state. c) Saturation region: When the forward-biased emitterebase junction generates sufficient collector current from the external circuit, it causes the collectorebase junction to become forward biased. In this region, both the nep junctions are forward biased. The BJT in this region is considered to be a closed switch. When the BJT is in this region, it is considered to be in the so-called on-state.

At this point it should be mentioned that the transistor in power electronics topologies operates as a switch, which means that it operates only in the cut-off region or in the saturation region. Finally, Fig. 10.5 shows the Darlington power transistor configuration, which exhibits higher current gain than the single transistor configuration (>100).

hfeT1 T1

B1

hfeT2 T2

R1

R2

B2 h fe(darlington) ≈ h feT1 ⋅ h feT2

Freewheeling diode

C

E

Figure 10.5 Darlington power transistor configuration with an integrated freewheeling diode.

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10.1.2 Dynamic Switching Characteristics of a BJT If a current pulse as the one shown in Fig. 10.6(b) is applied to the base of an npn power transistor in common emitter configuration, then the resulting collector current waveform is the one shown in Fig. 10.6(c). From the waveforms of Fig. 10.6(c), the following results and conclusions are obtained: a) Turn-on time: tc(on) ¼ td(on) þ tr where tdðonÞ ¼ delay time of transistor turn-on; due to the charge of the base-emitter qffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 junction diffusion capacitance z Cde VBðoffÞ s IBF

(10.3)

Cde ¼ base-emitter junction diffusion capacitance ðgiven by the manufacturer or being calculatedÞ

(a)

VS + RL

i BF

out

iB

iB

t i BR

(b) iB 0.9IBF

IBF

0.5IBF

tp

0.1IBF t

IBR

(c) iC

tc(on) td(on) tr

tc(off) ts

0.9IC

tf

IC 0.1IC t

Figure 10.6 npn BJT switching characteristics. (a) Common emitter configuration; (b) base current waveform; (c) collector current waveform.

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IBF ¼ amplitude of the positive base current VBEðoffÞ ¼ base-emitter voltage in cut-off state tr ¼ rise time of collector current The delay time can be reduced by increasing the amplitude IBF and the rise rate of the base current. The rise time tr of the collector current is given by: tr ¼ se 1n

hfe IBF s hfe IBF  0:9IC

(10.4)

where se ¼ lifetime of the minority carriers in the transistor base ¼

hfe ð1 þ 2RL Cde us Þ us

hfe ¼ transistor gain

(10.5)

iC ¼ collector current us ¼ transistor angular switching frequency The times td and tr are given by the transistor manufacturer. b) Turn-off time: tc(off) ¼ ts þ tf Time ts is defined as the total storage time and it is the time interval between the removal of the drive current and the time instant at which the collector current iC ¼ 0.9IC. When the transistor operates in saturation mode, retains an excess of minority carrier charge stored in its base region. For this reason the transistor is unable to respond to the abrupt fall of the drive pulse until all the excess stored charge is removed. The storage time is given in the manufacturer specifications. The turn-off transition starts with the removal of the positive base current pulse iBF and the application of the negative current pulse iBR. The minority carriers (i.e., the holes) at the n region of the collector begin to reduce due to the collector current. The redundant minority carriers of the base are withdrawn by the use of the negative base current pulse. The negative base current does not affect the n region of the collector during the recombination procedure. Time tf is defined as the fall time and is the time interval required for the collector current to fall from 0.9 to 0.1IC. Fall time tf is given by: tf ¼ se 1n

0:9 IC  hfe IBR s 0:1 IC  hfe IBR

(10.6)

Therefore, according to the above equation, fall time tfi can be reduced by increasing the amplitude of the negative base current pulse. This time is also given in the manufacturer specifications.

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10.1.3 First Breakdown of a BJT The first breakdown mode of a transistor is that mode in which the transistor operates in the collectoreemitter breakdown voltage region, which will result to its failure. The collectoreemitter breakdown voltage with an open base circuit VCEO is given in the specification of the manufacturer. Fig. 10.7 shows the collectoreemitter voltage breakdown characteristics for various npn transistor connections.

10.1.4 Second Breakdown of a BJT Power transistors can be destroyed when operating in the second breakdown mode. Many times as the collector voltage falls, a high rate of rise of the collector current is created causing a significant increase of power losses within the semiconductor device. What makes this operation mode dangerous is that the transistor power losses are not equally distributed within the device filaments, thus creating the so-called hot spot due to the collector current concentration at that point and this can be catastrophic for the transistor. Fig. 10.8 shows the phenomenon of the unequal current distribution within the device filaments which results into temperature increase of particular areas of the device and, consequently, the transistor goes to the second breakdown mode. If this problem is not corrected, then the transistor will be destroyed. Fig. 10.9 shows the first and second breakdown mode regions of a transistor in common emitter configuration. The second breakdown phenomenon can be avoided using one of the following methods: a) The device power losses to be kept under control. b) The unequal distribution of current density within the semiconductor device to be avoided during turn-on and turn-off transitions, because during these modes of operation the transistor exhibits maximum switching power losses. iC

Second breakdown

VΒcbo > VΒcev > VΒces > VΒcer > VΒceo

Vceo Vcer

Vces

Is/b

Vcev Vcbo

First breakdown Breakdown voltage VBceo

VBcer

VBces

VBcbo vCE

Figure 10.7 Collectoreemitter voltage breakdown characteristics for various npn BJT connections.

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Power Electronics and Motor Drive Systems

i

filament Α filament Β

R

V

iB

iA

iA > iB

Figure 10.8 Unequal current distribution within the filaments of the device. Second breakdown

iC

First breakdown

iB>0 iB=0 vCE VCE(sus)

VCEO

Figure 10.9 First and second breakdown mode regions of a BJT in common emitter configuration.

10.1.5

Safe Operating Area of a BJT

The safe operating area (SOA) represents the area in which the transistor operates with high reliability, without the risk of being destroyed. The operation limits are determined from the collector voltage and the power losses of the semiconductor device. There are two such areas: the first is the forward bias safe operating area (FBSOA), which is shown in Fig. 10.10(a) and the second is the reverse bias safe operating area (RBSOA), which is in Fig. 10.10(b). It must be mentioned that the forward or reverse bias operation is referred to whether the base current biases positively or negatively the basee emitter junction. In case of the forward bias the base current is positive, whereas in reverse bias it is negative, which results in transistor being in cut-off mode. As shown in Fig. 10.10(a), current ICM is the maximum absolute value of the collector current, the excess of which leads to the transistor failure. Tjmax is the maximum junction temperature of the transistor which is defined from the transistor thermal resistance and from the maximum allowable junction temperature. The second breakdown limit represents the possible voltage and current combinations that do not enter in the areas of ICeVCE level where the second breakdown phenomenon can occur. The area below the DC curve represents the safe operation of the transistor in case the current is continuous. This area increases when the current becomes a pulse and the area increases as the width of the current pulse decreases. The voltage VCEO represents the maximum collector voltage and ICM represents the maximum collector current.

Fully Controlled Semiconductor Devices

(a)

703

Influence of the collector current pulse width t p to the FSOA

logiC

t p4 =10μs A DC ICM current limit

B T po jm we ax rl im it C

t p3 =100μs

tp2 =1ms d

n 2 own akd it bre lim

t p1 =10ms D

voltage limit

(b)

Avalance breakdown voltage VCEO

logvCE

iC

ICM

VBE(off) = 0

VBE(off) < 0

BVCBO

vCE

Figure 10.10 Safe operating areas. (a) Forward bias safe operating area (FBSOA); (b) reverse bias safe operating area.

Example 10.1 The circuit shown below has the following specifications: VCE(sat) ¼ 1.6 V, hfe ¼ 50 and VBE(sat) ¼ 2 V. a) Calculate the minimum value of VB to ensure satisfactory conduction state. b) Calculate the conduction losses. c) If a transient overvoltage occurs and the dc voltage for a short time increases from 100 to 200 V, calculate the power dissipation in the device, assuming that the VCE(sat) has the same value. iC iB 5Ω

VB

VBE

R L = 10Ω

VL = 100V + _

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Power Electronics and Motor Drive Systems

Solution a) When the transistor is conducting, the collector current is given by: iC ¼

VL  VCEðsatÞ 100  1:6 ¼ 9:8 A ¼ 10 RL

The minimum base current required for turning the transistor to the conduction state is given by: iB ¼

iC 9:8 ¼ 196 mA ¼ 50 hfe

Therefore, the base voltage should be VB ¼ iBRB þ VBE(sat) ¼ 0.196  5 þ 2 ¼ 2.98 V. b) The collector power dissipation is Pcollector ¼ iCVCE(sat) ¼ 9.8  1.6 ¼ 15.7 W. The base power dissipation is Pbase ¼ iBVBE(sat) ¼ 0.196  2 ¼ 0.392 W. Therefore, the total internal dissipation is Ptotal ¼ 15.7 þ 0.392 ¼ 16.1 W. c) Assuming that the VCE(sat) has the same value, the following results are obtained: iC ¼

200  1:6 ¼ 19:84 A 10

Pcollector ¼ VCE iC ¼ 1:6  19:84 ¼ 31:74 W

10.2

Power Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET)

The metal-oxide-semiconductor field effect transistors (MOSFETs) are semiconductor switches that can be used for low power conversion applications and high switching frequencies. In contrast with the BJT the MOSFETs are voltage driven and not current driven, and they exhibit high current gain. Fig. 10.11(a) and (b) shows the cross sections and the symbols of an n-channel and p-channel MOSFET. The MOSFET has three terminals which are the gate, the drain and the source. The operation of a p-channel MOSFET is shown in Fig. 10.11(c). If a positive drain-source voltage VDS and a gate-source voltage VGS below the gate-source threshold voltage level VGS(th) is applied, then only a very small cut-off current IDSS will flow between the drain and source terminal (see Fig. 10.11(c)). When a positive voltage, which is above the threshold voltage value is applied to the gate with respect to the source (i.e., VGS > VGS(th)) an electric field is created pointing away from the gate and across the p-region directly under the gate. The electric field causes the positive charges of the p-region to move away from the gate inducing or enhancing an n-region in its place (see Fig. 10.11(d)). As shown in Fig. 10.11(c), during this mode of operation conduction takes place in the path nþ(drain)n(enhanced region)nþ(source). By increasing the gate voltage, the size of the n-channel is increased and, consequently, the current that flows from

Fully Controlled Semiconductor Devices

(a) Drain

705

Oxide Semiconductor

(b)

Drain

Metal

D

D

p

n p

Gate

Gate

G S

n

p- channel FET Source

n-channel FET

(c)

(d) Source

Gate

n+

Drain Metal n+

p-substrate Body VDS

S

p

Source

Oxide

G

n

VGS Gate

Source n+

N

Drain n+

Electric field from gate pushing away holes and allows electrons to pass p-type substrate

Body VDS

N-channel region

Figure 10.11 Cross sections and operation of a MOSFET. (a) n-channel MOSFET; (b) p-channel MOSFET; (c) operation of an n-channel MOSFET in the cut-off mode; (d) operation of an n-channel MOSFET in the conduction mode.

the drain to the source is increased. By decreasing the gate voltage, the size of the n-channel is decreased and, consequently, the current that flows from the drain to the source is decreased. Therefore, the gate voltage controls the drain current iD. The power MOSFET switches compared to bipolar transistors exhibit the following advantages: i) MOSFETs are basically majority carrier devices and, consequently, differ greatly from the bipolar transistors which are minority carrier devices. ii) MOSFETs are voltage-controlled devices in contrast with the bipolar transistors which are current controlled. iii) Since they are majority carrier devices they can operate in high switching frequencies. The bipolar transistors switching frequencies are limited to 30 kHz whereas MOSFETs can operate up to few mega Hertz. iv) When MOSFETs are used in power conversion circuits, their switching times (i.e., rise time and fall times) are much smaller than the respective bipolar transistor. This, results to lower power losses and, consequently, the power converters implemented with MOSFETs exhibit higher efficiency. v) The SOA of the MOSFET is not restricted due to the second breakdown as is with the bipolar transistor. vi) Parallel connection of a number of MOSFET for higher switching currents can be achieved which is not possible with the bipolar transistors. vii) Better temperature stability with respect to bipolar transistor.

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Fig. 10.12(a) shows the iDevDS output characteristics of an n-channel MOSFET where: iD ¼ drain current

vDS ¼ drain to source voltage

vGS ¼ gate to source voltage

The iDevDS output characteristics of a p-channel MOSFET are the same as the n-channel, with the difference that the voltage and current polarities are reversed. Therefore, the iDevDS characteristics of the p-channel MOSFET appear in the third quadrant of the IeV area. For comparison reasons Fig. 10.12(b) shows the iCevCE characteristics of a BJT. Comparing the characteristics of these two semiconductor switches, the following conclusions are obtained: i) The family of the power MOSFET curves is generated by the variations of the gate voltage and not by the variations of base current. For this reason the MOSFET is said to be a voltage semiconductor device whereas the BJT is said to be a current semiconductor device. ii) The curve slope in the saturation region of the transistor is greater than that of the linear region of the MOSFET. That indicates that the conduction resistance RDS(on) of the MOSFET is higher than the corresponding one of the BJT. iii) The curves slope in the active region of the BJT is higher than that of the corresponding region of the MOSFET. That makes the MOSFET a better dc current source.

As can be seen from the output characteristics of Fig. 10.12(a), a MOSFET can operate in any of the following three regions: a) Linear or ohmic region: When vDS  vGS  VGS(th) and vGS > VGS(th), the MOSFET operates in the linear region. In this region the MOSFET behaves as a closed switch and current

(a)

(b)

Figure 10.12 MOSFET and BJT IeV characteristics. (a) n-channel MOSFET iDevDS output characteristics; (b) BJT iCevCE output characteristics.

Fully Controlled Semiconductor Devices

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flows from drain to source. When the MOSFET operates in this region is considered to be in the so-called on-state. b) Cut-off region: When vGS < VGS(th), no conductive channel is present and the MOSFET operates in the cut-off region. In this region the MOSFET behaves as an open switch (i.e., iD ¼ 0). When the MOSFET operates in this region, it is considered to be in the so-called off-state. c) Active region: If vDS  vGS  VGS(th) and vGS > VGS(th), then the MOSFET is in the active region. The MOSFET in this region behaves as an amplifier and for this reason this mode is not used in switching power electronics topologies.

Fig. 10.13 shows the transfer characteristic of a MOSFET. As can be seen from the transfer characteristic, there is a minimum gate-to-source voltage value VGS(th) (voltage gate threshold) which is needed to trigger the MOSFET. The value of VGS(th) is given by the MOSFET manufacturer and usually is between 1 and 3 V. If the gate voltage of a MOSFET is greater than the threshold voltage (i.e., vGS > VGS(th)), then the MOSFET starts conducting and current flows from the drain to the source.

10.2.1 MOSFET Dynamic Switching Characteristics Fig. 10.14 shows the dynamic switching characteristics of a power MOSFET. Fig. 10.14(a) shows the gate signal waveforms under ideal and not ideal conditions, which is applied to the gate of a MOSFET. Fig. 10.14(b) shows the drain current and drain-to-source voltage during turn-on and turn-off transitions, respectively. The switching characteristics are useful to calculate the power losses of the device. The MOSFET switching times depend mainly on its internal parasitic capacitances illustrated in Fig. 10.15. These capacitances can create delay times in the

i D(A)

50

40 30

20 10 0

1

2

3

4 5 VGS(th)

6

Figure 10.13 Transfer characteristic of a typical MOSFET.

4 vGS V

(a)

vGS0

vGS

non − ideal

ideal

90%

0.9VGS vGS

VGS

0.1VGS t

(b)

v DS

VDD

0.9VDD

0.9VDD

iD

IDM 10%

0.1VDD

0.1VDD

tr

t d(on)

tf

VDS−on t d(off )

t c(on)

t

t c(off )

Figure 10.14 MOSFET dynamic switching characteristics. (a) Gate-source voltage vGS waveform; (b) drain current iD and drain-source voltage vDS waveforms.

(a) D

(b) C

CGD

CDS CGS

CDS

G

CGD 0

CGS

(c)

VDS(off )

VDS(on)

S

v DS

3000

Capacitance (pF)

2500 2000

Ciss

1500 1000 500

0

Coss

Crss

20

60 40 v DS (V)

80

Figure 10.15 MOSFET parasitic capacitances. (a) Power MOSFET with parasitic capacitances; (b) variation of characteristics as a function of drain-source voltage vDS; (c) variation of capacitances of a particular MOSFET. CGS, gate-to-source parasitic capacitance; CGD, gate-to-drain parasitic capacitance; CDS, drain-to-source parasitic capacitance; Ciss ¼ CGS þ CGD, input capacitance; Coss ¼ CGD þ CDS, output capacitance; Crss ¼ CGD, reverse transfer capacitance.

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semiconductor transient states and, consequently, decrease its switching capabilities. The MOSFET should posses the capability of quick charging and discharging of these parasitic capacitances during its turn-on and turn-off transitions so that phenomena of transient errors as well as turn-on and turn-off delays not to be present. For that reason the MOSFET gate drive circuit shall behave to the MOSFET as a voltage pulse source with low internal impedance. The voltage vGS must not exceed the value of 20 V, as this may destroy the device. In order for a power MOSFET to be switched into the conduction mode, a steepslope voltage pulse must be applied to its gate, as shown in Fig. 10.14(a) (vGSO waveform). However, due to the driving circuit internal resistance and the internal parasitic capacitance CGS, the nonideal pulse waveform is as shown in Fig. 10.14(a) (see vGS). As shown in Fig. 10.14(a) the nonideal waveform vGS has smaller slope with respect to the ideal vGSO. When voltage vGS reaches the threshold voltage VGS(th), then the voltage vDS starts decreasing while the drain current starts increasing. The time duration between the time instant at which voltage vGS has risen to 10% of its final value and the instant at which voltage vDS has fallen to 90% of its initial value, is called turn-on delay time td(on) (Fig. 10.14(b)). Furthermore, the time duration between the time instants where voltage vDS falls from 90% to 10% of its value is called rise time tr (Fig. 10.14(b)). Therefore, the time required for a MOSFET to switch to its conduction state is given by the following equation: tcðonÞ ¼ tdðonÞ þ tr tr ¼ rise timeðduration for vDS to fall from 0:9VDD to 0:1VDD at turn-onÞ

(10.7)

tf ¼ fall timeðduration for vDS to reach 0:9VDD from 0:1VDD at turn-offÞ where tr z 2:2RG  Ciss

RG ¼ driving circuit internal resistance

(10.8)

As shown in Fig. 10.14(b), the greater part of time ton is the time tr, which must be limited to low values, so that the MOSFET turn-on power losses to be minimized. The time tr can be minimized by employing a driving circuit with low internal resistance and inductor values. At the end of the time interval td(on) the voltage vDS has not reached the value of the conduction voltage (see Fig. 10.16) which is given by: Vcond ¼ IDM RDSðonÞ where IDM ¼ maximum drain current

(10.9)

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Power Electronics and Motor Drive Systems

Source

Gate

Drain metal

n+ Rch

Rch RJFET

n+

p-substrate Body

Figure 10.16 MOSFET conduction mode resistance components.

Moreover, using Fig. 10.16 the conduction resistance of the MOSFET is given by: RDSðonÞ ¼ resistannce during conduction

(10.10)

¼ Rsource þ Rch þ RA þ RJ þ RD þ Rsub þ Rwcml Rsource ¼ source diffusion resistance

Rch ¼ channel resistance

RA ¼ accumulation resistance

RJFET ¼ JFET component resistance

RD ¼ drift region resistance

Rsub ¼ substrate resistance

Rwcml ¼ sum of bond wire resistance Fig. 10.17 shows the variations of RDS(on) with respect to the junction temperature for two different values of drain current.The peak current present during MOSFET turn-on (i.e., at time instant ton), is generated due to the reverse recovery phenomenon

ID = 22 A

2.5 R DS(on) (Ω)

Drain to source resistance

3

2

ID = 11 A

1.5 0.5

−50 −25

25 50 75 100 Tj Junction temperature oC 0

125

Figure 10.17 MOSFET RDS(on) with respect to junction temperature for two different drain current values.

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of the freewheeling diode, many times connected in antiparallel to the MOSFET. In order for a power MOSFET to be switched into the cut-off mode, a zero or instantaneous negative voltage is applied to its gate. The negative voltage is required for the fast discharging of the parasitic capacitances, so that a greater switching frequency to be achieved. As shown in Fig. 10.14, even though the ideal gate voltage pulse vGSO (pulse before the connection of the driving circuit to the MOSFET) has a great slope, the real pulse vGS (pulse after the connection of the driving circuit to the MOSFET) exhibits smaller slope due to the internal parasitic capacitances of the MOSFET. That results in creation of some switching delays during the transition to the cut-off mode (i.e., during turn-off). First of all there is the delay time td(off) that is the time interval between the time instant voltage vGS has fallen to 90% of its initial value and the instant voltage vDS is at 10% of its final value (Fig. 10.14). After the time instant td(off), current iD starts decreasing and after the time interval of tf, which is called fall time, goes to zero. The turn-off time of the MOSFET is given by: tcðoffÞ ¼ tdðoffÞ þ tf

(10.11)

The times td(on), td(off), tr, and tf are given by the MOSFET manufacturer. These times are in the order of some tens of nanoseconds.

10.2.2 MOSFET Power Losses The total power losses of a power MOSFET are given by: Plosses ¼ total average power losses ¼ f s ðWon þ Woff Þ þ Wcond

(10.12)

tr where fs ¼ MOSFET switching frequency; Won ¼ turn-on losses ¼ IDM VDSðonÞ ; 2 tf 2 e Woff ¼ turn-off losses ¼ IDM VDD ; Wcond ¼ conduction losses ¼ IDM RDSðonÞ ; koff tr ¼ drain current rise time; tf ¼ drain current fall time. According to the switching schemes shown in Fig. 10.18, the values of the coefficient koff have as follows: i) koff ¼ 2 (in cases where vDS is applied to the MOSFET in the whole time interval of the drain current rise (Fig. 10.18(a)). ii) koff ¼ 6 (in cases where vDS falls with the same rate as with the rise of the drain current. It means that vDS and iD have the same slopes (Fig. 10.18(b)). 2VDD (in cases where vDS decreases very fast at the beginning of the turn-on iii) koff ¼ IDM RDSðonÞ state to the value of Vcond).

The above cases of koff coefficient values are illustrated in Fig. 10.18. Fig. 10.19 shows a measurement circuit of the MOSFET switching times where DUT is the device under test. Fig. 10.20 shows the drain current iD variation curve of a particular MOSFET with respect to the case temperature. Fig. 10.21 shows the power consumption variation curve of a particular MOSFET with respect to the case temperature.

(a)

(b)

v DS ,i D

v DS ,i D

VDD

VDD

I DM

I DM

VDS(on)

VDS(on)

t

tr

t

tr

(c)

v DS ,i D VDD

I DM VDS(on) t

tr

Figure 10.18 Three typical cases of vDS voltage and iD current in MOSFET turn-on phase. (a) Voltage vDS is applied to the MOSFET in the whole time interval where current increases; (b) voltage vDS falls with the same rise rate as drain current iD; (c) voltage vDS decreases very fast at the beginning of the turn-on state to the value of Vcond. VDD DUT=Device under test

RL

vout

Pulse generator

vin

Zo 20V

DUT

15Ω

Zo

15Ω

Figure 10.19 Measurement circuit of the MOSFET switching times. 40

i D (A)

30

20

10

50

150

100 o

Case temperature (Tcase in C)

Figure 10.20 Current iD variation curve in relation to the metal case temperature of a particular MOSFET.

Fully Controlled Semiconductor Devices

713

Power consumption P (W)

500 400

300 200

100

0

150 100 50 Case temperature (Tcase in oC)

Figure 10.21 Power consumption variation curve of a particular MOSFET with respect to the case temperature.

10.2.3 MOSFET Safe Operating Area Fig. 10.22 shows the FBSOA of a typical power MOSFET. This area is defined by the maximum drain-to-source voltage VDSM, the maximum conduction current IDM, and the constant power dissipation lines for various pulse durations. In this figure, the set of curves shows a dc line and four single-pulse operating lines, 10, 1 ms, 100, and 10 ms. The top of each line is truncated to limit the maximum drain current and is bounded by a positive slope line defined by the Rds(on) of the device. The right hand side of each line is terminated at the rated drain-to-source voltage limit (VDSM). Each line has a negative slope and is determined by the maximum allowed power dissipation of the device Plosses. Finally, it shall be noticed logi D

Area limited by R DS(on)

Power limits

I DM

t p4 =10μs t p3 =100μs it im rl we po

t limi ent curr

t p2 =1ms

DC

t p1 =10ms drain current pulse duration

Tj = 175 C TA = 25o single pulse o

logv DS VDSM voltage limit

Figure 10.22 Safe operating area of a typical MOSFET.

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Power Electronics and Motor Drive Systems

that regarding the SOA, there is no difference between forward and reverse bias states.

10.2.4

MOSFET Gate Driving Circuits

A gate drive circuit is an integrated circuit that accepts a low power input from a controller IC and produces the appropriate voltage and current for a power semiconductor switch. Fig. 10.23 shows the printed circuit board of two gate drive circuits which are driving the two MOSFETS of a three-phase inverter leg. A gate driver sometimes includes also the protection circuit of the semiconductor switch. Gate drivers may be implemented as dedicated ICs, discrete transistors, or transformers. They can also be integrated within a controller IC. As it was mentioned before, the MOSFET switching speed depends on the gate current that charges the parasitic capacitances of the semiconductor device. Therefore, the engineer has the capability to adjust the switching times (i.e., toff and ton) of a MOSFET through the design of the driving circuits. Figs. 10.24 and 10.25 show some examples of gate drive circuits that can be used to drive power MOSFETs. The gate drive circuits of Fig. 10.24 are applied directly to the MOSFET without any ohmic isolation. However, there are applications where the gate drive circuit must exhibit ohmic or galvanic isolation in order to prevent short-circuit problems within a power converter. Fig. 10.25 shows three different gate drive circuits that provide ohmic isolation between the control circuit of a converter and the power semiconductor devices. As can be seen from Fig. 10.25, the ohmic isolation is achieved using an opto-isolator or a transformer. The opto-isolator is used in applications where the duty cycle of the gating pulses is over 50%. Since the MOSFET is a voltage device, it can be driven easier and with a lower cost than a BJT which is a current device.

Figure 10.23 Gate drive circuit printed circuit board driving two MOSFET.

1 kΩ

RL Gating pulses from control circuit

RL

Main semiconductor switch

Gating pulses from control circuit

100 Ω

715

+12 V 22 Ω

1 kΩ

Main semiconductor switch

Fully Controlled Semiconductor Devices

Figure 10.24 MOSFET driving circuits without ohmic isolation.

Gating pulses from control circuit

Gating pulses from control circuit

(a) RL Main semiconductor switch 22 Ω

+12V

1 kΩ

RL Main semiconductor switch 2.2 μF 22 Ω

1 kΩ

150 Ω

(b)

+12V 10K

Diode

22K

Opto-isolator

1K

120

Gating pulses from control circuit

560pF HCPL 2200

IC1 (1/4)

IC1 (1/4) 56K

Main semiconductor switch SGSP477

IC1 (1/4)

BSS100 IC1 (1/4)

0V

Figure 10.25 MOSFET driving circuits with ohmic isolation. (a) Transformer ohmic isolation; (b) opto-isolation.

Fig. 10.26 shows the gate drive circuits for one phase leg of a three-phase inverter. As shown in Fig. 10.26 the gate drive circuits provide the following: a) Ohmic isolation between the gating circuits and the control circuit of the inverter. b) Since the two gating circuits are using two different power supplies there is no possibility to create short-circuit in the inverter power stage and, consequently, the point a to coincide with point o (i.e., short-circuit).

716

Power Electronics and Motor Drive Systems

+ Upper switch

Upper switch Gating signal

Ohmic isolation

_

Control circuit Power supply1 With ohmic isolation

a

+ Lower switch

Lower switch Gating signal

Ohmic isolation

_ Power supply 2 With ohmic isolation

o

Figure 10.26 MOSFET driving circuits with ohmic isolation for an inverter phase leg.

10.2.5

Converters Implementation Using MOSFETs

Fig. 10.27 shows different power electronics topologies implemented using power MOSFETs. Fig. 10.27(a) shows a half-bridge dcedc converter, where the main semiconductor devices are MOSFETs. Fig. 10.27(b) shows a dcedc chopper used to drive a dc motor. Finally, Fig. 10.27(c) shows a three-phase inverter used to drive an ac motor.

Fully Controlled Semiconductor Devices

(a)

717

+ Vin 2

Vin

+ -

O

Vin 2

Load + -

-

(b) + + DC MOTOR Vin

-

ac source

(c) AC MOTOR + -

Figure 10.27 Various MOSFET power circuits. (a) Half-bridge inverter; (b) buck converter for dc motor control; (c) three-phase inverter for ac motor control.

10.3

Insulated Gate Bipolar Transistor (IGBT)

The bipolar transistor was the only power transistor until the MOSFET came along in the 1970s. The bipolar transistor requires a high base current to turn-on and has relatively slow turn-off characteristics. In addition, the lowest attainable conduction-state voltage or conduction loss is governed by the collectoreemitter saturation voltage VCE(SAT). However, the MOSFET is a voltage-controlled semiconductor device and not current controlled as the transistor. MOSFETs have a positive temperature coefficient, stopping thermal runaway. The conduction-state resistance has no theoretical limit and, consequently, conduction-state losses can be by far lower. The main disadvantage of the MOSFETs is that they cannot handle high currents and voltages. Then in the 1980s the insulated gate bipolar transistor (IGBT) came along which is a combination between a transistor and a MOSFET and, consequently, includes the advantages of high current handling capability of a transistor and the voltage controllability of a MOSFET. Summarizing the main advantages and disadvantages of an IGBT when compared to MOSFETs and bipolar transistors are the following: Advantages 1) Has much smaller on-state resistance RCE and, consequently, the IcRCE drop across the bipolar structure is much lower. Therefore, the conduction losses of the device are

718

Power Electronics and Motor Drive Systems

decreased. Therefore, it is possible to replace the MOSFET with an IGBT and improve the efficiency and/or reduce the cost. 2) Low driving power and a simple drive circuit due to the input MOS gate structure. It can be easily controlled as compared to current controlled devices (thyristor, BJT) in high voltage and high current applications. 3) Wide SOA. It has superior current conduction capability compared to BJT. Disadvantages 1) Switching speed is inferior to that of a power MOSFET and superior to that of a BJT. The collector current tailing due to the minority carrier causes the turn-off speed to be slow. 2) There is a possibility of latch-up due to the internal pnpn thyristor structure.

Fig. 10.28(a) shows the symbol of the IGBT, Fig. 10.28(b) shows its simplified operation equivalent circuit, and Fig. 10.28(c) shows the crystal cross section of an IGBT. An n-channel IGBT is basically an n-channel power MOSFET constructed on a p-type substrate, as illustrated by the generic IGBT cross section in Fig. 10.28(c). Consequently, operation of an IGBT is very similar to a power MOSFET. A positive voltage applied across the emitter and gate terminals causes electrons to be drawn toward the gate terminal in the body region (Fig. 10.29). If the gate-emitter voltage is at or above what is called the threshold voltage, enough electrons are drawn toward the

(a)

(b) Collector

C

C PNP

iC

CCE NPN

vCE

G

CGC Rb

CGE

vGE Emitter

E

Body region resistance

Gate i G G

E

(c)

IGBT Gate Metal IGBT Emitter

SiO 2

J1 J2

SiO 2

n+ n+ Bipolar collector p Bipolar base drift region Buffer layer Bipolar Bipolar emitter emitter

J3 Parasitic thyristor

n-

MOSFET source

n+ p+

IGBT collector

Figure 10.28 IGBT semiconductor device. (a) Symbol; (b) simplified equivalent circuit; (c) crystal cross-section structure.

Fully Controlled Semiconductor Devices

719

IGBT Gate IGBT Emitter - n+

n+

-

p

Drift region nn+ emitter + + + + Bipolar + + p+ + + + + + +

IGBT collector

Figure 10.29 Hole and electron flow in the IGBT during conduction state.

gate to form a conductive channel across the body region, allowing current to flow from the collector to the emitter. (To be precise, it allows electrons to flow from the emitter to the collector.) This flow of electrons draws positive ions (i.e., holes), from the p-type substrate into the drift region toward the emitter. Fig. 10.30 shows a gate drive circuit of an IGBT and the resulted gating current. The gate drive circuit uses two transistors, an npn for its turn-on and an pnp for its turn-off. When a positive voltage pulse is applied to the gate drive circuit, the npn transistor turns on supplying through the resistance Ron the positive voltage Vs to the IGBT gate, which results to its turn-on. The voltage Vs is between 13 and 15 V. When a zero or a negative voltage pulse is applied to the IGBT gate drive circuit, the pnp transistor

(a)

Vs

Freewheeling diode

npn

Cs

R on

From control circuit

C

Gating pulses

R off pnp

iG

Gate 0V

Auxiliary Emitter

E

(b) iG

R on1

Ron1 < Ron2 Roff1 < Roff2

Turn-on Current R on2

R off1

t R off 2 Turn-off Current

Figure 10.30 IGBT control. (a) Driving circuit; (b) gate current iG waveforms.

720

Power Electronics and Motor Drive Systems

turns on supplying through the resistance Roff a zero voltage to the IGBT gate, which results to the IGBT turn-off and the discharging of the parasitic capacitances through the pnp transistor. The IGBT parasitic capacitances (Fig. 10.28(b)) must be discharged during the device turn-off transition, to prevent switching speed problems. The turn-on and turn-off transition times of the IGBT are adjusted by the values of Ron and Roff resistances, respectively (Fig. 10.30(a)). Fig. 10.30(b) shows the impact of these resistances on the gate current. An electrolytic capacitor Cs ¼ 4.7 mF is connected across the driving circuit voltage source Vs terminals, used for voltage Vs ripple reduction and a ceramic capacitor of 0.22 mF, connected in parallel to the electrolytic one, which is used for voltage Vs high-frequency ripple reduction. The cable between the driving circuit and the IGBT gate must be as small as possible (10 cm), to prevent any undesirable self-inductance, capacitance, and resistance, which would change the gate pulse shape. If the cable is thicker that 3 cm, then the two wires the cable has, must be twisted to each other, or a flat cable should be used so that the cable to exhibit the lower possible self-inductance, capacitance, and resistance. The voltage applied to the IGBT gate must not overcome the value of 20 V. The antiparallel diodes of Fig. 10.30(a) limit the IGBT gate voltage in case of a feedback between IGBT collector and gate through internal capacitance CCG (Fig. 10.28(b)). Due to the collector feedback toward the gate through CCG capacitance, IGBT can go to conduction mode in case the slope dv/dt takes high values.

10.3.1

IGBT Turn-On Characteristics

Fig. 10.31 shows the output iCvCE characteristics of a typical IGBT semiconductor switch. As can be seen from Fig. 10.31, an IGBT can operate in any of the following three regions: a) Active region: If vGE > VGE(th) and vCE > VGE(sat), then the IGBT operates in the active region where the on resistance has constant value. The switching power electronics topologies are not operating in this region. Increasing vGE

Saturation region (IGBT is on) Active region vGE7

Avalanche breakdown

Cons tant r esista nce

iC

vGE6 vGE5 vGE4 vGE3 vGE2 vGE1

vGE < VGE(th) vCE(SAT) = 5V

0.75 V

Figure 10.31 IGBT iCLvCE characteristics.

Cut-off region BV CE (IGBT is off)

vCE

Fully Controlled Semiconductor Devices

721

b) Cut-off region: If vGE < VGE(th), then the IGBT operates in the cut-off region and iC ¼ 0. In this region the IGBT behaves as an open switch. When the IGBT operates in this region, it is considered to be in the off-state. c) Saturation region: If vGE > VGE(th) and vCE  vCE(sat), then the IGBT operates in the saturation region. In this region the IGBT behaves as a closed switch. When the IGBT operates in this region, it is considered to be in the on-state.

As can be seen from Fig. 10.31, the iCevCE characteristics of an IGBT are qualitatively similar to those of a BJT except the controlling parameter is not the base current but the gateeemitter voltage. The IGBT is used only as a switch in power electronics topologies and, consequently, operates in the cut-off mode or in the saturation mode. Figs. 10.32 and 10.33 present the linear interpolation of the output characteristic and the transfer characteristic of an IGBT, respectively. A linear approximation can be used to relate iC to VCE(on). Finally, Fig. 10.34 shows the SOA of a typical IGBT.

R CE(on) =

ΔVCE ΔIC

ΔΙc iC (A)

ΔVCE

vCE (V)

VTO

Figure 10.32 Linear interpolation of the output characteristic at Tj [ 1508C.

vGE1

vGE2 vGE3

iC (A)

VGE3 >VGE2 > VGE1

5

vGE(th)

Figure 10.33 Transfer characteristic of a typical IGBT.

vGE (V)

722

Power Electronics and Motor Drive Systems

Influence of the collector current pulse width t p to the FSOA

logi C

ICM

t p5 =10μs

B IC A Current limit

t p4 =100μs po

Tj =150o C Tcase = 25o C

tp3 =10ms w

er lim it

t p2 =1ms

t p1 =100ms

DC

Voltage limit

C

D VCES

logvCE

Figure 10.34 Safe operating area of a typical IGBT. FSOA, forward bias safe operating area.

500

Tj =125 oC

Tj =25 oC

i F (A)

400 300

200 100

0

1

2 v F (V)

3

4

Figure 10.35 IGBT freewheeling diode forward bias characteristic for two different junction temperatures.

10.3.2

IGBT Freewheeling Diode Forward Bias Characteristic

As has been stated before, most of IGBTs incorporate an antiparallel diode called freewheeling diode, which provides current bidirectionality. Fig. 10.35 shows the forward bias characteristic of the freewheeling diode. As shown in Fig. 10.35 the threshold voltage value decreases when the diode junction temperature increases.

10.3.3

IGBT Dynamic Switching Characteristics

In BJTs the switching times depend on the base and collector current waveforms. For an IGBT these times depend on the gateeemitter voltage and the collector current.

Fully Controlled Semiconductor Devices

723

(a) vGE 0.9VGE VGE 0.1VGE 0

(b)

t

ICM

vCE

0.9IC

0.1IC 0

VCEM

iC

IC

Tailing iC

vCE(on)

tr

t d(on)

tf

t d(off ) t c(on)

t

t c(off )

Figure 10.36 Waveforms of IGBT dynamic switching characteristics. (a) Gateeemitter voltage (no need to be negative); (b) collectoreemitter voltage, vCE, and collector current, iC.

Fig. 10.36 shows the waveforms of an IGBT which present its dynamic switching behavior. These waveforms are presenting the switching times and the peak voltage and current values which are needed for the power losses and ratings calculations of an IGBT. Due to the fact that the waveforms of the dynamic behavior depend on the conditions of power and driving circuits, the values given in the manufacturer specifications can be used for general guidance. Real values of IGBT dynamic behavior are extracted only with the implementation of driving and power circuits by obtaining real experimental measurements. The maximum collector current value, ICM (Fig. 10.36(b)), created in turn-on transition mode is a result of the recovered charge of the freewheeling diode, antiparallel connected to the IGBT. The maximum collectoreemitter voltage, VCEM, created in turn-off transition is a result of the power circuit parasitic self-inductances. Voltage, VCEM, value is given by the following equation: VCEM ¼ ð Lstray ÞðdiC =dtÞ

(10.13)

where Lstray ¼ parasitic self-inductance of semiconductor device between its connection contacts; iC ¼ collector current. From Fig. 10.36, the following definitions are given: td(on) ¼ turn-on delay time; td(off) ¼ turn-off delay time; tr ¼ collector current rise time (duration for iC to reach 09IC from 0.1IC at turn-on);

724

Power Electronics and Motor Drive Systems

tf ¼ collector current fall time (duration for iC to fall from 09IC to 0.1IC at turn-off); tc(on) ¼ turn-on transition time of an IGBT (tc(on) ¼ tr þ td(on)); tc(off) ¼ turn-off transition time of an IGBT (tc(off) ¼ tf þ td(off)).

10.4

Gate Turn-Off Thyristor (GTO)

The gate turn-off thyristor (GTO) is a type of thyristor that turns on with the same way as a conventional thyristor but in contrast turns off by applying a negative voltage between the gate and the cathode (i.e., negative gate current ig). The negative gate current is dependent to the current to be turned off. The conventional thyristor is naturally commutated and the GTO is forced commutated. Fig. 10.37(a) shows all the possible symbols of a GTO, Fig. 10.37(b) shows its cross section and Fig. 10.37(c) shows its equivalent operation circuit. Like a thyristor, a GTO is also a four layer three junction penepen device with the outside p layer providing the anode connection, and the outside n layer providing the cathode connection. To attain high emitter efficiency, the cathode layer is highly doped to give an n þ region. This has the drawback that it renders the junction nearest to the cathode (normally referred to as J3) with a low breakdown voltagedtypically 20e40 V. The power applications ranging from 3 to 10 MW compose the field of GTO use as semiconductor switch. Its switching speed reaches the value of 10 kHz. The GTO is

(a)

A

Anode A

Gate G

G

Cathode K

A

(b)

A

G K

K

(c)

metal p1

p>>n

A iA

J1

T1

Anode junction

n1

iC2

n J2 p>>n n>>p

p2

iC1 ig

J3

n2

G

K G

T2 iK

K

Figure 10.37 GTO. (a) Possible symbols; (b) crystal cross-section structure; (c) equivalent operation circuit.

Fully Controlled Semiconductor Devices

725

able to maintain a very small voltage drop across its terminals during conduction mode, a fact that allows the flow of high-rated currents, whereas a short duration current pulse is enough switch it into the conduction mode. On the other side, GTO has large commutation times and during these commutations exhibits high switching losses, a fact that confines its switching frequency to some hundreds of Hz. Moreover, the GTO is extremely sensitive to abrupt current changes during turn-on commutation and abrupt voltage changes during turn-off commutation. This sensitivity imposes the usage of protection circuits (snubbers), to limit the current and voltage rate of change (di/dt, dv/dt). The GTO switches go to conduction mode when a positive voltage is applied across the gate and cathode terminals, generating in this way a positive turn-on current into the gate. The GTO switches from conduction mode to cut-off mode by applying a negative voltage across its gate and cathode terminals. At this point, it is important to note that the negative current generated in its gate due to negative voltage application is that which commands its turn-off. The iAevAK output characteristic of a typical GTO is shown in Fig. 10.38. This characteristic in the first quadrant is very similar to that of a thyristor. However, the latching current of a GTO is considerably higher than a thyristor of similar rating. The forward leakage current is also considerably higher. In fact, if the gate current is not sufficient to turn-on a GTO it operates as a high-voltage low gain transistor with considerable anode current. Summarizing, the advantage and disadvantages of a GTO when compared to the conventional thyristor are the following: Advantages 1) Elimination of commutating components exhibiting higher power density (i.e., W/cm3) and lower cost.

A iA

+

v AK

iA

Conduction Region

iG

G

K

iG3 > iG2 > iG1

Latching current IL Holding current IH

Critical reverse-blocking voltage Reverse-blocking region

iG3

iG2

iG1

Forward-blocking region

iG = 0 vA

Critical forward-blocking voltage

Figure 10.38 GTO iAevAK characteristic (same as conventional thyristor).

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Power Electronics and Motor Drive Systems

2) Reduction in acoustic and electromagnetic noise due to the elimination of commutation chokes. 3) Faster turn-off permitting high switching frequency. 4) Lower switching losses. 5) Higher di/dt rating during turn-on. Disadvantages 1) Higher conduction voltage drop. 2) Higher gating current. 3) Higher latching and holding currents. 4) Gate drive circuits exhibit higher power losses. 5) Its reverse voltage blocking capability is lower than its forward-blocking capability.

The GTO operation can be explained using the equivalent circuit of Fig. 10.37(c), which is the same equivalent circuit with that of a conventional thyristor. As in case of a thyristor, the GTO can be triggered to the conduction-state by applying a relatively small voltage pulse to its gate terminal which creates a positive gate current iG. However, to be switched-off due to its low turn-off current gain (about 1/3 to 1/5 of anode current) requires a very high negative gate current pulse with width of the order of some ms. For example, a GTO of 2500 V and anode current of iA ¼ 600 A requires a current pulse of 150 A peak. Fig. 10.39 shows an example of a gate current pulse which is needed to turn on and turn off a GTO. As shown in Fig. 10.39 the gate signal consists of three parts. The first part (1) is the gate current required at the beginning of the GTO turn-on process, where the gate requires an amplified current for a short time, so that the GTO exhibits small turn-on commutation times and, consequently, low power losses. The second part (2) is the current applied to the GTO to remain in iG (A) 1 0.8 0.6

0.2 0

t

-1

on − pulse

-2

off − pulse

-3 -4 -5 -6 -7

1

2

iG (A)

Figure 10.39 Typical gating signal of a GTO.

3

Fully Controlled Semiconductor Devices

727

conduction. Parts (1) and (2) compose the turn-on GTO gating pulse. The third part (3) is a negative current pulse and, consequently, at the beginning of this pulse the turn-off process of the GTO starts. The gating signals are created by the control circuit and for interfacing reasons are feed to the GTOs through the driving circuits. The control circuit consists of integrated circuits, microprocessors, digital signal processors, and analog circuits. If the current gain of transistor T2 (Fig. 10.37(c)) is designed to be approximately equal to unity and if the gate negative current is able to divert the collector current of transistor T1, iC1, away from the gate, then the GTO will be turned off. Fig. 10.40 shows a very simple GTO driving circuit, which will be used to explain how to generate the appropriate current pulses to turn on and turn off a GTO. The GTO turn-on pulses are applied to transistor T1 through opto-coupler and whereas the GTO turn-off pulses are applied to transistor T2 through a transformer isolation. The driving circuit of Fig. 10.40 consists of three parts: the turn-off circuit, the turn-on circuit, and the power supply circuit. When, the GTO is in the cut-off mode, it is necessary to apply

Turn-on pulse

Turn-on circuit

GTO T3

iG

Turn-on pulse From control circuit vgK

Opto-coupler

T1 + Vcc Power supply with 0 ohmic isolation −V cc

Turn-off pulse Vin

C

Turn-off pulse From control circuit

T2

Turn-off circuit Figure 10.40 Example of a GTO driving circuit.

728

Power Electronics and Motor Drive Systems

to the gate continuously a negative voltage, so that a false turn-on to be avoided due to dv/dt. The transformer and opto-coupler are needed to provide ohmic isolation between the control circuit and the power circuit of a converter, thus avoiding various grounding problems. When a positive pulse is applied to the base of transistor T1, collector current, ic1, is created resulting to the turn-on of transistor T3. During the conduction of T3 the power supply voltage þVcc is applied to the gate of the GTO creating positive gating current and, consequently, the GTO turns on. When at a certain time a positive voltage pulse is applied to transistor T2 the transistor turns on and along with capacitor C (which is charged to voltage Vin) and the self-inductance of the transformer primary winding, generates a current pulse. This current pulse, although it is positive in the transformer primary winding, is negative in the secondary winding (i.e., the current in the secondary winding flows toward the anode of diodes), which results in the GTO gate being supplied by negative current forcing the GTO to switch to cut-off mode. The diode, connected in series with input voltage Vin, is required to block the discharging of capacitor C toward the source side. The diodes, connected in series, as well as transistor T3, are required to prevent the interaction between the turn-on and turn-off circuits.

10.4.1

GTO Dynamic Switching Behavior

The GTO switching characteristics are a little different than those of a conventional thyristor and for that reason some additional explanations shall be given. The GTO turn-on switching characteristics are the same with those of a conventional thyristor, but their turn-off characteristics differ considerably. To understand the GTO turn-off dynamic behavior the circuit of Fig. 10.41 will be used. The power circuit is a dcedc converter (chopper), where the GTO is utilized as a semiconductor switch that turns on and off in such a way, so as to chop input voltage Vin, applying it across the terminals of an ReL load. It means that by GTO turning on and off a pulsed voltage across the

Rs

Protection circuit (Snubber)

Cs Ds

Ls

G

R

Gating pulses

L

LL

Figure 10.41 GTO dcedc converter (chopper) power circuit.

Freewheeling diode

ig

GTO

LOAD

Vin

LL ,Ls Wiring inductances

Fully Controlled Semiconductor Devices

729

load terminals is generated. A protection circuit (snubber) is connected to GTO terminals, consisting of Ds, Rs, and Cs elements. This circuit provides protection to GTO switch against possible overvoltages across anode and cathode terminals. Across the load terminals there is a freewheeling diode required for the inductor current flow when the GTO turns off. The LL and LS are the parasitic inductances of the load and the protection circuits, respectively. These inductances are caused by the power circuit wiring and connections. The snubber circuit decreases the voltage rate, dv/dt, across the GTO terminals (when switched to turn-off state) but improves its turn-off switching characteristics. The snubber capacitance, Cs, is charged to the input voltage Vin before the GTO turns on. The capacitor Cs is charged through the input source, Vin, and the circuit path ReLeLLeLseDseCs. When the GTO is in the conduction-state, capacitance Cs is discharged through the snubber resistance Rs and the GTO, consuming most of its power on resistance Rs. When the GTO turns off, the capacitance is charged again to the input voltage through the circuit path ReLe LLeLseDseCs with a resonant current (due to the circuit capacitance and selfinductance) which results to a decreased dv/dt value across the GTO terminals. The electric power consumed by the protection circuit is given approximately by: 1 Ps z Cs V2in f s 2

(10.14)

where fs is the GTO switching frequency. Fig. 10.42 presents the dynamic switching characteristics of a GTO. The GTO turnoff characteristics are different than those of a conventional thyristor (see Fig. 3.6). As shown in Fig. 10.42, when a negative gate current is applied to GTO then the anode current iA starts decreasing after a delay time, ts (storage time). Hereafter, the anode current requires a certain time interval tf (fall time) to drop from 0.9 to 0.1IA. However, during the turn-off transition of the GTO, as its current falls and its voltage rises, the anode current tends to leak through the protection circuit and, consequently, to create, through parasitic inductance, Ls, a voltage peak (VAK(peak)), shown in Fig. 10.42. A high-voltage peak is too dangerous, because it may cause local overheating inside the semiconductor device, which will be catastrophic (second breakdown). For this reason, care must always be taken to reduce the parasitic inductance, Ls, of the protection circuit. After the voltage peak VAK(peak), the GTO anode voltage rises, creating another voltage peak (VAK(max), Fig. 10.42) which is a result of the resonant circuit LseCs of the protection circuit, ending afterward to source voltage, Vin. During the overvoltage period, the anode current iA, as shown in Fig. 10.42, does not reach the zero value, but creates a tail Itail, which lasts for a time interval ttail. The tail time can be reduced by decreasing the value of protection circuit capacitor Cs. Reducing time ttail, the turn-off switching power losses of the GTO are also reduced and, consequently, the converter exhibits higher power efficiency. The selection of Cs must be done after a compromise between the tail time interval and the protection circuit losses. Increasing the gate current rise rate, the turn-off transition time of the GTO is decreased. Regarding Fig. 10.42, the GTO turn-off transition time is given by: toff ¼ ts þ tf þ ttail.

730

Power Electronics and Motor Drive Systems

VAK(max)

v AK 0.9Vin Anode to cathode Voltage

Vin

0.1Vin

tr

td t gt

iA

VAK(spike) dv / dt VT

Vin t

t on

di / dt

0.9I A

Anode Current IA

0.1IA

I tail

ts tf t tail t gq

vGK Gate to cathode Voltage

0.01 IA

VGR

t

t

iG

Gate Current

0.1Ip

Ip

0.1IGQ

t

IGQ

Figure 10.42 Waveforms of GTO dynamic switching behavior.

10.5

MOS-Controlled Thyristor (MCT)

The MOS controlled thyristor (MCT) is another type of thyristor that combines the high power operation of a thyristor and the high switching frequency of a MOSFET. The MCT, when is compared to thyristor and GTO devices, has the following advantages: 1) 2) 3) 4) 5) 6)

Low forward voltage drop during conduction Fast turn-on and turn-off times Low switching losses Low reverse voltage blocking capability High gate input impedance High di/dt and dv/dt capability

Based on the polarity of the device, the MCTs can be classified into two categories: n-type MCTs and p-type MCTs. The n-MCT has a p-type turn-off MOSFET and a lower npn transistor, while both the turn-off MOSFET and the lower transistor of the p-MCT are n-type. Fig. 10.43(a) and (b) are showing the symbols of the p-MCT and n-MCT, respectively. Most of the MCT characteristics can be understood easily by referring to the equivalent circuit of p-MCT which is shown in Fig. 10.43(c). Moreover, Fig. 10.43(c) shows the cross-section structure of n-channel MCT. As shown in Fig. 10.43(c) the two MOSFETs S3 and S4 provide the high switching frequencies capability, while the thyristor, comprising of transistors S1 and S2, provides high power

Fully Controlled Semiconductor Devices

(a) Gate-return GR

731

(b)

Anode A

Anode A n-MCT

G Gate

Gate G

p-MCT

GR Gate-return K Cathode

K Cathode

Anode

(c)

(d)

Anode

Gate

iA off

n-channel off-FET

+14 V on -7 V S4 Gate

n-type MOSFET for turn-off

S1

S3 p-type MOSFET for turn-on

oxide

oxide n+

p

n+

p+

p

p-channel on-FET

n

S2 p-

Cathode

Thyristor equivalent

n+ Metal

Cathode

Figure 10.43 MCT. (a) n-channel MCT; (b) p-channel MCT; (c) p-MCT operation equivalent circuit; (d) crystal cross section structure.

operation capability. It is very important to note that the thyristor inside the device has low turn-on voltage and, consequently, low turn-on power losses are achieved. When the MCT is in the forward-blocking state, it can be turned on by applying a negative voltage pulse to the gate with respect to the anode. The negative pulse turns on the p-type MOSFET switch S3 whose drain current flows through the baseeemitter junction of S2 and, consequently, turning it on. Next, the drain current of S2 is supplied to the base of transistor S1, forcing S1 into conduction mode and, consequently, current starts flowing from the anode to the cathode of the MCT. The MCT latches to the conduction mode as it was with the conventional thyristor and will remain to this state until a turn-off pulse is applied to its gate. In order for the MCT to be turned off, a positive voltage pulse (of about þ10 V) is applied to the gate with respect to anode. The positive pulse turns on the n-type MOSFET, thereby diverting the base current of S2 away to the anode of the MCT and breaking the latching action of the SCR. This stops the regenerative feedback within the SCR and turns the MCT off. The iAevAK characteristics of the MCT are similar to those of thyristors and GTOs and are shown in Fig. 10.44. The dynamic switching characteristics of the MCT switch are shown in Fig. 10.45.

732

Power Electronics and Motor Drive Systems

iA

turn − off

turn − on

vAK

Figure 10.44 MCT iAevAK characteristics.

vGA +5V

VGA1 0

VGA2

-5V

v AK

t

dv AK dt

di A dt

0.9Vin

iA

0.9IT

Vin

IT

VTM

0.1Vin

0

t d(on)

t d(off)

tr

0.1IT t

t c(off)

t c(on) t d(on) = turn-on delay t r = current rise time t c(on) = t d(on) + t r

tf

t d(off) = turn-off delay t f = current fall time t c(off) = t d(off) + t f

VTM = on-state voltage

Figure 10.45 MCT dynamic switching characteristics.

Fig. 10.46 shows a driving circuit for MCT devices. As shown in Fig. 10.46 the comparator OA2 generates a variable pulse width modulated (PWM) waveform by comparing the carrier triangular signal and a variable reference voltage (Vref). The driving circuit waveforms are shown in Fig. 10.47. The comparator OA1 is used as a Schmitt trigger with the same output as the OA2. The reference voltage is adjusted through the potentiometer R1. The operational amplifier OA3 is a summer, which is driving the two bipolar transistors Q1 and Q2. Transistor Q1 generates the positive gating pulses and transistor Q2 generates the negative pulses. Finally, Fig. 10.48 shows the power circuit of a dc chopper that uses MCT switch.

Fully Controlled Semiconductor Devices

733

+10V

+10V RD

R2 Vref

-10V

Triangle Wave Generator ICL8083 CCPD

+10V

OA1 +

R8

vo2 R6

R5 +10V

R3 R4

Q1 TIP29C

+10V

-10V

R1

+10V

OA3 +

vo1 R7 R9

vo Q2 TIP30C

-10V

OA2 +

+10V

-10V

-10V -10V

Figure 10.46 Driving circuit for an MCT switch.

PWM

vREF t

vO2 ton

t

toff

vO1 t tp

vO

t

Figure 10.47 Key waveforms of the driving circuit shown in Fig. 10.46.

LOAD RL

LL

K DF Rs G Cs Gating pulses

A

-10 RG

Vin

Protection circuit (snubber)

Figure 10.48 Power circuit of a dc chopper that utilizes MCT switch.

RGA

GAT

734

10.6

Power Electronics and Motor Drive Systems

Gate Commutated Thyristor (GCT) and Integrated Gate Commutated Thyristor (IGCT)

The gate commutated thyristor (GCT) is a new thyristor device, which is based on the GTO structure. When a GTO changes from conduction to blocking state (turn-off transition), it goes through an indeterminate state where it is neither a thyristor nor a transistor. This state is sometimes referred to as the GTO mode. This mode requires snubber circuits to reduce the rate at which voltage is reapplied to the circuit. The GCT is a device that does not have the GTO mode and, consequently, there is no need for snubber circuits. The idea behind the GCT is to commutate the entire cathode current to the gate at turn-off. By doing this a smooth transition from thyristor (latching operation) to transistor operation can be achieved. The GCT is a gate-controlled turnoff switch like a transistor but conducts like a thyristor with the lowest conduction losses. A GCT can be turned on and turned off from its gate as a GTO but with lower conduction losses and higher dv/dt ratings voltage. Since the GCT can withstand high dv/dt ratings there is no necessity for snubber protection circuits for most applications. Fig. 10.49(a) shows the symbol of a GCT. The operation of GCTs require a very low inductive and low resistive connection between the GCT device and the gate drive unit, the GCT housing is directly connected to the gate drive unit (Fig. 10.49(b)), resulting in an integrated gate commutated thyristor (IGCT). This design requires close attention to creepage distances and thermal stressing of the gate drive unit. In addition, the gate drive of IGCTs is usually much larger than an IGBT driver and consumes considerably more power. The goal of the GCT is to reduce the cost and complexity of the gate drive and snubbers required in GTO applications. The idea behind the GCT is to commutate the entire cathode current to the gate at turn-off. By doing this a smooth transition from SCR (latching operation) to transistor operation can be achieved. Fig. 10.50 shows the dynamic switching characteristics of IGCT. Finally, Table 10.1 presents a comparison between GTOs, IGCTs, and IGBTs.

(a)

Anode A iA

+ v AK

Gate i G G K Cathode

-

(b)

Figure 10.49 (a) GCT symbol and package; (b) IGCT package with driving circuit.

Fully Controlled Semiconductor Devices

735

v AK (anode-cathode voltage)

Vin 0.9Vin

v AK

i A (anode current) di A dt

SCR transistor mode mode

IA

0.9IA 0.4IA

0.1Vin

0

t d(off)

tf

t

iG (gate current)

0 t d(on)

di G1 dt t r vG (gate-cathode voltage) diG2 dt

t

Figure 10.50 IGCT dynamic switching characteristics. SCR, silicon-control rectifier. Table 10.1 Comparison between gate turn-off thyristors (GTOs), integrated gate commutated thyristors (IGCTs), and insulated gate bipolar transistors (IGBTs) Specification

GTO

IGCT

IGBT

Maximum switch power device (VxI)

36 MVA

36 MVA

7 MVA

Active di/dt and dv/dt control

No

No

Yes

Active short-circuit protection

No

No

Yes

Turn-off (dv/dt) snubber

Required

Not required

Not required

Turn-on (di/dt) snubber

Required

Required

Not required

Parallel connection

No

No

Yes

Switching speed

Slow

Moderate

Fast

Behavior after failure

Shorted

Shorted

Open in most cases

Conduction losses

Low

Low

High

Switching losses

High

Low

Low

Gate driver

Complex separated

Complex integrated

Simple compact

Gate driver power consumption

High

High

Low

10.7

Silicon Carbide Technology for Power Semiconductor Construction

It is worldwide accepted today that a real breakthrough in the power electronics field may mainly come from the development and use of wide band gap (WBG)

736

Power Electronics and Motor Drive Systems

semiconductor devices. In power electronic systems, there has been a continuous trend toward a higher system power density (i.e., W/cm3) in the last decades and due to environmental concerns and rising energy costs, also the efficiency of the systems became an important system performance criterion over the past years besides costs. For meeting these demands, the development of power semiconductors is a crucial factor. WBG semiconductors show superior material properties, which allow operation at high switching speed, high voltage, and high temperature. These unique performances provide a qualitative change in their application to energy processing. From energy generation (carbon, oil, gas, or any renewable) to the end user (domestic, transport, industry, etc.), the electric energy undergoes a number of conversions. These conversions are currently highly inefficient to the point that it is estimated that only 20% of the whole energy involved in energy generation reaches the end user. WBG semiconductors can increase the conversion efficiency, thanks to their outstanding material properties. In the area of power electronic converter systems there is a general trend to higher power densities and higher efficiency which is driven by cost reduction, an increased functionality, saving resources and, in some applications, by the limited weight/space requirements. To continue this trend, new devices, which enable high switching frequencies at higher power levels or show reduced losses at moderate switching frequencies, are required.

10.7.1

Characteristics of Wide Band Gap Semiconductors

Power semiconductor devices made from materials with band gap energies larger than that in Si have been touted for many decades. The potential advantages of these WBG devices include higher achievable junction temperatures and thinner drift regions (because of the associated higher critical electric field values) that can result in much lower on resistance than is possible in Si. WBG semiconductor materials allow power electronic components to be smaller, faster, more reliable, and more efficient than their silicon (Si)-based counterparts. These capabilities make it possible to reduce weight, volume, efficiency, and life-cycle costs in a wide range of power applications. Harnessing these capabilities can lead to dramatic energy savings in industrial processing and consumer appliances, accelerate widespread use of electric vehicles and fuel cells, and help integrate renewable energy onto the electric grid. The continuous development of improved power semiconductors is a key enabling factor for propelling the constantly increasing demand for high power density and higher efficiency in many power electronic applications. The technological progress in manufacturing power devices based on WBG materials has resulted in a significant improvement of the operating voltage range, of the switching speed and on resistance compared to silicon power devices. Table 10.2 is presented with various semiconductor materials with their characteristics. From this table, it can be noted that the materials with a value of thermal conductivity close to or exceeding Si are GaN, GaP, SiC, and C (diamond). This implies higher melting temperatures. Out of these four semiconductors, GaP has much lower carrier mobility values than Si. So, one good semiconductor material for the future is C (diamond). It has the largest thermal

Fully Controlled Semiconductor Devices

737

Table 10.2 Characteristics of wide band gap semiconductor materials at 300K

Semiconductor material

Band gap (eV) Direct, D Indirect, I

Critical or breakdown Field Ec (V/cm)

Thermal conductivity (W/(m*K))

Coefficient of thermal expansion (ppm/K)

GaN

3.44 D

3,000,000

110

5.4e7.2

Ge

0.661 I

100,000

58

5.9

Si

1.12 I

300,000

130

2.6

GaP

2.26 I

1,000,000

110

4.65

SiC (3C,b)

2.36 I

1,300,000

700

2.77

SiC (6H,a)

2.86 I

2,400,000

700

5.12

SiC (4H,a)

3.25 I

3,180,000

700

5.12

C

5.6 I

5,700,000

600e2000

0.8

conductivity and band gap of any of the materials from Table 10.2. Diamond also has the largest electron mobility of any material from Table 10.2 with a band gap larger than Si. However, there are some aspects of C (diamond) that make it less than ideal. First, the material and device fabrication technology is much less mature and developed than for SiC and GaN. Second, the thermal expansion coefficient (CTE) for C (diamond) is very low. So there is a clear thermomechanical mismatch which would make the package unreliable. Also, the diamond is one of the most expensive materials which make it inappropriate for integration in large scale systems. On the other hand, GaN and SiC are by comparison to C (diamond) very well suited to typical package materials, and in fact provide a better thermomechanical match than Si. At present, SiC is considered to have the best trade-off between properties and commercial maturity with considerable potential for both high temperature applications and high power devices. However, the industrial interest for GaN power devices is increasing recently. For this reason, SiC and GaN are the more attractive candidates to replace Si in such applications. In fact, some SiC devices, such as Schottky diodes, are already competing in the semiconductor market with Si power diodes. Currently, it is a sort of competition between SiC and GaN in a battle of performance versus cost. Nevertheless, scientific and industrial actors agree in considering that both will find the respective application fields with a tremendous potential market. However, many of the material advantages still remain not fully exploited due to specific material quality, technology limitations, nonoptimized device designs, and reliability issues. It is worth mentioning that diamond exhibits the best properties of all the WBG semiconductors. Theoretically diamond would be ideal for bipolar device designs, particularly in operating environments of elevated temperatures. The high values of carrier mobilities, as well as the large band gap and high thermal conductivity, make diamond the ideal

738

Power Electronics and Motor Drive Systems

future material for electronic devices of all power levels and types. However, there are critical problems related with the crystal growth (small areas single crystal wafers), both p-type and n-type dopings and processing. Therefore, there is not a diamond power device in the market and it is not expected in the next decade. SiC power devices recently reported in literature include high-voltage and high-temperature diodes, junction controlled devices (like junction field effect transistors (JFETs)), MOSFETs and metal-semiconductor-field effect transistors (MESFETs). Those based on GaN include diodes, HEMTs, and MOSFETs; and advanced research on novel devices concerning low-losses digital switches based on SiC and GaN is also of main concern. These novel devices represent a real breakthrough in power devices.

10.7.2

Silicon Carbide Overview

Silicon carbide (SiC) was accidentally discovered in 1890 by Edward G. Acheson, an assistant to Thomas Edison, when he was running an experiment on the synthesis of diamonds. Acheson thought the new material was a compound of carbon and alumina present in the clay, leading him to name it carborundum, a name that is still being used on some occasions. Silicon carbide occurs naturally in meteorites, though very rarely and in very small amounts. Being the discoverer of SiC, Acheson was the first to synthesize SiC by passing an electric current through a mixture of clay and carbon. Today, SiC is still produced via a solid-state reaction between sand (silicon dioxide) and petroleum coke (carbon) at very high temperatures in an electric arc furnace. Silicon carbide is a semiconductor material with highly suitable properties for highpower, high-frequency, and high-temperature applications. This almost worn-out opening statement may be found in many papers dealing with SiC. Yet, it cannot be left out because it really brings forward the essence of the material’s potential. Silicon carbide is a WBG semiconductor material with high breakdown electric field strength, high saturated drift velocity of electrons, and a high thermal conductivity. Therefore, these properties make SiC ideally suited for a vast number of applications. Today there are high-frequency metal-semiconductor-field effect transistors offered commercially, as well as an emerging market for Schottky diodes made from SiC. Silicon carbide is the only chemical compound of carbon and silicon. It was originally produced by a high temperature electrochemical reaction of sand and carbon. The SiC crystals consist of 50% carbon atoms covalently bonded with 50% silicon atoms. There are over 100 different crystal structures (polytypes), each SiC polytype has its own distinct set of electrical semiconductor properties. However, only few polytypes are used for semiconductor production, the cubic 3C-SiC, hexagonal 4H-SiC, and 6H-SiC. •

Mechanical and chemical properties Silicon carbide is a very hard substance. It is chemically inert and reacts poorly (if at all) with any known material at room temperature. It is practically impossible to diffuse anything into SiC. Dopants need to be implanted or grown into the material. Furthermore, it lacks a liquid phase and instead sublimes at temperatures above 1800 C. The vapor constituents during sublimation are mainly Si, Si2C, and SiC2 in specific ratios, depending on the temperature.

Fully Controlled Semiconductor Devices

•

•

•

•

739

Band gap The band gap varies depending on the polytype between 2.36 eV for 3C-SiC to 3.33 eV for 2H-SiC. The most commonly used polytype is 4H-SiC, which has a band gap of 3.265 eV. The WBG makes it possible to use SiC for very high temperature operation. Thermal ionization of electrons from the valence band to the conduction band, which is the primary limitation of Si-based devices during high temperature operation, is not a problem for SiC-based devices because of this WBG. Critical field For power device applications, perhaps the most notable and most frequently quoted property is the breakdown electric field strength, Ec(max). This property determines how high the largest field in the material may be before material breakdown occurs. This type of breakdown is obviously referred to as catastrophic breakdown. Curiously, the absolute value of Ec(max) for SiC is frequently quoted as the relative strength of the Ec(max) against that of Si. Most discussions on this subject note that Ec(max) of SiC is 10 times that of Si. As with Si, there exists a dependence of Ec(max) with doping concentration. Thus, for a doping of approximately 1016 cm3, Ec(max) is 2.49 MV/cm. For Si, the value of Ec(max) is about 0.401 MV/cm for the same doping. As can be seen, the value for SiC is only about a factor of six higher than that of Si and not the often-claimed 10 times higher critical field strength. Why the discrepancy? It is more correct to compare the critical strengths between devices made for the same blocking voltage. Thus, a Si device constructed for a blocking voltage of 1 kV would have critical field strength of about 0.2 MV/cm, which should be compared to the 2.49 MV/cm of SiC. This is where the order of magnitude larger breakdown field spec comes from. Saturated drift velocity For high-frequency devices, the breakdown electric field strength is not as important as the saturated drift velocity. In SiC, this is 2  107 cm/s, which is twice that of Si. A highsaturated drift velocity is advantageous to obtain as high channel currents as possible for microwave devices, and clearly SiC is an ideal material for high-gain solid-state devices. Thermal conductivity The second most important parameter for power and high-frequency device applications is the material’s thermal conductivity. An increase in temperature generally leads to a change

Breakdown Electric Field 3 (MV/cm2)

2

3 Energy Gap (eV)

2

SiC 1

1

Si 0 1

1

2

3

e- mobility (cm2/V∙s)

2 3

Figure 10.51 Properties of Si and SiC materials.

Thermal Conductivity (W/(cm x K))

740

Power Electronics and Motor Drive Systems

in the physical properties of the device, which normally affects the device in a negative way. Most important is the carrier mobility, which decreases with increasing temperature. Heat generated through various resistive losses during operation must be conducted away from the device and into the package. More detailed studies have been made where the thermal conductivity in the different crystal directions have been determined for SiC. As can be seen, there is dependence on the purity of the crystal as well as on the crystal direction. High-purity semi-insulating SiC material has the highest reported thermal conductivity with a value of 4.9 W/(cm K). Lower values are measured for the doped crystals but they are all above 4 W/(cm K) at room temperature. Finally, Fig. 10.51 presents the advantageous properties of SiC against Si.

10.7.3

Silicon Carbide Devices

In this section, an overview of the available SiC devices is given. The dramatic quality improvement of the SiC material in combination with excellent research and development efforts on the design and fabrication of SiC devices by several research groups has recently resulted in a strong commercialization of SiC switch-mode devices. Nevertheless, the SiC device market is still in an early stage, and today, some available SiC switches are the JFET, BJT, MOSFET, and Schottky barrier diodes (SBDs). Commercially available SiC devices are still not in mass production. Finally, it is also worth mentioning the progress of the research on the SiC IGBT.

10.7.3.1 SiC Schottky Barrier The SiC version of this pen junction may offer many improvements in contrast to Silicon’s version. Silicon carbide SBDs have been available for more than a decade but were not commercially viable until recently. The highest performance silicon power diodes are SBDs. Not only do SBDs have the lowest reverse recovery time (trr) compared to the various types of fast recovery (fast recovery epitaxial), ultrafast recovery, and superfast recovery diodes, they also have the lowest forward voltage drop (VF).

10.7.3.2 SiC MOSFET Several years have been spent on the research and development of the SiC MOSFET. The fabrication and stability of this oxide layer has been challenging. SiC oxides are not showing the same reliability as in Si MOSFETs. They have higher threshold voltage shifts, gate leakage, and oxide failures than comparably biased silicon MOSFET’s. This has detrimental impact on SiO2 electrical quality. Consequently, much longer and higher temperature maintenance (annealing) is required to improve the SiC oxide quality. A cross section of a popular commercialized vertical double implanted SiC MOSFET structure is shown in Fig. 10.52. The normally-off behavior of the SiC MOSFET makes it attractive to the designers of power electronic converters. Unfortunately, the low channel mobility cause additional conduction-state resistance of the device, and thus increases conduction-state power losses. Additionally, the reliability and the stability of the gate oxide layer, especially over long time periods and at

Fully Controlled Semiconductor Devices

Source

741

Gate

Source

metal S iO 2 g ate o x id e lay er

n+

n+

p-base

p-base

n- drift region

n+ SiC substrate Drain

Figure 10.52 Cross section of 4H-SiC vertical double implanted MOSFET.

elevated temperatures, have not been confirmed yet. Fabrication issues also contribute to the deceleration of SiC MOSFET development.

10.7.3.3 SiC-Based IGBT The Si-based IGBT has shown an excellent performance for a wide range of voltage and current ratings during the last two decades. The fabrication of a Si n-type IGBT started on a p-type substrate. Such substrates are also available in SiC, but their resistivity is unacceptably high and prevents these components from being used in power electronics applications. Furthermore, the performance of the gate oxide layer is also poor, resulting in high channel resistivities. These issues have already been investigated by many highly qualified scientists, and it is believed that such SiC devices will not be commercialized within the next 10 years.

10.7.3.4 SiC Bipolar Junction Transistor The SiC BJT is a bipolar normally-off device, which combines both a low conductionstate voltage drop (0.32 V at 100 A/cm2) and a quite fast switching performance. A cross section of this device is shown in Fig. 10.53 where it is obvious that this is an npn BJT. The low conduction-state voltage drop is obtained because of the cancellation of the baseeemitter and baseecollector junction voltages. The SiC BJT is a current-driven device, which means that a substantial continuous current is required as long as it conducts a collector current.

10.7.3.5 SiC Junction Field Effect Transistor A JFET has no SiO2eSiC interface and could, therefore, be available as a commercial power device in the next few years. The high quality of the conduction channel and good control of the channel dimensions and doping are crucial for the JFET performance. The normally-on JFET design is capable of extremely low conduction-state

742

Power Electronics and Motor Drive Systems

Emitter Contact Base Contact SiO2 passivation

Ni/Ti/Al

Ni/Ti/Al n+ SiC emitter

Base implant

p+ SiC base

Space modulated JTE implant

n- SiC collector

Base Contact polyimide Ni/Ti/Al Base implant

Space modulated JTE implant

n+ SiC Substrate Ni Collector Contact

Figure 10.53 Cross section of SiC BJT.

resistance. Normally-on JFETs are not easily accepted by the market due to system safety requirements, regardless of their excellent on resistance. Normally-off JFETs on the other hand require a narrow and relatively low-doped channel to ensure the N-off performance, and thus pay a penalty in terms of the conduction-state performance. Normally-off JFETs are also vulnerable to the electromagnetic interference (EMI) noise due to the small range of the gate control voltage. Hence, the gate control circuitry for JFETs requires special attention to ensure reliable operation. In the case of normally-on JFETs the development of inherently safe gate drivers is particularly desired to guarantee the safety of the whole system. A significant difference between the JFET and the MOSFET is that the MOSFET is normally-off, whereas the JFET can be either normally-on or normally-off. Normally-on means that the JFET conducts when no voltage is applied to the gate. Fig. 10.54 shows the JFETs symbols and the equivalent circuit of the n-type. Fig. 10.55 presents the iDevGS characteristic in the saturation region of a SiC JFET. As can be seen from Fig. 10.55, the slope of the characteristic is equal to b0.5, and the value of the threshold voltage is defined as that voltage of vGS for which the drain current ID is approximately zero. Moreover, Fig. 10.56 presents the iDevDS characteristic of a SiC JFET (Table 10.3). •

Lateral channel junction field effect transistor (LCJFET) The most successful JFET type in terms of voltage and current ratings has been the lateral channel JFET. The cross section of the LCJFET is shown in Fig. 10.57. The LCJFET allows optimal control of the channel parameters and offers the largest ease of fabrication compared to other concepts. It also offers the use of the inherent body diode as an antiparallel diode in switching applications since the buried gate is preferably connected to source. This is necessary to reduce the Miller capacitance, and thus maintain high speed operation. The original LCJFET structure uses ion-implantation for the gate and the base region, and planar epitaxial growth for the defect-free channel layer. This leads to advantages in terms of ease of

Fully Controlled Semiconductor Devices

743

(a)

(b) D

G

Drain

Drain G Gate

n-channel

D RD

D

CGD IGD

p-channel

G

RG

CDS IGS

Gate Source

Source S

ID

CGS

S

RS S

Figure 10.54 SiC junction field effect transistor symbols and equivalent circuit. (a) Symbols; (b) equivalent circuit of the n-type.

i D (A)

IDSS

β = Trasconductance Saturation region Slope = β0.5 Linear Region Channel-off Vth

0 v (V) GS

Figure 10.55 Normally-on SiC junction field effect transistor iDevGS input characteristic for a certain value of VDS.

iD (A)

IDSS

λ = channel length modulation parameter slope = gD,sat = λID VGS0=0 Linear region

VGS1
0

Channel-off vDS (V)

Figure 10.56 Normally-on SiC junction field effect transistor iDevDS output characteristic.

744

Table 10.3

Power Electronics and Motor Drive Systems

SiC junction field effect transistor model parameters

Name

Parameter

Units

VTO

Threshold voltage, Vth

V

Beta

Transconductance, b

A/V2

Lamda

Channel length modulation parameter, l

V1

Rd

Drain ohmic resistance

Ohm

Rs

Source ohmic resistance

Ohm

Is

Gate junction saturation current

A

Cgs

Zero-bias GeS junction capacitance

F

Cgd

Zero-bias GeD junction capacitance

F

PB

Gate junction potential

V

M

Junction grading coefficient

e

KF

Flicker-noise coefficient

e

AF

Flicker-noise exponent

e

FC

Coefficient for forward-bias depletion capacitance formula

e

TNOM

Parameter measurement temperature

C

XTI

IS temperature coefficient

e

VTOTC

Threshold voltage temperature coefficient

V/ C

BETATC

Transconductance exponential temperature coefficient

 C1

Gate Source

Source Lateral p+ top gate Channel

n+ p+ buried gate

n+ p+ buried gate

n- drift region

n Field Stop Substrate n++

Drain

Figure 10.57 Cross section of SiC lateral channel junction field effect transistor.

Fully Controlled Semiconductor Devices

•

745

fabrication, freedom of parameter choice due to a wide design window, and small fabrication tolerances. Its main disadvantage is a relative large specific on resistance, which is related to the large cell pitch due to the lateral configuration of the channel. Vertical trench junction field effect transistor (VTJFET) The cross section of a VTJFET is shown in Fig. 10.58. The VTJFET SiC JFET can be either a normally-off (enhancement-mode VTJFETdEMVTJFET) or a normally-on (depletionmode VTJFETdDMVTJFET) device, depending on the thickness of the vertical channel and the doping levels of the structure. As other normally-on JFET designs, a negative gate-source voltage is necessary to keep it in the cut-off mode. On the other hand, a significant gate current (approximately 200 mA for a 30-A device) is necessary for the normally-off JFET to keep it in the conduction mode. The pinch-off voltage for the DMVJFET equals approximately 6 V, whereas the positive pinch-off voltage for the normally-off one is slightly higher than 1 V. Comparing this type of SiC JFETs to the LCJFET there is no physical antiparallel body diode in this design. However, the VTJFET can conduct current in the reverse direction. When the vertical channel JFETs are used for freewheeling purpose, the reverse-recovery currents are only caused by the depletion charge of the device and no minority injection is involved.

Fig. 10.59 presents the heat sinks of two inverter stages of the same power one implemented with Si IGBTs and the other with SiC JFETs. As can be seen from Fig. 10.59, the power semiconductor stage of the SiC inverter is exhibiting higher power density (W/cm2) due to the higher efficiency. Fig. 10.60 shows the power circuit of a three-phase voltage source inverter implemented with SiC JFETs. Source

Vertical Channel

Gate n+

n+

Gate

n+

SiO2

SiO2

SiO2

SiO2

p

p

p

p

Depletion region

Implanted p-type Gate Current Flow n- drift region

4H-SiC n+ Substrate

Drain

Figure 10.58 Cross-section of vertical trench junction field effect transistor.

746

Power Electronics and Motor Drive Systems

Figure 10.59 Heat sinks of two inverter stages of the same power but with different semiconductor devices. (a) Using Si semiconductor devices; (b) using SiC semiconductor devices.

Figure 10.60 Three-phase inverter implemented using normally-on SiC junction field effect transistors.

Fig. 10.61 shows a driving circuit of a normally-on SiC JFET. Since the normally-on SiC JFET needs 0 V at its gate to turn on and 15 V to turn off the conventional pulses of þ15 are converted through the totem pole MOSFETs (IXDD_609) to 15 V pulses. Fig. 10.62 shows a driving circuit of a normally-off SiC JFET. When an inverter is implemented with SiC JFETs, it is important to solve the Miller effect; otherwise unwanted overvoltage effects may appear across the semiconductor devices. Fig. 10.63 shows the Miller effect on one phase leg of an inverter. Specifically, when the upper SiC JFET is in the turn-on transition and the lower is in the cut-off mode, then the voltage of the lower JFET drain increases very fast from 0 to þVin with a very high dv/dt. Since the semiconductor switch S2 is conducting the parasitic current ICGD, which is generated from Miller capacitance CGD, will flow through the resistor Rgl toward the ground increasing the voltage VGS. If VGS ¼  Vgg þ Rgl$IGCD

-Vout

POWER SUPPLY Com

MC7805CT +Vout

IN 1

HEF4071BP HEF4071BP

0.33uF0.33uF -15V

0V

+15V 0V

+15V

0V

All diodes are NXP PMEG6010CHE

+5V

GND OUT 2 3

0V

+5V

IXDD_609 2

1 8 Vcc 6 OUT 7 3 EN GND 4 5

-15V

100nF

Vcc 8 3.3V

Rc 100Ω

Vdd Rs_off 5Ω

-15V

1

D1

+5V

+5V

OPTOCOUPLER HCPL-2231

DSP Pulses

-15V

Normally-on SJDP120R085 SiC JFET

100nF

IN

D2

D

+5V

G

7

IXDD_609

0V 2

GND 5 1 8 Vcc 6 OUT 7 3 EN GND 4 5

100nF

2 IN

HEF4071BP

HEF4071BP

0V

-15V

0V

Cgs 1nF

D3

S

Rs_on 5Ω

330pF -15V

500Ω

-15V

-15V

-15V

-15V

Figure 10.61 Driving circuit for normally-on SiC junction field effect transistors.

-Vout

POWER SUPPLY Com +Vout

MC7805CT IN GND OUT 1 2 3

Diodes are NXP PMEG 6010CEH

0.33uF0.33uF

-15V

0V

+15 V

+15V 0V

DSP Pulses

1

0V

2

IXDD_609 +5V

Vcc8 7

Vdd

100nF 1 8 IN Vcc 6 OUT 3 7 EN GND 4 5 2

GND5

100nF

Rs 2Ω

D

Cp 94nF D1

G

Rc 20Ω Cgs 1nF

-15V

0V

Rp 3kΩ

D2

Normally-Off SJEP120R100 SiC JFET

OPTOCOUPLER HCPL-2231 3.3V

+5V

+5V

S

-15V

Figure 10.62 Driving circuit for normally-off SiC junction field effect transistors.

-Vgg

D CGD Rgh G

Vin

Ci

S1

S + −

-Vgg

CGD

D S2

Rgl G ICGD

S

Figure 10.63 SiC junction field effect transistor Miller effect on an inverter leg.

748

Power Electronics and Motor Drive Systems

is increased above its threshold voltage value, then S2 might go faulty to conduction and together with S1 a short-circuit is created on the phase leg which will be catastrophic for both semiconductor switches.

10.8

Mount Package Types of Semiconductor Devices and Types of Heat Sinks

Fig. 10.64 shows different types of mount packages of power semiconductor devices. As can be seen from Fig. 10.64(a), the mount packages TO-220, TO-268, and TO-264 are for low power semiconductor devices. The mount packages shown in Fig. 10.64(b) and (c) are for higher power applications. The high power semiconductor switches analyzed in the previous sections, due to the high density of current that flows through their junctions, they exhibit power losses and, consequently, generate internally high temperature levels. Since the high temperature levels are affecting negatively the operation and the life time of the semiconductor devices, there is a need to design a proper heat sink system for temperature dissipation to keep the device under manufacturer’s temperature specifications. The aim of the heat

Figure 10.64 Different types of mount packages of power semiconductor switches mount packages. (a) Single semiconductor switches with different types of mount packages; (b) two-semiconductor switches in one mount package to implement one phase leg; (c) six-semiconductor switches in one mount package to implement three-phase legs.

Fully Controlled Semiconductor Devices

749

sinks is to increase the temperature conductivity between the device module case and the ambient temperature in order for the heat dissipation to become more effective. Fig. 10.65 shows different types of heat sinks that can be used to cool and keep the semiconductor devices to manufacturer’s temperature levels. The heat sink is considered to be a natural cooling system. Fig. 10.66 shows two different heat sinks with natural air cooling for power semiconductor devices. Besides the natural heat sink air cooling systems there are the so-called heat forced air or liquid cooling techniques which are using air fans or liquid pumps for temperature dissipation. These techniques are applied in applications where the power electronics converter needs high power density. Fig. 10.67 shows two different forced cooling techniques.

Figure 10.65 Different types of heat sinks with different thermal resistance.

Figure 10.66 Heat sinks with natural air cooling.

750

Power Electronics and Motor Drive Systems

Figure 10.67 Heat sinks with forced cooling. (a) Forced air cooling with fans; (b) forced cooling with liquid.

10.8.1

Heat Sink Computations

When the power semiconductor devices are operating, they exhibit power switching and conduction losses which are converted to heat. If the junction temperature of the power semiconductor exceeds the manufacturer’s specifications the device will be destroyed. Therefore, this high value temperature has to be reduced. The usual way to increase the transfer of excess heat from the crystal of a semiconductor device to the ambient air is to attach the semiconductor device to a heat sink and many times an air fan is also include for faster air flow. The heat sink is made of metal and most of the times from aluminum and is constructed with fins to allow maximum contact with ambient air. The heat flow power is equal to the power losses. The heat flows from the highest temperature region, which is the junction of the crystal, to the lowest, which is the ambient air. The heat flows from the junction to the ambient air through a thermal path consisted of the case of the device, a thermal grease or insulator and a heat sink.

Fully Controlled Semiconductor Devices

751

Figure 10.68 Heat sink with four power semiconductor switches.

Fig. 10.68 shows a heat sink which is used for natural air cooling of four power semiconductor switches. Fig. 10.69(a) shows the direction of the heat flow and the steady-state thermal resistances between different points. Also, Fig. 10.69(b) shows the steady-state thermal resistance equivalent model where the thermal resistance of the thermal grease and the thermal resistance are added to a single thermal resistance case-sink. The power losses of a semiconductor device are equal to the heat transfer power. To understand the thermal analysis of semiconductor switch mounted on a heat sink Table 10.4 presents how the electrical parameters are associated with the thermal parameters. To estimate and select the right heat sink for the right application, it is necessary to understand the heat transfer power between two points which is given by: Pheattrasf ¼

DT Rth

(10.15)

where Rth ¼ thermal resistance between the two points in  C/W or  K/W (since Rth is based on a temperature difference and not on the absolute temperature, both units are perfectly equivalent (for example, 5 C/W ¼ 5 K/W)); DT ¼ Temperature difference (rise). In case of semiconductor switches that are mounted on a heat sink, the total thermal resistance consists of the following three main components: 1) Thermal resistance, Rjc: It is the thermal resistance between the silicon junction and the case of the semiconductor device. This resistance is given in the manufacturer’s specifications. 2) Thermal resistance, Rcs: It is the thermal resistance between the case of the device and the heat sink. This resistance also depends on the thermal grease or insulator that there is between the case and the heat sink. If the thermal grease is applied correctly between the case and the heat sink, then its thermal resistance value is negligible and can be ignored. The thermal resistance of an insulator is provided by the manufacturer.

752

Power Electronics and Motor Drive Systems Device crystal junction

(a) Semiconductor case Insulator or thermal grease

Tj

R jc Tc

R cs

Ts R sa

heat flow Ambient air surroundings

(b)

Tj = junction temperature

Tj

Tc = case temperature

Rjc

Ti = insulator or thermal grease temperature Ts = heat sink temperature

Tc

Ta = ambient temperature

Rcs

Plosses

Ta

R jc = thermal resistance between junction and semiconductor case R ci = thermal resistance between case and insulator

Ts Rsa

R is = thermal resistance between insulator and heat sink R sa = thermal resistance between heat sink and ambient

Ta

R cs = R ci + R is

Figure 10.69 Heat sink thermal resistances for single semiconductor device. (a) Heat flow through a heat sink and thermal resistances between different points; (b) steady-state thermal resistances equivalent model.

Table 10.4

Association between electrical and thermal parameters

Electrical parameters

Thermal parameters Plosses

I V

R electrical

Rel ¼ electrical resistance (U) V ¼ potential difference (V) I ¼ electrical current V ¼ I  Rel

ΔT

Rth

Rth ¼ thermal resistance ( C/W or  K/W) DT ¼ temperature difference ( C or  K) Plosses ¼ power losses of the semiconductor device (W) DT ¼ Plosses  Rth ( C)

Fully Controlled Semiconductor Devices

753

3) Thermal resistance, Rsa: It is the thermal resistance between the heat sink and the ambient temperature. This resistance depends on the characteristics of the heat sink (i.e., material, color, shape, and dimensions).

Therefore, the total steady-state (i.e., constant power losses) thermal resistance between the junction and the ambient air is given by: Rja ¼ Rjc þ Rcs þ Rsa ¼

Tjmax  Ta PlossesðavÞ

(10.16)

where Tjmax ¼ maximum junction temperature; Ta ¼ ambient air temperature; Plosses(av) ¼ maximum permissible power average losses of the semiconductor device. Also, from Fig. 10.69(b), the following equations can be obtained: Tj ¼ Ta þ Tc þ Ts ¼ Ta þ Rjc PlossesðavÞ þ PlossesðavÞ Rcs þ PlossesðavÞ Rsa ¼ Ta þ PlossesðavÞ ðRjc þ Rcs þ Rsa Þ

(10.17)

¼ Ta þ PlossesðavÞ  Rja DTja ¼ Tj  Ta ¼ PlossesðavÞ  Rja

(10.18)

Tc ¼ Ta þ PlossesðavÞ  ðRcs þ Rsa Þ

(10.19)

Ts ¼ Ta þ PlossesðavÞ  Rsa

(10.20)

Rsa ¼ heat sink thermal resistance ¼ ¼

Tj  Ta  Rjc  Rcs PlossesðavÞ

Tj  Ta  Rjs  C=W PlossesðavÞ

(10.21)

Example 10.2 Calculate the maximum average power that an IGBT can dissipate (a) without a heat sink and (b) with a heat sink. The following data are given: Rjc ¼ 1.8 C/W, Rcs ¼ 0.8 C/W, Rsa ¼ 4 C/W, Rja ¼ 50 C/W, Ta ¼ 35 C, and Tjmax ¼ 130 C.

Solution PlossesðavÞwithout-sink ¼ PlossesðavÞwith-sink ¼

Tjmax  Ta 130  35 ¼ 1:9 W ¼ 50 Rja

Tjmax  Ta 130  35 ¼ 14:4 W ¼ Rjc þ Rcs þ Rsa 1:8 þ 0:8 þ 4

754

Power Electronics and Motor Drive Systems

Example 10.3 An IGBT is operating with average conduction and switching losses of 10 W. Find its operating temperatures, given the following data: Rjc ¼ 3.8 C/W, Rcs ¼ 1 C/W, Rsa ¼ 6 C/W, and Ta ¼ 35 C.

Solution Tj ¼ Ta þ PlossesðavÞ ðRjc þ Rcs þ Rsa Þ ¼ 35 þ 10ð3:8 þ 1 þ 6Þ ¼ 143 C Tc ¼ Ta þ PlossesðavÞ ðRcs þ Rsa Þ ¼ 35 þ 10ð1 þ 6Þ ¼ 105 C Ts ¼ Ta þ PlossesðavÞ ðRsa Þ ¼ 35 þ 10ð6Þ ¼ 95 C

Example 10.4 An IGBT is operating with average conduction and switching losses of 25 W for junction temperature of 150 C. Find the thermal resistance of the heat sink that is needed to keep the maximum junction temperature to 150 C when the ambient temperature is 50 C. The following data are given: Rjc ¼ 1.5 C/W (given by the manufacturer) and Rcs ¼ 0.6 C/W (insulator and thermal grease).

Solution Using the above given specifications the following steady-state thermal resistances equivalent model is obtained: Tj = 150ο C R jc = 1.5o C / W

Tc

Plosses = 20W

R cs = 0.6o C / W

Ts R sa = ?

Ta = 50o C

Rsa ¼

Tj  Ta 150  50  1:5  0:6 ¼ 1:9 C=W  Rjc  Rcs ¼ 25 PlossesðavÞ

Fully Controlled Semiconductor Devices

755

Figure 10.70 Different types of heat sinks and their respective specifications given in Table 10.5. (Courtecy of BAL GROUP Ltd).

Therefore to keep the device junction to 150 C the device should be mounted on a heat sink with thermal resistance of 1.9 C/W. From the heat sinks of Fig. 10.70 and according to their specifications, which are given in Table 10.5, the best choice is the heat sink no. 1.

Table 10.5 Specifications of the aluminum type heat sinks shown in Figure 10.71 Heat sink no

Rsa (oC/W)

Height mm

Width mm

Length mm

1

1.9

27

65

300

2

0.95

40

96

300

3

0.8

50

125

300

4

0.71

50

140

300

5

1.05

25

100

300

6

0.9

40

100

300

7

0.6

50

125

300

8

0.45

73

145

300

756

Power Electronics and Motor Drive Systems

Example 10.5 A BJT has an average power loss of 25 W at a junction temperature of 120 C. The transistor manufacturer specifies a thermal resistance Rjc ¼ 0.9 C/W. A 75-mm thick mica insulator is used with thermal grease, and the thermal resistance of the combination is 0.5 C/W. Find the thermal resistance of the heat sink that is needed to keep the maximum junction temperature to 120 C when the worst case ambient temperature is 60 C.

Solution Rsa ¼

Tj  Ta 120  60  0:9  0:5 ¼ 1:0 C=W  Rjc  Rcs ¼ 25 PlossesðavÞ

Therefore, from the heat sinks of Fig. 10.70 the best choice is the heat sink no. 5. When multiple power semiconductor devices are mounted on a common heat sink, their thermal resistance model can be one of the models shown in Figs. 10.71 and 10.72. Fig. 10.71 presents the thermal resistance steady-state model when the power semiconductor devices have individual mounting case and Fig. 10.72 presents the thermal resistance steady-state model when the power semiconductor devices have common mounting case.

n

3

1

Plosses(av)

Tj

R jc

R jc

R jc

R jc

R jc

R cs

R cs

R cs

R cs

R cs

Ts n semiconductors with their individual case (For example case type ΤΟ247)

R sa Ta

Figure 10.71 Thermal resistance model for multiple semiconductors mounted on the same heat sink with individual mounting cases.

Fully Controlled Semiconductor Devices

1

757

n

2

Tj

semiconductors case

R jc

R jc

R jc

R jc

R jc

Plosses(av)

Tc

R cs n semiconductor devices inside the same case

Ts

R sa Ta

Figure 10.72 Thermal resistance models for multiple semiconductors mounted on the same heat sink with common mounting case.

According to Fig. 10.71, when power semiconductors have individual mounting case and are mounted on a heat sink then the total thermal resistance of the heat sink is given by: Rsa ¼

Tj  Ta Rjc þ Rcs   C=W PlossesðavÞ n

(10.22)

Also, according to Fig. 10.72, when power semiconductors have common case the total thermal resistance of the heat sink is given by: Rsa ¼

Tj  Ta Rjc  Rcs  C=W  PlossesðavÞ n

(10.23)

where n is the number of semiconductor devices.

Example 10.6 Find the required heat sink to mount eight power semiconductor devices with individual cases. The following specifications are given: Tj ¼ power semiconductors junction temperature (by manufacturer)  150 C Ta ¼ ambient temperature ¼ 50 C Rjc ¼ power semiconductors thermal resistance between junction and case (by manufacturer) ¼ 1.5 C/W Rcs ¼ thermal grease and isolator thermal resistance (by manufacturer) ¼ 0.6 C/W Plosses(av) ¼ average value of a single semiconductor power losses ¼ 24.23 W

758

Power Electronics and Motor Drive Systems

Solution Using the thermal model of Fig. 10.71, the following thermal resistance model is obtained.

R cs = 0.6 °

Plosses(av) =(8)(24.3)=194.4W

1

C R = 1.5° C jc W W

Tj = 15°C

4

8

R jc

R jc

R jc

R jc

R jc

R jc

R jc

R cs

R cs

R cs

R cs

R cs

R cs

R cs

Ts

8 individual semiconductors with case type ΤΟ247

R sa Ta = 5°C

Thermal resistance model applied to this example

Using Eq. (10.22), the following results are obtained: Rsa ¼

150  50 1:5 þ 0:6  ¼ 0:5144  0:26 ¼ 0:255 C=W 194:4 8

Ts ¼ Ta þ PlossesðavÞ ðRsa Þ ¼ 50 þ 194:4ð0:255Þ ¼ 99:57 C Therefore to maintain the junction temperature of the semiconductor devices Tj  150 C they have to be mounted on a heat sink that will have thermal resistance of Rsa  0.255 C/W. Fig. 10.73 presents a proposed heat sink and the respective air flow speed characteristics. Company: Birmingham Aluminum Series: 1500 series Length: 300 mm Thermal resistance: 0.255 C/W

The steady-state thermal resistance is not enough for finding peak junction temperatures for pulsed current applications. Using the peak power value, results in overestimating the actual junction temperature, while using the average power value underestimates the peak junction temperature at the end of the power pulse. The reason for the discrepancy lies in the thermal capacity of the semiconductor and its housing (i.e., its ability to store heat and to cool down before the next current pulse). Fig. 10.74 presents the modified thermal equivalent circuit when transient thermal analysis is needed.

Fully Controlled Semiconductor Devices

759

Figure 10.73 Proposed heat sink that can be used in this example. (a) Type and dimensions of the heat sink; (b) heatingelength characteristics of the heat sink. Tj

R jc p(t)losses

Ts

Tc

Cj

R cs Cc

Cs

R sa Ta

Figure 10.74 Transient thermal resistance equivalent model.

The normally distributed thermal capacitances have been lumped into single capacitors labeled Cj, Cc, and Cs. This simplification assumes current is evenly distributed across the silicon crystal and that the only significant power losses occur in the junction. When a step of heating power, Plosses(max), is introduced at the junction of the semiconductor, Tj will rise exponentially to some steady-state value dependent upon the response of the thermal network. When in a time instant the current pulse becomes zero and, consequently, the power losses become zero, Tj will decrease exponentially until the next current pulse. The transient thermal impedance between junction and case at time t is given by: Zjc ðtÞ ¼

DTjc ðtÞ PlossesðmaxÞ

(10.24)

760

Power Electronics and Motor Drive Systems

P Plosses(max) Plosses(av) =

T

Heating Cooling phase phase Tj

Tc

tp

tp Ts

Plosses(max)

t

Plosses(max) × Z jc Plosses(av) × R sa

Ta 0

t

Figure 10.75 Variation of junction and case temperature when the pulse time is small compared to thermal time constant of the heat sink.

where DTjc(t) ¼ difference of temperature between junction and case at a given time t; Plosses(max) ¼ amplitude of the step power losses. The junction to case temperature is always assumed to be constant under transient operation. This is valid in practice when the power pulse width is less than about 1 s. As can be seen from Fig. 10.75, Tjc does not change significantly under this condition. This is because heat sinks have a high thermal capacity and, consequently, a high thermal time constant. Thus, Eq. (10.24) is valid for transient operation when the pulse time is less than 1 s. Therefore, using Eq. (10.24) the value of Tj can be calculated as follows: Tj ¼ PlossesðmaxÞ Zjc þ Tc

(10.25)

If the power pulse width tp exceeds 1 s (see Fig. 10.76), the semiconductor device is temporarily in thermal equilibrium since such a pulse width is significantly greater than the thermal time constant of the semiconductor. Therefore, in this case Eq. (10.24) becomes: Tj ¼ PlossesðmaxÞ Rjc þ Tc

(10.26)

The following expression describes how to select the heat sink that keeps the junction at/or below a given temperature: Rsa ¼

Tj  Ta PlossesðmaxÞ

 Zjc  Rcs

(10.27)

Fully Controlled Semiconductor Devices

761

P Plosses(max)

tp

T

t

Tj

Plosses(max) × R jc Tc

Plosses(av) × Zsa Ta 0

t

Figure 10.76 Variation of junction and case temperature when the pulse time is not small compared to thermal time constant of the heat sink.

Example 10.7 Calculate the junction temperature of the IGBT type SGP20N60 under the following operating conditions: D ¼ duty cycle ¼ 0.5 fs ¼ switching frequency ¼ 75 kHz Ta ¼ ambient temperature ¼ 40 C Tc ¼ case temperature ¼ 80 C Plosses(max) ¼ 45 W K Rcs ¼ thermal resistance between case and heat sink ¼ 0.45 W C K is equivalent to W W

Fig. 10.77 presents the thermal impedance of the IGBT type SGP20N60 for different duty cycles given by the manufacturer.

Solution Since the operating duty cycle is 0.5 and the switching frequency 75 kHz, then the pulse width of the power losses is given by: D¼

ton ¼ Ts

tp ¼ 0:5 1 75  103

or tp ¼ 6:67 ms

762

Power Electronics and Motor Drive Systems

Figure 10.77 Thermal impedance of IGBT type SGP20N60 for different duty cycles (provided by the manufacturer).

From Fig. 10.77, for tp ¼ 6.67 ms and D ¼ 0.5 the thermal impedance is    Zjc ¼ 0:35 WK. At this point it should be mentioned that WK is equivalent to WC. Therefore using Eqs. (10.26) and (10.27), the following results are obtained:   C Tj ¼ ð45WÞ 0:35 þ 80 C ¼ 95:75 C W Rsa ¼

C C C 95:75 C  40 C  0:35  0:45 ¼ 0:44 45 W W W W

Therefore, from the heat sinks of Fig. 10.70 according to their specifications, which are given in Table 10.5, the best choice is a heat sink with higher dimensions of no. 8.

Fully Controlled Semiconductor Devices

763

Example 10.8 For the step-down converter shown below, the following parameters are given: IGBT Conduction voltage ¼ 2 V Conduction resistance ¼ 3 mU Won ¼ 20 mJ (measured at 400 A with 600 V dc supply) Woff ¼ 40 mJ (measured at 400 A with 600 V dc supply) Thermal resistance junction case 0.05 K/W Diode Conduction voltage ¼ 2.5 V Conduction resistance ¼ 2 mU Thermal resistance junction case ¼ 0.1 K/W a) Calculate the power dissipated in the IGBT and diode. b) Estimate the junction temperature of the IGBT and diode for a case temperature of 60 C. ii

S

fs=13.266 kH 600 V

10 mH

is iD

D

io

iL iC

Co

+ −

RL

Vo = 198 V

Solution 1 J ¼ 1Ws D¼

Vo 198 ¼ 0:33 ¼ Vin 600

Assuming that the semiconductor switch operates with a duty cycle D ¼ 0.33 and switching frequency 13.266 kHz, then the power losses of the IGBT are: Pturn-on ¼ Wturn-on  f s ¼ 20 mJ  13266 Hz ¼ 265:32 W Pturn-off ¼ Wturn-off  f s ¼ 40 mJ  13266 Hz ¼ 530:64 W

764

Power Electronics and Motor Drive Systems

Pconduction ¼ Wconduction  f s ¼ Is  Vconduction  ton  f s ¼ Is  Vconduction  ton 

1 ¼ Is  Vconduction  D Ts

¼ 400 A  2 V  0:33 ¼ 264 W Therefore, the total power losses of the IGBT are: PtotalðIGBTÞ ¼ Pturn-on transition þ Pturn-off transition þ Pon-state ¼ 265:32 W þ 530:64 W þ 264 W ¼ 1060 W Moreover, the power losses of the diode are calculated as follows: VF ¼ Total forward voltage drop across the diode ¼ diode; s resistance voltage drop þ voltage drop across drift region ¼ VR þ VJ ¼ 2  103  400 þ 2:5 V ¼ 3:3 V The conduction losses of the diode are given by: PconductionðdiodeÞ ¼ ID  VF  DD ¼ ID  VF  ð1  DÞ ¼ 200  3:3ð1  0:33Þ ¼ 224:4 W where DD ¼ diode duty cycle. Also, it is known that: PD ¼ dissipated semiconductor losses ¼

maximum junction temperature  case temperature TjðmaxÞ  Tc ¼ thermal resistance between junction and case Rjc

Therefore, the junction temperature of a semiconductor device is given by: TjðmaxÞ ¼ PD Rjc þ Tc Therefore, the junction temperature of the IGBT is: TjðmaxÞIGBT ¼ PtotalIGBT Rjc þ Tc ¼ ð1060WÞð0:05K=WÞ þ 60 C ¼ 113 C and the junction temperature of the diode is: TjðmaxÞðdiodeÞ ¼ PconductionðdiodeÞ Rjc þ Tc ¼ ð224:4WÞð0:1K=WÞ þ 60 C ¼ 82:44 C

Fully Controlled Semiconductor Devices

765

The total power that a power device can dissipate is based on the maximum junction temperature and the thermal resistance Rqjc at a case temperature of 25 C.

10.9

Protection Circuits (Snubbers) for Power Semiconductor Devices

Power semiconductor devices need protection circuits, which are called snubber circuits, because they have a limited SOA at turn-on and turn-off transitions. The objective of snubber is to help the semiconductor device during switching transitions to survive the voltage and current stresses that can cause its failure. These stresses are caused by the interruption of the current at turn-off and the collapse of the voltage at turn-on. A useful plot that illustrates how switching takes place from on to off and vice versa is called a switching trajectory, which is simply a plot of the semiconductor switch current is versus the voltage across the switch vs. Fig. 10.78 shows the switching trajectories of PWM hard switching and soft switching techniques. Moreover, Fig. 10.78 illustrates the difference between the PWM hard switching with and without snubber protection. Overvoltage at switching-off and overcurrent at switching-on often occur, and it is important to ensure both the on and off switching trajectories stay within the SOA of the switch, otherwise the switch may fail. Fig. 10.79 shows the voltage waveform across a semiconductor switch without and with a snubber. As can be seen from Fig. 10.79, by applying a snubber across the semiconductor switch or device the voltage spike and the ringing have been reduced considerably. The functions and classifications of snubbers are as follows: Functions • Limiting voltages applied to devices during turn-off transients. • Limiting device currents during turn-on transients. • Limiting device current rising rate (di/dt) at device turn-on. PWM switching without snubber

iswitch SOA on

Ion

off

sw

off

ft

on

So

f

Ideal on switch off 0

on

f of

of

PWM switching with snubber

itc hin

g o n

Voff

vswitch

Figure 10.78 Voltage and current switching trajectories of pulse width modulation hard switching with and without snubber.

766

Power Electronics and Motor Drive Systems

Figure 10.79 Voltage waveforms across a semiconductor device. (a) Without a snubber; (b) with a snubber. • Limiting the rate of rise (dv/dt) of voltages across devices during device turn-off. • Limiting EMI. • Shaping the switching trajectory of the device. Classification 1) Unpolarized series ReC snubbers, which are the simplest snubber, is connected across the semiconductor device. Are used to protect diodes and thyristor. Fig. 10.80 shows such snubbers applied to a thyristor and to a diode. 2) Polarized ReC turn-off snubbers (Table 10.6): • Used as turn-off snubbers to shape the turn-on switching trajectory of semiconductor switches. • Used as overvoltage snubbers to clamp voltages applied to the semiconductor switches to safe values. • Used for limiting the semiconductor device dv/dt at turn-off. 3) Polarized LeR turn-on snubbers (Table 10.6): • Used as turn-on snubbers to shape the turn-off switching trajectory of semiconductor switches. • Used for limiting the semiconductor device di/dt at turn-on.

10.9.1

Thyristor and Diode Snubber Protection

10.9.1.1 Turn-Off Snubber for Overvoltage and dv/dt Protection dv across a thyristor As it was mentioned in Chapter 3, if the rate of rise of voltage dt   dv during device turn-off goes over a critical value , which is given by the mandt max ufacturer’s specifications, then the thyristor randomly might go to the conduction state

Q

Rs

D

Cs

Figure 10.80 Unpolarized series RseCs turn-off snubbers.

Rs Cs

Fully Controlled Semiconductor Devices

Table 10.6

767

Classification of snubbers Turn-on (series) snubber

Turn-off (parallel) snubber

Unpolarized S

R s Ls

Rs Cs

S

Polarized Rs Ds

S

Ls

Rs

Ds

Cs

S

Combined

Polarized turn-on snubber

Ri

Ls

Di

S Gating signal

Rs

Ds

Cs Polarized turn-off snubber

even if it was in the reverse-blocking state. To avoid this phenomenon and any overvoltages across the thyristor an RseCs snubber circuit can be applied across the thyristor as shown in Fig. 10.81(a). The influence of the RseCs circuit depends on the value of the inductance Ls which is the inductance of the cables and the inductance connected in series with the thyristor to limit the rate of rise of the thyristor di current . dt Assume that the thyristor was contacting and by an external commutation circuit is forced to enter the commutation state (i.e., the off-state) and the input voltage of the circuit of Fig. 10.81(a) at that instant is a step voltage of value Vstep. As can be seen from Fig. 10.81(b), the forward current iA starts decaying by a slope of Vstep/Ls and reaches the maximum recovery current, IRM which is the initial current that will flow through the snubber circuit. At time instant t ¼ trr the thyristor turns off and the snubber circuit is activated. Fig. 10.82 shows the equivalent circuit of the circuit of Fig. 10.81(a) right after the thyristor is turned off.

768

Power Electronics and Motor Drive Systems

(a)

Turn − on snubber

iL

vL Vstep

vi

Turn − off snubber

Ls iA

is Rs

Q

vs

0

Cs

(b) Thyristor current during conduction, iA Thyristor commutation current Vstep ⎛ di⎞ ⎜dt⎟ = − L ⎝ ⎠c s

IA

t rr

0

t Snubber current

I RM

Vp

vs (t)

Vstep

Vstep

I RM R s

0

t = t1

t=0

t

Figure 10.81 Thyristor or diode RseCs snubber and generated waveforms during commutation. (a) Thyristor snubber circuit; (b) waveforms. iL

Ls

is

vL vi = Vstep

Q

Rs

vs

Cs

Figure 10.82 Equivalent circuit of the circuit of Fig. 10.81(a) when the thyristor is turned off and capacitor starts charging.

According to Fig. 10.82, when the thyristor at the end of the reverse recovery time trr will go to the off-state the capacitor will start charging and the following equations hold: Ls

dis 1 þ R s is þ Cs dt

Z is dt þ vCs ðt ¼ 0þÞ ¼ Vstep

(10.28)

Fully Controlled Semiconductor Devices

vs ðtÞ ¼ Vstep  Ls

769

dis dt

(10.29)

with initial conditions according to Fig. 10.81(b) is ðt ¼ 0þÞ ¼ IRM and vCs ðt ¼ 0þÞ ¼ 0

(10.30)

Solving Eq. (10.28) using the initial conditions of Eq. (10.30), then for an underdamped case the voltage across the thyristor during the charging mode of the capacitor is given by the following equation:   x IRM sinud t ext þ sinutext vs ðtÞ ¼ Vstep  ðVstep  Rs IRM Þ cosud t  ud Cs ud for an underdamped case z ¼

x <1 ud (10.31)

where Vstep ¼ amplitude of the voltage pulse applied to the snubber. 1 uR ¼ resonance frequency of the snubber ¼ pffiffiffiffiffiffiffiffiffiffi LS Cs

(10.32)

Rs 2Ls

(10.33)

x ¼ decrement factor ¼

(Is a measure of how fast the transient response will disappear after the stimulus has been removed). z ¼ damping factor ¼

x Rs ¼ pffiffiffiffiffiffiffiffiffiffiffiffi uR 2 Ls =Cs

(10.34)

(Determines the type of transient that the circuit will exhibit). (z < 1 underdamped, z ¼ 1 critically damped, and z > 1 overdamped). ud ¼ damped resonance frequency or ringing frequency ¼ uR

qffiffiffiffiffiffiffiffiffiffiffiffiffi 1  z2 (10.35)

1 uR Ls 1 Q ¼ circuit quality factor ¼ ¼ ¼ uR Rs Cs Rs Rs

rffiffiffiffiffi Ls Cs

(10.36)

770

Power Electronics and Motor Drive Systems

IRM ¼ thyristor maximum reverese recovery current ¼

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2Qrr ðdi=dtÞc

(10.37)

  di ¼ thyristor current rate of change during commutation dt c Z

trr

Qrr ¼ reverse recovery charge ¼

ir dt mCb

(10.38)

0

Using Eq. (10.31) the initial voltage across the snubber and, consequently, across the thyristor at the end of the reverse recovery time is given by: vs ðt ¼ 0þÞ ¼ Vstep  ðVstep  Rs IRM Þ ¼ Rs IRM

(10.39)

Differentiating Eq. (10.31) the rate of rise of the voltage across the thyristor is found and is given by: " # dvs ðtÞ u2d  x2 ¼ ðVstep  Rs IRM Þ 2x cosud t þ sinud t ext dt ud þ

  IRM x sinud t ext cosud t  ud C

for underdamped case z ¼ Using Eq. (10.40) the initial

(10.40)

x <1 ud

dvs ðtÞ is given by: dt

dvs ðt ¼ 0þÞ IRM ðVstep  Rs IRM ÞRs IRM ¼ ðVstep  Rs IRM Þ2x þ ¼ þ dt Cs Ls Cs   2 ¼ Vstep uR 2z  4z c þ c

(10.41)

where IRM c ¼ initial current factor ¼ Vstep c2 ¼

rffiffiffiffiffi Ls I RM ¼ Cs IP

Inductor initial energy ð1=2ÞLI2RM ¼ Capacitor final energy ð1=2ÞCs V2step

(10.42)

(10.43)

For positive dvs/dt 2z  4z2c þ c > 0 and, consequently: z<

1þ

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1 þ 4c2 4c

(10.44)

Fully Controlled Semiconductor Devices

771

As can be seen from Fig. 10.81(b), the peak voltage across the snubber and, consequently, across the thyristor takes place at t ¼ t1 and at that time instant dvs/dt ¼ 0. Therefore, by setting Eq. (10.40) equal to zero the value of the time instant is found as follows: IRM Cs tanud t1 ¼  2 2 u x aIRM ðVstep  Rs IRM Þ d  ud Cs ud ðVstep  Rs IRM Þ2x þ

(10.45)

The peak voltage across the snubber and, consequently, across the thyristor can be found using the equation: Vp ¼ vs ðt ¼ t1 Þ

(10.46)

Therefore, using Eqs. (10.31) and (10.46) the peak reverse voltage is given by: sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2xðVstep  Rs IRM ÞIRM I2RM Vp ¼ Vstep þ ext1 ðVstep  Rs IRM Þ2   u2R Cs u2R C2s (10.47) As can be seen from Eq. (10.47), the value of the peak voltage depends on the rffiffiffiffiffi x IRM Ls I RM damping factor z ¼ and the initial current factor c ¼ . For a ¼ uR Vstep Cs IP given value of c, there is an optimum damping factor zoptimum, which minimizes the peak voltage. Fig. 10.83 shows a family of optimized curves, which were presented by W. McMurray, that can be used to obtain the best possible snubber RseCs values for a thyristor or a diode.

10.9.1.2 Turn-On Snubber for Thyristor Overcurrent and di/dt Protection As discussed in Chapter 3 in connection with turn-on switching of a thyristor, the anode current, just after turn-on is restricted to a small area of the cathode which increases with time at a finite rate. Now, if the rate of rise of anode current diA/dt is higher than that rate the current density in a portion of the cathode cross section will keep on increasing leading to the formation of local hot spots. The device may be destroyed in the process. The manufacturers usually specify a limiting value of diA/dt (20e500 A/ms) which should not be exceed to avoid this type of failure. In a thyristor converter circuit the rate of rise of anode current is restricted by connecting an inductor of appropriate value in series with the thyristor. This is called the diA/dt limiting inductor. Fig. 10.84(a) shows the conventional turn-on snubber circuit for a thyristor which equally can be applied to other semiconductor devices in case an inductive turn-on snubber is required. Fig. 10.84(b) shows the equivalent circuit of Fig. 10.84(a) when the thyristor is in the turn-on transition and the capacitor is discharging through the thyristor and the resistor Rs.

772

Power Electronics and Motor Drive Systems

Figure 10.83 Optimum thyristor snubber parameters for RseCs calculation. Presented by W. McMurray.

(a)

iL

Turn − on snubber

vL

is

iA

Vstep vi

Turn − off snubber

Ls

Rs

Q

0

vs

Cs

(b)

iL

Ls iA

vi = Vstep

Rs Q

Cs

Figure 10.84 Snubber circuit and the equivalent circuit when the thyristor is turned on. (a) Snubber circuits; (b) equivalent circuit when the thyristor is turned on.

Fully Controlled Semiconductor Devices

773

Example 10.9 The maximum recovery current of a thyristor is IRM ¼ 10 A and the inductance of the circuit of Fig. 10.84(a) is Ls ¼ 10 mH. The input step voltage of the circuit is 300 V. If it is necessary to limit the peak transient voltage to 1.3 of the input voltage, determine the following: a) The optimum initial current factor and the optimum damping factor. b) The snubber capacitance Cs and resistance Rs. c) The initial reverse voltage.

Solution



a) From Fig. 10.83, for

Vp Vstep

 ¼ 1:3, the following optimum factors are obtained: optimum

coptimum ¼ 0.7, zoptimum ¼ 0.42. b) Using Eq. (10.42)

Cs ¼ Ls

IRM coptimum $Vstep

!2



2 10 ¼ 10 mH ¼ 0:022 mF 0:7$300

Moreover, using Eq. (10.34) the snubber resistance is calculated: sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffiffi Ls 10 mH ¼ 17:9 U ¼ 2  0:42 Rs ¼ 2zoptimum 0:022 mF Cs c)

uR ¼ resonance frequency of the snubber 1 1 rad ¼ pffiffiffiffiffiffiffiffiffiffiffi ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ¼ 2:13  106 s 10 mH  0:022 mF LS C s f R ¼ 2p  2:13  106 ¼ 13:37 MHz   dvs =dt ¼ 0:87 From Fig. 10.83, for coptimum ¼ 0:7 Vstep uR optimum Therefore: dvs V V ¼ 0:87Vstep uR ¼ 0:87  300  2:13  106 ¼ 555:93  106 ¼ 555:93 dt s ms

d) Using Eq. (10.39), vs(t ¼ 0þ) ¼ RsIRM ¼ 17.9  10 ¼ 179 V.

The figure below shows the simulation results of Example 10.9 where a diode is used which has the same turn-off mode as a thyristor. As can be seen from this figure the theoretical results are in close agreement with the simulation ones.

774

Power Electronics and Motor Drive Systems

Simulation results of Example 10.9

Fully Controlled Semiconductor Devices

775

10.9.2 Snubbers for IGBTs 10.9.2.1 Polarized Turn-Off Snubber Fig. 10.85 shows a step-down converter (Chapter 7) and the IGBT switching characteristics which will be used to explain the operation of turn-off snubber. To simplify the turn-off analysis of the circuit of Fig. 10.85(a) the stray circuit inductances are ignored. Moreover, as can be seen from Fig. 10.85(b), just before the turn-off transition, the load current is assumed to have constant value Io and the IGBT collectore emitter saturation voltage is equal to zero. Fig. 10.86 shows the converter of Fig. 10.85 with the addition of an IGBT turn-off RsCsDs snubber. As it was mentioned before the turn-off snubber is used to reduce the power losses and the rate of rise of the voltage across the semiconductor switch during the turn-off transition. Moreover, Fig. 10.87 shows the currents in the circuit at turn-off and the respective equivalent circuit. At turn-off the snubber capacitor is charged to a

ii

(a)

iQ Q

vQ

Vin

io

Df

Io

LL

Freewheeling diode

RL

i Df

(b)

turn-off

Io

pQ (t)=vQ (t)iQ (t)

t rv

vQ

vQ

Vin

iQ

t c(off) t fi

= t rv +t fi

turn-on iQ

Vin

t ri

L o a d

Io

t c(on) = t ri = t fv

t

t fv

PQ(peak)

Area=Wc(off) energy losses

Area =Wc(on) energy losses t

Figure 10.85 Step-down converter without snubber. (a) Power circuit; (b) IGBT current and voltage waveforms at turn-off and turn-on transitions ignoring tail current and overshoots.

776

Power Electronics and Motor Drive Systems

ii iQ Q

Rs

vQ

Vin

Ds

vs

Cs i Cs

i o = Io

LL

Df

RL

i Df

L o a d

Figure 10.86 Step-down converter with an IGBT turn-off snubber.

(a)

(b)

ii iCs Rs

Q

Q

Ds

iQ

Vin

Cs

Df

Vin

iQ

Ds Cs iCs = Io − iQ

i o = Io

LL L o

R L da

Df

Io

Figure 10.87 Currents during turn-off transition and the respective equivalent circuit.

maximum value, which is for this circuit equal to the converter input voltage Vin, and is discharged to zero voltage during the turn-on transition. At turn-off transition of the IGBT due to the presence of the RsCsDs snubber, the IGBT current iQ starts decreasing with a constant diQ/dt and Io  iQ flows into the capacitor through the snubber diode Ds. During the turn-off transition the freewheeling diode Df is reverse biased and is not conducting. Fig. 10.88 shows the turn-off transition waveforms of the circuit of Fig. 10.86 with a snubber with increasing values of capacitance. As can be seen from Fig. 10.88, although the fall time of the IGBT device, tf is constant, the snubber capacitor charging time tcharge and, consequently, the energy stored in the capacitor depends on the capacitance value. When the capacitance value increases the charging time and the stored energy of the capacitor are increased. However, as can be seen from Fig. 10.89, the turn-of power losses of the IGBT are decreased when the values of capacitance are decreased.

Fully Controlled Semiconductor Devices

777

(a)

iQ

(b)

(c)

iQ

Io

iQ

Io

i Df

0

i Df

i Df

0

t fi

0

t fi

t

t fi

Energy stored in the capacitor during turn-off iCs

iCs

iCs

Vin

Vin

vCs

Vin

vCs 0

t

t charge

t charge

t charge

Cs small

vCs Cs = Cs1

0

0

Cs large

t

Figure 10.88 Turn-off waveforms of the circuit of Fig. 10.86 with a turn-off snubber with increasing values of capacitance. (a) With small capacitance value that achieves tfi > tcharge; (b) with capacitance value that achieves tfi ¼ tcharge; (c) with large capacitance value that achieves tfi < tcharge.

(a) i

Io

t f >t charge

(b)

Vin

vCs

Q

tf t charge

vCs

Vin

t f =t charge

t

Io

pQ (t)

0

iQ

t

0

(c) iQ

vCs

Io

Vf

t f
tf

t charge

Vin t

Figure 10.89 IGBT turn-off power losses with a snubber with increasing values of capacitance (the tail of iQ and overshoots have been neglected).

Using Figs. 10.87 and 10.88 the IGBT and snubber capacitor currents are given by the following equations: 8   > 1 > < Io 1  for 0  t  tfi tfi iQ ðtÞ ¼ (10.48) > > :0 for t  t fi

778

Power Electronics and Motor Drive Systems

iCs ðtÞ ¼

8 > > I t > > Io  iQ ¼ o > > tf > < > Io > > > > > > :0

for 0  t < tf (10.49)

for tf  t < tcharge for t  tcharge

where Io ¼ constant load current; tfi ¼ IGBT current fall time; tcharge ¼ capacitor charge time. The value of the snubber capacitor is chosen on the basis of the desired voltage at the instant the IGBT current reaches zero. According to Fig. 10.88(d) the capacitor voltage is given by: 8 > > > Z t Z t > > > 1 1 Io t Io t2 > > i dt ¼ dt ¼ Cs > > Cs 0 Cs 0 tfi 2Cs tfi > > > < Z t vCs ðtÞ ¼ 1 Io Io tfi > Io dt þ vCs ðtfi Þ ¼ ðt  tfi Þ þ > > Cs tfi Cs 2Cs > > > > > > > Vin > > > :

for 0  t  tfi for tfi  t  tcharge for t  tcharge (10.50)

If the semiconductor switch current goes to zero before the snubber capacitor is fully charged, then using the first part of Eqn (10.50) the capacitor voltage at the instant of current fall time can be found and is given by: Vf ¼ vCs ðtfi Þ ¼

Io t2fi Io tfi ¼ 2Cs tfi 2Cs

(10.51)

Therefore, using Eq. (10.51) the value of the snubber capacitance is given by:

Cs ¼

Io tfi 2Vf

(10.52)

where Vf ¼ desired capacitor (and IGBT) voltage when IGBT current reaches zero.

Fully Controlled Semiconductor Devices

779

Using Fig. 10.85(b) the power losses at turn-off of the IGBT without a snubber are given by: WcðoffÞ Area of the triangle 12Vin Io ðtrv þ tfi Þ ¼ ¼ Ts Ts Ts 1 ¼ Vin Io ðtrv þ tfi Þf s 2

PQðoffÞðwithout snubberÞ ¼

(10.53) Using Fig. 10.89(b) and Eqs. (10.48) and (10.50), the power losses of the IGBT at turn-off when the snubber is added is given: PQðoffÞðwith nubberÞ ¼

1 Ts

Z

tfi

vCs iQ dt ¼

0

1 Ts

Z tf  0

   Io t2 1 Io 1  dt tf 2Cs tfi (10.54)

2

I t2 f s ¼  o fi 24Cs

for tfi  tcharge

The final voltage across IGBT voltage is selected according to the topology where the IGBT is used. For example, in a step-down converter or in a two-level voltage source inverter the voltage across the IGBT is chosen to be equal to the input voltage Vin. However, for some other topologies such as flyback or forward dcedc converters, as it was mentioned in previous chapters, the voltage across the IGBT should be 2Vin. The capacitor Cs is discharged during the turn-on transition through the IGBT and the resistor Rs. Fig. 10.90 shows the currents of the circuit and the respective equivalent circuit. The value of the snubber resistor Rs generally is chosen so that the time constant for resetting the capacitor voltage to be less than or equal to one-fifth of the conduction time ton of the IGBT switch. Therefore: ss ¼ snubber time constant ¼ Rs Cs 

ton 5

(10.55)

ii iQ Q

Vin

iCs

Rs Cs

Df

Ds

Vin

Q

Rs

iQ

Cs iCs = Io − iQ

io = Io LL L o

R L da

Df

Io

Figure 10.90 Currents during turn-on transition and the respective equivalent circuit.

780

Power Electronics and Motor Drive Systems

or Rs 

ton 5Cs

(10.56)

The capacitor discharges through the resistor and the IGBT during the turn-on transition. The energy stored in the capacitor is given by: WCs ¼

1 Cs V2in 2

(10.57)

The most of this energy is dissipated in the resistor during the turn-on transition. Therefore, the power dissipated in the snubber resistor is given by: PRs ¼

WCs Ts

1 Cs V2in 2 ¼ Ts ¼

(10.58)

1 Cs V2in f s 2

where fs ¼ switching frequency; Vin ¼ input dc voltage. From Fig. 10.89 and Eq. (10.55), it can be concluded that when the value of the snubber capacitance increases the IGBT turn-off power losses decrease at the expense of the power dissipated in the snubber resistor. The total turn-off power losses of the IGBT are the sum of the IGBT and snubber power losses. In case there is a stray inductance in the input dc link, voltage overshoots will occur at IGBT turn-off given by: vovershoot ¼ Lstray

di dt

(10.59)

These voltage overshoots may destroy the IGBT because they are added to the dc input voltage and may led to vCE > vCE(max) vCE ¼ vovershoot þ Vin

(10.60)

In this case the snubber capacitor works as a low-pass filter and eliminates part of the overshoot voltage.

Fully Controlled Semiconductor Devices

781

Example 10.10 For the step-down circuit of Fig. 10.85(a), the following specifications are given: Vin ¼ 200 V, Io ¼ 10 A, fs ¼ 100 kHz, D ¼ 0.5, tc(off) ¼ IGBT turn-off time ¼ 0.6 ms. a) Calculate the turn-off losses of the IGBT without a snubber and using the criterion that the IGBT voltage reaches its final value Vin in 0.1 ms. b) Design a turn-off snubber using the criterion that the IGBT voltage reaches its final value at the same time that the IGBT current reaches zero. c) When the snubber is applied to IGBT calculate the IGBT turn-off losses and the power dissipated in the snubber resistor.

Solution a) According to the above specifications the IGBT switching characteristics and power losses before the snubber is added are shown in Fig. 10.91. As can be seen from Fig. 10.91, during turn-off transition the IGBT reaches 200 V while the current remains to have a value of 10 A which results to peak instantaneous power of (200)(10) ¼ 2 kW. According to Fig. 10.91 the energy losses of the IGBT during turn-off transition, are given by: Z WQðoffÞ ¼ IGBT turn-off transition energy losess ¼ 0

tcðoffÞ

1 vQ ðtÞiQ ðtÞdt ¼ Vin Io tcðoffÞ 2

  1 ¼ ð200Þð10Þ 0:6  106 ¼ 600 mJ or mW s 2

vQ 200V

iQ

10A

t c(off) = t rv +t fi =0.6μs t fi = 0.5μs

t rv = 0.1μs

t

PQ(peak) = (200)(10) = 2kW

WQ(off)

0.6μsec

t

Figure 10.91 IGBT current and voltage turn-off waveforms without snubber.

782

Power Electronics and Motor Drive Systems

Therefore, the turn-off transition power losses consumed on the IGBT are: WQðoffÞðwithout snubberÞ ¼ WQðoffÞðwithout snubberÞ $f s Ts   ¼ 600  106 ð100000Þ ¼ 60 W

PQðoffÞðwithout snubberÞ ¼

b) Using Eq. (10.52) the snubber capacitance is:   Io tfi ð10Þ 0:5  106 Cs ¼ ¼ ¼ 0:0125 mF 2Vf ð2Þð200Þ Since the duty cycle D ¼ 0.5, then the time interval of the conduction time of the IGBT ton is 50% of the switching period and is given by: Ts ¼ switching period ¼

1 1 ¼ ¼ 10 ms f s 100  103

ton ¼ DTs ¼ ð0:5Þð10 msÞ ¼ 5 ms Using Eq. (10.56) the snubber resistor value is: Rs 

ton 5  106 ¼ 80 U ¼ 5Cs 5ð0:0125  106 Þ

Therefore: s ¼ RsCs ¼ (80)(0.0125 mF) ¼ 1 ms (capacitor discharging in 5s ¼ 5 ms). c) Using Eq. (10.56) the power dissipated by the snubber resistor during turn-off transition is given by: PRs ¼

   1 1 Cs V2in f s ¼ 0:0125  106 ð200Þ2 100  103 ¼ 25 W 2 2

Using Eq. (10.54) the turn-off power losses of the IGBT with a snubber are given by: PQðoffÞðwith snubberÞ ¼

 2   2 Io t2fi f s 102 0:5  106 100  103 ¼ 8:3 W ¼ 24Cs 24ð0:0125  106 Þ

Therefore: Total power losses at turn-off ¼ PQðoffÞðwith snubberÞ þ PRs ¼ 8:3 þ 25 ¼ 33:3 W which has been reduced from 60 W (i.e., almost by half) when snubber circuit was not used.

Fig. 10.92 shows the simulation results of Example 10.10. As can be seen from Fig. 10.92(e) and (f), when the snubber is used the dvQ/dt is increased and diQ/dt is decreased resulting to lower IGBT turn-off power losses.

Fully Controlled Semiconductor Devices

783

Figure 10.92 Simulation results of Example 10.10. (a) IGBT gating signal; (b) snubber capacitor current; (c) snubber capacitor voltage; (d) snubber resistor current; (e) IGBT voltage and current turn-off waveforms with snubber (iQ ¼ iin  iCs); (f) IGBT voltage and current turnoff waveforms without snubber (iQ ¼ iin).

784

Power Electronics and Motor Drive Systems

Figure 10.92 cont’d.

10.9.2.2 Polarized Turn-On Snubber Since there is a large FBSOA for most power semiconductor switches including MOSFETs, GTOs, and IGCTs, the turn-on snubbers are used only to reduce the turnon switching power losses at high switching frequencies. The turn-on snubber is employed to decrease the voltage across the switching device, the power losses, and the over-current (due to the reverse recovery of the freewheeling diode Df) during turn-on. Fig. 10.93 shows a step-down converter that employs only a turn-on snubber. As can be seen the turn-on snubber is in series with the power semiconductor switch. i DLs D Ls R Ls

ii Ls

iQ Q

Vin

vQ io = Io

LL

Df i Df

RL

L o a d

Figure 10.93 Step-down converter that employs only a turn-on snubber.

Fully Controlled Semiconductor Devices

785

(a) vQ iQ Vin

Io

t

t ri t fv t c(on)

WQ(on)

t

(b)

vQ

Vin

t ri t fv

(c) vQ

iQ

iQ Vin

Io

t t ri

Io

t

t fv

WQ(on)

WQ(on)

t

t

Figure 10.94 Turn-on waveforms of the circuit of Fig. 10.93 with a turn-on snubber with increasing values of snubber inductance Ls. (a) Without a turn-on snubber; (b) with small snubber inductance; (c) with large snubber inductance.

Fig. 10.94 shows the turn-on waveforms of the circuit of Fig. 10.93 with a turn-on snubber with increasing values of the snubber inductance Ls. As can be seen from Fig. 10.94, increasing the snubber inductance value decreases the turn-on losses of the IGBT. At turn-on the inductor Ls controls the rate of rise of the switch current and supports a portion of the input voltage Vin while the switch voltage falls. The snubber energy

stored during turn-on 12 Ls i2 is dissipated in the resistor RLs during switch turnoff. The snubber diode DLs is off during turn-on, while the freewheeling diode Df is on. The inductor energy during turn-on must be discharged into the resistance RLs and diode DLs during turn-off, and this release should be done in time duration lower than the IGBT toff, to allow energy storage at the next turn-on state. The discharge time of an inductor is approximately three times the time constant of an RL circuit. Therefore, the following equations hold: vL ¼ snubber inductor voltage ¼ Ls s ¼ RL circuit time constant ¼ RLs >

3Ls toff

Ls RLs

diL dt

(10.61)

(10.62)

(10.63)

786

Power Electronics and Motor Drive Systems

Ls

R Ls

Ds2

Rs

Vin

Ds1

Cs LOAD

Df

Figure 10.95 Step-down converter that employs turn-off and turn-on snubbers.

The use of a turn-on snubber will generate during turn-off an overvoltage across the semiconductor switch which is given by: b Qðturn-offÞ ¼ RLs Io V

(10.64)

Therefore, according to the above equations a large inductance will result in lower turn-on losses, but it will create an overvoltage during turn-off and, consequently, higher losses at turn-off. Therefore, LS and RLs must be selected based on the tradeoffs mentioned above. Since the turn-on snubber inductance must carry the load current, which this snubber is expensive, it is rarely used alone. However, if the turn-off snubbers are to be used in a power electronics bridge configuration, then the turn-on snubbers are used. Fig. 10.95 shows a step-down converter that employs both snubbers.

10.9.3

Power Semiconductor Devices Connected in Series and in Parallel

10.9.3.1 Diodes and Thyristors Connected in Series and in Parallel When the required voltage rating exceeds the power diode voltage rating, a number of diodes can be connected in series to share the forward and reverse voltage. It is necessary that series devices have the same part number, and it is also highly recommended to use power devices from the same production lot. As it is not possible to have diodes of completely identical characteristics, deviation in characteristics lead to the following two major problems during series connections of the diodes: i) Unequal distribution of voltage across diodes. ii) Difference in operating temperature.

Fully Controlled Semiconductor Devices

(a)

787

(b)

Cs

Ds Rs

Cs

Cs

Ds Rs

Cs

Snubber resistance

Re

Q2

Q1 Ds Rs

Ds Rs

Re

Re

Static equalization resistance

Dn

D2

D1 Ds Rs

Re

Re

Re

Qn Cs

Ds Rs

Cs

Figure 10.96 Connecting diodes and thyristor in series. (a) Diodes in series; (b) thyristors in series.

Care must be taken to share the voltage equally. For steady-state conditions, voltage sharing is achieved by using a voltage equalization resistance across each diode. The snubber circuit of each diode is providing transient voltage sharing. The same voltage equalization procedure is used also for thyristors in series. Fig. 10.96 shows how diodes and thyristors with same specifications can be connected in series. To calculate the value of the equalization resistance and the new value of the snubber capacitance (due to the series connection), the following equations can be used for diodes and thyristor: Re ¼ equalization resistance ¼

Cs ¼

nVRRM  Vstring ðn  1ÞDIRMðmaxÞ

ðn  1ÞDQsðmaxÞ nVRRM  Vstring

PRe ¼ Re power dissipation ¼

(10.65)

(10.66) e2 V Re Re

(10.67)

where n ¼ number of diodes in series; VRRM ¼ repetitive peak reverse voltage rating of each diode; Vstring ¼ total voltage across the string; DIRM(max) ¼ IRM(max)  IRM(min) ¼ maximum variation of reverse recovery current of the diodes at rated voltage ¼ 0.5IRM; IRM ¼ maximum reverse recovery current (specified by the manufacturer); DQsðmaxÞ ¼ QsðmaxÞ  QsðminÞ ¼ maximum variation of the storage charge IRM ts e ; VRe ¼ rms voltage of the diodes ¼ 0:5Qs ; Qs ¼ charge during storage time ¼ 2 across Re . In case of series connected thyristors, the gating signal through a proper gating circuit is applied simultaneously to the thyristors gates as shown in Fig. 10.97.

788

Power Electronics and Motor Drive Systems

+

Rg

Rg

Rs

Q1

Re

Re

Gating pulse

Rg

Cs

Rs

Q2

Re

Ds

Cs

Rs

Q3

Ds

Ds

Cs

−

Figure 10.97 Thyristor series stack with simultaneous triggering.

Example 10.11 Calculate the values of Re and Cs that will balance the voltage during steady state and transient state across 18 thyristors when the same type are connected in series to a voltage string of 17 kV DC. Also, the manufacturer’s specifications given are: Qs ¼ 110 mC, VRRM ¼ 1000 V, and IRM ¼ 20 mA.

Solution Re ¼

18ð1000Þ  17000 ¼ 5:9 kU ð18  1Þð0:5  20  103 Þ

Cs ¼

ð18  1Þð0:5  110 mCÞ ¼ 0:935 mF 18ð1000Þ  17000 

PRe ¼ Re power dissipation ¼

e2 V Re ¼ Re

17000 18 5900

2 ¼ 151 W

When the required current rating exceeds the current rating of the power diode, a number of diodes can be connected in parallel to share the load current. It is necessary that parallel devices have the same part number, and it is also highly recommended to use power devices from the same production lot ensuring minimum variation in their

Fully Controlled Semiconductor Devices

789

characteristics. However, as it is not possible to have diodes of completely identical characteristics, deviation in characteristics lead to the following two major problems during parallel connections of the diodes: i) Unequal current distribution through diodes. ii) Difference in recovery characteristics.

For steady-state current sharing, the circuits of Fig. 10.98(a) and (c) are used for paralleling diodes and thyristors, respectively. For transient-state current sharing, the circuits of Fig. 10.98(b) and (d) are used. If two diodes or two thyristor are to be operated in parallel, then the same value of resistance is used insuring proper current sharing during steady-state conditions. Current equalization by this method needs 1.5 V voltage drop across each of the series resistors at rated diode current. The addition of resistors reduces the efficiency and regulation of the system. As can be seen from Fig. 10.98(b) and (d), the transient current sharing is achieved with the use of coupled inductors, which is a more efficient method compared to the resistors. If the current through diode D1 rises, then the voltage across the inductor L1 (VL1 ¼ L1di1/dt) increases, causing a voltage of opposite polarity to be induced across inductor L2. This causes a low impedance path for current flow through diode D2, and more current is shifted through this diode to D1. The disadvantage of using current sharing inductors under transient conditions is that the inductors would generate voltage spikes and would be expensive and bulky.

(b)

(a)

R

D1

D2

(c)

R

Q1

L1

R

D1

L2

D2

(d)

L1

R

Q2

Q1

L2

Q2

Figure 10.98 Diodes and thyristors connected in parallel. (a) Steady-state current sharing; (b) transient-state current sharing; (c) steady-state current sharing; (d) transient-state current sharing.

790

Power Electronics and Motor Drive Systems

10.9.3.2 IGBTs Connected in Series and in Parallel 10.9.3.2.1

IGBTs Connected in Series

For high-voltage converters, the series connection of IGBTs is a direct and simple way to improve the converter’s voltage stress. To compare with single high-voltage IGBT, the structure of several low-voltage IGBTs series connection has some advantages that include lower switching losses and higher transient performance. It is necessary that the series devices have the same part number, and it is also highly recommended to use power devices from the same production lot ensuring minimum variation in their characteristics. When IGBTs are connected in series they exhibit unequal distribution of voltage across IGBTs because of the dispersions of the IGBT’s parameters or the differences between the gate driving signals. Therefore, voltage sharing of the IGBT series stack under static and dynamic conditions is the key issue must to be solved. Some voltage balancing methods are using active components for detecting the IGBT’s collectoreemitter voltage and form a feedback loop control circuit through which the gating signal of the IGBT is adjusted for voltage balancing. This method increases the cost and the complexity of the power switch, restricts also the number of the series connected IGBTs and is unreliable. RCD snubber together with an equalization resistance is a basic voltage balance passive method where the value of the paralleled capacitor decides the dynamic transient. Fig. 10.99 shows the series connection of n number IGBTs using a snubber and an equalization resistance. The single switch failure in the series connection needs to be handled carefully, to avoid damaging of the whole series stack. In the off-state the IGBT is approximately equivalent to a resistor Roff. Therefore, the equivalent circuit of the off-state series connected IGBT with equalization resistor Re will be a circuit with the two resistors in parallel. Normally, the value of Re is 1/10 of the Roff. Fig. 10.100 shows an example of a 40 kV series stack switch consisting of 10 IGBTs which is used as a protection semiconductor switch in a 45 kV HVDC bus.

C

Re

Static equalization resistance Re

Rs

Rs

Rs

Cs Ds

Cs Ds

Cs Ds

ic S 1

S2

Sn

Driving circuit for simulaneously triggering Vs = stack voltage

Figure 10.99 IGBTs connected in series (IGBT series stack).

Freewheeling diode

RCD Snubber Re

E

Fully Controlled Semiconductor Devices

791

ii = 1500A

C

iC

Freewheeling Resistor for static voltage sharing diode

RCD Snubber S1

Cs

G

HVDC = 40kV

G

G

Ds

S2

Rs

Cs Ds

S10

Rs

Cs Ds

Rs

R e VCE(rated) = 4.5kV

Re

Re

E

Figure 10.100 40 kV IGBT series stack switch.

This switch is also used as the so-called director switch for the implementation of a modular multilevel converter (M2C).

10.9.3.2.2

IGBTs Connected in Parallel

When the load current exceeds the IGBT current rating, IGBTs are connected in parallel to share the load current. But when IGBTs are operated in parallel, the current sharing between them may not be proper. It is necessary that parallel devices have the same part number, and it is also highly recommended to use power devices from the same production lot ensuring minimum variation in their characteristics. Among the IGBT parallel stack the IGBTs having lower dynamic resistance will tend to share more current in comparison to others. This will rise the temperature of the particular IGBTs in comparison to others, thereby reducing further its dynamic resistance and increasing current through them. This process is cumulative and continues and will cause the failure of the IGBTS. Another point to be considered is the on-state voltage across the device. For equal sharing of currents by the devices voltage drop across the parallel paths must be equal. The AC output resistance, saturation voltage (VCE(sat)), diode forward voltage, and gateeemitter voltage (vGE) affect the static current balancing of the stack. The DC bus

792

Power Electronics and Motor Drive Systems

stray inductance, gateeemitter threshold voltage (VGE(th)) and gate driver (including the gate loop inductance, gate loop resistance, and switching delay time) affect the dynamic current balancing of the stack. The junction temperature variance between the paralleling IGBTs affects both the static and dynamic current balancing of the stack. It is best to use a common gate driver for all paralleled modules because gate signals are synchronized (uniform propagation delay for each gate). Individual gate drivers for each module could cause some variation in turn-on and turn-off delay times, causing asymmetric switching behavior. This increases even more the switching losses and potential risks of module failures. It is, however, possible to parallel power modules and their associated drivers if the differences in driver delay times are negligible. The following is a list of guidelines for paralleling IGBTs: 1) 2) 3) 4) 5) 6) 7)

Balancing of the dc bus stray inductance The bus bars should be laminated Minimize the stray inductance of the drive circuit Minimize drive circuit impedance The IGBTs should have almost the same saturation voltage (VCE(sat)) The IGBTs must have the same part number and manufactured from the same production lot Use high speed opto-couplers or CT technologies for drive circuits

It is a common practice to insert resistors on the driver to control both turn-on and turn-off behavior of the power devices. These resistors can be distributed among the devices connected in parallel as gate resistors RG and return gate resistors RE as shown in Fig. 10.101. These resistors are used for damping the parasitic oscillations that might be induced by cross-coupled gate feedback between devices. In addition, each individual gateeemitter is driven in differential mode that compensates negative + C o m m o n g a t e d r i v e

R G1

IGBT1

common gate i R E1 E1

IGBTn R Gn

IGBT2 RG2

G2

G1

E1

Cn

C2

C1

R E2

Gn

i E2 E2

R En

common emitter

L1stray

L 2stray

L nstray

−

Figure 10.101 IGBTs connected in parallel (parallel stack).

i En En

Fully Controlled Semiconductor Devices

793

effects of possible differences in transfer characteristics between the IGBTs. The RE value (approximately 0.5 U) should be lower than RG (in practice RE z RG/3). For operation of all the IGBTs connected in parallel at the same temperature, it becomes necessary to use a common heat sink for their mounting. To understand the contribution of the resistors to the current balancing of the IGBTs, we will examine the operation of the first two IGBTs where the IGBT1 is faster than the IGBT2. The fast IGBT1 causes a higher di/dt, and a higher induced voltage across the emitter stray inductances of L1stray will occur. So a loop current flows through RE1, RE2 and L2stray to L1stray. The gate voltage of IGBT1 vG1E1 ¼ VGate  vRE1 due to the voltage drop VRE1 across the RE1, and the gate voltage of IGBT2 increases up to vG1E1 ¼ VGate þ vRE2 V. As a consequence, the current of two parallel IGBTs achieve symmetry. Based on application experience, the emitter resistor is recommended to select pulse power resistor and approximate 0.5 U or 50% of the gate resistance.

10.9.4 Power Semiconductor Devices Overvoltage Protection Power semiconductor devices are very sensitive to overvoltages, and perhaps this is their main cause of failure. The sources of overvoltages can be divided into the following types: • • • • • •

Overvoltages generated at the input source of a converter Overvoltages generated by inductive loads Overvoltages generated by the semiconductor device itself Overvoltages generated by the stray inductances of the power converter circuit Overvoltages generated by the reverse recovery of a diode or thyristor Overvoltage generated by an inverter arm that includes an inductor under fault conditions

The operating voltage across a power semiconductor device according to Fig. 10.102 can be classified as follows: 1) Maximum nonrepetitive forward and reverse voltage (VDSM, VRSM): This is the absolute maximum single-pulse voltage that the devices can instantaneously block. If a voltage spike above this level is applied, then the semiconductor will fail.

v(t)

Repetitive peak off-state voltage (VDRM )

Non-repetitive peak off-state positive voltage (VDSM ) ωt

Normal operating off-state peak voltage (VDWM )

Repetitive peak off-state negative voltage (VRRM )

Non-repetitive peak off-state negative voltage (VRSM )

Figure 10.102 Classification of nonrepetitive, repetitive, and normal operating voltage across a power semiconductor device.

794

Power Electronics and Motor Drive Systems

2) Maximum repetitive peak forward and reverse-blocking voltage (VDRM, VRRM): This is the maximum voltage that the device can block repetitively. Above this level the device will thermally “run-away” and fail. 3) Crest working off-state forward and negative voltage (VDWM, VRWM): This is the maximum working voltage at line frequency.

Depending on the application and the energy stored in the inductors in a power electronics converter, an overvoltage across a power semiconductor device can be suppressed using one of the following methods: 1) Snubber circuits that are designed to limit the overvoltages across the semiconductor device. Advantages • Availability • Usability Disadvantages • Low power density • Limited energy absorption and current capability • High power losses • Cost 2) Zener diodes: These devices clamp voltages at their reverse avalanche breakdown value. Advantages • Excellent voltage clamping • Compact • Sub nanosecond response time Disadvantages • Limited impulse or current capability high conduction voltage yields high transient dissipation limiting impulse current capability 3) Variable resistors (varistors) or metal oxide varistors (MOVs): The MOV is a voltagedependent variable resistor. Its structure consists of metal oxide grains with boundaries between the grains acting as pen junctions. The MOVs behave in a similar manner to the back-to-back zener diodes. Advantages • Cost • High clamping voltages • Absorb a lot of energy • Availability • Usability • Surge current capability Disadvantages • TOV (temporary overvoltage) susceptibility • Capacitance 4) Gas discharge tubes: A voltage switching device that has conductance properties that change very rapidly from open-circuit to quasi short-circuit when breakdown occurs and arc voltage occurs. Advantages • Handle very high impulse currents • Absorb a lot of energy • Low capacitance (1e5 pF) • Low conduction voltage

Fully Controlled Semiconductor Devices

795

• Rugged and compact Disadvantages • Extinguishing not guaranteed • 2e3 ms response time • Usability • Cost • Breakdown voltage depends on transient rise time allowing high overshoot voltage 5) Transorbs (transient voltage suppressors) are basically power Zener diodes. Advantages • Excellent voltage clamping • Sub nanosecond response time • Compact Disadvantages • Limited energy absorption and current capability • High conduction voltage • Cost

The MOV, which is shown in Fig. 10.103, is the most common overvoltage protection device. MOVs provide the most cost-effective means of limiting the transient voltage magnitude and can absorb a lot of energy. Until its voltage threshold is reached, the MOV acts as a high value resistor, curing a small leakage current. When the threshold voltage is reached or exceeded the MOV changes state and becomes a low value resistor and, consequently, clamps the voltage to the threshold voltage and a high current is flowing though the MOV. Fig. 10.104 shows the vveiv characteristic of a typical MOV. Connected in parallel with a power semiconductor device or power electronics circuit can provide overvoltage protection. The voltage that triggers the operation of the MOV is called clamping voltage and normally is 10e20% higher that the rated voltage of the device under protection. A lower clamping voltage could provide better protection but on the other hand the voltage must not be that low, because smaller continuous power changes will destroy the MOV. Fig. 10.105 shows the voltage waveforms across an electronic circuit without and with the application of an MOV. The currentevoltage dependence of MOVs may be approximately characterized by the following equation: I ¼ KVa

(10.68)

(a)

(b) iv vv

Figure 10.103 Metal oxide varistors (MOVs). (a) Different types of MOVs; (b) MOV symbol.

796

Power Electronics and Motor Drive Systems

iv

Varistor operating voltage

+ Ip

Normal current

Varistor clamping voltage +VC vv

−VC + I N = 1mA

−Ip Low resistance region

High resistance region

Low resistance region

Figure 10.104 Metal oxide varistor typical vveiv bidirectional characteristic.

(a)

v1 (t)

Voltage spike or surge + Clamping voltage

ωt

− Clamping voltage

(b)

v 2 (t)

Voltage spike or surge + Clamping voltage

ωt

− Clamping voltage

Figure 10.105 Voltage waveforms before and after the application of a bidirectional varistor. (a) Without metal oxide varistor (MOV); (b) with MOV.

where a ¼ a, measure of the steepness of the VeI curve. In MOVs, a > 30 making the VeI curve of MOVs are similar to zener diodes. If a ¼ 1 the behavior is ohmic (i.e., the current is proportional to the applied voltage) and when a /N the current varies infinitely for small changes in the applied field; K ¼ ceramic constant (depending on MOV type). When choosing an MOV for a given application, there are the following key specifications that need to be considered: •

Clamping voltage (Vc) is the voltage at which the MOV is activated and starts to show significant conduction.

Fully Controlled Semiconductor Devices

i

797

20 μs to get to 50% of max rise time =8 μs

100% 90%

Im IP

di dt 50%

10%

8μs

20μs

t

Figure 10.106 A typical 8/20 nonrepetitive surge current according to IEC 60060 standards. • • •

• •

• • • •

• •

Maximum clamping voltage (Vcmax) is the maximum voltage across the MOV when 8/20 ms rated surge current (see Fig. 10.106) is applied. Varistor voltage at 1 mA (nominal voltage, VN) is the voltage across the MOV measured at 1 mA dc. It has no particular physical significance but is often used as a practical standard reference. Rated varistor operating voltage (VRMS, VDC) is the maximum steady-state continuous ac (rms value) or dc voltage that can be applied across the MOV at a specified temperature. The higher the operating of the selected MOV compared to the circuit operating voltage, the better its reliability is over time, as the MOV is able to withstand more surge currents without degrading performance. Rated peak single surge current (Ip) is the maximum surge current that the MOV can handle for a given time when an 8/20 ms surge current is applied (see Fig. 10.106). Rated pulse energy (Wmax) is the maximum energy of a pulse, expressed in Joules that the MOV can dissipate. The energy rating for the MOV is often defined using standardized current transients. The transient is expressed in the format x/y where x is the time for the transient rise and y is the time to reach its half peak value (see Fig. 10.106). Response time is the time for the varistor to start conduction after the transient is applied. In many instances this is not an issue. Typical values are sub 100 ns. Leakage current (IL) is the current flowing through the MOV when it is in nonconducting state. Standby current is the level of current that is drawn by the MOV when it is operating below the clamping voltage. Normally this current will be specified at a given operating voltage across the device. Typical capacitance (Ctyp) is the MOV which has a relatively high capacitance across the device. Although for low frequency applications, this may not be an issue, it may present problems when it is used with lines carrying data, etc. It is, therefore, necessary to check the value of the capacitance across the device for any circuit where this could be an issue. Typical MOVs may have capacitance levels between 100 and 1000 pF, although low capacitance versions are available. Rated power (Pmax) is the maximum power that can be applied in the specified ambient temperature. Varistor degradation (lifetime-number of surges) is the degradation to excessive current surges exceeding the MOV’s rating while in operation.

798

Power Electronics and Motor Drive Systems

Maximum withstanding voltage of the protected device Maximum clamping voltage of MOV Actual clamping voltage

MOV operating voltage

Operating voltage of protected device

Voltage surge without MOV

Voltage surge with MOV

Figure 10.107 Voltage classification of a metal oxide varistor (MOV).

Fig. 10.107 presents the voltage classification of an MOV that was discussed before. Fig. 10.108 shows an IGBT which is protected by a snubber for dv/dt protection and an MOV for overvoltage protection. As can be seen from Fig. 10.108(a), the MOV is placed across the primary of the transformer, which is the source of creating the overvoltage due to the transformer inductance. However, in the circuit of Fig. 10.108(b) the MOV is placed across the IGBT. In the circuit of Fig. 10.108(b) when the IGBT is turned on current flows through the stray inductance and the IGBT and energy is stored in the stray inductance. When the IGBT is turned off or a fault appears in the circuit

(a)

C

(b) L Pr imary

C

Lstray

MOV

iV iC

G

iC

Cs Ds

E

Snubber

Snubber

G

Cs Ds

Rs

Rs

MOV iv

E

Figure 10.108 Metal oxide varistor (MOV) protecting an IGBT from overvoltages. (a) MOV protecting IGBT from overvoltages due to the transformer inductance (MOV is placed at the overvoltage source); (b) MOV protecting IGBT from overvoltages due to the circuit stray inductances (MOV is placed across the IGBT).

Fully Controlled Semiconductor Devices

799

vCE

IGBT IGBT on off

IGBT off ωt

iC

ωt

(a) vCE

ωt

iC

ωt

iv

(b)

tp

ωt surge duration

Figure 10.109 Voltage and current waveforms of the IGBT. (a) Without metal oxide varistor (MOV); (b) with MOV.

that causes discontinuity of the stray inductance current, then the stored energy will be dissipated by the MOV preventing the generation of an overvoltage which will cause the failure of the IGBT. Fig. 10.109 shows the voltage and current waveforms of the circuit of Fig. 10.108(b) without and with the application of an MOV. In applications the selection of an MOV is based on the following five steps: 1) 2) 3) 4) 5)

Determination of the necessary steady-state voltage rating (operating voltage) Establishing the transient energy absorbed by the MOV Calculation of the peak transient current through the MOV Determination of the power dissipation requirements Selection of a model to provide the required voltage-clamping characteristic

Example 10.12 An MOV is connected across an IGBT. The rated voltage of the IGBT is vCE(rated) ¼ 2500 V. The overvoltage that appears across the IGBT is 3000 V for duration of 20 ms. The maximum current that flows into MOV when it is in the clamping state is 100 A. Calculate the energy that will be dissipated in the MOV.

800

Power Electronics and Motor Drive Systems

Solution Given the above data, then the MOV has to be able to dissipate a minimum energy of W ¼ energy ¼ overvoltage  current  duration ¼ 3000  100  20  106 ¼ 6 J Therefore, the MOV to be selected must have at least a minimum of 6 J energy rating.

Example 10.13 For the circuit shown below, find the required MOV that will protect the IGBT from an overvoltage failure due to the series inductance of 1 mH. The circuit conditions are (1) Vin ¼ 900 V dc and (2) input peak current during the overvoltage is 200 A. +900V L = 1mH

iv iC Ds

Cs Rs

Solution To find the voltage rating of the MOV, a 20% tolerance is allowed to account for voltage swell and power supply tolerances. Therefore, 900 V dc  1.2 ¼ 1080 V dc will be the rated operating voltage of the required MOV. The maximum energy that will be stored in the series inductance is given by: WðstoredÞmax ¼ energy ¼

 1 2 1 LI ¼ 1  103 ð200Þ2 ¼ 20 J 2 2

(10.69)

Therefore, the required MOV must have a rated operating continuous voltage of 1080 V, must be able to dissipate 20 J of energy per current surge pulse and to be able to withstand the circuit current of 200 A. The MOV type V1000LA80AP (VMDC ¼ 1200 V and WTM ¼ 220 J) satisfies these requirements. Fig. 10.110 shows the technical data sheets characteristics of the selected MOV. As can be seen from Fig. 10.110(a), when the peak current of the selected MOV is 200 A the maximum clamping voltage Vc is approximately 3200 V which will appear

Fully Controlled Semiconductor Devices

801

Figure 10.110 Metal oxide varistor type V1000LA80AP technical data sheets characteristics. (a) Transient VeI characteristics curves (maximum clamping voltage); (b) pulse rating curves (repetitive capability assuming an 8/20 ms current surge). Courtesy of Littefuse. Vc = 3200V

vCE vv

900V

off

on 200A

iC iv

ωt

I peak = 200A surge duration

ωt

tp

ωt

Figure 10.111 Voltage and current waveforms of the IGBT and metal oxide varistor.

across the IGBT when the IGBT is turned off or during a discontinuity fault. Therefore, for this application the rated voltage of the IGBT (i.e., VCE(max)) must be higher than 3200 V (e.g., 3500 V). Fig. 10.111 shows the waveforms of the IGBT and MOV. The energy that will be absorbed by each MOV is given by: WMOV ¼ energy absorbed by one MOV ¼ WðstoredÞmax ¼ kVc Ipk tp

(10.70)

where k ¼ 1 (when the current impulse is a square wave); k ¼ 0.5 (when the current impulse is a triangular wave); Vc ¼ clamping voltage; IPK ¼ peak current; tp ¼ current impulse duration time. Therefore, using Eqs. (10.69) and (10.70) and knowing that the current through the MOV is triangular, the current impulse duration time is found to be: tp ¼

WMOV 20 ¼ 62:6 ms ¼ KVc Ipk ð0:5Þð3200Þð200Þ

802

Power Electronics and Motor Drive Systems

Next, using Fig. 10.110(b) for tp ¼ 62.6 ms and current peak surge value of 200 A, a rate repetition of 1000 is found. This means that the MOV can withstand 1000 current surge events before replacement.

Example 10.14 Design a dc power bidirectional semiconductor switch with overvoltage protection to be used for the arm protection of an alternate arm converter (AAC). The MOV type V1000LA80AP to be used again. The switch has the following specifications: Switch maximum operating voltage 40 kV Switch maximum current 1500 A Arm inductance 3.2 mH Under normal operation there is always current flowing through the arm inductance and the semiconductor switches (through the IGBTs or the freewheeling diodes) 5) Switching frequency 50 Hz 6) Under fault conditions (e.g., current discontinuity) all IGBTs are turned off simultaneously. 1) 2) 3) 4)

Solution Fig. 10.112 shows the power circuit of a proposed dc power semiconductor switch that exhibits the above specifications. The proposed switch is implemented using a stack of 40 IGBTs in series. As can be seen from Fig. 10.112, besides the snubbers and the static equalization resistors, a series stack of 40 MOVs have been applied across the IGBTs stack to protect the IGBTs from surge voltages that can be created by the arm inductance during an unwanted arm current discontinuity. To find the voltage rating of each MOV, a 20% headroom is allowed to account for voltage swell and power supply tolerances. Therefore, 40 kV dc  1.2 ¼ 48 kV/40 ¼ 1.2 kV dc will be the rated operating voltage of each MOV. When the switch current goes through the arm inductance the maximum stored energy will be:  1 1 Wmax ¼ energy ¼ Larm I2switch ¼ 3:2  103 ð1500Þ2 ¼ 3600 J 2 2 Therefore, each MOV should have a rated operating continuous voltage of 1200 V, must be able to dissipate 3600/40 ¼ 90 J of energy per current surge pulse and to be able to withstand the circuit current of 1500 A. We could use again the MOV type V1000LA80AP (V MDC ¼ 1200 V and W TM ¼ 220 J), which satisfies these requirements.

Fully Controlled Semiconductor Devices iswitch = 1500A

803

Larm = 3.2mH C

ic G

SW1

RCD Snubber Cs Ds

SW2

C o m m o n

Cs Ds

G

SW3

Rs

Cs Ds

g a HVDC = 40kV t e

Re

MOV1

Resistor for static voltage sharing

E G

Rs

MOV rated operating voltage 1.2kV

Rs

Re

MOV2

Re

MOV3

vCE(operating) = 1kV vCE(rated) = 4.5kV

d r i v e bidirectional current flow

G

SW39

Cs Ds

G

SW40

Rs

Cs Ds

Rs

Re

Re

MOV39

MOV40

E

Figure 10.112 Proposed power semiconductor switch. HVDC, high voltage DC; MOV, metal oxide varistor.

Examining Fig. 10.110(a), when the peak current of the selected MOVs is 1500 A the maximum clamping voltage Vc for each MOV is approximately 4000 V. Fig. 10.113 shows the waveforms of each IGBT and MOV. Therefore, for this application the rated voltage of each IGBT (i.e., VCE(max)) must be higher than 4000  40 ¼ 4000 V (e.g., 4500 V). 40

804

Power Electronics and Motor Drive Systems

Vc = 4000V

vCE vv

1000V

off

on

1500A

iC iv

ωt

I peak = 1500A surge duration

ωt

tp

ωt

Figure 10.113 Voltage and current waveforms of the IGBT and metal oxide varistor.

To find the repetitive capability of each MOV the duration time of the current surge has to be calculated: WMOV ¼ energy absorbed by the MOV ¼ WðstoredÞmax ¼ kVc Ipk tp tp ¼

WðstoredÞmax 90 ¼ 30 ms ¼ ð0:5Þð4000Þð1500Þ kVc Ipk

Next, using Fig. 10.110(b) for tp ¼ 30 ms and current peak surge value of 1500 A, a rate repetition of 2 is found.

Bibliography and Publications [1] S.M. Sze, Physics of Semiconductor Devices, second ed., John Willey & Sons, New York, 1981, pp. 35e38. [2] B.G. Streetman, S.K. Banerjee, Solid State Electronic Devices, sixth ed., Prentice Hall, Englewood Cliffs, NJ, 2006, pp. 184e193. [3] S.K. Ghandhi, Semiconductor Power Devices, John Wiley & Sons, New York, 1997. [4] R.N. Hall, Power rectifiers and transistors, Proceedings of the IRE 40 (1952) 1512e1518. [5] H. Benda, E. Spenke, Reverse recovery processes in silicon power rectifiers, Proceedings of the IEEE 55 (1967) 1331e1354. [6] B. Baliga, The future of power semiconductor device technology, Proceedings of the IEEE 89 (6) (2001) 822e832. [7] B.J. Baliga, Silicon Carbide Power Devices, World Scientific, Singapore, 2005. [8] J. Cooper, A. Agarwal, SiC power switching devices e the second electronics revolution? IEEE proceedings 90 (6) (June 2002) pp. 956e968. [9] A. Elasser, T.P. Chow, Silicon carbide benefits and advantages for power electronics circuits and systems, IEEE proceedings 90 (6) (2002) 969e986. [10] SEMIKRON, SEMIKRONeinnovationþservice, Databook (1999). [11] MITSUBISHI-Semiconductors, HVIGBT and HVDI Data Sheets, 2001. www. mitsubishichips.com.

Fully Controlled Semiconductor Devices

[12] [13] [14] [15] [16]

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EUPEC, website: www.eupec.com. POWEREX, website: www.pwrx.com. MITSHUBISHI, electric semiconductor website: www.mitshubishichips.com. International Rectifier(IRF), website: www.irf.com. Semisouth, SJDP120R085 Normally-on Trench Silicon Carbide Power JFET, datasheet rev 1.3. [17] M.L. Heldwein, J.W. Kolar, A novel SiC J-FET gate drive circuit for sparse matrix converter applications, in: Nineteenth Annual IEEE, September 2004, vol. 1, APEC, 2004, pp. 116e121. [18] R. Mousa, D. Planson, H. Morel, B. Allard, C. Raynaud, Modeling and high temperature characterization of SiC-JFET, in: Power Electronics Specialists Conference, PESC 2008, IEEE, June 15e19, 2008, pp. 3111e3117. Rhodes Greece.