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Functional delay test generation based on software prototype
Microelectronics Reliability 49 (2009) 1578–1585
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Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Functional delay test generation based on software prototype Eduardas Bareisa, Vacius Jusas *, Kestutis Motiejunas, Rimantas Seinauskas Kaunas University of Technology, Informatics Faculty, Department of Software, Studentu 50, Kaunas, Lithuania
a r t i c l e
i n f o
Article history: Received 21 January 2009 Received in revised form 30 June 2009 Available online 11 August 2009
a b s t r a c t The paper presents two methods of functional delay test development based on the software prototype as well as the results of their application to benchmark circuits. The first method is used to construct the functional delay test on the base of a pin pair test generated at the functional level for detection of stuck-at faults at the gate-level. The constructed test is a single input transition test. The latter appears to be quite large. Therefore, we provide the method for compacting it. The compacted single input transition test becomes a multi-input transition test. The second method is used to generate a multi-input transition test. The generated functional test pattern pairs possess function-robust and/or functionnon-robust properties. The introduction of the function-non-robust property enriches the functional delay test. The presented test construction approach based on the software prototype allows obtaining a functional delay test, which detects the transition faults at the gate-level of a circuit quite completely. Ó 2009 Elsevier Ltd. All rights reserved.
1. Introduction Continuously growing complexity of digital devices creates new challenges for test designers. Delay testing is gaining more and more industry attention to maintain test quality for speed-related failures. The purpose of a delay test is to verify that a circuit operates correctly at a desired clock speed. A pair of test patterns is used to detect delay faults. The first pattern sets the initial values on the inputs of the circuit, whereas the second pattern launches the transition. Conventional delay test generation techniques based on gate-level fault models are not suitable for circuits whose implementation details are unavailable. The functional test can be generated for such circuits according to their specifications. According to the functional delay fault models proposed in [1– 3], a fault is a tuple (I, O, tI, tO), where I is an input of the circuit under test (CUT), O is a CUT output, tI is a rising or falling transition at I, and tO is a rising or falling transition at O. A test for the functional delay fault is a pair of input patterns hu, vi that propagates a transition from a primary input to a primary output of the circuit. Under the model introduced in [1], only one pair of test patterns must be generated per fault. Pomeranz and Reddy [2] proposed that all possible patterns are generated for each fault. This model guarantees detection of all robustly testable path delay faults in any gate-level implementation. However, the sizes of the resulting test sets as well as test generation times are very large and make this model impractical, especially for large circuits. The studies in
* Corresponding author. Tel.: +370 37 327617; fax: +370 37 300352. E-mail addresses: [email protected] (E. Bareisa), [email protected] (V. Jusas), [email protected] (K. Motiejunas), [email protected] (R. Seinauskas). 0026-2714/$ - see front matter Ó 2009 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2009.06.050
[3] showed that it is not necessary to generate all possible test patterns for each fault in order to guarantee that actual path delays are covered in some gate-level implementation of the function. The model [2] was modified in [3] by considering D different test patterns per fault. Here, D is a positive integer, usually in low hundreds, and is given as an input parameter for each CUT. The problem is the selection of D. Several black-box fault models based on input stimuli and output responses were suggested in [4–7]. The most universal is the single coupling fault model proposed in [5] and extended in [6], which is defined in terms of a single input/output pair. The average size of the test set is 2n 1, where n denotes the number of inputs of the module [6]. Therefore, the test sets are very large even for small modules and not practical in many cases. Yi and Hayes [8] extended high-level delay fault models to large modular logic circuits applying a hierarchical approach to delay test generation for modular circuits. The proposed new fault model based on the coupling delay fault model [6] imposes requirements for robust delay testing on module implementation and on the input pattern pair. The proposed fault model has several drawbacks. Each circuit is manually partitioned into multiple modules such that the output of every module has at most 12-inputs so that the coupling delay test set is kept reasonably small. Although the coupling delay test set for a function z detects all robust path delay faults in any gate-level realization of z [6], the module path delay test set (MPDTS) [8] for a modular realization of z may fail to detect all such faults. This is possible either because many path delay faults are not testable robustly or because some robust path delay faults are not detectable by an MPDTS. Since complete coverage of robust path delay faults is not guaranteed by MPDTSs, any strong conclusions cannot be drawn from the proposed model.
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The functional fault models [7] that are named pin pair (PP) and pin triplet (PT) enable to develop the functional test on a base of the software prototype at early stages of the design process, while a synthesized description of the device is not available yet. Very promising results were achieved in functional test generation for detecting stuck-at faults when the generation was based on the PP fault model [7]. The average percent of undetected faults did not exceed 0.5% for ISCAS’85 benchmark circuits. The test sets for PP faults are larger than the test sets generated at the gate-level by TetraMAX only six times on average. Therefore, the PP fault model was chosen as the basic model for the functional delay test generation.
2. The significance of functional test The test designer prepares a functional test according to the specification of the device under test. The functional test is used to verify the next steps of the design. Functional test sequences were shown to detect unique defects in VLSI circuits [9]. However, functional test sequences do not achieve complete stuck-at fault coverage. Therefore, there is a sense to use the functional test as the basis for gate-level test generation, thereby reducing or eliminating the need for separate stuck-at test generation [10]. During the design process, a software prototype of the device is created according to the specification. The software prototype simulates the functions of the device, enabling to calculate the output values according to the input values, and can be regarded as a black-box model of the device. The functional test can be generated on the base of the software prototype. The software prototype defines the functionality of the device using input variables, output variables and state variables. The calculation of the output values and new state values is based on the input values and the old state values. Therefore, we treat the state variables in two different ways: as the input variables before the calculation and as the output variables after the calculation. Generally, the variables of the software prototype can be classified into two groups: the input variables and the output variables keeping in mind that the state variables take part in both groups. Consequently, we always can assume that the software prototype model is the combinational one, and the output values depend on the input values only. The software prototype used in the initial stages of the design process exposes the primary idea of the device only. Therefore, its functionality can be described in a very simple form. For example, the circuit S344 from the benchmark suite ISCAS’89 and the circuit C6288 from the benchmark suite ISCAS’85 are multipliers. The body of the software prototype of these circuits consists of a single expression, which multiplies the first operand by the second operand and assigns the multiplication result to the third operand. Meanwhile, the gate-level description of the circuit C6288 has a very large number of paths. There exist various implementations of the circuit S344. Some of these implementations are the combinational ones; the others are the sequential ones. The test patterns constructed using the software prototype can be applied to the combinational circuits directly. The application of test patterns, constructed according to the software prototype, which has no state variables, to sequential circuits requires the use of the test frame [11,12] that makes possible expanding the functional test time-wise and adjusting it to the implementation details of the circuit. The test frame allows introduction of reset, start, clock signals, which usually are not present in the software prototype model. When the test frame is used, the rated-clock non-scan sequential test methodology has to be adopted for testing delay faults [13,14]. The functional test is based on the function of a circuit, which can be realized in many ways. The possible defects of the circuit
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depend on an implementation. The test is usually developed for the specific implementation and it is devoted to detect the defects of this particular implementation. The manufacturing test can be developed using the specific implementation only. Meanwhile, the functional test is not related to a particular implementation because it is generated from a circuit’s specification rather than its gate-level implementation. The size of a functional test is usually much larger than that of an implementation-dependent one to assure good fault coverage for many implementations. The functional test, which is independent of the implementation, has several advantages over the implementation-dependent test. The functional test can be used to correct testability problems early in the design process [2], to identify the design errors [15,16], to test many potential implementations [4,17], and to detect hard-to-detect faults at gate-level implementation [17]. The objective of the paper is to research and to develop functional delay test generation methods based on a software prototype. We start with the presentation of the method that enables the construction of a functional delay test using the PP fault test in Section 3. The problem of constructing a compact functional delay test set is addressed in Section 4. We present a method that allows multi-input transition in test pattern pairs, which possess function-robust and/or function-non-robust properties in Section 5. We conclude in Section 6.
3. Functional delay test construction based on PP fault test We start this section by providing a brief presentation of the main concepts of the PP fault model [7]. Let a circuit have a set of primary inputs X = {x1, . . . , xi, . . . , xn}, and a set of primary outputs Y = {y1, . . . , yj, . . . , ym}. We will write x1i , x0i for stuck-at 1/0 faults at the primary input xi, i 2 1, . . . , n}, and y1j , y0j for stuck-at 1/0 faults at the primary output yj, j 2 1, . . . , m}, respectively. Under PP fault model, a fault is described by a pair of stuck-at faults (xti , ykj ), t = 0, 1, k = 0, 1. The fault (xti , ykj ) is detected by test pattern p that satisfies the following conditions: 1. The test pattern p detects the single fault xi stuck-at t. 2. The fault free value of output yj under p is k. 3. In the presence of xi stuck-at t, the value of output yj is k. Let us consider an example. Suppose we are given the three-input, two-output circuit that implements the functions y1 ¼ x1 x2 þ x1 x3 , and y2 ¼ x1 x2 x3 . We examine the test pattern p = h1 0 1i. Under p = h1 0 1i, we obtain the output vector y (1 0 1) = h0 0i. The test pattern p detects the following PP faults: (x01 , y11 ), (x12 , y11 ), (x12 , y12 ). The number of possible PP faults of the circuit is at most 4 n m. It may appear that there exist no electric connections between the primary input xi and the primary output yj of the circuit, and the PP fault associated to xi and yj cannot be detected. These faults are untestable. The PP fault (xti , ykj ) of a circuit is testable if a conventional deterministic test generator for a realization of the circuit finds a test pattern, which detects a pin fault xti on the primary output yj meanwhile the primary input xi and the primary output yj are set up to the opposite values (not t on the primary input and not k on the primary output). The number of testable PP faults equals 4 n m minus the number of untestable PP faults. The main drawback of the PP model is that the untestable faults are not known a priori. The test generation for the PP fault is based on the random search procedure [7]. The test pattern is generated randomly, and then it is simulated on the functional model of the circuit. The sensitivity of the value on each primary input is checked by complementing it one by one and simulating again. If the responses of the generated pattern and the changed pattern
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differ on some primary outputs, an appropriate PP faults are detected. A similar fault model, called PI–PO, was presented in [18]. But Pomeranz and Reddy [18] use this fault model only for the metric in order to predict relative gate-level stuck-at fault coverage of different test sets, when the gate-level description of a logic block is unknown. They showed through experimental results that the proposed metric is accurate in predicting relative gate-level fault coverage. It is more accurate than a fault model that consists only of primary input faults (without taking into account primary output values). We have understood this property much earlier [19]. The PP fault model lies at the background of many of our researches. If we compare functional delay [1,2] and PP fault models we see that both models have almost the same meaning with one distinction: the functional delay model is intended for detection of malfunctions in the dynamic behavior of the module, whereas the PP fault model – for detection of malfunctions in the static state of the module. For example, consider a circuit, which has five inputs x1, x2, x3, x4, x5, and two-outputs y1, y2. The model of the circuit presented in the form of a Boolean expression is shown in Fig. 1. The circuit response to the input pattern h1 0 0 1 1i is h0 1i. This pattern detects the PP faults (x12 , y11 ), (x13 , y11 ), (x13 , y02 ), and (x05 , y02 ). The functional delay fault (x2, y1, fx2, fy1) is detected by the pair of input patterns h1 1 0 1 1, 1 0 0 1 1i, where the second pattern of the pair coincides with the pattern that detects the PP faults. Based on this observation and on the properties of the delay test [6,20,21], we can define a rule how to extend the PP fault test to the functional test for delay fault.
Y 1 ¼ x1 x2 þ x1 x3 þ x1 x2 x3 þ x1 x2 x3 x4 Y 2 ¼ x2 x3 þ x2 x4 þ x2 x3 x5 þ x2 x3 x4 x5 Rule. If the input pattern q detects the PP fault (xti , ykj ), t = 0,1, k = 0,1, then the pair of input patterns hp, qi, while the signal value of input xi in the pattern q is t and the signal value of input xi in the pattern p is t, detects functional delay faults: (xi, yj , rxi, ryj), when t = 0, k = 0; (xi, yj , rxi, fyj), when t = 0, k = 1; (xi, yj , fxi, ryj), when t = 1, k = 0; (xi, yj , fxi, fyj), when t = 1, k = 1 (r and f denote rising and falling transitions, respectively). Suppose an input pattern w detects l PP faults. Then, according to Rule, the transformation of this pattern can provide at most l pairs of input patterns for detection of the corresponding l functional delay faults (signal transition on one input can cause signal
y1 = x1x2 + x1x3 + x1x2x3 + x1x2x3x4 y2 = x2x3 + x2x4 + x2x3x5 + x2x3x4x5 Fig. 1. The model of the circuit.
transitions on s outputs, therefore, only one pair of input patterns is needed for detection of s functional delay faults). For example, let us consider the input pattern h1 0 0 1 1i. Let us complement the input values one by one and measure the responses at the outputs. The following five different test patterns would be formed: h0 0 0 1 1i, h1 1 0 1 1i, h1 0 1 1 1i, h1 0 0 0 1i, h1 0 0 1 0i. The complement of the value on the first and fourth inputs does not change the values at the outputs. Therefore, the values on these inputs are not sensitive. The transitions from these inputs would not propagate to the outputs. The complement of the value on the second input changes the value on the first output only. The complement of the value on the third input changes the values on both outputs. The complement of the value on the fifth input changes the value on the second output only. Therefore, the transformation of the input pattern h1 0 0 1 1i results into three pairs of delay test patterns (h1 1 0 1 1, 1 0 0 1 1i, h1 0 1 1 1, 1 0 0 1 1i, h1 0 0 1 0, 1 0 0 1 1i) that detect the functional delay faults (x2, y1, fx2, fy1), (x3, y1, fx3, fy1), (x3, y2, fx3, ry2), and (x5, y2, rx5, ry2). Note, that all pairs of test patterns derived from PP tests, using Rule, are single input transition (SIT) tests, and, therefore, all test pattern pairs satisfy the function robust propagation property [20]. During the experiments, we have used software prototype models written in the C programming language. Non-redundant ISCAS’85 benchmark circuits have been selected for the experiments, because they are more demanding for testing purposes than combinational parts of the sequential circuits of the benchmark suite ISCAS’89. The comparison of the sizes of test sets and coverage of the transition faults of the non-redundant ISCAS’85 benchmark circuits are given in Table 1. In [22], no results are provided for the circuit C1355, therefore it is not included in the table. Note that the functional test sets detect 100% of targeted PP faults. The average percent of the detected transition faults by the tests generated for the function delay faults exceeds 95.67%, but the minimum percent of the detected transition faults is 83.08% (circuit c3540). We can see that, for the considered circuits, the size of the functional delay test obtained by the above-described transformation is on average 3.77 times larger than the size of PP fault tests. Thus, almost four test pattern pairs are generated for each separate test pattern. As we briefly reviewed in the introduction, there are many studies devoted to the development of methods for testing of functional delay faults. However, the obtained numerical results – the test sizes for the considered circuits – are reported only in [22]. Therefore, the last two columns of Table 1 show the results of the approach in [22]. The approach by Tragoudas and Michael [22] utilizes such techniques as Reduced Ordered Binary Decision Diagrams (ROBDDs) and Boolean Satisfiability (SAT). The problem of finding a set of test patterns for a given (I, O, tI, tO) combination is reduced to solving a SAT formula in conjunctive normal form. A different formula is constructed for each (I, O, tI, tO). Therefore,
Table 1 Transition fault coverage. Circuit
C432 C499 C880 C1908 C2670 C3540 C5315 C6288 C7552 Average
Test size of PP
Functional delay test size
Coverage (%)
Tragoudas–Michael [22] method. Test size
Coverage (%)
117 1077 381 620 448 515 1169 268 2115
348 5180 1001 2359 1820 1457 4950 1065 5801
95.56 94.40 98.91 95.24 96.51 83.08 98.41 99.75 99.21
804 3915 1321 3153 3956 2493 10,662 2085 13,815
96.6 90.5 96.6 97.8 98.5 91.3 99.5 89.2 99.2
746
2965
95.67
4689
95.47
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this approach is not truly functional, because ROBDD and SAT formulas are constructed according to the structure of the circuit. We see that in our approach the test sizes are considerably shorter, except the circuit C499, but the fault coverage is noticeably better for this circuit. In general, the fault coverage for about a half of circuits is slightly better in [22], nevertheless on average it is slightly better in our approach, because the approach by Tragoudas and Michael [22] looses very significantly for the circuit C6288. ROBDD of this circuit cannot be constructed. ROBDD was created by simplifying the function after preselecting inputs randomly [22]. We have never had any problems with circuit models because they in our approach are always functional. We see from Table 1 that the sizes of the test sets obtained using the presented method are significantly larger in comparison with the sizes of the initial PP test sets. It is very important to have compact test sets in order to reduce the cost of testing of very large scale integrated circuits by reducing the test application time. This is especially critical for the scan-based circuits as the test application time for such circuits is directly proportional to the product of the test set size and the number of storage elements used in the scan chain. Small test sets also reduce the requirements for test storage. The only way to compact a functional delay fault test is to allow multi-input transition (MIT) in test pattern pairs. The problem of constructing a compact MIT functional delay test is addressed in the next section.
4. Functional test compaction Test pattern pairs constructed according to Rule hold the change of the signal value only on a single input. Let us continue the analysis of our example. The considered input pattern h1 0 0 1 1i detects 4 PP faults, though for detection of the corresponding functional delay faults only three test pattern pairs are built as the signal transition on input x3 invokes the signal transitions on both outputs y1 and y2 simultaneously. Therefore, the number of the test pattern pairs obtained using Rule is equal to the number of inputs involved in PP fault detection on the considered test pattern. In our case, three such inputs are present, and, consequently, three test pattern pairs are built. Another way to obtain functional delay fault tests from PP tests is described in [23]. By applying the approach from [23] every input pattern that detects PP faults is transformed only into a single input pattern pair. This is done in such a way that the signal value transition occurs on every input involved in PP fault detection on the considered test pattern. In our example, only a single input pattern pair h1 1 1 1 0, 1 0 0 1 1i is constructed. Consequently, if a test for PP faults consists of p input patterns the constructed functional delay fault test would consist of p input pattern pairs, as well. Thus, the obtained test is much shorter than that produced by applying Rule. The experiments on ISCAS’85 benchmark circuits demonstrated the test shortening of 3.8 times on average, but the transition fault coverage is 91.29% only [23]. This number is significantly smaller than the transition fault coverage shown in Table 1. Test pattern pairs constructed by applying the approach from [23] hold the change of the signal value on more than one input. Therefore, these pattern pairs are MIT tests [20]. Some of functional delay faults that are functional robustly detectable on SIT test may become functional non-robustly detectable [20] or, even worse, not detectable on the considered test pattern pair, because some activation conditions needed for signal transition propagation from a particular input to a particular output may be corrupted. But the MIT tests are indispensable in some cases as some delay faults can be detected by the MIT tests only. This statement is supported by the results from [23], where the transition fault coverage of MIT tests for the circuit C3540 is increased comparing with SIT tests.
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However, the approach in [23] is too much straightforward. The simple initiation of several transitions at the same time may not produce a good coverage of the transition faults in every situation. The transitions can propagate by the same paths and they can cancel each other. The MIT test should include only those transitions that do not mask each other. Therefore, we have to define the necessary conditions for the transition propagation from a particular input to a particular output when the test pattern pair possesses multi-input transitions. Suppose: 1. We are given a multi-input transition test pattern pair hp, qi. 2. The signal value on the input xi in the pattern p is t and the signal value on the input xi in the pattern q is t. 3. The signal value k on the output yj is the circuit response to on the output y is the input pattern p, and the signal value k j the circuit response to the input pattern q. Lemma. If sticking the signal value to t on a single input xi in both test patterns p and q sets a stable signal value k on the output yj in both test patterns, then signal value on the input xi has an effect on this circuit response only. Proof. Suppose a stable signal value k on the output yj is caused by signal values on the input xr in the patterns p and q. Thus, a different circuit response on the output yj could be set solely by the signal value change on the input xr either in both test patterns p and q or in one of them. However, it is a contradiction to the statement of Lemma saying that the signal value change occurs only on single input xi. Therefore, the stable signal value k on the output yj is caused by sticking to t the signal value on a single input xi in the patterns p and q. h Corollary 1. The MIT test pattern pair hp, qi detects the functional y Þ, where t ! t denotes the falling delay fault ðxi ; yj ; t ! t xi ; k ! k j denotes the falling transition on transition on the input xi, and k ! kk the output yj. It is desirable that the generated MIT test would posses the function-robust propagation (FRP) property. According to the definition given in [2], a transition tI on the input I is function-robustly propagated as a tO transition to the output O when the signal value on O changes if and only if the signal value on I changes, independent of the order or speed at which other inputs change. Now we can formulate the next corollary. Corollary 2. The signal value transition t ! t on the input xi, which on the output y , satisfies the causes the signal value transition k ! kk j FRP property. When the MITs are launched in the test pattern pair, logic hazards can occur during this transition. Some logic hazards depend on the implementation of the circuit. When the circuit is considered at the functional level, the gate-level of it is unknown. Therefore, such logic hazards cannot be evaluated at the functional level. The other logic hazards that depend on the order of signal changes on the inputs can be considered at the functional level. An appropriate definition of the FRP property, which evaluates the order of the signal changes on the inputs, is presented in [24]. According to this definition, all the input patterns that may be obtained during the transition from p to q have to produce the same output value as q does. This adds an overhead to test generation, which may require quite a substantial amount of CPU time. Therefore, we have decided to ignore possible logic hazards that can occur during transitions in the MIT test pattern pairs and can invalidate the FRP property of the pattern pair. On the basis of Lemma and its corollaries, we have developed a procedure, named PP2CFD, for transformation of a PP test into a
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Table 2 Test size reduction. Circuit
Test size
Reduction (%)
Coverage (%)
SIT test
PP2CFD
C432 C499 C880 C1355 C1908 C2670 C3540 C5315 C6288 C7552
348 5180 1001 5162 2359 1820 1457 4950 1065 5801
SIT test
PP2CFD
244 1159 743 1068 1814 1153 1166 3382 903 4331
30 78 26 79 23 37 20 32 15 25
95.56 94.40 98.91 97.13 95.24 96.51 83.08 98.41 99.75 99.21
94.69 93.00 100 95.01 94.58 98.12 94.21 99.91 99.89 98.03
Average
2914
1596
36.5
95.82
96.74
compact functional delay test. The main blocks of this procedure are the following: (1) selection of circuit inputs related with PP fault detection (we call them sensitive inputs) in the test pattern Pk and generating of a test pattern pair hP1, P2i where P2 :¼ Pk while signal values on sensitive inputs in the pattern P1 are complemented in regard to signal values in the test pattern Pk; (2) construction of MIT test pattern pairs, which satisfy FRP property, on the basis of hP1, P2i. We conducted an experiment on the SIT test sets, transition fault coverage of which was reported in Table 1. The results are presented in Table 2. The circuit C1355 was not included in Table 1, but we always use this circuit in our experiments, therefore the circuit C1355 is presented in Table 2. The reduction of the test size is expressed in percents. We see that very significant reduction of the test size is achieved for the circuits C499 and C1355. The obtained result is determined by the function of the circuits. The tests of the circuits C499 and C1355 have a large number of sensitive values in every test pattern. This property of the test allowed compressing a lot of SIT test pattern pairs into a single MIT test pattern pair. The last two columns of the table present the transition fault coverage before compaction and after compaction. The best transition fault coverages are shown in bold. It has to be noticed that the compaction did not change the fault coverage of the functional delay faults. The functional delay faults were covered completely before compaction and remained as such after compaction. But the compaction had some impact on the transition fault coverage. The transition fault coverage was not retained – it either increased or decreased. The general tendency is positive; the fault coverage after compaction on average is higher. That highlights the value of the MIT test. The decrease of the fault coverage of the MIT test can be explained by the fact that the logic hazards were not taken into account during the construction of the MIT test. However, the MIT test sensitizes additional branches in the circuit and thereby detects additional transition faults. This helps to increase the fault coverage of the MIT test. The functional delay test can be constructed not only from PP test, but it can be generated on its own. The main problem is the quality assessment of the functional delay test because the implementation of the circuit is not available yet. The criteria of the quality assessment of the functional test do not suit quite well for such a purpose, because the detection of the delay faults requires a pair of test patterns. The problem of the functional delay test quality assessment is addressed in the next section. 5. Function-robust and function-non-robust propagation of the delay faults Our experiences in functional delay fault testing revealed that typically not all the delay faults of the circuits can be detected by
SIT tests. For detecting of some delay faults, MIT tests are required. The MIT test launches several signal transitions on the inputs of the circuit simultaneously. Some of these signal transitions can overlap or partly block each other. Therefore, some delay fault effects can be propagated as signal glitches, which can be observed and measured by test equipment. Such a propagation of the fault effect is called a weak non-robust propagation [21]. A conventional transition fault test uses the weak non-robust propagation [21]. The weak non-robust propagation at the gate-level is equivalent to the function-non-robust propagation at the functional level. Therefore, it is meaningful to think of the rules that allow generating the functional delay test, which enables the function-non-robust propagation. When the fault effect propagates as the signal glitch, there is no signal transition on the output, if we observe it in the static mode. The value transitions from the inputs are propagated to the outputs along the paths of the circuit. In order to generate a functional test it is necessary to determine which input signal transition influences a particular output signal transition. Therefore, it would be rational to examine the influence of the blocking of separate input signal transition on the output signal transition. Signal transitions on the inputs have to be blocked one by one keeping the value in the second pattern the same as the value in the first one. Let us use an example to explain in detail the concept of the blocking of the input signal transition. Suppose that there exists a pair of input patterns h1 0 1 0, 0 1 1 1i, where signal transitions are observed on the first, the second, and the fourth inputs. When the transition is blocked on the first input, the pair of patterns becomes the following: h1 0 1 0, 1 1 1 1i. When the transition is blocked on the second input, the pair of patterns becomes the following: h1 0 1 0, 0 0 1 1i. When the transition is blocked on the fourth input, the pair of patterns becomes the following: h1 0 1 0, 0 1 1 0i. The transition blocking on the input may disable transitions on some outputs. Such behavior means that the blocked transition on the input directly influences the transition on the output where the transition was disabled. Therefore, such a pair of patterns allows the function-robust propagation of the delay faults. The other possible case is when the delay faults are detected in the function-non-robust manner. Such a situation arises when the blocked transition on the input invokes the transition on the output that had no transition before. The considered transition on the input blocked the influence of the transition on some other input, and, when this transition was disabled, the additional transition appeared on the output, on which it was not observed before. Let us consider a small example. Suppose that two opposite transitions 0 ? 1 and 1 ? 0 appear on the 2-inputs AND gate. There is no transition on the output of this gate. But, if one input delays, the glitch will be observed on the output. This glitch can be measured by test equipment and the delay will be detected. The detection of the functional delay faults can be represented by the detection matrix kXk2n4m, where n – number of primary inputs, and m – number of primary outputs. The primary input i is represented by two rows: namely 2i 1 and 2i, in the matrix. The row 2i 1 describes the effect of the signal transition 0 ? 1 on the primary input, and the row 2i describes the effect of the signal transition 1 ? 0 on the primary input. The primary output j is represented by four columns. The column 4j 3 stands for the function-robust detection of the delay faults when the signal transition 0 ? 1 appears on the primary output. The column 4j 2 stands for the function-robust detection of the delay faults when the signal transition 1 ? 0 appears on the primary output. The column 4j 1 stands for the function-non-robust detection of the delay faults when the signal transition 0 ? 1 appears on the primary output. The column 4j stands for the function-non-robust detection of the delay faults when the signal transition 1 ? 0 appears on the primary output. The corresponding entry of the matrix X
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is set to 1 if the disabled signal transition on the primary input invokes or disables the signal transition on the primary output. The functional delay test generation can be carried out according to the ideas presented in this section. The generation is based on the random search method. A pair of test patterns is generated randomly. Signal transitions are blocked one by one keeping the same value in the second pattern of the pair as in the first one. The responses are measured at the primary outputs of the circuit. If the blocking of the value on the primary input has some influence on the primary output response as explained before the corresponding entry of the detection matrix is set to 1, which means that the corresponding functional delay fault is detected, and the randomly generated pair of test patterns is included into the test set. The generation procedure is allowed to run until all the functional delay faults are detected both function-robustly and function-non-robustly. The number of the functional delay faults is less than or equal to 4 n m. Usually, some of these faults are untestable, because the logic paths do not exist between some primary inputs and some primary outputs. In general case, this number is unknown a priori. The solution to the problem of stopping the functional delay test generation using the detection matrix is presented in [25]. Let us consider an example of the 3-input function z = ac0 + a0 c + bc (Fig. 2) [6]. The coupling delay test set is presented in Table 3 [6]. This is an ideal test set, because it covers all the paths in the circuit realization only once. The problems of the coupling delay test generation were enumerated in Introduction. Suppose that only a single transition is allowed on the inputs of the circuit. It is worth to pay attention to the fact that in the case of a single transition the function-non-robust detection is not possible. The functional delay pattern pairs are presented in Table 4. The corresponding detection matrix X is given in Table 5. In order to understand the filling up of the detection matrix easier, Table 6 shows the test pattern pairs that detect the corresponding functional delay faults in the function-robust manner. The detection matrix X, which is shaded in Table 5 and Table 6, has 6 rows and 4 columns that obey the formula 2n 4m. Two rows are reserved for every input, and four columns are reserved for every output. The first row that is reserved for the input a corresponds to the formula 2i 1, when i is 1 and it is filled up for the signal transition 0 ? 1 on this input. The second row that is reserved for the input a corresponds to the formula 2i when i is 1 and it is filled up for the signal transition 1 ? 0 on this input. The single primary output is represented by four columns. The first
a
1
c
&
1
&
1
z
&
b
Fig. 2. A realization of the function z = ac0 + a0 c + bc.
Table 3 Coupling delay test set. t1 t3 t5 t7 t9 t11
h0 1 0, h1 0 1, h1 0 1, h0 0 0, h0 1 0, h1 0 1,
1 1 0i 0 0 1i 1 1 1i 0 0 1i 0 1 1i 1 0 0i
t2 t4 t6 t8 t10 t12
h1 1 0, h0 0 1, h1 1 1, h0 0 1, h0 1 1, h1 0 0,
0 1 0i 1 0 1i 1 0 1i 0 0 0i 0 1 0i 1 0 1i
Table 4 Functional delay test with single transition. Input
Output
t1 t3 t5 t7
h0 1 0, h1 0 1, h1 0 1, h0 0 0,
1 1 0i 0 0 1i 1 1 1i 0 0 1i
t11
h1 0 1, 1 0 0i
t2 t4 t6
h1 1 0, 0 1 0i h0 0 1, 1 0 1i h1 1 1, 1 0 1i
t10 t12
h0 1 1, 0 1 0i h1 0 0, 1 0 1i
t1 t3 t5 t7
h0, h0, h0, h0,
1i 1i 1i 1i
t11
h0, 1i
t2 t4 t6
h1, 0i h1, 0i h1, 0i
t10 t12
h1, 0i h1, 0i
Table 5 Detection matrix X for single transition. Input
Output Function-robust detection
Function-non-robust detection
a
1 1
1 1
0 0
0 0
b
1 0
0 1
0 0
0 0
c
1 1
1 1
0 0
0 0
Table 6 Test pattern pairs used to construct X. Input
Output Function-robust detection
Function-non-robust detection
a
t1 t3
t4 t2
0 0
0 0
b
t5 0
0 t6
0 0
0 0
c
t7 t11
t12 t10
0 0
0 0
column corresponds to the formula 4j 3, when j is 1. It stands for the function-robust detection when the signal transition 0 ? 1 appears on the primary output. The second column corresponds to the formula 4j 2, when j is 1. It stands for the function-robust detection when the signal transition 1 ? 0 appears on the primary output. The same rule applies to the other two columns that stand for the function-non-robust detection. Comparing the functional delay test set (Table 6) with ideal test set (Table 3), we see that former set does not include two test pattern pairs, namely t8 and t9. The answer to this problem lies in the detection matrix X. The input c is included into 3 minterms which means that six test pattern pairs are needed in order to propagate the transition from this input to the output by all the possible different paths in the circuit, but the matrix X for the relationship between input c and output has only 4 entries that are allocated for identifying the function-robust fault detection. So, at most four test pattern pairs for input c can be produced when generation is based on the matrix X and single transition. Certainly, the lack of two test pattern pairs means that some delay faults will be uncovered. Suppose that the generation of functional delay test including MIT in test pattern pairs is allowed. The corresponding functional delay test patterns are listed in Table 7, and the detection matrix X is presented in Table 8. As we can see, the function-robust detection includes nine test pattern pairs, while the function-non-robust detection includes six test pattern pairs. Indexing of test pattern pairs is different from those in Table 3 or Table 4. The function-robust detection was divided into two parts: a single input transition pairs of test patterns and multi-input transitions pairs of test patterns. Note that the test pattern pairs, which hold the property of
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Table 7 Functional delay test with multiple transitions. SIT
Output
Function-robust detection h0 0 0, 0 0 1i t1 h1 0 0, 0 0 0i t3 h1 0 1, 1 0 0i t5 MIT h0 0 0, 1 1 1i t7 h0 1 1, 1 0 1i t9
t2 t4 t6
h0 1 1, 0 1 0i h0 1 0, 1 1 0i h1 0 1, 0 0 1i
t1 t3 t5
h0, 1i h1, 0i h0, 1i
t2 t4 t6
h1, 0i h0, 1i h0, 1i
t8
h1 1 0, 1 0 1i
t7 t9
h0, 1i h1, 0i
t8
h1, 0i
h1 1 0, 0 1 1i h0 1 0, 1 0 1i h1 0 1, 0 0 0i
t10 t12 t14
h1, 1i h1, 1i h1, 1i
t11 t13 t15
h1, 1i h0, 0i h0, 0i
Function-non-robust detection h0 0 1, 1 0 0i t11 t10 h1 1 1, 0 0 1i t13 t12 h0 0 1, 1 1 1i t15 t14
Table 8 Detection matrix X for multiple transitions. Input
Output Robust detection
Non-robust detection
a
1 1
1 1
1 1
1 1
b
1 0
0 1
0 1
1 0
c
1 1
1 1
1 1
1 1
the function-non-robust detection, have no transition on the output. This simple example shows that the MITs do not exclude entirely the SITs. In general, the number of test pattern pairs is increased. These test pattern pairs cover all the paths of the circuit realization already. That shows that the generation based on the detection matrix X and MIT is preferable than the generation based on the detection matrix X and SIT only. Not all the paths are covered function-robustly but nevertheless all the paths are covered. That has another advantage. The non-robust delay test is effective in reducing the test size [8]. The new functional delay test generation algorithm was implemented, and the experiments were carried out. In the first experiment, we took for the investigation the transition fault test that was generated automatically at the gate-level by TetraMAX and that has complete transition fault coverage. The results are summarized in Table 9. It should be noticed that some benchmark circuits have untestable transition faults. Such faults were excluded from the calculation of the transition fault coverage. It is worth to pay attention to the column under name ‘‘Kmax”. This column shows the maximum number of non-zero entries of
Table 9 Function-robust and function-non-robust detection. Circuit
C432 C499 C880 C1355 C1908 C2670 C3540 C5315 C6288 C7552
Kmax
540 5184 1326 5184 3004 3320 2588 10,540 3068 12,188
Test size
142 223 137 306 316 259 403 301 122 461
Number of non-zero entries
Coverage (%)
Functionrobust detection
Function-nonrobust detection
Functionrobust
Total
345 907 606 1518 1001 1758 1672 4992 2346 5236
345 1258 599 1313 1027 1512 1664 4772 2354 5087
64 18 46 29 34 53 65 47 77 43
87 36 62 48 43 66 77 60 82 53
the matrix X for function-robust detection. In other words, Kmax is the number of the detectable functional delay faults. These values were taken from [20]. To obtain the number of detectable functional delay faults according to the software prototype is quite a complex task, because not all the inputs have influence on the outputs, and the transition may propagate through the even and/or odd number of the inversions. The number of non-zero entries of the detection matrix X was calculated for function-robust and function-non-robust detection separately (the fourth and fifth columns of Table 9). The results show that the obtained values are comparable. The last two columns present the coverage of the functional delay faults by the transition fault test. The values in the penultimate column indicate how many functional delay faults were covered in the function-robust mode. The values in the last column show the total coverage of functional delay faults when functional faults were covered in the function-robust or in the function-non-robust mode. As we can see, the obtained values are very far from 100%. The results in the last two columns allow evaluating the usefulness of the test pattern pairs, selected on the base of the function-non-robust property. We see, that these test pattern pairs always added their value to the total coverage of functional delay faults. It means that some functional delay faults are covered function-non-robustly by the given complete transition fault test only. As a conclusion to the experiment, we can state that the test, which is generated at the gate-level and detects all the transition faults, does not cover the functional faults completely at the functional level. Such an outcome can be explained by the differences between the functional level and the structural level of the circuit. At the functional level, the structural implementation of the circuit is unknown. The circuit can be implemented in many different ways. Therefore, the functional faults target to cover all the possible implementations. Consequently, the test patterns constructed for a particular implementation can not cover all the functional faults. In order to determine the influence of the function-robust and function-non-robust detection on the selection of test pattern pairs the second experiment was carried out (Table 10). We took for the investigation the transition fault test (Table 9) that has complete transition fault coverage at the gate-level. During the experiment, the number of not selected test patterns from the initial complete transition fault test was determined. The selection was based on both properties separately as well as on both properties together. The columns of Table 10 next to the first column are grouped in pairs and the headings were allocated for the pairs of the columns. The heading of the pair indicates the property of test pattern pairs, according to which they were selected. The first column of a pair shows the number of test pattern pairs that were not selected according to the named property, whereas the second column of
Table 10 Not selected test patterns. Circuit
C432 C499 C880 C1355 C1908 C2670 C3540 C5315 C6288 C7552
Function-robust
Function-non-robust
Total
Number
Percentage (%)
Number
Percentage (%)
Number
Percentage (%)
37 110 28 151 145 60 96 18 2 74
26 49 20 49 45 23 23 5 1 16
40 86 21 133 138 64 88 10 4 67
28 38 15 43 43 24 21 3 3 14
13 15 5 46 95 22 33 3 1 25
9 6 2 15 30 8 8 1 1 5
E. Bareisa et al. / Microelectronics Reliability 49 (2009) 1578–1585
The proposed methods are applicable for the combinational circuits or the sequential ones, which can be tested using the enhanced scan methodology.
Table 11 Transition fault coverage of MIT test. Circuit
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Multiple transition
Compacted
Test size
Transition fault coverage (%)
Test size
Transition fault coverage (%)
C432 C499 C880 C1355 C1908 C2670 C3540 C5315 C6288 C7552
257 1944 621 1869 1094 769 854 1948 481 3960
96.08 99.88 98.46 98.51 94.41 99.17 96.90 100 100 99.13
244 1159 743 1068 1814 1153 1166 3382 903 4331
94.69 93.00 100.00 95.01 94.58 98.12 94.21 99.91 99.89 98.03
Average
1380
98.85
1596
96.74
the pair expresses this value in percent. As we can see, the percent of the lost valuable test pattern pairs is quite high when both properties were considered separately. The results are much better when the selection is based on both properties together. The latter outcome indicates the value of the function-non-robust detection. During the third experiment, the functional test was generated according to the detection matrix X, when the algorithm selected the test pattern pairs that possess the function-robust and/or function-non-robust property. The obtained test was evaluated at the gate-level for the transition fault coverage (Table 11). The functional test detects all the testable functional delay faults at the functional level. The full coverage of transition faults was obtained for the circuits C5315 and C6288. It is an excellent result. This outcome justifies the hope that the test for the transition faults can be generated at the functional level according to the software prototype. The results in the columns under name ‘‘Compacted” are taken from Table 2 and included for the comparison purposes. The higher fault coverages are shown in bold. We remind that the compacted test was constructed from the SIT test and it became the MIT test. We see that the generated test is better than the compacted test with respect to both criteria: (1) the test size on average is smaller; (2) the fault coverage on average is higher. 6. Conclusions In the paper, we have presented the methods of functional delay test development based on the software prototype. Some methods are designed to generate SIT tests, other methods – MIT tests. The quality of the functional delay test is evaluated at the functional level and then the transition fault coverage is determined at the gate-level. Our experimental results show that the test sets, which are generated according to the functional delay fault model, achieve high fault coverage of transition faults. SIT tests cover up to 95.82% of transition faults. MIT tests, which consider the function-robust and function-non-robust propagation of the delay faults, allow obtaining even higher transition fault coverage (98.85%). The test size of a MIT test is almost two times lesser than that of a SIT test. But the SIT test can be compacted according to the presented Lemma and its Corollaries. The compacted test becomes the MIT test. Nevertheless, it still retains the functional robust propagation property.
References [1] Underwood B, Law WO, Kang S, Konuk H. Fastpath: a path-delay test generator for standard scan designs. In: Proceedings of 1994 international test conference (1994); 1994. p. 154–63. [2] Pomeranz I, Reddy SM. On testing delay faults in macro-based combinational circuits. In: Proceedings of international conference on computer-aideddesign, San Jose, CA; 1994. p. 332–9. [3] Pomeranz I, Reddy SM. Functional test generation for delay faults in combinational circuits. In: Proceedings of 1995 international conference on computer-aided-design (1995); 1995. p. 687–94. [4] Kim H, Hayes JP. Realization-independent ATPG for designs with unimplemented blocks. IEEE Trans CAD 2001;20(2):290–306. [5] Yi J, Hayes JP. a fault model for function and delay testing. In: Proceedings of the IEEE European test workshop, ETW’ 01; 2001. p. 27–34. [6] Yi J, Hayes JP. The coupling model for function and delay faults. J Electron Test: Theory Appl 2005;21(6):631–49. [7] Bareisa E, Jusas V, Motiejunas K, Seinauskas R. Test generation at the algorithm-level for gate-level fault coverage. Microelectron Reliab 2008;48(7):1093–101. [8] Yi J, Hayes JP. High-level delay test generation for modular circuits. IEEE Trans Comput-Aid Des Integr Circ Syst 2006;25(3):576–90. [9] Maxwell PC, Aitken RC, Kollitz KR, Brown AC. IDDQ and AC scan: the war against unmodeled defects. In: Proceedings of international test conference, March 2006. p. 250–8. [10] Pomeranz I, Reddy SM. On improving the stuck-at fault coverage of functional test sequences by using limited-scan operations. In: Proceedings of the IEEE international test conference; 2001. p. 211–20. [11] Seinauskas R, Targamadze A, Jusas V. Test and test bench generation by algorithmic models. In: Information technology and control, Kaunas, Technologija, No. 1; 1997. p. 19–25. [12] Bareisa E., Jusas V., Motiejunas K., Seinauskas R. functional test generation remote tool. In: Proceedings of the 8th EuroMicro conference on digital system design (DSD’2005), Porto, Portugal, 30 August–3 September; 2005. p. 192–5. [13] Bushnell M, Agrawal V. Essentials of electronic testing. Kluwer Academic Publishers; 2000. nas K, Šeinauskas R. Functional delay clock fault [14] Bareiša E, Jusas V, Motieju models. In: Information technology and control, Kaunas, Technologija, vol. 37(1); 2008. p. 12–8. [15] Ferrandi F, Fummi F, Pravadelli G, Sciuto D. Identification of design errors through functional testing. IEEE Trans Reliab 2003;52(4):400–12. nas K, Šeinauskas R. The use of a software prototype [16] Bareiša E, Jusas V, Motieju for verification test generation. In: Information technology and control, Kaunas, Technologija, vol. 37(4); 2008. p. 265–74. [17] Ferrandi F, Fummi F, Sciuto D. Implicit test generation for behavioral VHDL models. In: Proceedings of international test conference, 18–23 October1998. p. 587–96 . [18] Pomeranz I, Reddy SM. Estimating the relative single stuck-at fault coverage of test sets for a combinational logic block from its functional description. In: Proceedings of sixth IEEE international high-level design validation and test workshop; 2001. p. 31–5. [19] Seinauskas R, Bareisa E. Test selection based on the evaluation of input stuckat faults transmissions to output. In: Information technology and control, Kaunas, Technologija, vol. 2(3); 1996. p. 15–8. [20] Michael M, Tragoudas S. ATPG tools for delay faults at the functional level. ACM Trans Des Automat Electron Syst 2002;7(1):33–57. [21] Shao Y, Pomeranz I, Reddy SM. On generating high quality tests for transition faults. In: Proceedings of the 11th Asian test symposium (ATS’02); 2002. p. 1– 8. [22] Tragoudas S, Michael M. ATPG tools for delay faults at the functional level. In: Proceedings of design. Automation and test in Europe conference and exhibition; 1999. p. 631–5. nas K, Šeinauskas R. functional delay test [23] Bareiša E, Jusas V, Motieju construction approaches. In: Elektronika ir elektrotechnika = Electronics and electrical engineering, Kaunas, Technologija, vol. 2(74); 2007. p. 49–54. ISSN 1392-1215. [24] Pomeranz I, Reddy SM. Vector-based functional fault models for delay faults. In: Proceedings of the 8th Asian test symposium (ATS’99); 1999. p. 41–6. nas K, Šeinauskas R. Functional test generation [25] Bareiša E, Jusas V, Motieju based on combined random and deterministic search methods. Informatica 2007;18(1):3–26.
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Functional delay test generation based on software prototype Eduardas Bareisa, Vacius Jusas *, Kestutis Motiejunas, Rimantas Seinauskas Kaunas University of Technology, Informatics Faculty, Department of Software, Studentu 50, Kaunas, Lithuania
a r t i c l e
i n f o
Article history: Received 21 January 2009 Received in revised form 30 June 2009 Available online 11 August 2009
a b s t r a c t The paper presents two methods of functional delay test development based on the software prototype as well as the results of their application to benchmark circuits. The first method is used to construct the functional delay test on the base of a pin pair test generated at the functional level for detection of stuck-at faults at the gate-level. The constructed test is a single input transition test. The latter appears to be quite large. Therefore, we provide the method for compacting it. The compacted single input transition test becomes a multi-input transition test. The second method is used to generate a multi-input transition test. The generated functional test pattern pairs possess function-robust and/or functionnon-robust properties. The introduction of the function-non-robust property enriches the functional delay test. The presented test construction approach based on the software prototype allows obtaining a functional delay test, which detects the transition faults at the gate-level of a circuit quite completely. Ó 2009 Elsevier Ltd. All rights reserved.
1. Introduction Continuously growing complexity of digital devices creates new challenges for test designers. Delay testing is gaining more and more industry attention to maintain test quality for speed-related failures. The purpose of a delay test is to verify that a circuit operates correctly at a desired clock speed. A pair of test patterns is used to detect delay faults. The first pattern sets the initial values on the inputs of the circuit, whereas the second pattern launches the transition. Conventional delay test generation techniques based on gate-level fault models are not suitable for circuits whose implementation details are unavailable. The functional test can be generated for such circuits according to their specifications. According to the functional delay fault models proposed in [1– 3], a fault is a tuple (I, O, tI, tO), where I is an input of the circuit under test (CUT), O is a CUT output, tI is a rising or falling transition at I, and tO is a rising or falling transition at O. A test for the functional delay fault is a pair of input patterns hu, vi that propagates a transition from a primary input to a primary output of the circuit. Under the model introduced in [1], only one pair of test patterns must be generated per fault. Pomeranz and Reddy [2] proposed that all possible patterns are generated for each fault. This model guarantees detection of all robustly testable path delay faults in any gate-level implementation. However, the sizes of the resulting test sets as well as test generation times are very large and make this model impractical, especially for large circuits. The studies in
* Corresponding author. Tel.: +370 37 327617; fax: +370 37 300352. E-mail addresses: [email protected] (E. Bareisa), [email protected] (V. Jusas), [email protected] (K. Motiejunas), [email protected] (R. Seinauskas). 0026-2714/$ - see front matter Ó 2009 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2009.06.050
[3] showed that it is not necessary to generate all possible test patterns for each fault in order to guarantee that actual path delays are covered in some gate-level implementation of the function. The model [2] was modified in [3] by considering D different test patterns per fault. Here, D is a positive integer, usually in low hundreds, and is given as an input parameter for each CUT. The problem is the selection of D. Several black-box fault models based on input stimuli and output responses were suggested in [4–7]. The most universal is the single coupling fault model proposed in [5] and extended in [6], which is defined in terms of a single input/output pair. The average size of the test set is 2n 1, where n denotes the number of inputs of the module [6]. Therefore, the test sets are very large even for small modules and not practical in many cases. Yi and Hayes [8] extended high-level delay fault models to large modular logic circuits applying a hierarchical approach to delay test generation for modular circuits. The proposed new fault model based on the coupling delay fault model [6] imposes requirements for robust delay testing on module implementation and on the input pattern pair. The proposed fault model has several drawbacks. Each circuit is manually partitioned into multiple modules such that the output of every module has at most 12-inputs so that the coupling delay test set is kept reasonably small. Although the coupling delay test set for a function z detects all robust path delay faults in any gate-level realization of z [6], the module path delay test set (MPDTS) [8] for a modular realization of z may fail to detect all such faults. This is possible either because many path delay faults are not testable robustly or because some robust path delay faults are not detectable by an MPDTS. Since complete coverage of robust path delay faults is not guaranteed by MPDTSs, any strong conclusions cannot be drawn from the proposed model.
E. Bareisa et al. / Microelectronics Reliability 49 (2009) 1578–1585
The functional fault models [7] that are named pin pair (PP) and pin triplet (PT) enable to develop the functional test on a base of the software prototype at early stages of the design process, while a synthesized description of the device is not available yet. Very promising results were achieved in functional test generation for detecting stuck-at faults when the generation was based on the PP fault model [7]. The average percent of undetected faults did not exceed 0.5% for ISCAS’85 benchmark circuits. The test sets for PP faults are larger than the test sets generated at the gate-level by TetraMAX only six times on average. Therefore, the PP fault model was chosen as the basic model for the functional delay test generation.
2. The significance of functional test The test designer prepares a functional test according to the specification of the device under test. The functional test is used to verify the next steps of the design. Functional test sequences were shown to detect unique defects in VLSI circuits [9]. However, functional test sequences do not achieve complete stuck-at fault coverage. Therefore, there is a sense to use the functional test as the basis for gate-level test generation, thereby reducing or eliminating the need for separate stuck-at test generation [10]. During the design process, a software prototype of the device is created according to the specification. The software prototype simulates the functions of the device, enabling to calculate the output values according to the input values, and can be regarded as a black-box model of the device. The functional test can be generated on the base of the software prototype. The software prototype defines the functionality of the device using input variables, output variables and state variables. The calculation of the output values and new state values is based on the input values and the old state values. Therefore, we treat the state variables in two different ways: as the input variables before the calculation and as the output variables after the calculation. Generally, the variables of the software prototype can be classified into two groups: the input variables and the output variables keeping in mind that the state variables take part in both groups. Consequently, we always can assume that the software prototype model is the combinational one, and the output values depend on the input values only. The software prototype used in the initial stages of the design process exposes the primary idea of the device only. Therefore, its functionality can be described in a very simple form. For example, the circuit S344 from the benchmark suite ISCAS’89 and the circuit C6288 from the benchmark suite ISCAS’85 are multipliers. The body of the software prototype of these circuits consists of a single expression, which multiplies the first operand by the second operand and assigns the multiplication result to the third operand. Meanwhile, the gate-level description of the circuit C6288 has a very large number of paths. There exist various implementations of the circuit S344. Some of these implementations are the combinational ones; the others are the sequential ones. The test patterns constructed using the software prototype can be applied to the combinational circuits directly. The application of test patterns, constructed according to the software prototype, which has no state variables, to sequential circuits requires the use of the test frame [11,12] that makes possible expanding the functional test time-wise and adjusting it to the implementation details of the circuit. The test frame allows introduction of reset, start, clock signals, which usually are not present in the software prototype model. When the test frame is used, the rated-clock non-scan sequential test methodology has to be adopted for testing delay faults [13,14]. The functional test is based on the function of a circuit, which can be realized in many ways. The possible defects of the circuit
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depend on an implementation. The test is usually developed for the specific implementation and it is devoted to detect the defects of this particular implementation. The manufacturing test can be developed using the specific implementation only. Meanwhile, the functional test is not related to a particular implementation because it is generated from a circuit’s specification rather than its gate-level implementation. The size of a functional test is usually much larger than that of an implementation-dependent one to assure good fault coverage for many implementations. The functional test, which is independent of the implementation, has several advantages over the implementation-dependent test. The functional test can be used to correct testability problems early in the design process [2], to identify the design errors [15,16], to test many potential implementations [4,17], and to detect hard-to-detect faults at gate-level implementation [17]. The objective of the paper is to research and to develop functional delay test generation methods based on a software prototype. We start with the presentation of the method that enables the construction of a functional delay test using the PP fault test in Section 3. The problem of constructing a compact functional delay test set is addressed in Section 4. We present a method that allows multi-input transition in test pattern pairs, which possess function-robust and/or function-non-robust properties in Section 5. We conclude in Section 6.
3. Functional delay test construction based on PP fault test We start this section by providing a brief presentation of the main concepts of the PP fault model [7]. Let a circuit have a set of primary inputs X = {x1, . . . , xi, . . . , xn}, and a set of primary outputs Y = {y1, . . . , yj, . . . , ym}. We will write x1i , x0i for stuck-at 1/0 faults at the primary input xi, i 2 1, . . . , n}, and y1j , y0j for stuck-at 1/0 faults at the primary output yj, j 2 1, . . . , m}, respectively. Under PP fault model, a fault is described by a pair of stuck-at faults (xti , ykj ), t = 0, 1, k = 0, 1. The fault (xti , ykj ) is detected by test pattern p that satisfies the following conditions: 1. The test pattern p detects the single fault xi stuck-at t. 2. The fault free value of output yj under p is k. 3. In the presence of xi stuck-at t, the value of output yj is k. Let us consider an example. Suppose we are given the three-input, two-output circuit that implements the functions y1 ¼ x1 x2 þ x1 x3 , and y2 ¼ x1 x2 x3 . We examine the test pattern p = h1 0 1i. Under p = h1 0 1i, we obtain the output vector y (1 0 1) = h0 0i. The test pattern p detects the following PP faults: (x01 , y11 ), (x12 , y11 ), (x12 , y12 ). The number of possible PP faults of the circuit is at most 4 n m. It may appear that there exist no electric connections between the primary input xi and the primary output yj of the circuit, and the PP fault associated to xi and yj cannot be detected. These faults are untestable. The PP fault (xti , ykj ) of a circuit is testable if a conventional deterministic test generator for a realization of the circuit finds a test pattern, which detects a pin fault xti on the primary output yj meanwhile the primary input xi and the primary output yj are set up to the opposite values (not t on the primary input and not k on the primary output). The number of testable PP faults equals 4 n m minus the number of untestable PP faults. The main drawback of the PP model is that the untestable faults are not known a priori. The test generation for the PP fault is based on the random search procedure [7]. The test pattern is generated randomly, and then it is simulated on the functional model of the circuit. The sensitivity of the value on each primary input is checked by complementing it one by one and simulating again. If the responses of the generated pattern and the changed pattern
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differ on some primary outputs, an appropriate PP faults are detected. A similar fault model, called PI–PO, was presented in [18]. But Pomeranz and Reddy [18] use this fault model only for the metric in order to predict relative gate-level stuck-at fault coverage of different test sets, when the gate-level description of a logic block is unknown. They showed through experimental results that the proposed metric is accurate in predicting relative gate-level fault coverage. It is more accurate than a fault model that consists only of primary input faults (without taking into account primary output values). We have understood this property much earlier [19]. The PP fault model lies at the background of many of our researches. If we compare functional delay [1,2] and PP fault models we see that both models have almost the same meaning with one distinction: the functional delay model is intended for detection of malfunctions in the dynamic behavior of the module, whereas the PP fault model – for detection of malfunctions in the static state of the module. For example, consider a circuit, which has five inputs x1, x2, x3, x4, x5, and two-outputs y1, y2. The model of the circuit presented in the form of a Boolean expression is shown in Fig. 1. The circuit response to the input pattern h1 0 0 1 1i is h0 1i. This pattern detects the PP faults (x12 , y11 ), (x13 , y11 ), (x13 , y02 ), and (x05 , y02 ). The functional delay fault (x2, y1, fx2, fy1) is detected by the pair of input patterns h1 1 0 1 1, 1 0 0 1 1i, where the second pattern of the pair coincides with the pattern that detects the PP faults. Based on this observation and on the properties of the delay test [6,20,21], we can define a rule how to extend the PP fault test to the functional test for delay fault.
Y 1 ¼ x1 x2 þ x1 x3 þ x1 x2 x3 þ x1 x2 x3 x4 Y 2 ¼ x2 x3 þ x2 x4 þ x2 x3 x5 þ x2 x3 x4 x5 Rule. If the input pattern q detects the PP fault (xti , ykj ), t = 0,1, k = 0,1, then the pair of input patterns hp, qi, while the signal value of input xi in the pattern q is t and the signal value of input xi in the pattern p is t, detects functional delay faults: (xi, yj , rxi, ryj), when t = 0, k = 0; (xi, yj , rxi, fyj), when t = 0, k = 1; (xi, yj , fxi, ryj), when t = 1, k = 0; (xi, yj , fxi, fyj), when t = 1, k = 1 (r and f denote rising and falling transitions, respectively). Suppose an input pattern w detects l PP faults. Then, according to Rule, the transformation of this pattern can provide at most l pairs of input patterns for detection of the corresponding l functional delay faults (signal transition on one input can cause signal
y1 = x1x2 + x1x3 + x1x2x3 + x1x2x3x4 y2 = x2x3 + x2x4 + x2x3x5 + x2x3x4x5 Fig. 1. The model of the circuit.
transitions on s outputs, therefore, only one pair of input patterns is needed for detection of s functional delay faults). For example, let us consider the input pattern h1 0 0 1 1i. Let us complement the input values one by one and measure the responses at the outputs. The following five different test patterns would be formed: h0 0 0 1 1i, h1 1 0 1 1i, h1 0 1 1 1i, h1 0 0 0 1i, h1 0 0 1 0i. The complement of the value on the first and fourth inputs does not change the values at the outputs. Therefore, the values on these inputs are not sensitive. The transitions from these inputs would not propagate to the outputs. The complement of the value on the second input changes the value on the first output only. The complement of the value on the third input changes the values on both outputs. The complement of the value on the fifth input changes the value on the second output only. Therefore, the transformation of the input pattern h1 0 0 1 1i results into three pairs of delay test patterns (h1 1 0 1 1, 1 0 0 1 1i, h1 0 1 1 1, 1 0 0 1 1i, h1 0 0 1 0, 1 0 0 1 1i) that detect the functional delay faults (x2, y1, fx2, fy1), (x3, y1, fx3, fy1), (x3, y2, fx3, ry2), and (x5, y2, rx5, ry2). Note, that all pairs of test patterns derived from PP tests, using Rule, are single input transition (SIT) tests, and, therefore, all test pattern pairs satisfy the function robust propagation property [20]. During the experiments, we have used software prototype models written in the C programming language. Non-redundant ISCAS’85 benchmark circuits have been selected for the experiments, because they are more demanding for testing purposes than combinational parts of the sequential circuits of the benchmark suite ISCAS’89. The comparison of the sizes of test sets and coverage of the transition faults of the non-redundant ISCAS’85 benchmark circuits are given in Table 1. In [22], no results are provided for the circuit C1355, therefore it is not included in the table. Note that the functional test sets detect 100% of targeted PP faults. The average percent of the detected transition faults by the tests generated for the function delay faults exceeds 95.67%, but the minimum percent of the detected transition faults is 83.08% (circuit c3540). We can see that, for the considered circuits, the size of the functional delay test obtained by the above-described transformation is on average 3.77 times larger than the size of PP fault tests. Thus, almost four test pattern pairs are generated for each separate test pattern. As we briefly reviewed in the introduction, there are many studies devoted to the development of methods for testing of functional delay faults. However, the obtained numerical results – the test sizes for the considered circuits – are reported only in [22]. Therefore, the last two columns of Table 1 show the results of the approach in [22]. The approach by Tragoudas and Michael [22] utilizes such techniques as Reduced Ordered Binary Decision Diagrams (ROBDDs) and Boolean Satisfiability (SAT). The problem of finding a set of test patterns for a given (I, O, tI, tO) combination is reduced to solving a SAT formula in conjunctive normal form. A different formula is constructed for each (I, O, tI, tO). Therefore,
Table 1 Transition fault coverage. Circuit
C432 C499 C880 C1908 C2670 C3540 C5315 C6288 C7552 Average
Test size of PP
Functional delay test size
Coverage (%)
Tragoudas–Michael [22] method. Test size
Coverage (%)
117 1077 381 620 448 515 1169 268 2115
348 5180 1001 2359 1820 1457 4950 1065 5801
95.56 94.40 98.91 95.24 96.51 83.08 98.41 99.75 99.21
804 3915 1321 3153 3956 2493 10,662 2085 13,815
96.6 90.5 96.6 97.8 98.5 91.3 99.5 89.2 99.2
746
2965
95.67
4689
95.47
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this approach is not truly functional, because ROBDD and SAT formulas are constructed according to the structure of the circuit. We see that in our approach the test sizes are considerably shorter, except the circuit C499, but the fault coverage is noticeably better for this circuit. In general, the fault coverage for about a half of circuits is slightly better in [22], nevertheless on average it is slightly better in our approach, because the approach by Tragoudas and Michael [22] looses very significantly for the circuit C6288. ROBDD of this circuit cannot be constructed. ROBDD was created by simplifying the function after preselecting inputs randomly [22]. We have never had any problems with circuit models because they in our approach are always functional. We see from Table 1 that the sizes of the test sets obtained using the presented method are significantly larger in comparison with the sizes of the initial PP test sets. It is very important to have compact test sets in order to reduce the cost of testing of very large scale integrated circuits by reducing the test application time. This is especially critical for the scan-based circuits as the test application time for such circuits is directly proportional to the product of the test set size and the number of storage elements used in the scan chain. Small test sets also reduce the requirements for test storage. The only way to compact a functional delay fault test is to allow multi-input transition (MIT) in test pattern pairs. The problem of constructing a compact MIT functional delay test is addressed in the next section.
4. Functional test compaction Test pattern pairs constructed according to Rule hold the change of the signal value only on a single input. Let us continue the analysis of our example. The considered input pattern h1 0 0 1 1i detects 4 PP faults, though for detection of the corresponding functional delay faults only three test pattern pairs are built as the signal transition on input x3 invokes the signal transitions on both outputs y1 and y2 simultaneously. Therefore, the number of the test pattern pairs obtained using Rule is equal to the number of inputs involved in PP fault detection on the considered test pattern. In our case, three such inputs are present, and, consequently, three test pattern pairs are built. Another way to obtain functional delay fault tests from PP tests is described in [23]. By applying the approach from [23] every input pattern that detects PP faults is transformed only into a single input pattern pair. This is done in such a way that the signal value transition occurs on every input involved in PP fault detection on the considered test pattern. In our example, only a single input pattern pair h1 1 1 1 0, 1 0 0 1 1i is constructed. Consequently, if a test for PP faults consists of p input patterns the constructed functional delay fault test would consist of p input pattern pairs, as well. Thus, the obtained test is much shorter than that produced by applying Rule. The experiments on ISCAS’85 benchmark circuits demonstrated the test shortening of 3.8 times on average, but the transition fault coverage is 91.29% only [23]. This number is significantly smaller than the transition fault coverage shown in Table 1. Test pattern pairs constructed by applying the approach from [23] hold the change of the signal value on more than one input. Therefore, these pattern pairs are MIT tests [20]. Some of functional delay faults that are functional robustly detectable on SIT test may become functional non-robustly detectable [20] or, even worse, not detectable on the considered test pattern pair, because some activation conditions needed for signal transition propagation from a particular input to a particular output may be corrupted. But the MIT tests are indispensable in some cases as some delay faults can be detected by the MIT tests only. This statement is supported by the results from [23], where the transition fault coverage of MIT tests for the circuit C3540 is increased comparing with SIT tests.
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However, the approach in [23] is too much straightforward. The simple initiation of several transitions at the same time may not produce a good coverage of the transition faults in every situation. The transitions can propagate by the same paths and they can cancel each other. The MIT test should include only those transitions that do not mask each other. Therefore, we have to define the necessary conditions for the transition propagation from a particular input to a particular output when the test pattern pair possesses multi-input transitions. Suppose: 1. We are given a multi-input transition test pattern pair hp, qi. 2. The signal value on the input xi in the pattern p is t and the signal value on the input xi in the pattern q is t. 3. The signal value k on the output yj is the circuit response to on the output y is the input pattern p, and the signal value k j the circuit response to the input pattern q. Lemma. If sticking the signal value to t on a single input xi in both test patterns p and q sets a stable signal value k on the output yj in both test patterns, then signal value on the input xi has an effect on this circuit response only. Proof. Suppose a stable signal value k on the output yj is caused by signal values on the input xr in the patterns p and q. Thus, a different circuit response on the output yj could be set solely by the signal value change on the input xr either in both test patterns p and q or in one of them. However, it is a contradiction to the statement of Lemma saying that the signal value change occurs only on single input xi. Therefore, the stable signal value k on the output yj is caused by sticking to t the signal value on a single input xi in the patterns p and q. h Corollary 1. The MIT test pattern pair hp, qi detects the functional y Þ, where t ! t denotes the falling delay fault ðxi ; yj ; t ! t xi ; k ! k j denotes the falling transition on transition on the input xi, and k ! kk the output yj. It is desirable that the generated MIT test would posses the function-robust propagation (FRP) property. According to the definition given in [2], a transition tI on the input I is function-robustly propagated as a tO transition to the output O when the signal value on O changes if and only if the signal value on I changes, independent of the order or speed at which other inputs change. Now we can formulate the next corollary. Corollary 2. The signal value transition t ! t on the input xi, which on the output y , satisfies the causes the signal value transition k ! kk j FRP property. When the MITs are launched in the test pattern pair, logic hazards can occur during this transition. Some logic hazards depend on the implementation of the circuit. When the circuit is considered at the functional level, the gate-level of it is unknown. Therefore, such logic hazards cannot be evaluated at the functional level. The other logic hazards that depend on the order of signal changes on the inputs can be considered at the functional level. An appropriate definition of the FRP property, which evaluates the order of the signal changes on the inputs, is presented in [24]. According to this definition, all the input patterns that may be obtained during the transition from p to q have to produce the same output value as q does. This adds an overhead to test generation, which may require quite a substantial amount of CPU time. Therefore, we have decided to ignore possible logic hazards that can occur during transitions in the MIT test pattern pairs and can invalidate the FRP property of the pattern pair. On the basis of Lemma and its corollaries, we have developed a procedure, named PP2CFD, for transformation of a PP test into a
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Table 2 Test size reduction. Circuit
Test size
Reduction (%)
Coverage (%)
SIT test
PP2CFD
C432 C499 C880 C1355 C1908 C2670 C3540 C5315 C6288 C7552
348 5180 1001 5162 2359 1820 1457 4950 1065 5801
SIT test
PP2CFD
244 1159 743 1068 1814 1153 1166 3382 903 4331
30 78 26 79 23 37 20 32 15 25
95.56 94.40 98.91 97.13 95.24 96.51 83.08 98.41 99.75 99.21
94.69 93.00 100 95.01 94.58 98.12 94.21 99.91 99.89 98.03
Average
2914
1596
36.5
95.82
96.74
compact functional delay test. The main blocks of this procedure are the following: (1) selection of circuit inputs related with PP fault detection (we call them sensitive inputs) in the test pattern Pk and generating of a test pattern pair hP1, P2i where P2 :¼ Pk while signal values on sensitive inputs in the pattern P1 are complemented in regard to signal values in the test pattern Pk; (2) construction of MIT test pattern pairs, which satisfy FRP property, on the basis of hP1, P2i. We conducted an experiment on the SIT test sets, transition fault coverage of which was reported in Table 1. The results are presented in Table 2. The circuit C1355 was not included in Table 1, but we always use this circuit in our experiments, therefore the circuit C1355 is presented in Table 2. The reduction of the test size is expressed in percents. We see that very significant reduction of the test size is achieved for the circuits C499 and C1355. The obtained result is determined by the function of the circuits. The tests of the circuits C499 and C1355 have a large number of sensitive values in every test pattern. This property of the test allowed compressing a lot of SIT test pattern pairs into a single MIT test pattern pair. The last two columns of the table present the transition fault coverage before compaction and after compaction. The best transition fault coverages are shown in bold. It has to be noticed that the compaction did not change the fault coverage of the functional delay faults. The functional delay faults were covered completely before compaction and remained as such after compaction. But the compaction had some impact on the transition fault coverage. The transition fault coverage was not retained – it either increased or decreased. The general tendency is positive; the fault coverage after compaction on average is higher. That highlights the value of the MIT test. The decrease of the fault coverage of the MIT test can be explained by the fact that the logic hazards were not taken into account during the construction of the MIT test. However, the MIT test sensitizes additional branches in the circuit and thereby detects additional transition faults. This helps to increase the fault coverage of the MIT test. The functional delay test can be constructed not only from PP test, but it can be generated on its own. The main problem is the quality assessment of the functional delay test because the implementation of the circuit is not available yet. The criteria of the quality assessment of the functional test do not suit quite well for such a purpose, because the detection of the delay faults requires a pair of test patterns. The problem of the functional delay test quality assessment is addressed in the next section. 5. Function-robust and function-non-robust propagation of the delay faults Our experiences in functional delay fault testing revealed that typically not all the delay faults of the circuits can be detected by
SIT tests. For detecting of some delay faults, MIT tests are required. The MIT test launches several signal transitions on the inputs of the circuit simultaneously. Some of these signal transitions can overlap or partly block each other. Therefore, some delay fault effects can be propagated as signal glitches, which can be observed and measured by test equipment. Such a propagation of the fault effect is called a weak non-robust propagation [21]. A conventional transition fault test uses the weak non-robust propagation [21]. The weak non-robust propagation at the gate-level is equivalent to the function-non-robust propagation at the functional level. Therefore, it is meaningful to think of the rules that allow generating the functional delay test, which enables the function-non-robust propagation. When the fault effect propagates as the signal glitch, there is no signal transition on the output, if we observe it in the static mode. The value transitions from the inputs are propagated to the outputs along the paths of the circuit. In order to generate a functional test it is necessary to determine which input signal transition influences a particular output signal transition. Therefore, it would be rational to examine the influence of the blocking of separate input signal transition on the output signal transition. Signal transitions on the inputs have to be blocked one by one keeping the value in the second pattern the same as the value in the first one. Let us use an example to explain in detail the concept of the blocking of the input signal transition. Suppose that there exists a pair of input patterns h1 0 1 0, 0 1 1 1i, where signal transitions are observed on the first, the second, and the fourth inputs. When the transition is blocked on the first input, the pair of patterns becomes the following: h1 0 1 0, 1 1 1 1i. When the transition is blocked on the second input, the pair of patterns becomes the following: h1 0 1 0, 0 0 1 1i. When the transition is blocked on the fourth input, the pair of patterns becomes the following: h1 0 1 0, 0 1 1 0i. The transition blocking on the input may disable transitions on some outputs. Such behavior means that the blocked transition on the input directly influences the transition on the output where the transition was disabled. Therefore, such a pair of patterns allows the function-robust propagation of the delay faults. The other possible case is when the delay faults are detected in the function-non-robust manner. Such a situation arises when the blocked transition on the input invokes the transition on the output that had no transition before. The considered transition on the input blocked the influence of the transition on some other input, and, when this transition was disabled, the additional transition appeared on the output, on which it was not observed before. Let us consider a small example. Suppose that two opposite transitions 0 ? 1 and 1 ? 0 appear on the 2-inputs AND gate. There is no transition on the output of this gate. But, if one input delays, the glitch will be observed on the output. This glitch can be measured by test equipment and the delay will be detected. The detection of the functional delay faults can be represented by the detection matrix kXk2n4m, where n – number of primary inputs, and m – number of primary outputs. The primary input i is represented by two rows: namely 2i 1 and 2i, in the matrix. The row 2i 1 describes the effect of the signal transition 0 ? 1 on the primary input, and the row 2i describes the effect of the signal transition 1 ? 0 on the primary input. The primary output j is represented by four columns. The column 4j 3 stands for the function-robust detection of the delay faults when the signal transition 0 ? 1 appears on the primary output. The column 4j 2 stands for the function-robust detection of the delay faults when the signal transition 1 ? 0 appears on the primary output. The column 4j 1 stands for the function-non-robust detection of the delay faults when the signal transition 0 ? 1 appears on the primary output. The column 4j stands for the function-non-robust detection of the delay faults when the signal transition 1 ? 0 appears on the primary output. The corresponding entry of the matrix X
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is set to 1 if the disabled signal transition on the primary input invokes or disables the signal transition on the primary output. The functional delay test generation can be carried out according to the ideas presented in this section. The generation is based on the random search method. A pair of test patterns is generated randomly. Signal transitions are blocked one by one keeping the same value in the second pattern of the pair as in the first one. The responses are measured at the primary outputs of the circuit. If the blocking of the value on the primary input has some influence on the primary output response as explained before the corresponding entry of the detection matrix is set to 1, which means that the corresponding functional delay fault is detected, and the randomly generated pair of test patterns is included into the test set. The generation procedure is allowed to run until all the functional delay faults are detected both function-robustly and function-non-robustly. The number of the functional delay faults is less than or equal to 4 n m. Usually, some of these faults are untestable, because the logic paths do not exist between some primary inputs and some primary outputs. In general case, this number is unknown a priori. The solution to the problem of stopping the functional delay test generation using the detection matrix is presented in [25]. Let us consider an example of the 3-input function z = ac0 + a0 c + bc (Fig. 2) [6]. The coupling delay test set is presented in Table 3 [6]. This is an ideal test set, because it covers all the paths in the circuit realization only once. The problems of the coupling delay test generation were enumerated in Introduction. Suppose that only a single transition is allowed on the inputs of the circuit. It is worth to pay attention to the fact that in the case of a single transition the function-non-robust detection is not possible. The functional delay pattern pairs are presented in Table 4. The corresponding detection matrix X is given in Table 5. In order to understand the filling up of the detection matrix easier, Table 6 shows the test pattern pairs that detect the corresponding functional delay faults in the function-robust manner. The detection matrix X, which is shaded in Table 5 and Table 6, has 6 rows and 4 columns that obey the formula 2n 4m. Two rows are reserved for every input, and four columns are reserved for every output. The first row that is reserved for the input a corresponds to the formula 2i 1, when i is 1 and it is filled up for the signal transition 0 ? 1 on this input. The second row that is reserved for the input a corresponds to the formula 2i when i is 1 and it is filled up for the signal transition 1 ? 0 on this input. The single primary output is represented by four columns. The first
a
1
c
&
1
&
1
z
&
b
Fig. 2. A realization of the function z = ac0 + a0 c + bc.
Table 3 Coupling delay test set. t1 t3 t5 t7 t9 t11
h0 1 0, h1 0 1, h1 0 1, h0 0 0, h0 1 0, h1 0 1,
1 1 0i 0 0 1i 1 1 1i 0 0 1i 0 1 1i 1 0 0i
t2 t4 t6 t8 t10 t12
h1 1 0, h0 0 1, h1 1 1, h0 0 1, h0 1 1, h1 0 0,
0 1 0i 1 0 1i 1 0 1i 0 0 0i 0 1 0i 1 0 1i
Table 4 Functional delay test with single transition. Input
Output
t1 t3 t5 t7
h0 1 0, h1 0 1, h1 0 1, h0 0 0,
1 1 0i 0 0 1i 1 1 1i 0 0 1i
t11
h1 0 1, 1 0 0i
t2 t4 t6
h1 1 0, 0 1 0i h0 0 1, 1 0 1i h1 1 1, 1 0 1i
t10 t12
h0 1 1, 0 1 0i h1 0 0, 1 0 1i
t1 t3 t5 t7
h0, h0, h0, h0,
1i 1i 1i 1i
t11
h0, 1i
t2 t4 t6
h1, 0i h1, 0i h1, 0i
t10 t12
h1, 0i h1, 0i
Table 5 Detection matrix X for single transition. Input
Output Function-robust detection
Function-non-robust detection
a
1 1
1 1
0 0
0 0
b
1 0
0 1
0 0
0 0
c
1 1
1 1
0 0
0 0
Table 6 Test pattern pairs used to construct X. Input
Output Function-robust detection
Function-non-robust detection
a
t1 t3
t4 t2
0 0
0 0
b
t5 0
0 t6
0 0
0 0
c
t7 t11
t12 t10
0 0
0 0
column corresponds to the formula 4j 3, when j is 1. It stands for the function-robust detection when the signal transition 0 ? 1 appears on the primary output. The second column corresponds to the formula 4j 2, when j is 1. It stands for the function-robust detection when the signal transition 1 ? 0 appears on the primary output. The same rule applies to the other two columns that stand for the function-non-robust detection. Comparing the functional delay test set (Table 6) with ideal test set (Table 3), we see that former set does not include two test pattern pairs, namely t8 and t9. The answer to this problem lies in the detection matrix X. The input c is included into 3 minterms which means that six test pattern pairs are needed in order to propagate the transition from this input to the output by all the possible different paths in the circuit, but the matrix X for the relationship between input c and output has only 4 entries that are allocated for identifying the function-robust fault detection. So, at most four test pattern pairs for input c can be produced when generation is based on the matrix X and single transition. Certainly, the lack of two test pattern pairs means that some delay faults will be uncovered. Suppose that the generation of functional delay test including MIT in test pattern pairs is allowed. The corresponding functional delay test patterns are listed in Table 7, and the detection matrix X is presented in Table 8. As we can see, the function-robust detection includes nine test pattern pairs, while the function-non-robust detection includes six test pattern pairs. Indexing of test pattern pairs is different from those in Table 3 or Table 4. The function-robust detection was divided into two parts: a single input transition pairs of test patterns and multi-input transitions pairs of test patterns. Note that the test pattern pairs, which hold the property of
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Table 7 Functional delay test with multiple transitions. SIT
Output
Function-robust detection h0 0 0, 0 0 1i t1 h1 0 0, 0 0 0i t3 h1 0 1, 1 0 0i t5 MIT h0 0 0, 1 1 1i t7 h0 1 1, 1 0 1i t9
t2 t4 t6
h0 1 1, 0 1 0i h0 1 0, 1 1 0i h1 0 1, 0 0 1i
t1 t3 t5
h0, 1i h1, 0i h0, 1i
t2 t4 t6
h1, 0i h0, 1i h0, 1i
t8
h1 1 0, 1 0 1i
t7 t9
h0, 1i h1, 0i
t8
h1, 0i
h1 1 0, 0 1 1i h0 1 0, 1 0 1i h1 0 1, 0 0 0i
t10 t12 t14
h1, 1i h1, 1i h1, 1i
t11 t13 t15
h1, 1i h0, 0i h0, 0i
Function-non-robust detection h0 0 1, 1 0 0i t11 t10 h1 1 1, 0 0 1i t13 t12 h0 0 1, 1 1 1i t15 t14
Table 8 Detection matrix X for multiple transitions. Input
Output Robust detection
Non-robust detection
a
1 1
1 1
1 1
1 1
b
1 0
0 1
0 1
1 0
c
1 1
1 1
1 1
1 1
the function-non-robust detection, have no transition on the output. This simple example shows that the MITs do not exclude entirely the SITs. In general, the number of test pattern pairs is increased. These test pattern pairs cover all the paths of the circuit realization already. That shows that the generation based on the detection matrix X and MIT is preferable than the generation based on the detection matrix X and SIT only. Not all the paths are covered function-robustly but nevertheless all the paths are covered. That has another advantage. The non-robust delay test is effective in reducing the test size [8]. The new functional delay test generation algorithm was implemented, and the experiments were carried out. In the first experiment, we took for the investigation the transition fault test that was generated automatically at the gate-level by TetraMAX and that has complete transition fault coverage. The results are summarized in Table 9. It should be noticed that some benchmark circuits have untestable transition faults. Such faults were excluded from the calculation of the transition fault coverage. It is worth to pay attention to the column under name ‘‘Kmax”. This column shows the maximum number of non-zero entries of
Table 9 Function-robust and function-non-robust detection. Circuit
C432 C499 C880 C1355 C1908 C2670 C3540 C5315 C6288 C7552
Kmax
540 5184 1326 5184 3004 3320 2588 10,540 3068 12,188
Test size
142 223 137 306 316 259 403 301 122 461
Number of non-zero entries
Coverage (%)
Functionrobust detection
Function-nonrobust detection
Functionrobust
Total
345 907 606 1518 1001 1758 1672 4992 2346 5236
345 1258 599 1313 1027 1512 1664 4772 2354 5087
64 18 46 29 34 53 65 47 77 43
87 36 62 48 43 66 77 60 82 53
the matrix X for function-robust detection. In other words, Kmax is the number of the detectable functional delay faults. These values were taken from [20]. To obtain the number of detectable functional delay faults according to the software prototype is quite a complex task, because not all the inputs have influence on the outputs, and the transition may propagate through the even and/or odd number of the inversions. The number of non-zero entries of the detection matrix X was calculated for function-robust and function-non-robust detection separately (the fourth and fifth columns of Table 9). The results show that the obtained values are comparable. The last two columns present the coverage of the functional delay faults by the transition fault test. The values in the penultimate column indicate how many functional delay faults were covered in the function-robust mode. The values in the last column show the total coverage of functional delay faults when functional faults were covered in the function-robust or in the function-non-robust mode. As we can see, the obtained values are very far from 100%. The results in the last two columns allow evaluating the usefulness of the test pattern pairs, selected on the base of the function-non-robust property. We see, that these test pattern pairs always added their value to the total coverage of functional delay faults. It means that some functional delay faults are covered function-non-robustly by the given complete transition fault test only. As a conclusion to the experiment, we can state that the test, which is generated at the gate-level and detects all the transition faults, does not cover the functional faults completely at the functional level. Such an outcome can be explained by the differences between the functional level and the structural level of the circuit. At the functional level, the structural implementation of the circuit is unknown. The circuit can be implemented in many different ways. Therefore, the functional faults target to cover all the possible implementations. Consequently, the test patterns constructed for a particular implementation can not cover all the functional faults. In order to determine the influence of the function-robust and function-non-robust detection on the selection of test pattern pairs the second experiment was carried out (Table 10). We took for the investigation the transition fault test (Table 9) that has complete transition fault coverage at the gate-level. During the experiment, the number of not selected test patterns from the initial complete transition fault test was determined. The selection was based on both properties separately as well as on both properties together. The columns of Table 10 next to the first column are grouped in pairs and the headings were allocated for the pairs of the columns. The heading of the pair indicates the property of test pattern pairs, according to which they were selected. The first column of a pair shows the number of test pattern pairs that were not selected according to the named property, whereas the second column of
Table 10 Not selected test patterns. Circuit
C432 C499 C880 C1355 C1908 C2670 C3540 C5315 C6288 C7552
Function-robust
Function-non-robust
Total
Number
Percentage (%)
Number
Percentage (%)
Number
Percentage (%)
37 110 28 151 145 60 96 18 2 74
26 49 20 49 45 23 23 5 1 16
40 86 21 133 138 64 88 10 4 67
28 38 15 43 43 24 21 3 3 14
13 15 5 46 95 22 33 3 1 25
9 6 2 15 30 8 8 1 1 5
E. Bareisa et al. / Microelectronics Reliability 49 (2009) 1578–1585
The proposed methods are applicable for the combinational circuits or the sequential ones, which can be tested using the enhanced scan methodology.
Table 11 Transition fault coverage of MIT test. Circuit
1585
Multiple transition
Compacted
Test size
Transition fault coverage (%)
Test size
Transition fault coverage (%)
C432 C499 C880 C1355 C1908 C2670 C3540 C5315 C6288 C7552
257 1944 621 1869 1094 769 854 1948 481 3960
96.08 99.88 98.46 98.51 94.41 99.17 96.90 100 100 99.13
244 1159 743 1068 1814 1153 1166 3382 903 4331
94.69 93.00 100.00 95.01 94.58 98.12 94.21 99.91 99.89 98.03
Average
1380
98.85
1596
96.74
the pair expresses this value in percent. As we can see, the percent of the lost valuable test pattern pairs is quite high when both properties were considered separately. The results are much better when the selection is based on both properties together. The latter outcome indicates the value of the function-non-robust detection. During the third experiment, the functional test was generated according to the detection matrix X, when the algorithm selected the test pattern pairs that possess the function-robust and/or function-non-robust property. The obtained test was evaluated at the gate-level for the transition fault coverage (Table 11). The functional test detects all the testable functional delay faults at the functional level. The full coverage of transition faults was obtained for the circuits C5315 and C6288. It is an excellent result. This outcome justifies the hope that the test for the transition faults can be generated at the functional level according to the software prototype. The results in the columns under name ‘‘Compacted” are taken from Table 2 and included for the comparison purposes. The higher fault coverages are shown in bold. We remind that the compacted test was constructed from the SIT test and it became the MIT test. We see that the generated test is better than the compacted test with respect to both criteria: (1) the test size on average is smaller; (2) the fault coverage on average is higher. 6. Conclusions In the paper, we have presented the methods of functional delay test development based on the software prototype. Some methods are designed to generate SIT tests, other methods – MIT tests. The quality of the functional delay test is evaluated at the functional level and then the transition fault coverage is determined at the gate-level. Our experimental results show that the test sets, which are generated according to the functional delay fault model, achieve high fault coverage of transition faults. SIT tests cover up to 95.82% of transition faults. MIT tests, which consider the function-robust and function-non-robust propagation of the delay faults, allow obtaining even higher transition fault coverage (98.85%). The test size of a MIT test is almost two times lesser than that of a SIT test. But the SIT test can be compacted according to the presented Lemma and its Corollaries. The compacted test becomes the MIT test. Nevertheless, it still retains the functional robust propagation property.
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