- Email: [email protected]
GaAs field effect transistors fabricated by imprint lithography
Microelectronic Engineering 60 (2002) 451–455 www.elsevier.com / locate / mee
GaAs field effect transistors fabricated by imprint lithography a, a a a b I. Martini *, J. Dechow , M. Kamp , A. Forchel , J. Koeth a
b
¨ Wurzburg ¨ ¨ , Am Hubland, D-97074 Wurzburg , Germany Technische Physik, Universitat Nanoplus Nanosystems and Technologies GmbH, Oberer Kirschberg 4, D-97218 Gerbrunn, Germany Received 28 February 2001
Abstract A GaAs metal–semiconductor field-effect transistor (MESFET) has been realized based on mix-and-match fabrication using optical lithography for the ohmic contacts and imprint lithography for the gate. The gate length and width are 1.2 and 80 mm, respectively, the channel length is 4 mm. For the gate definition a Si-mold is embossed into a thin polymer film located on top of an n-doped GaAs layer. The gate is fabricated by metal evaporation and lift-off. 2002 Elsevier Science B.V. All rights reserved. Keywords: Imprint lithography; Mix-and-match fabrication; Microelectronic devices; FET
1. Introduction Optical lithography, the standard patterning technology on the industrial level is fast, rather expensive, however limited to feature sizes down to 100 nm. For lithographic mask production and patterning of features down to a few nanometer by direct writing on wafers, electron beam lithography (EBL) is a well established technique. EBL is expensive and slow due to serial processing, therefore not suitable for industrial high throughput applications. Other technologies like extreme ultraviolet lithography, X-ray lithography, electron projection lithography and ion projection lithography have potentially high resolution and provide high throughput, however they are expensive. Imprint lithography provides a resolution down to 10 nm [1], is semi-fast and above all inexpensive. The method is based on embossing a mold into a thin polymer film [2]. Various groups have concentrated on basic developments of imprint techniques [3–8]. For applications in device fabrication imprint lithography has to be integrated with conventional processing. Particularly issues like precise alignment and imprint on a prepatterned surface with significant height variations have to be addressed. * Corresponding author. Tel.: 1 49-931-888-5119; fax: 1 49-931-888-5143. E-mail address: [email protected] (I. Martini). 0167-9317 / 02 / $ – see front matter PII: S0167-9317( 01 )00705-5
2002 Elsevier Science B.V. All rights reserved.
452
I. Martini et al. / Microelectronic Engineering 60 (2002) 451 – 455
Quantum device fabrication using nanoimprint lithography has been demonstrated in terms of a quantum point contact [9]. Especially pattern transfer for devices operating at room temperature is of great interest for the semiconductor industry. A distributed feedback laser with gratings fabricated by imprint has been reported by Rogers et al. [10]. J. Hu et al. demonstrated the fabrication of an FET with gate lengths ranging from 20 to 50 mm using polymer injection as pattern transfer technique [11]. In this paper we show that alignment accuracy down to 1 mm is feasible and demonstrate this by mix-and-match fabrication of a MESFET.
2. Substrate structure The schematic of the MESFET is shown in Fig. 1. The device is based on a 100 nm Si-doped GaAs layer (n Si 5 1.5 3 10 17 cm 23 ) grown on top of a GaAs buffer by molecular beam epitaxy (MBE). In order to reduce the number of fabrication steps, no further highly doped cap-layer for lower contact resistances was applied. The mesa is defined by wet etching using photoresist patterned by optical lithography as etching mask. Prior to the AuGe / Ni /Au evaporation for ohmic contacts, the sample is dipped into diluted NH 3 . After lift-off procedure, the contacts are annealed at 480 8C for 30 s. The distance between the source and the drain contact is 4 mm. The metal of the ohmic contact layer is also used to form alignment marks. For the subsequent imprint process, the structure is spin-coated with PMMA 50 K (200 nm thickness).
3. Mold fabrication Prior to this work, reference transistors were fabricated using optical contact lithography (resolution 1 mm). The dimensions of the imprinted devices presented here were chosen to be comparable to the devices fabricated by optical lithography. The mold is fabricated from double side polished Si pk100l with a size of 7 3 7 mm. The gate pattern (gate length 1.2 mm, gate width 80 mm) is exposed by high resolution electron beam lithography (100 kV) in PMMA. A chromium layer serves as etching mask
Fig. 1. Schematic of the MESFET. The overall size is 30 3 100 mm.
I. Martini et al. / Microelectronic Engineering 60 (2002) 451 – 455
453
for the ECR-RIE etching with CHF 3 /Ar gas. The height of the gate pattern corresponds to the thickness of the ohmic contacts, i.e. 400 nm. To prevent adhesion of PMMA to the Si during imprint process, the mold is treated with octadecyltrichlorosilane (OTS) CH 3 (CH 2 ) 17 SiCl 3 . 4. Alignment and imprint lithography The most critical step is the alignment of substrate and mold. The difficulty is to place the gate stamp between the ohmic contacts. Touching the ohmic contacts with the gate mold would result in loss of the anti-adhesion film or even the damaging of the gate mold. The metal marks (4 mm wide crosses) of the contact level on the sample and the Cr marks on the mold are aligned under backside IR-illumination in an optical mask aligner (Suss, MJB3), as illustrated in Fig. 2. The Si mold is fixed by vacuum to the upper stationary stage. The substrate is vacuum fixed to the moving stage equipped with manual drives. The alignment gap is about 10 mm. The IR image is displayed 400 3 magnified on a monitor. When the alignment crosses are overlapping, the substrate is brought into soft contact with the mold. The alignment accuracy is about 62 mm. Then, both sample and mold are transferred into a press where the actual imprint is performed. The press is a commercially available tool (Weber, Germany) with a maximum force of 130 kN and capable for imprint up to 40 wafer. First, the pressure is build up (force 0.9 kN). Eighteen gates were embossed in parallel. The corresponding pressure would be 5 3 10 6 bar, assuming that the mold touches the substrate only on the gate structures. However, this is unlikely due to mold bending and polymer bulging resulting from spin-coating. Therefore, it is difficult to determine the actual pressure on the gate patterns. Subsequently, the temperature of the heating plates is increased to 115 8C. The gate pattern is embossed into the PMMA 50 K (105 8C glass transition temperature). The lower molecular weight PMMA is chosen for its lower viscosity. About 8 min later the heating plates are cooled down to room temperature and the pressure is released. During the imprint process, the mold should not touch the GaAs surface to avoid mechanical damages of mold and substrate. The thin residual PMMA film is removed in a O 2 /Ar plasma. The gate is fabricated by metal evaporation of Cr /Au and lift-off. The last fabrication step consists of contacting the gate and the ohmic contacts with Au stripes to allow measurements. Fig. 3 shows an optical micrograph of the finished MESFET device. The device with 4 mm channel length was the smallest functional device that could be obtained.
Fig. 2. Schematic to illustrate the IR backside alignment of substrate and gate mold.
454
I. Martini et al. / Microelectronic Engineering 60 (2002) 451 – 455
Fig. 3. Optical micrograph of the complete MESFET. The gate length is 1.2 mm, the channel length is 4 mm and gate width 80 mm.
5. Device characteristics The DC-characteristics at room temperature of a representative MESFET are shown in Fig. 4. Fig. 4 (a) shows the drain-source current IDS versus drain-source voltage VDS for a series of gate voltages. The transfer characteristics were measured at VDS 5 2 V and are shown in Fig. 4(b). The extrinsic transconductance of about 40 mS / mm is reduced by contact resistances in the order of a few Vmm. The performance of the device is comparable to those with gates patterned by optical lithography.
6. Conclusion In conclusion, we have shown the fabrication of a functional MESFET using imprint lithography to pattern the transistor gate. The MESFET dimensions were chosen with respect to already existent optical masks and do not represent the limits of the imprint method itself. The performance of the device based on doped GaAs layer cannot compete with devices fabricated on HEMT structures. Nevertheless, imprint lithography in combination with moderate alignment has proven its applicability in electronic device fabrication. Especially for niche applications, where standard lithography techniques have particular problems or are too expensive, one can think about imprint lithography as the adequate patterning technique.
Acknowledgements The authors would like to thank M. Fischer, C. Kilian, and S. Kuhn for technical assistance during device processing. This work is financially supported by the EU ESPRIT-LTR Project SPINUP and the State of Bavaria.
I. Martini et al. / Microelectronic Engineering 60 (2002) 451 – 455
455
Fig. 4. Characteristics of the MESFET fabricated by imprint lithography. (a) Drain-source characteristics and (b) transfer characteristics measured at VDS 5 2 V. The threshold voltage is VT 5 2 0.36 V.
References [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
S.Y. Chou, P.R. Krauss, W. Zhang, L. Guo, L. Zhuang, J. Vac. Sci. Technol. B 15 (6) (1997) 2897. S.Y. Chou, P.R. Krauss, P.J. Renstrom, Appl. Phys. Lett. 67 (21) (1995) 3114. J. Haisma, M. Verheijen, K. van den Heuvel, J. Vac. Sci. Technol. B 14 (6) (1996) 4124. H.-C. Scheer, H. Schulz, T. Hoffmann, C.M. Sotomayor Torres, J. Vac. Sci. Technol. B 16 (6) (1998) 3917. R.W. Jaszewski, H. Schift, J. Gobrecht, P. Smith, Microelectron. Eng. 41\42 (1998) 575. M. Tormen, T. Borzenko, G. Schmidt, J. Liu, L.W. Molenkamp, Electron. Lett. 36 (11) (2000) 983. D. Eisert, W. Braun, S. Kuhn, J. Koeth, A. Forchel, Microelectron. Eng. 46 (1999) 179. A. Lebib, Y. Chen, J. Bourneix, F. Carcenac, E. Cambril, L. Couraud, H. Launois, Microelectron. Eng. 46 (1999) 319. I. Martini, D. Eisert, M. Kamp, J. Koeth, L. Worschech, A. Forchel, Appl. Phys. Lett. 77 (14) (2000) 2237. J.A. Rogers, M. Meier, A. Dodabalapur, E.J. Laskowski, M.A. Cappuzzo, Appl. Phys. Lett. 74 (22) (1999) 3257. J. Hu, R.G. Beck, T. Deng, R.M. Westervelt, K.D. Maranowski, A.C. Gossard, G.M. Whitesides, Appl. Phys. Lett. 71 (14) (1997) 2020.
GaAs field effect transistors fabricated by imprint lithography a, a a a b I. Martini *, J. Dechow , M. Kamp , A. Forchel , J. Koeth a
b
¨ Wurzburg ¨ ¨ , Am Hubland, D-97074 Wurzburg , Germany Technische Physik, Universitat Nanoplus Nanosystems and Technologies GmbH, Oberer Kirschberg 4, D-97218 Gerbrunn, Germany Received 28 February 2001
Abstract A GaAs metal–semiconductor field-effect transistor (MESFET) has been realized based on mix-and-match fabrication using optical lithography for the ohmic contacts and imprint lithography for the gate. The gate length and width are 1.2 and 80 mm, respectively, the channel length is 4 mm. For the gate definition a Si-mold is embossed into a thin polymer film located on top of an n-doped GaAs layer. The gate is fabricated by metal evaporation and lift-off. 2002 Elsevier Science B.V. All rights reserved. Keywords: Imprint lithography; Mix-and-match fabrication; Microelectronic devices; FET
1. Introduction Optical lithography, the standard patterning technology on the industrial level is fast, rather expensive, however limited to feature sizes down to 100 nm. For lithographic mask production and patterning of features down to a few nanometer by direct writing on wafers, electron beam lithography (EBL) is a well established technique. EBL is expensive and slow due to serial processing, therefore not suitable for industrial high throughput applications. Other technologies like extreme ultraviolet lithography, X-ray lithography, electron projection lithography and ion projection lithography have potentially high resolution and provide high throughput, however they are expensive. Imprint lithography provides a resolution down to 10 nm [1], is semi-fast and above all inexpensive. The method is based on embossing a mold into a thin polymer film [2]. Various groups have concentrated on basic developments of imprint techniques [3–8]. For applications in device fabrication imprint lithography has to be integrated with conventional processing. Particularly issues like precise alignment and imprint on a prepatterned surface with significant height variations have to be addressed. * Corresponding author. Tel.: 1 49-931-888-5119; fax: 1 49-931-888-5143. E-mail address: [email protected] (I. Martini). 0167-9317 / 02 / $ – see front matter PII: S0167-9317( 01 )00705-5
2002 Elsevier Science B.V. All rights reserved.
452
I. Martini et al. / Microelectronic Engineering 60 (2002) 451 – 455
Quantum device fabrication using nanoimprint lithography has been demonstrated in terms of a quantum point contact [9]. Especially pattern transfer for devices operating at room temperature is of great interest for the semiconductor industry. A distributed feedback laser with gratings fabricated by imprint has been reported by Rogers et al. [10]. J. Hu et al. demonstrated the fabrication of an FET with gate lengths ranging from 20 to 50 mm using polymer injection as pattern transfer technique [11]. In this paper we show that alignment accuracy down to 1 mm is feasible and demonstrate this by mix-and-match fabrication of a MESFET.
2. Substrate structure The schematic of the MESFET is shown in Fig. 1. The device is based on a 100 nm Si-doped GaAs layer (n Si 5 1.5 3 10 17 cm 23 ) grown on top of a GaAs buffer by molecular beam epitaxy (MBE). In order to reduce the number of fabrication steps, no further highly doped cap-layer for lower contact resistances was applied. The mesa is defined by wet etching using photoresist patterned by optical lithography as etching mask. Prior to the AuGe / Ni /Au evaporation for ohmic contacts, the sample is dipped into diluted NH 3 . After lift-off procedure, the contacts are annealed at 480 8C for 30 s. The distance between the source and the drain contact is 4 mm. The metal of the ohmic contact layer is also used to form alignment marks. For the subsequent imprint process, the structure is spin-coated with PMMA 50 K (200 nm thickness).
3. Mold fabrication Prior to this work, reference transistors were fabricated using optical contact lithography (resolution 1 mm). The dimensions of the imprinted devices presented here were chosen to be comparable to the devices fabricated by optical lithography. The mold is fabricated from double side polished Si pk100l with a size of 7 3 7 mm. The gate pattern (gate length 1.2 mm, gate width 80 mm) is exposed by high resolution electron beam lithography (100 kV) in PMMA. A chromium layer serves as etching mask
Fig. 1. Schematic of the MESFET. The overall size is 30 3 100 mm.
I. Martini et al. / Microelectronic Engineering 60 (2002) 451 – 455
453
for the ECR-RIE etching with CHF 3 /Ar gas. The height of the gate pattern corresponds to the thickness of the ohmic contacts, i.e. 400 nm. To prevent adhesion of PMMA to the Si during imprint process, the mold is treated with octadecyltrichlorosilane (OTS) CH 3 (CH 2 ) 17 SiCl 3 . 4. Alignment and imprint lithography The most critical step is the alignment of substrate and mold. The difficulty is to place the gate stamp between the ohmic contacts. Touching the ohmic contacts with the gate mold would result in loss of the anti-adhesion film or even the damaging of the gate mold. The metal marks (4 mm wide crosses) of the contact level on the sample and the Cr marks on the mold are aligned under backside IR-illumination in an optical mask aligner (Suss, MJB3), as illustrated in Fig. 2. The Si mold is fixed by vacuum to the upper stationary stage. The substrate is vacuum fixed to the moving stage equipped with manual drives. The alignment gap is about 10 mm. The IR image is displayed 400 3 magnified on a monitor. When the alignment crosses are overlapping, the substrate is brought into soft contact with the mold. The alignment accuracy is about 62 mm. Then, both sample and mold are transferred into a press where the actual imprint is performed. The press is a commercially available tool (Weber, Germany) with a maximum force of 130 kN and capable for imprint up to 40 wafer. First, the pressure is build up (force 0.9 kN). Eighteen gates were embossed in parallel. The corresponding pressure would be 5 3 10 6 bar, assuming that the mold touches the substrate only on the gate structures. However, this is unlikely due to mold bending and polymer bulging resulting from spin-coating. Therefore, it is difficult to determine the actual pressure on the gate patterns. Subsequently, the temperature of the heating plates is increased to 115 8C. The gate pattern is embossed into the PMMA 50 K (105 8C glass transition temperature). The lower molecular weight PMMA is chosen for its lower viscosity. About 8 min later the heating plates are cooled down to room temperature and the pressure is released. During the imprint process, the mold should not touch the GaAs surface to avoid mechanical damages of mold and substrate. The thin residual PMMA film is removed in a O 2 /Ar plasma. The gate is fabricated by metal evaporation of Cr /Au and lift-off. The last fabrication step consists of contacting the gate and the ohmic contacts with Au stripes to allow measurements. Fig. 3 shows an optical micrograph of the finished MESFET device. The device with 4 mm channel length was the smallest functional device that could be obtained.
Fig. 2. Schematic to illustrate the IR backside alignment of substrate and gate mold.
454
I. Martini et al. / Microelectronic Engineering 60 (2002) 451 – 455
Fig. 3. Optical micrograph of the complete MESFET. The gate length is 1.2 mm, the channel length is 4 mm and gate width 80 mm.
5. Device characteristics The DC-characteristics at room temperature of a representative MESFET are shown in Fig. 4. Fig. 4 (a) shows the drain-source current IDS versus drain-source voltage VDS for a series of gate voltages. The transfer characteristics were measured at VDS 5 2 V and are shown in Fig. 4(b). The extrinsic transconductance of about 40 mS / mm is reduced by contact resistances in the order of a few Vmm. The performance of the device is comparable to those with gates patterned by optical lithography.
6. Conclusion In conclusion, we have shown the fabrication of a functional MESFET using imprint lithography to pattern the transistor gate. The MESFET dimensions were chosen with respect to already existent optical masks and do not represent the limits of the imprint method itself. The performance of the device based on doped GaAs layer cannot compete with devices fabricated on HEMT structures. Nevertheless, imprint lithography in combination with moderate alignment has proven its applicability in electronic device fabrication. Especially for niche applications, where standard lithography techniques have particular problems or are too expensive, one can think about imprint lithography as the adequate patterning technique.
Acknowledgements The authors would like to thank M. Fischer, C. Kilian, and S. Kuhn for technical assistance during device processing. This work is financially supported by the EU ESPRIT-LTR Project SPINUP and the State of Bavaria.
I. Martini et al. / Microelectronic Engineering 60 (2002) 451 – 455
455
Fig. 4. Characteristics of the MESFET fabricated by imprint lithography. (a) Drain-source characteristics and (b) transfer characteristics measured at VDS 5 2 V. The threshold voltage is VT 5 2 0.36 V.
References [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
S.Y. Chou, P.R. Krauss, W. Zhang, L. Guo, L. Zhuang, J. Vac. Sci. Technol. B 15 (6) (1997) 2897. S.Y. Chou, P.R. Krauss, P.J. Renstrom, Appl. Phys. Lett. 67 (21) (1995) 3114. J. Haisma, M. Verheijen, K. van den Heuvel, J. Vac. Sci. Technol. B 14 (6) (1996) 4124. H.-C. Scheer, H. Schulz, T. Hoffmann, C.M. Sotomayor Torres, J. Vac. Sci. Technol. B 16 (6) (1998) 3917. R.W. Jaszewski, H. Schift, J. Gobrecht, P. Smith, Microelectron. Eng. 41\42 (1998) 575. M. Tormen, T. Borzenko, G. Schmidt, J. Liu, L.W. Molenkamp, Electron. Lett. 36 (11) (2000) 983. D. Eisert, W. Braun, S. Kuhn, J. Koeth, A. Forchel, Microelectron. Eng. 46 (1999) 179. A. Lebib, Y. Chen, J. Bourneix, F. Carcenac, E. Cambril, L. Couraud, H. Launois, Microelectron. Eng. 46 (1999) 319. I. Martini, D. Eisert, M. Kamp, J. Koeth, L. Worschech, A. Forchel, Appl. Phys. Lett. 77 (14) (2000) 2237. J.A. Rogers, M. Meier, A. Dodabalapur, E.J. Laskowski, M.A. Cappuzzo, Appl. Phys. Lett. 74 (22) (1999) 3257. J. Hu, R.G. Beck, T. Deng, R.M. Westervelt, K.D. Maranowski, A.C. Gossard, G.M. Whitesides, Appl. Phys. Lett. 71 (14) (1997) 2020.