- Email: [email protected]
Gate-array design. A hierarchical development trend
World Abstracts on Microelectronics and Reliability high technology motion control in conjunction with optimum mechanical equipment fits a wide range of automation requirements. Perhaps the most unique is the processing of semiconductor wafers. By transferring a robot mechanism over the full travel of the wafer processing line, a multitude of operations are handled. Using the full articulation of a moving robot, highly accurate positioning of the robot at each work station is achieved. Optimization of the process is implemented through a central, flexible automation controller utilizing software algorithms for all motion requirements. Class 100 environment is achieved over the work surface by laminar air flow or forced, vertical air columns.
Chemical analysis of electronic gases and volatile reagents for device processing. J. W. MITCheLL. Solid St. Technol. 131 (March 1985). The reliable trace characterization of electronic gases and volatile chemicals for device processing presents new challenges in trace analysis. Recent advances and existing frontiers in analyzing these chemicals are outlined. For the vast majority, impurity specifications are still undefined. A viable approach to determining practical specifications is provided. Reagents most widely used as carriers, transport agents, and dopants, for fabricating thin film device structures, and for atmospheric control during electronic device processing have been catalogued into six groups. Current state-of-the-art trace analysis techniques applicable to their characterization are discussed briefly, and the most critical areas for future method developments are noted.
Packaging changes make automatic testing tougher, more costly. HOWARDBIERMAN.Electronics 48 (15 July 1985). The shift to surface-mounted devices and increased sensitivity to line noise plague test engineers.
Gate-array design. A hierarchical development trend. MARK C. STANSBERRY.Electron. Power, 519 (July 1985). With the proliferation of applications for semicustom integrated circuits, the design tools available to meet ever more demanding specifications are also evolving. This article shows how the basic building blocks of semicustom design are themselves growing in complexity.
791
room design is determined by many factors, including product types, process types and production capacity.
Contamination study of plasma etching. ROGER LACHENBRUCH,TOM WICKERand JERRIS PEAVEY.Semiconductor Int. 164 (May 1985). Characterization of contaminated sources and methods of reducing particle contamination in plasma etching systems. Advances in diffusion furnace technology. PETER H. SINGER. Semiconductor Int. 276 (May 1985). Cassette-to-cassette handling, five zone heating and vertical designs are some of the recent advances in diffusion furnaces. Refractory metals silicides. DAVID R. MCCLACHLAN and JONATHAN B. AVINS.Semiconductor Int. 129 (October 1984). The increase in packing density and in complexity of VLSI devices dictates the need for improved metallurgical contacts in semiconductor devices. Testing particle generation by a wafer handling robot. BRIAN HARDEGEN and ANDREW P. LANE. Solid St. Technol. 189 (March 1985). Particles are now regarded as one of the prime contributors to yield loss in advaced IC fabrication. As a result, semiconductor manufacturers are now requiring that processing equipment be qualified with respect to particle generation. A typical particle generation evaluation of a wafer handling robot is presented. Both surface and airborne measurement techniques were employed to determine the extent of particle generation from the moving mechanisms associated with the robot. The need for a controlled environment in which to perform particle studies and the length of time to obtain meaningful data are discussed.
Design and performance of "l.25-/zm" CMOS for digital applications. EDWARD T. LEWIS. Proc. IEEE 73 (3) 419
(March 1985). This paper presents a detailed approach for the design and performance analysis of 1.25-/~m CMOS digital circuit technology based on relatively simple sets of fundamental device parametric and circuit equations. As a start, a topological and "in-depth" baseline is assumed for this 1.25-~tm CMOS technology based, in part, on a set of The CAE workstation in semicustom design. ANDREWWATTS. achievable lithographic feature sizes and alignment tolerElectron. Power 523 (July 1985). The short-turnround advanances together with a set of reasonable process geometric tage that makes the semicustom IC such an attractive propo- parameters. The process baseline is TWIN-WELL CMOS sition has been made possible in no small measure by the using n- epi on an n ÷ substrate as the host starting material. development of small powerful computer-aided-engineering Two of the key geometric parameters defined are effective workstations. This development is continuing, and new fea- channel length, L e = l#m, and gate oxide thickness, tures are still being added to aid the designer. tox = 250A. Other dimensions have been selected using quasi-scaling rules consistent with a 2). of 1.25 #m. The High performance packaging. ERNEL R. WINKLER. Semi- design process starts with the selection of the average "well" conductor Int. 350 (May 1985). Pin grid array or fine pitch doping levels from a consideration of some key shortchip carriers are used for current high performance packag- channel effects: simple charge sharing and drain-induced ing. Future packaging may require TAB technology. barrier lowering (DIBL). The selection of a suitable operating voltage, Voo is considered during this process as it effects RIE of GaAs in chlorinated plasma. A. P. WEBB. Semi- junction breakdown voltage, gate oxide fields, and more conductor Int. 154 (May 1985). Reaction mechanisms are a importantly, potential hot-electron injection. Additional prime concern because of the chemical nature of the process design analyses are presented with respect to the technique. establishment of gate threshold voltages and field inversion voltages. A simple transient analysis procedure is developed Production RIE-II. Selective aluminum alloy etching. DANIEL for a basic inverter structure which yields results close to H. G. CHOE,CHRISKNAPPand ADIRJACOB.Solid St. Technol. those obtained through more detailed SPICE simulations. A 165 (March 1985). Uniform and reproducible directional unit delay (single fan-out) analysis is performed yielding etching of aluminum alloyed with silicon and copper was delays of 214 ps for a Voo of 5 V and 270 ps for a Voo of 3.3 V. performed in a commercial automatic, load-locked, cassetteto-cassette reactive ion etcher. An automatic, sequential, An algorithm to determine wafer flatness. Ernest G. MEDER. two-stage process, utilizing a BC13 and CI 2 based multicom- Semiconductor Int. 110 (July 1985). An algorithm is provided ponent etch mixture, yielded clean anisotropic etch profiles which can be used to quickly calculate wafer flatness based with good selectivity to SiO 2 at reasonable photoresist etch on parameters which are assigned quantitative values. rates. The submicron lithography labyrinth. A. N. BROERS.Solid St. Clean rooms for VLSI fabrication. PHILIPW. MORRISONand Technol. 119 (June 1985). Optical lithography should offer RICHARDJ. YEVAK.Semiconductor Int. 208 (May 1985). Clean adequate resolution and throughput for volume production
Chemical analysis of electronic gases and volatile reagents for device processing. J. W. MITCheLL. Solid St. Technol. 131 (March 1985). The reliable trace characterization of electronic gases and volatile chemicals for device processing presents new challenges in trace analysis. Recent advances and existing frontiers in analyzing these chemicals are outlined. For the vast majority, impurity specifications are still undefined. A viable approach to determining practical specifications is provided. Reagents most widely used as carriers, transport agents, and dopants, for fabricating thin film device structures, and for atmospheric control during electronic device processing have been catalogued into six groups. Current state-of-the-art trace analysis techniques applicable to their characterization are discussed briefly, and the most critical areas for future method developments are noted.
Packaging changes make automatic testing tougher, more costly. HOWARDBIERMAN.Electronics 48 (15 July 1985). The shift to surface-mounted devices and increased sensitivity to line noise plague test engineers.
Gate-array design. A hierarchical development trend. MARK C. STANSBERRY.Electron. Power, 519 (July 1985). With the proliferation of applications for semicustom integrated circuits, the design tools available to meet ever more demanding specifications are also evolving. This article shows how the basic building blocks of semicustom design are themselves growing in complexity.
791
room design is determined by many factors, including product types, process types and production capacity.
Contamination study of plasma etching. ROGER LACHENBRUCH,TOM WICKERand JERRIS PEAVEY.Semiconductor Int. 164 (May 1985). Characterization of contaminated sources and methods of reducing particle contamination in plasma etching systems. Advances in diffusion furnace technology. PETER H. SINGER. Semiconductor Int. 276 (May 1985). Cassette-to-cassette handling, five zone heating and vertical designs are some of the recent advances in diffusion furnaces. Refractory metals silicides. DAVID R. MCCLACHLAN and JONATHAN B. AVINS.Semiconductor Int. 129 (October 1984). The increase in packing density and in complexity of VLSI devices dictates the need for improved metallurgical contacts in semiconductor devices. Testing particle generation by a wafer handling robot. BRIAN HARDEGEN and ANDREW P. LANE. Solid St. Technol. 189 (March 1985). Particles are now regarded as one of the prime contributors to yield loss in advaced IC fabrication. As a result, semiconductor manufacturers are now requiring that processing equipment be qualified with respect to particle generation. A typical particle generation evaluation of a wafer handling robot is presented. Both surface and airborne measurement techniques were employed to determine the extent of particle generation from the moving mechanisms associated with the robot. The need for a controlled environment in which to perform particle studies and the length of time to obtain meaningful data are discussed.
Design and performance of "l.25-/zm" CMOS for digital applications. EDWARD T. LEWIS. Proc. IEEE 73 (3) 419
(March 1985). This paper presents a detailed approach for the design and performance analysis of 1.25-/~m CMOS digital circuit technology based on relatively simple sets of fundamental device parametric and circuit equations. As a start, a topological and "in-depth" baseline is assumed for this 1.25-~tm CMOS technology based, in part, on a set of The CAE workstation in semicustom design. ANDREWWATTS. achievable lithographic feature sizes and alignment tolerElectron. Power 523 (July 1985). The short-turnround advanances together with a set of reasonable process geometric tage that makes the semicustom IC such an attractive propo- parameters. The process baseline is TWIN-WELL CMOS sition has been made possible in no small measure by the using n- epi on an n ÷ substrate as the host starting material. development of small powerful computer-aided-engineering Two of the key geometric parameters defined are effective workstations. This development is continuing, and new fea- channel length, L e = l#m, and gate oxide thickness, tures are still being added to aid the designer. tox = 250A. Other dimensions have been selected using quasi-scaling rules consistent with a 2). of 1.25 #m. The High performance packaging. ERNEL R. WINKLER. Semi- design process starts with the selection of the average "well" conductor Int. 350 (May 1985). Pin grid array or fine pitch doping levels from a consideration of some key shortchip carriers are used for current high performance packag- channel effects: simple charge sharing and drain-induced ing. Future packaging may require TAB technology. barrier lowering (DIBL). The selection of a suitable operating voltage, Voo is considered during this process as it effects RIE of GaAs in chlorinated plasma. A. P. WEBB. Semi- junction breakdown voltage, gate oxide fields, and more conductor Int. 154 (May 1985). Reaction mechanisms are a importantly, potential hot-electron injection. Additional prime concern because of the chemical nature of the process design analyses are presented with respect to the technique. establishment of gate threshold voltages and field inversion voltages. A simple transient analysis procedure is developed Production RIE-II. Selective aluminum alloy etching. DANIEL for a basic inverter structure which yields results close to H. G. CHOE,CHRISKNAPPand ADIRJACOB.Solid St. Technol. those obtained through more detailed SPICE simulations. A 165 (March 1985). Uniform and reproducible directional unit delay (single fan-out) analysis is performed yielding etching of aluminum alloyed with silicon and copper was delays of 214 ps for a Voo of 5 V and 270 ps for a Voo of 3.3 V. performed in a commercial automatic, load-locked, cassetteto-cassette reactive ion etcher. An automatic, sequential, An algorithm to determine wafer flatness. Ernest G. MEDER. two-stage process, utilizing a BC13 and CI 2 based multicom- Semiconductor Int. 110 (July 1985). An algorithm is provided ponent etch mixture, yielded clean anisotropic etch profiles which can be used to quickly calculate wafer flatness based with good selectivity to SiO 2 at reasonable photoresist etch on parameters which are assigned quantitative values. rates. The submicron lithography labyrinth. A. N. BROERS.Solid St. Clean rooms for VLSI fabrication. PHILIPW. MORRISONand Technol. 119 (June 1985). Optical lithography should offer RICHARDJ. YEVAK.Semiconductor Int. 208 (May 1985). Clean adequate resolution and throughput for volume production