- Email: [email protected]
Getting more out of handlers
894
World Abstracts on Microelectronics and Reliability
and SPESA, and requires only a modest increase in computational effort. Comparison of simulated resist profiles with published experimental data shows that our model qualitatively explains the asymmetries in photolithographic response recently observed as a function of focus offset position in a single-layer resist process. The question of the optimum focal position within the resist layer is discussed by means of simulated focus-exposure diagrams and the concept of effective defocus. A new low temperature polysilieon CVD process. DOUGLAS MEAKIN. Semiconductor int., 74 (July 1988). A technique of depositing a fully crystalline layer, at the same temperature at which standard poly LPCVD results in amorphous silicon, has been developed. Determining shelf life of epoxy molding compounds. KARL ROSENGARTH and PRESTON HEINLE. Semiconductor int., 212 (May 1988). A linear regression model that fits spiral flow length vs storage time data can be used to determine shelf life behavior for two molding compounds. Scheduling semiconductor wafer fabrication. LAWRENCEM. WEIN. IEEE Trans. Semiconductor Mfo 1(3), 115 (1988). This paper is concerned with assessing the impact that scheduling can have on the performance of semiconductor wafer fabrication facilities. The performance measure considered here is the mean throughout time (sometimes called cycle time, turnaround time or manufacturing interval) for a lot of wafers. A variety of input control and sequencing rules are evaluated using a simulation model of a representative but fictitious semiconductor wafer fab. Certain of these scheduling rules are derived by restricting attention to the subset of stations that are heavily utilized, and using a Brownian network model, which approximates a multiclass queueing network model with dynamic control capability. Three versions of the wafer fab model are studied, which differ only by the number of servers present at particular stations. The three versions have one, two and four stations, respectively, which are heavily utilized (near 90-percent utilization). The simulation results indicate that scheduling has a significant impact on average throughout time, with larger improvements coming from discretionary input control than from lot sequencing. The effects that specific sequencing rules have are highly dependent upon both the type of input control used and the number of bottleneck stations in the fab.
parts requires handlers that provide both speed and reliability. Unfortunately, that short statement only scratches the surface of the challenges facing today's device manufacturers. Critical issues include avoiding package damage, avoiding lead damage, and coping with mechanical and operational implications of temperature variations. Dedicating handlers to particular package types, reducing handler throughput and using carriers incorporating special notches that accommodate thermal expansion provide some of the solutions. In situ tapered contact etch. SCOTT ROTH, WAYNE RAY and GLENN WISSEN. Semiconductor int., 138 (May 1988). Argon assisted in situ, tapered contact etch provides the slope and dimension control necessary to define and etch 1-2p,m contact holes or vias. Statistical control of VLSI fabrication processes: a framework. PURNENDUK. MOZUMBER,C. R. SHYAMSUNDARand ANDRZFA J. STROJWAS. IEEE Trans. Semiconductor Mfg 1(2), 62 (1988). In this paper, the first of two parts, we present a methodology for statistical process control of VLSI fabrication processes. We formally introduce a general framework for a computer-aided manufacturing system that can be used to monitor, diagnose, and control IC manufacturing. We formulate the task of process control as one of profit maximization and develop the associated objective function and the constraints for a number of manufacturing scenarios. Finally, we formalize the IC fabrication process as a stochastic system and present the necessary conditions for efficient statistical control of VLSI fabrication processes. Effects of contamination on aluminum films. Part 1: room temperature deposition. G. J. VAN DER KOLK, M. J. VERKERKand W. A. M. C. BRANKAERT.Semiconductor int., 224 (May 1988). Oxygen and water vapor were introduced during metalization to determine the effects on A1 film microstructure.
Submicron E-beam process control. M1RGHAN!WIDAT-ALLA, AL WONG, DAVID DAMERONand CHONG-CHENG Fu. Semiconductor int., 252 (May 1988). Photomask pattern quality can be significantly improved by modifying e-beam resist processing conditions.
Liquid dropping resin for IC encapsulation. SHIGENORI YAMAOKA,AKINOBUKUSUHARAand YUKIHIROOKABE.IEEE Trans. Compon. Hybrids Mfg Technol. 11, 145 (1988). The demand for ICs is increasing in line with the development of the electronics industry. Encapsulation methods are getting more diversified due to smaller IC packages and larger chips. Conventionally, the most common method of encapsulation of bare ICs with plastics is a method in which encapsulation is made using epoxy resin for transfer molding. In addition, a method to encapsulate bare ICs on an organic substrate with liquid epoxy resin also finds limited use. This paper introduces a new type of liquid epoxy resin used for the latter method. This resin had been commercially used for chip on board (COB) having applications for wrist watches, etc. More recently, with diversification of IC package forms, plasticbase pin grid array (PPGA), plastic leaded chip carrier (PLCC), IC cards, and tape automated bonding (TAB) made their debut accelerating their commercial use. Epoxy resin used for this purpose should be of high reliability, comparable to that of the monolithic ICs, which had not been realized on conventional resins used for COB. In order to meet these requirements, studies have been made by us on characteristics of resin which allow to obtain resin of high reliability, as well as on methods to improve these characteristics. Furthermore, this paper includes such effective factors which had been found, by reliability tests, to contribute to higher reliability, by conducting such tests on resin samples produced by us based on results of these studies.
Getting more out of handlers. STEPHEN F. SCHEIBER. Test Measurement Wld, 99 (May 1988). Automatically delivering complex devices to testers and receiving and sorting tested
New directions in wet chemical processing. PETERH. SINGER. Semiconductor int., 41 (July 1988). Increased sophistication in wet benches, along with new developments in HF vapor and
Analysis of package cracking during reflow soldering process. MAKOTO KITANO, ASAO NISH1MURA, SUEO KAWAI and KUNImKONISHL Proc. IEEE/IRPS, 90 (1988). Surface mount packages are heated up above solder melting temperature during reftow soldering process. If the plastic encapsulant has absorbed moisture, package cracking may occur. In this study, an evaluation method of the package cracking is developed by means of moisture diffusion analysis of plastic and deformation and stress analysis of packages. ASIC photolithography: characterization challenges. K. ANDERSON, P. SANDHOLM and A. ZANDRA. Semiconductor int., 262 (May 1988). Extensive resist and exposure system characterization is necessary for optimal contrast and latitude with minimized variability.
World Abstracts on Microelectronics and Reliability
and SPESA, and requires only a modest increase in computational effort. Comparison of simulated resist profiles with published experimental data shows that our model qualitatively explains the asymmetries in photolithographic response recently observed as a function of focus offset position in a single-layer resist process. The question of the optimum focal position within the resist layer is discussed by means of simulated focus-exposure diagrams and the concept of effective defocus. A new low temperature polysilieon CVD process. DOUGLAS MEAKIN. Semiconductor int., 74 (July 1988). A technique of depositing a fully crystalline layer, at the same temperature at which standard poly LPCVD results in amorphous silicon, has been developed. Determining shelf life of epoxy molding compounds. KARL ROSENGARTH and PRESTON HEINLE. Semiconductor int., 212 (May 1988). A linear regression model that fits spiral flow length vs storage time data can be used to determine shelf life behavior for two molding compounds. Scheduling semiconductor wafer fabrication. LAWRENCEM. WEIN. IEEE Trans. Semiconductor Mfo 1(3), 115 (1988). This paper is concerned with assessing the impact that scheduling can have on the performance of semiconductor wafer fabrication facilities. The performance measure considered here is the mean throughout time (sometimes called cycle time, turnaround time or manufacturing interval) for a lot of wafers. A variety of input control and sequencing rules are evaluated using a simulation model of a representative but fictitious semiconductor wafer fab. Certain of these scheduling rules are derived by restricting attention to the subset of stations that are heavily utilized, and using a Brownian network model, which approximates a multiclass queueing network model with dynamic control capability. Three versions of the wafer fab model are studied, which differ only by the number of servers present at particular stations. The three versions have one, two and four stations, respectively, which are heavily utilized (near 90-percent utilization). The simulation results indicate that scheduling has a significant impact on average throughout time, with larger improvements coming from discretionary input control than from lot sequencing. The effects that specific sequencing rules have are highly dependent upon both the type of input control used and the number of bottleneck stations in the fab.
parts requires handlers that provide both speed and reliability. Unfortunately, that short statement only scratches the surface of the challenges facing today's device manufacturers. Critical issues include avoiding package damage, avoiding lead damage, and coping with mechanical and operational implications of temperature variations. Dedicating handlers to particular package types, reducing handler throughput and using carriers incorporating special notches that accommodate thermal expansion provide some of the solutions. In situ tapered contact etch. SCOTT ROTH, WAYNE RAY and GLENN WISSEN. Semiconductor int., 138 (May 1988). Argon assisted in situ, tapered contact etch provides the slope and dimension control necessary to define and etch 1-2p,m contact holes or vias. Statistical control of VLSI fabrication processes: a framework. PURNENDUK. MOZUMBER,C. R. SHYAMSUNDARand ANDRZFA J. STROJWAS. IEEE Trans. Semiconductor Mfg 1(2), 62 (1988). In this paper, the first of two parts, we present a methodology for statistical process control of VLSI fabrication processes. We formally introduce a general framework for a computer-aided manufacturing system that can be used to monitor, diagnose, and control IC manufacturing. We formulate the task of process control as one of profit maximization and develop the associated objective function and the constraints for a number of manufacturing scenarios. Finally, we formalize the IC fabrication process as a stochastic system and present the necessary conditions for efficient statistical control of VLSI fabrication processes. Effects of contamination on aluminum films. Part 1: room temperature deposition. G. J. VAN DER KOLK, M. J. VERKERKand W. A. M. C. BRANKAERT.Semiconductor int., 224 (May 1988). Oxygen and water vapor were introduced during metalization to determine the effects on A1 film microstructure.
Submicron E-beam process control. M1RGHAN!WIDAT-ALLA, AL WONG, DAVID DAMERONand CHONG-CHENG Fu. Semiconductor int., 252 (May 1988). Photomask pattern quality can be significantly improved by modifying e-beam resist processing conditions.
Liquid dropping resin for IC encapsulation. SHIGENORI YAMAOKA,AKINOBUKUSUHARAand YUKIHIROOKABE.IEEE Trans. Compon. Hybrids Mfg Technol. 11, 145 (1988). The demand for ICs is increasing in line with the development of the electronics industry. Encapsulation methods are getting more diversified due to smaller IC packages and larger chips. Conventionally, the most common method of encapsulation of bare ICs with plastics is a method in which encapsulation is made using epoxy resin for transfer molding. In addition, a method to encapsulate bare ICs on an organic substrate with liquid epoxy resin also finds limited use. This paper introduces a new type of liquid epoxy resin used for the latter method. This resin had been commercially used for chip on board (COB) having applications for wrist watches, etc. More recently, with diversification of IC package forms, plasticbase pin grid array (PPGA), plastic leaded chip carrier (PLCC), IC cards, and tape automated bonding (TAB) made their debut accelerating their commercial use. Epoxy resin used for this purpose should be of high reliability, comparable to that of the monolithic ICs, which had not been realized on conventional resins used for COB. In order to meet these requirements, studies have been made by us on characteristics of resin which allow to obtain resin of high reliability, as well as on methods to improve these characteristics. Furthermore, this paper includes such effective factors which had been found, by reliability tests, to contribute to higher reliability, by conducting such tests on resin samples produced by us based on results of these studies.
Getting more out of handlers. STEPHEN F. SCHEIBER. Test Measurement Wld, 99 (May 1988). Automatically delivering complex devices to testers and receiving and sorting tested
New directions in wet chemical processing. PETERH. SINGER. Semiconductor int., 41 (July 1988). Increased sophistication in wet benches, along with new developments in HF vapor and
Analysis of package cracking during reflow soldering process. MAKOTO KITANO, ASAO NISH1MURA, SUEO KAWAI and KUNImKONISHL Proc. IEEE/IRPS, 90 (1988). Surface mount packages are heated up above solder melting temperature during reftow soldering process. If the plastic encapsulant has absorbed moisture, package cracking may occur. In this study, an evaluation method of the package cracking is developed by means of moisture diffusion analysis of plastic and deformation and stress analysis of packages. ASIC photolithography: characterization challenges. K. ANDERSON, P. SANDHOLM and A. ZANDRA. Semiconductor int., 262 (May 1988). Extensive resist and exposure system characterization is necessary for optimal contrast and latitude with minimized variability.