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gm-boosted flat gain UWB low noise amplifier with active inductor-based input matching network
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gm-boosted flat gain UWB low noise amplifier with active inductor-based input matching network A. Saberkari a,n, Sh Kazemi a, V. Shirmohammadli a, M.C.E. Yagoub b a b
Department of Electrical Engineering, University of Guilan, Rasht, Iran School of Electrical Engineering and Computer Science, University of Ottawa, Ottawa, Ontario, Canada
art ic l e i nf o
Keywords: Active inductor Flat gain gm-boosting Low noise amplifier Ultra-wideband
a b s t r a c t In this paper, an ultra-wideband (UWB) CMOS low noise amplifier (LNA) utilizing an active inductorbased input matching network is presented. The proposed 0.18 mm CMOS LNA consists of three stages; a gm-boosted common-gate input stage, a common-source gain stage, and an output buffer. Designed in the 3.1–10.6 GHz UWB frequency range, the proposed circuit exhibits a flat forward gain of 12.1 7 0.7 dB, a reverse isolation less than 56.1 dB, an input return loss less than 9.5 dB, and a noise figure of 4.56– 4.7 dB over the entire frequency band, while the total power dissipation is 13.6 mW under a 1.8 V supply. & 2015 Published by Elsevier B.V.
1. Introduction Ultra-wideband (UWB) technology provides the ability to send and receive information in a widespread frequency spectrum, divided into the lower frequency band (3–5 GHz) and the upper frequency band (6–10.6 GHz) [1–3]. One advantage of the UWB network is its capability to transmit digital signals in a high data rate with very low power consumption, low complexity, and high immunity [4]. In modern wireless communication systems, the low noise amplifier (LNA) is an essential block in the receiver chain. It should maintain low noise figure (NF) while exhibiting high and flat gain to amplify the weak input RF signal, low power consumption and chip area, high linearity and stability, and robustness against process, voltage, and temperature (PVT) variations. Furthermore, as the first gain stage after the antenna, its input impedance should match with the characteristic impedance of antenna (typically 50 Ω), which results in lower return loss. Based on noise performance and input matching network characteristics, the CMOS UWB LNA architectures can be categorized into two main groups, as shown in Fig. 1, namely, common-source (CS) and common-gate (CG) LNAs. Their input impedance, Zin(s), as well as the quality factor of their input matching network at the resonance frequency, Qmatch, are listed in Table 1, where gm and Cgs are the transconductance and the parasitic gate-source capacitance of the transistor, respectively [5,6]. The main limitation in CS LNAs is their relatively high Qmatch, while this later should be low to satisfy the UWB matching requirements in terms of bandwidth. To improve the input matching condition of CS-LNAs, different advanced design
n
Corresponding author. Tel: þ 98 13 33690274–8; fax: þ98 13 33690271. E-mail address: [email protected] (A. Saberkari).
techniques have been indeed proposed such as the resistive termination, shunt-series feedback [7], inductive source degeneration [8,9], and current-reuse approach [10,11]. However, the input termination method suffers from higher noise figure due to the noise contribution of an added resistor at the input port of the LNA. The shunt-series feedback technique needs higher power consumption and creates bigger noise figure compared with other methods with the same performance. The inductive source degeneration method is suitable for narrow band applications, and finally, the current-reuse approach occupies a large area of the chip. On the other hand, because of its parallel resonant network and knowing that Cgs is proportional to the transistor size, the Qmatch of the CG-LNA would decrease when the technology becomes scaled down, and hence, the bandwidth would show a wideband behavior. Therefore, as the CG-LNA has a constant wideband input impedance (E1/ gm) it can be considered as a good candidate for wideband impedance matching, without using additional components, while preserving area consumption and avoiding from more resistance losses of onchip inductors. Moreover, in addition to providing a simple input matching network in a wide bandwidth, the CG-LNA has more linearity and stability performance, lower power consumption, better input–output isolation, and more immunity to PVT variations [3,12]. Another point of view is that the noise figure of CS-LNA is linearly proportional to the operating frequency and thus increases when the frequency reaches the gigahertz range. On the other hand, the noise figure in the CG-LNA is approximately independent of the operating frequency. However, it depends on the device size and process parameters, and also, has an inseparable link with the input matching resistance, 1/gm. While the device transconductance has been fixed by setting 1/gm to 50 Ω, the noise performance of the CG-LNA will be limited by the input matching condition. Thus, utilizing a separation method between the input matching condition and the noise figure
http://dx.doi.org/10.1016/j.vlsi.2015.06.002 0167-9260/& 2015 Published by Elsevier B.V.
Please cite this article as: A. Saberkari, et al., gm-boosted flat gain UWB low noise amplifier with active inductor-based input matching network, INTEGRATION, the VLSI journal (2015), http://dx.doi.org/10.1016/j.vlsi.2015.06.002i
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Fig. 1. Popular topologies for LNA input transistor, (a) common-source, (b) common-gate.
Table 1 Input impedance and quality factor of common-source and common-gate LNAs. Architecture
Zin(s)
Qmatch
Common-source (CS)
g m1 LS 1 S2 þ SðLS þ Lg ÞC gs1 þ ðLS þ Lg ÞC gs1 =ðS=ðLS þ Lg ÞÞ
1 2ωC gs1 RS
S=C gs1 g S2 þ SC m1 þ L
ωC gs1 RS 2
Common-gate (CG)
gs1
1 S C gs1
characteristic such as the resistive feedthrough [13], the gm-boosting technique [4,14], or the combination of CG–CS amplifiers with single input differential output structure [15,16] can improve the performance of CG-LNA. As for the matching network itself, aforementioned LNAs mainly utilize on-chip passive spiral inductors. However, these inductors are very bulky with low and fixed inductance, low quality factor and self-resonant frequency, and then, incompatible with low cost standard CMOS processes. It is then preferable to use gyrator-based active inductors, which are more appropriate for reducing size and cost of the chips [17]. Furthermore, the tunability performance of active inductors makes them very attractive in multi-channel communications, as it can be applied in the input matching network of the LNA, creating an active input matching network with tunable resonance frequency. Recently, some CMOS LNA architectures have been proposed based on active inductor [18–20] but suffer from relatively not flat gain over the operating bandwidth, making them unsuitable for UWB applications. In this paper, a flat gain gm-boosted CG-LNA structure with an active inductor-based input matching network is presented to decrease the LNA noise characteristic and reduce the total chip area. The paper is organized as follows: Section 2 introduces the basic principle of gm-boosting mechanism. In Section 3, the active inductor is explained and its equivalent circuit parameters extracted. The design approach with final proposed circuit is discussed in Section 4. Noise analysis is performed in Section 5. Finally, circuit characterization and conclusion are in Sections 6 and 7, respectively.
2. gm-boosting mechanism in LNA To maintain the benefits of the common-gate topology and overcome its limitations, a gm-boosting technique has been applied to the CG-LNA to disconnect the strong coupling between input matching and noise figure characteristic, causing a reduction in both noise and
power losses. As mentioned before, the noise factor of CG-LNA is confined by 1/gm due to input matching condition. Fig. 2(a) shows a basic CG-LNA configuration with its noise sources. As the gate-induced noise is insignificant and usually negligible in CG-LNA, the dominant noise sources are the thermal channel noise of transistor, ind, and the noise current of source resistance, ins. Thus, the noise factor can be obtained as: 2 2 i2 nd : 1 þ 1g Rs i2 nd 1 m F ¼ 1þ ¼ 1 þ ð1Þ 2 i2 ns g m Rs i2 ns : 1 þgmgRsRs m
By substituting the equivalent relations for i2 nd and i2 ns , Eq. (1) can be rewritten as: 2 4KTγg d0 Δf 1 F ¼ 1þ 4KTGs Δf g m Rs γg γ ¼ 1 þ 2d0 ¼ 1 þ ð2Þ α g m Rs ¼ 1 g m Rs where K and T are the Boltzmann constant and absolute temperature, respectively. gd0 is the zero-bias output conductance of the transistor, γ is the thermal channel noise coefficient of the MOS transistor, and Δf is the bandwidth. The conductance Gs is equal to 1/Rs. The parameter α ¼gm/gd0 is equal to unity for long channel devices and has a lower value when the channel length scales down. Both α and γ are bias-dependent parameters. Due to the input matching condition expressed as gmRS ¼1, gm cannot be increased arbitrarily to reduce the noise factor. Nevertheless, it is still possible to improve the noise performance by decoupling input matching and noise figure. As shown in Eq. (3), this aim can be achieved by increasing the effective transconductance of the device at the source terminal, while remaining gd0 unchanged. As shown in Fig. 2(b), this can be reached by inserting at the input of the device, an inverting gain block, A, between the gate and source terminals and thus, boosting the effective transconductance by a factor of (1þ A) [21]. With this, new input matching condition, (1þA) gmRS ¼1, helps improving the noise factor as follow: 2 4KTγg d0 Δf 1 F ¼ 1þ 4KTGs Δf ð1 þ AÞg m Rs γg d0 γ ¼ 1þ ¼ 1 þ ð3Þ αð1 þ AÞð1 þ AÞgm Rs ¼ 1 ð1 þ AÞ2 g m 2 Rs From Eq. (3), it is clear that the noise factor is now reduced by a factor of (1 þ A). Additionally, a lower bias current is needed in the gm-boosted CG-LNA in comparison to the conventional one,
Please cite this article as: A. Saberkari, et al., gm-boosted flat gain UWB low noise amplifier with active inductor-based input matching network, INTEGRATION, the VLSI journal (2015), http://dx.doi.org/10.1016/j.vlsi.2015.06.002i
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Fig. 2. CG-LNA configuration, (a) conventional, (b) with gm-boosting.
Fig. 3. Gyrator-C based active inductor and its equivalent circuits.
resulting in less channel noise of the input transistor. One way to achieve the inverting gain would be using a pair of cross coupling capacitors. However, it requires a differential configuration [4,22].
Thus, although this approach has lower noise contribution due to using passive reactive components, it needs a differential structure for LNA, and hence, a differential RF input signal has to be
Please cite this article as: A. Saberkari, et al., gm-boosted flat gain UWB low noise amplifier with active inductor-based input matching network, INTEGRATION, the VLSI journal (2015), http://dx.doi.org/10.1016/j.vlsi.2015.06.002i
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generated through a balun stage which will occupy a large chip area. In this paper, as shown in Fig. 2(b), a common-source amplifier is used as inverting gain block.
3. Active inductor As pointed out, passive spiral inductors suffer from many drawbacks such as low and non-tunable self-resonant frequency, low and fixed inductance value, and large silicon area. On the other hand, gyrator-based active inductors offer a number of unique advantages such as small area, large and tunable inductance value and selfresonant frequency, and compatibility with standard CMOS technology. Fig. 3(a) shows the block diagram of an active inductor consisting of two back-to-back connected positive and negative transconductors and a capacitor at the output terminal as a gyrator-C network [23]. This network exhibits an inductive behavior at its input terminal, but due to the parasitic capacitance and the finite output impedance of the transconductors, this behavior remains inductive only within a narrow frequency range. Active inductors are available in both single-ended and differential pair. As in the proposed LNA, a single-ended inductor was needed for the input matching network as shown in Fig. 3(b) [24]. According to Fig. 3(c) and carrying out a small signal analysis, the input admittance of the active inductor is given by: Y in ¼
SC gs þ g m 1 ¼ þ SRC gs þ 1 R Sð
1 RC gs 1 g m 1=RÞ þ gm 1=R
ð4Þ
On the other hand, as shown in Fig. 3(d), the obtained input admittance can be modeled by a parallel RL circuit with the input
admittance given by: 0
Y in ¼ Gp þ
1 LS þ Rs
ð5Þ
where Gp ¼ 1/Rp and Rse are defined as parallel and series resistance with inductor L, respectively. By substituting the corresponding terms in (4) and (5), the parameters of the RL equivalent circuit can be extracted as: Rp ¼ R UL ¼
R2 C gs R U Rse ¼ Rg m 1 Rgm 1
ð6Þ
The zero and pole frequencies of the input admittance of the active inductor are at ωz ¼ 1=RC gs and ωp ¼ g m =C gs , respectively. In order to obtain an inductance effect, Rse should be positive and Rgm should be greater than unity. The latter condition also ensures that ωz o ωp while the circuit will have an inductive behavior in the frequency range of ωz o ω oωp . 4. LNA circuit topology The circuit schematic of the proposed gm-boosted LNA is shown in Fig. 4. It consists of two stages along with a buffer; the first one (M1, M2, and Mactive), the input stage, is a common-gate configuration with gm-boosting approach and active input impedance matching network. The common-gate transistor M1 with low input impedance provides a relatively frequency-independent noise factor. Also, canceling the Miller effect of its gate–drain capacitance provides better isolation against output return signal. The common-source transistor M2 with resistor RD forms the inverting gain block between the gate and source terminals of M1 to boost its transconductance with a factor
Fig. 4. Proposed gm-boosted LNA with active input impedance matching network.
Please cite this article as: A. Saberkari, et al., gm-boosted flat gain UWB low noise amplifier with active inductor-based input matching network, INTEGRATION, the VLSI journal (2015), http://dx.doi.org/10.1016/j.vlsi.2015.06.002i
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of A¼gm2RD without increasing the bias current and transistor size. Resistors RB1 and RB2 and coupling capacitors CB1 and CB2 constitute the bias network of M1 and M2. The active inductor of the input matching network has been realized by Mactive and R. For proper operation, the zero and pole frequencies (ωz, ωp) of the active inductor circuit should be equal to the lowest and highest operating frequency, respectively. According to (6), it is obvious that increasing R will increase the inductance value, and therefore, using a tunable component like a voltage-controlled resistor allows changing the resonance frequency, an attractive option for multi-channel communications. It has to be noted that the
5
matching condition is achieved by a conjugation between active inductor and CG stage; the active inductor is used to cancel the capacitive effects at the input terminal and the gm-boosted CG structure guaranties the real part matching. The second stage of the LNA, the gain stage, includes a commonsource transistor, M3, to increase the power gain and a source follower transistor, Mbuffer, to act as buffer stage. The coupling capacitors, CB3 and CB4, and bias resistors, RB3 and RB4, form the bias network of the above transistors. Due to UWB bandwidth requirements, it is very important to have a flat power gain over the entire frequency range. Therefore, resistor
Fig. 5. (a) The segmented proposed LNA with passive inductor, (b) noise sources of the first stage, (c) noise sources of the second stage.
Please cite this article as: A. Saberkari, et al., gm-boosted flat gain UWB low noise amplifier with active inductor-based input matching network, INTEGRATION, the VLSI journal (2015), http://dx.doi.org/10.1016/j.vlsi.2015.06.002i
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RL1 and inductor Lshunt have been added as shunt-peaking to enhance the bandwidth and provide a smooth gain [25]. Note that the small value of the inductor (Lshunt ¼2.9 nH) is much smaller than the inductor of the input impedance matching network, and hence, will not occupy a large chip area. Although, replacing this spiral inductor with an active one will decrease the chip area, the required voltage headroom, power losses, and noise figure will be increased, and consequently, using a spiral inductor will be more suitable.
F ¼ 1þ
γ 1 γ 1þA 1 Aþ2 2 4 þ 4g m1 RD þ g m1 RD ð Þ þ α 1þA α A Aþ1 A RL1 g m1 ð1 þAÞ ð8Þ
γ 1 γ 1þA 1 Aþ2 2 4 þ 4g m1 RD þ g m1 RD ð Þ þ F ¼ 1þ α 1þA α A Aþ1 A RL1 g m1 ð1 þAÞ |fflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl{zfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl} Stage 1
1 γ 1 1 þ4 þ α g m1 g m3 R2L1 1 þ A ðg m3 RL1 Þ2 g m1 RL2 1 þ A |fflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl{zfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl} 4
Stage 2
5. Noise analysis As shown in Fig. 5(a), the circuit has been segmented into two blocks for the purpose of noise analysis. As first analysis, the active inductor was replaced by its passive counterpart, Lopt. Fig. 5(b) shows the noise sources of the first stage namely, the thermal noise sources of RS, RD, and RL1, as well as the thermal channel noise of transistors M1 and M2. Similarly, the second stage noise sources are from transistor M3 and resistor RL2, as illustrated in Fig. 5(c). The noise of the buffer stage is not included in this analysis, as it has not any significant influence on the overall noise performance of the LNA. As mentioned above, the input impedance matching condition GmRS ¼1, with Gm ¼(1þA)gm1 and A¼gm2RD, allows obtaining the noise factor of the LNA as (7). Here, the contribution of the second stage noise is very small and can be neglected. Hence, the total noise factor can be expressed as (8). If the active inductor is considered in the noise analysis, the noise contribution of the active inductor elements should be added to the noise sources of the first stage namely, the channel noise of Mactive, the channel noise of the transistor which provides the bias current IB (with transconductance of gmB), and the thermal noise of R, while other noise sources are kept unchanged, as shown in Fig. 6. As a consequence, the total noise factor of the proposed LNA can be written as (9). As it can be seen, the noise contribution from the active inductor network is reduced by a factor of (1 þ A) and can be then neglected; same for the second stage noise, as already mentioned. γ 1 γ 1þA 1 Aþ2 2 4 F ¼ 1þ þ 4g m1 RD þ g m1 RD ð Þ þ α 1þA α A Aþ1 A RL1 g m1 ð1 þ AÞ |fflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl{zfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl} Stage1
1 γ 1 1 þ4 þ α g m1 g m3 R2L1 1 þA ðg m3 RL1 Þ2 g m1 RL2 1 þ A |fflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl{zfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl} 4
ð7Þ
þ
g2 γ g m;active þ g mB 1 1 þ R m;active α 1þA g m1 g m1 1 þA |fflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl{zfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl}
ð9Þ
Active Inductor
6. Simulation results The proposed 1.8 V common-gate LNA with active inductorbased input matching network was designed and simulated using the HSPICE-RF simulator in BSIM3V3 0.18 mm TSMC RF CMOS process. The design parameter values are listed in Table 2. The simulated forward gain (S21), noise figure (NF), input return loss (S11), and reverse isolation (S12) of the LNA are depicted in Fig. 7. As it can be seen, a smooth forward gain of 12.17 0.7 dB has been obtained over the operating frequency range of 3.1–10.6 GHz along with a noise figure in the range of 4.56–4.7 dB. Additionally, the input return loss and reverse isolation are greater than 9.5 dB and 56.1 dB, respectively. Furthermore, we investigated the two particular bands of 3– 5 GHz and 4.8–6 GHz, used for wireless personal area network (WPAN) according to IEEE 802.15.3a standard [2] and wireless local area network (WLAN) according to IEEE 802.11a standard [3], respectively. As reported in Table 3, the proposed circuit exhibits Table 2 Design parameter values. Transistor W/L [mm/mm]
Resistor [Ω]
Capacitor [F]
Inductor [H]
M1, M3 ¼ 30/0.18 M2 ¼ 100/0.18 Mactive ¼10/0.18
RB1, RB2, RB3 ¼15k RL1 ¼220, RL2 ¼ 750 RD ¼180, RS ¼ 50 R¼ 200k
C1, CB1, CB2 ¼20p CB3, Cout ¼10p
LShunt ¼ 2.9n
Stage2
Fig. 6. The added noise sources to the first stage due to the active inductor of input matching network.
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Fig. 7. Characteristics of the proposed LNA, (a) gain (S21), (b) noise figure (NF), (c) input return loss (S11), (d) reverse isolation (S12).
excellent performance used in WPAN/WLAN receivers. Also, the active inductor-based input matching network yields proper input return loss without occupying a large area. If a passive spiral inductor was used in the input matching network, it would occupy an area about 0.13 mm2 while the area needed by the active inductor is only about 234 mm2. The total chip area (including 2.9 nH spiral inductor and all other elements) is about 0.095 mm2. In order to highlight the contribution of the gm-booster stage on the total noise figure of the LNA, noise contribution of the transistor M2 and resistor RD are canceled by keeping their temperature at 0 K. Fig. 8 shows the noise figure of the LNA from this point of view in comparison with the case of considering the gm-booster noise, which reveals a difference of 0.11 dB, confirming that the gm-booster stage has a little impact on the total noise figure of the LNA. Similarly, for considering the active inductor influence on the noise performance of the LNA, noise contribution of the active inductor elements are canceled by keeping their temperature at 0 K. Accordingly, a noise simulation was performed in comparison with the case of considering the active inductor noise. The result, shown in Fig. 9, indicates a maximum difference of 0.12 dB over the entire frequency range, stabilizing the theoretical analysis. By applying two tones at 5 GHz frequency with 100 MHz spacing, 1-dB compression point (P1 dB), second-order and third-order input intercept points (IIP2 and IIP3) of the LNA are given in Fig. 10. The LNA has reached to a P1 dB of 27.2 dBm, IIP3 of 12.5 dBm, and IIP2 of þ4 dBm. Monte Carlo analysis was performed on the proposed LNA in order to consider the effect of channel length, threshold voltage, and gateoxide thickness mismatch of all transistors on parameters of NF, S21 and S11. Fig. 11 demonstrates the aforementioned parameters histogram for 75% tolerance with a uniform distribution and 100 iterations on the channel length of all transistors in three different frequencies. The horizontal axis is divided into five groups; each of
Table 3 LNA characteristics in two frequency ranges. BW (GHz)
3–5
4.8–6
NF (dB) S21 (dB) S11 (dB)
4.56–4.59 12.7 7 0.1 o 9.43
4.56–4.57 12.6 7 0.0 o 11.3
Fig. 8. Noise figure of the proposed LNA with assuming the booster stage as noiseless (ideal) and noisy (non-ideal) one.
them indicates the deviation from the ideal mode. The vertical axis indicates the number of iterations that a specific deviation happens. For the noise figure, the maximum deviation from the ideal mode due to the 75% tolerance on the channel length of all transistors is 0.08– 0.1 dB at 10.6 GHz frequency, which occurs on 2% of samples. For the
Please cite this article as: A. Saberkari, et al., gm-boosted flat gain UWB low noise amplifier with active inductor-based input matching network, INTEGRATION, the VLSI journal (2015), http://dx.doi.org/10.1016/j.vlsi.2015.06.002i
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forward gain, the maximum deviation is between 0.3 and 0.4 dB at 10.6 GHz, occurring on 6% of samples. Finally, for the input return loss, 1% of samples at 3.1 GHz frequency have the maximum deviation between 0.4–0.5 dB and 5% of samples at 5 GHz frequency have the same maximum deviation. Fig. 12 shows the circuit parameters histogram for a tolerance on the threshold voltage of all transistors based on Pelgrom's model in three different frequencies with a Gaussian distribution and 100 iterations. In this case, the horizontal axis is divided into 4 groups, indicating the deviation from the ideal mode. For the noise figure, the maximum deviation from the ideal mode due to the threshold voltage mismatch of all transistors is 0.01– 0.02 dB at 3.1, 5, and 10.6 GHz frequencies, which occurs on 1%, 5%, and 8% of samples, respectively. For the forward gain, the maximum deviation is between 0.05 and 0.1 dB at 3.1 GHz, 5 GHz and 10.6 GHz,
Fig. 9. Noise figure of the proposed LNA while the noise sources of the active inductor are enabled and disabled.
occurring on 40%, 38% and 15% of samples, respectively. Finally, for the input return loss, 9% of samples at 3.1 GHz frequency have the maximum deviation between 0.15 and 0.2 dB, 8% of samples at 5 GHz frequency, and 4% of samples at 10.6 GHz frequency have the same maximum deviation. Additionally, Monte Carlo analysis at the same three frequencies on the aforementioned parameters of the proposed LNA due to the mismatch on the gate-oxide thickness of all transistors with a Gaussian distribution and 100 iterations is shown in Fig. 13. For the noise figure, the maximum deviation from the ideal mode is 0.3– 0.4 dB at 10.6 GHz frequency, which occurs on 4% of samples. For the forward gain, the maximum deviation is between 1.2 and 1.5 dB at 3.1 GHz, occurring on 8% of samples. Finally, for the input return loss, 17% of samples at 5 GHz frequency have the maximum deviation between 1.2 and 1.5 dB. In Table 4, the performance of the proposed LNA is compared to recent published works. It highlights the fact that despite of the active inductor, which can inherently increase the power dissipation and noise of the gm-boosted CG-LNA, the designed circuit exhibits a flat and smooth gain while its power consumption is lower than in [11,18,26], and comparable to the one reported in [19,27]. Moreover, the noise figure is in the range of 4.56–4.7 dB, i.e., only 0.14 dB of variation over the entire 7.5 GHz bandwidth. Although the power consumption of the LNA in [4] is less than the proposed one, its gain is not flat and even though it used a passive inductor, its noise figure is high and increases with frequency. In [11,18], the gain is also not flat and the circuits consume more than 14 and 16 mW power, respectively. Although, passive inductors are used in [26], its noise figure is higher than the proposed one. Additionally, it shows large gain variations and high power consumption of 23 mW. The input return loss in [27] is high and its noise figure increases with frequency, particularly in the band of 3–5 GHz.
Fig. 10. Linearity performance (a) power gain versus input power for deriving 1-dB compression point, (b) main and third-order intermodulation signals for deriving IIP3, and (c) main and second-order intermodulation signals for deriving IIP2.
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Fig. 11. Histogram of NF, S21 and S11 resulted from Monte Carlo analysis at different frequencies for 7 5% tolerance on the channel length of all transistors. The horizontal axis is divided into five groups, indicating the deviation from the ideal mode and the vertical axis indicates the number of iterations that a specific deviation happens.
Fig. 12. Histogram of NF, S21 and S11 resulted from Monte Carlo analysis at different frequencies for mismatch on the threshold voltage of all transistors based on Pelgrom's model. The horizontal axis is divided into four groups, indicating the deviation from the ideal mode and the vertical axis indicates the number of iterations that a specific deviation happens.
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Fig. 13. Histogram of NF, S21 and S11 resulted from Monte Carlo analysis at different frequencies for mismatch on the gate-oxide thickness of all transistors. The horizontal axis is divided into five groups, indicating the deviation from the ideal mode and the vertical axis indicates the number of iterations that a specific deviation happens.
Table 4 Performance summary of the proposed LNA and recent works. Ref.
[4]
Data Architecture Design Method Technology (lm) Power supply (V) BW (GHz) NF (dB) S21 (dB) S11 (dB) Pdiss (mW)
Simulated Measured CG-LNA CS-LNA gm-boosting passive inductor Passive inductor 0.18 0.18 1.5 1.5 2–14 3.1–10.6 2.7–6.2 2.8–4.7 8–10 13.5–15.6 o 10 o 10 9 14.1
n
[11]
[18]
[19]
[26]
[27]
This work
Simulated CS-LNA Active inductor 0.09 1.2 2–11 2.2–3.4 16.5n o 12 16.5
Simulated CS-LNA Active inductor 0.13 1.5 2–11.2 2.2–4 11–12 o 10 13.5
Measured CG-LNA Passive inductor 0.18 1.8 3.1–10.6 4.5–6.2 13.2** o 9.5 23
Simulated CG-LNA Passive inductor 0.18 0.9 3–5 2.1–4.3 16.7 7 0.15 o 5 13
Simulated CG-LNA gm-boosting active inductor 0.18 1.8 3.1–10.6 4.56–4.7 12.17 0.7 o 9.5 13.6
Average gain. Maximum gain.
nn
7. Conclusion An ultra-wideband CMOS LNA utilizing an active inductor in the input matching network is presented. A common-gate structure with gm-boosting approach has been used as the core of the LNA due to its better input matching characteristic in ultra-wideband and relatively frequency independent noise figure. Furthermore, a common-source amplifier has been used as feedback path to boost the gm of the common-gate stage to reduce the noise specification of the LNA. It also decreases the noise contribution of the active inductor. The proposed structure was designed and simulated in BSIM3V3 0.18 mm RF CMOS process in 3.1–10.6 GHz frequency range and 1.8 V supply voltage and the results show that the proposed LNA has reached a flat forward gain of 12.170.7 dB, a reverse isolation of less than 56.1 dB, an input return loss of less than 9.5 dB, and a noise figure of 4.56– 4.7 dB over the entire frequency band, while the total power
dissipation including the output buffer is 13.6 mW. Furthermore, using the active inductor in the input matching network allows reducing the chip area by a factor of approximately 1580. The total chip area (including 2.9 nH spiral inductor and all other elements) is about 0.095 mm2.
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Please cite this article as: A. Saberkari, et al., gm-boosted flat gain UWB low noise amplifier with active inductor-based input matching network, INTEGRATION, the VLSI journal (2015), http://dx.doi.org/10.1016/j.vlsi.2015.06.002i
A. Saberkari et al. / INTEGRATION, the VLSI journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎ [5] D. Ponton, P. Palestri, D. Esseni, L. Selmi, M. Tiebout, B. Parvais, D. Siprak, G. Knoblinger, Design of ultra wideband low noise amplifiers in 45 nm CMOS technology: comparison between planar bulk and SOI FinFET devices, IEEE Trans. Circuits Syst. I 56 (5) (2009) 920–932. [6] H. Zhang, X. Fan, E.S. Sinencio, A low power, linearized, ultrawideband LNA design technique, IEEE J. Solid-State Circuits 44 (2) (Feb. 2009) 320–330. [7] A. Saghafi, A. Nabavi, An ultra-wideband low-noise amplifier for 3–5 GHz wireless systems, in: Proceedings of the IEEE International Conference on Microelectronics, December 2006, pp. 20–23. [8] D.K. Shaeffer, T.H. Lee, A 1.5 V, 1.5 GHz CMOS low noise amplifier, IEEE J. SolidState Circuits 32 (5) (1997) 745–759. [9] T.T.T. Nga, Ultra Low-Power Low-Noise Amplifier Design for 2.4 GHz ISM Band Applications (Ph.D. dissertation), Nanyang Tech. Univ, 2012. [10] Y.-J. Lin, S.-H. Hsu, J.-D. Jin, C.-Y. Chan, A 3.1–10.6 GHz ultra wideband CMOS LNA with current-reused technique, IEEE Microw. Wirel. Compon. Lett. 17 (3) (2007) 232–234. [11] Q. Wan, C. Wang, Design of 3.1–10.6 GHz ultra-wideband CMOS low noise amplifier with current reuse technique, Int. J. Electron. Commun. 65 (12) (2011) 1006–1011. [12] X. Fan, E. Sanchez-Sinencio, J. Silva-Martinez, A 3 GHz–10 GHz common gate ultrawideband low noise amplifier, in: Proceedings of IEEE International Symposium on Circuits and Systems, August 2005, pp. 631–634. [13] X. Guan, A. Hajimiri, A 24- GHz CMOS front-end, IEEE J. Solid-State Circuits 39 (2) (2004) 368–373. [14] M. Khurram, S.M. Rezaul Hassan, A 3-5 GHz current reuse gm-boosted CG LNA for ultrawideband in 130 nm CMOS, IEEE Trans. Very Large Scale Integr. Syst. 20 (3) (2012) 400–409. [15] S.C. Blaakmeer, E.A.M. Klumperink, D.M.W. Leenaerts, B. Nauta, Wideband balun-LNA with simultaneous output balancing, noise-canceling and distortion-canceling, IEEE. J. Solid-State Circuits 43 (6) (2008) 1341–1350. [16] D. Murphy, H. Darabi, A. Abidi, A.A. Hafez, A. Mirzaei, M. Mikhemar, M.C. F. Chang, A blocker-tolerant, noise-cancelling receiver suitable for wideband wireless applications, IEEE J. Solid-State Circuits 47 (12) (2012) 2943–2963. [17] A. Saberkari, S. Ziabakhsh, H. Martinez, E. Alarcon, Design and comparison of flipped active inductors with high quality factors, Electron. Lett. 50 (13) (2014) 925–927. [18] M.M. Reja, I. Filanovsky, K. Moez, A compact CMOS UWB LNA using tunable active inductors for WLAN interference rejection, in: Proceedings of IEEE International Symposium on Circuits and Systems, May 2011, pp. 281–284. [19] M.M. Reja, I. Filanovsky, K. Moez, A CMOS 2.0–11.2 GHz UWB LNA using active inductor circuit, in: Proceedings of IEEE International Symposium on Circuits and Systems, May 2008, pp. 2266–2269. [20] M Moezzi, M.S. Bakhtiar, Wideband LNA using active inductor with multiple feed-forward noise reduction paths, IEEE Trans. Microw. Theory Technol. 60 (4) (2012) 1069–1078. [21] X. Li, S. Shekhar, D. Allstot, Gm-boosted common gate LNA and differential colpitts VCO/QVCO in 0.18 mm CMOS, IEEE J. Solid-State Circuits 40 (12) (2005) 2609–2619. [22] W. Zhuo, S. Embabi J.P. de Gyvez, E. Sanchez-Sinencio, Using capacitive crosscoupling technique in RF low noise amplifiers and down-conversion mixer design, in: Proceedings of IEEE Solid-State Circuits Conference, September 2000, pp. 77–80. [23] F. Yuan, CMOS Active Inductors and Transformers Principle, Implementation, and Applications, Springer, NY, 2008. [24] F. Carreto-Castro, J. Silva-Martinez, R. Murphy-Arteaga, RF low-noise amplifiers in BiCMOS technologies, IEEE Trans. Circuits Syst. II, 46, 1999974–977, Analog and Digital Signal Processing. [25] T.H. Lee, The design of CMOS radio frequency integrated circuits, 2nd ed., Cambridge University Press, 2004. [26] B. Park, S. Choi, S. Hong, A low-noise amplifier with tunable interference rejection for 3.1 to 10.6 GHz UWB systems, IEEE Microw. Wirel. Compon. Lett. 0 (1) (2010) 40–42. [27] H. Alavi-Rad, S. Ziabakhsh, S. Ziabakhsh, M.C.E. Yagoub, A 0.9 V CMOS 3–5 GHz broadband flat gain low-noise amplifier for ultra-wide band receivers, Can. J. Electr. Comput. Eng. 36 (2) (2013) 87–91.
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technical program committee (TPC) member of the IEEE Latin American Symposium on Circuits and Systems (LASCAS'13, LASCAS'14, and LASCAS'15) and IEEE International Conference on Emerging Technologies and Factory Automation (ETFA'14), and also the organizing committee member of the IEEE International Conference on Pattern Recognition and Image Analysis (IPRIA'15) and IEEE International ISC Conference on Information Security and Cryptology (ISCISC'15). He has served as a reviewer for the IEEE Transactions on Electron Devices, Electronics Letters, Analog Integrated Circuits and Signal Processing, Wiley International Journal of Circuit Theory and Applications, International Journal of Electronics, Elsevier Microelectronics Journal, Elsevier integration, the VLSI Journal, Journal of Circuits, Systems, and Computers, Electronics and Electrical Engineering, International Journal for the Computation and Mathematics in Electrical and Electronic Engineering, Journal of Low Power Electronics, International Journal of Signal and Data Processing, Iranian Journal of Electrical and Computer Engineering, and also ISCAS, MWSCAS, ICECS, LASCAS, ECCTD, ETFA, and ISWTA conferences. His fields of interest include the areas of Analog, RF, and Mixed-Signal Microelectronics with particular interest in On-Chip Power Management Circuits, Analog Circuits for Energy Harvesting Applications and Biomedical Implants, Linear and Low-Dropout Regulators, Current-Mode Circuit Design, CMOS LNAs and Mixers, RF Power Amplifiers, and Low-Power and Low-Voltage Integrated Circuits. Dr. Saberkari is a member of IEEE Solid-State Circuits and Circuits and Systems societies.
Shima Kazemi is currently an M.Sc. student in Electrical Engineering at University of Guilan, Rasht, Iran. She works on CMOS LNA based on active inductors toward her M.Sc.
Vahideh Shirmohammadli received the B.Sc. degree in Electrical Engineering from University of Guilan, Rasht, Iran, in 2013 and is currently an M.Sc. student in Electrical Engineering at University of Guilan, Rasht, Iran. Her fields of interest include On-Chip Power Management Circuits, specially Low-Dropout Regulators, CMOS LNAs, and RF Power Amplifiers.
M.C.E. Yagoub received the Dipl.-Ing. degree in Electronics and the Magister degree in Telecommunications, both from the École Nationale Polytechnique, Algiers, Algeria, in 1979 and 1987, respectively, and the Ph.D. degree from the Institut National Polytechnique, Toulouse, France, in 1994. After a few years working in industry, he joined the Institute of Electronics, Université des Sciences et de la Technologie Houari Boumédiene, Algiers, Algeria, first as a Lecturer during 1983–1991 and then as Assistant Professor from 1994– 1999. From 1999 to 2001, he was a visiting scholar with the Department of Electronics, Carleton University, Ottawa, Canada, working on neural applications in microwave areas. In 2001, he joined the School of Electrical Engineering and Computer Science, University of Ottawa, Ottawa, Canada, where he is currently a Professor. His research interests include RF/microwave CAD, RFID design, neural networks for high frequency applications, planar antennas, and applied electromagnetics. He has authored or co-authored 2 books and over 350 publications in these topics in international journals and refereed conferences. Dr. Yagoub is a senior member of the IEEE Microwave Theory and Techniques Society, a member of the Professional Engineers of Ontario, Canada, and a member of the Ordre des ingénieurs du Québec, Canada.
Alireza Saberkari (S'09–M'11) received the B.Sc. degree in Electrical Engineering from Iran University of Science and Technology (IUST), Tehran/University of Guilan, Rasht, Iran, in 2002 and the M.Sc. and Ph.D. degrees both in Electrical Engineering from Iran University of Science and Technology (IUST), Tehran, Iran, in 2004 and 2010, respectively (all with honors). Since 2010, he has been with the Department of Electrical Engineering at University of Guilan as an Assistant Professor. During the period 2008–2009, he joined the group of Energy Processing Integrated Circuits (EPIC), Department of Electronics Engineering, Technical University of Catalunya (UPC), Barcelona, Spain, as a Visiting Scholar and worked on “CMOS Linear Low-Dropout Regulators for Wideband-Tracking LinearAssisted Scheme” and “RF Transmitter Architectures Considering Wideband Adaptive Supply of RF PA”. He has authored or co-authored more than 50 international scientific publications including journals and conference proceedings. He was the
Please cite this article as: A. Saberkari, et al., gm-boosted flat gain UWB low noise amplifier with active inductor-based input matching network, INTEGRATION, the VLSI journal (2015), http://dx.doi.org/10.1016/j.vlsi.2015.06.002i
Contents lists available at ScienceDirect
INTEGRATION, the VLSI journal journal homepage: www.elsevier.com/locate/vlsi
gm-boosted flat gain UWB low noise amplifier with active inductor-based input matching network A. Saberkari a,n, Sh Kazemi a, V. Shirmohammadli a, M.C.E. Yagoub b a b
Department of Electrical Engineering, University of Guilan, Rasht, Iran School of Electrical Engineering and Computer Science, University of Ottawa, Ottawa, Ontario, Canada
art ic l e i nf o
Keywords: Active inductor Flat gain gm-boosting Low noise amplifier Ultra-wideband
a b s t r a c t In this paper, an ultra-wideband (UWB) CMOS low noise amplifier (LNA) utilizing an active inductorbased input matching network is presented. The proposed 0.18 mm CMOS LNA consists of three stages; a gm-boosted common-gate input stage, a common-source gain stage, and an output buffer. Designed in the 3.1–10.6 GHz UWB frequency range, the proposed circuit exhibits a flat forward gain of 12.1 7 0.7 dB, a reverse isolation less than 56.1 dB, an input return loss less than 9.5 dB, and a noise figure of 4.56– 4.7 dB over the entire frequency band, while the total power dissipation is 13.6 mW under a 1.8 V supply. & 2015 Published by Elsevier B.V.
1. Introduction Ultra-wideband (UWB) technology provides the ability to send and receive information in a widespread frequency spectrum, divided into the lower frequency band (3–5 GHz) and the upper frequency band (6–10.6 GHz) [1–3]. One advantage of the UWB network is its capability to transmit digital signals in a high data rate with very low power consumption, low complexity, and high immunity [4]. In modern wireless communication systems, the low noise amplifier (LNA) is an essential block in the receiver chain. It should maintain low noise figure (NF) while exhibiting high and flat gain to amplify the weak input RF signal, low power consumption and chip area, high linearity and stability, and robustness against process, voltage, and temperature (PVT) variations. Furthermore, as the first gain stage after the antenna, its input impedance should match with the characteristic impedance of antenna (typically 50 Ω), which results in lower return loss. Based on noise performance and input matching network characteristics, the CMOS UWB LNA architectures can be categorized into two main groups, as shown in Fig. 1, namely, common-source (CS) and common-gate (CG) LNAs. Their input impedance, Zin(s), as well as the quality factor of their input matching network at the resonance frequency, Qmatch, are listed in Table 1, where gm and Cgs are the transconductance and the parasitic gate-source capacitance of the transistor, respectively [5,6]. The main limitation in CS LNAs is their relatively high Qmatch, while this later should be low to satisfy the UWB matching requirements in terms of bandwidth. To improve the input matching condition of CS-LNAs, different advanced design
n
Corresponding author. Tel: þ 98 13 33690274–8; fax: þ98 13 33690271. E-mail address: [email protected] (A. Saberkari).
techniques have been indeed proposed such as the resistive termination, shunt-series feedback [7], inductive source degeneration [8,9], and current-reuse approach [10,11]. However, the input termination method suffers from higher noise figure due to the noise contribution of an added resistor at the input port of the LNA. The shunt-series feedback technique needs higher power consumption and creates bigger noise figure compared with other methods with the same performance. The inductive source degeneration method is suitable for narrow band applications, and finally, the current-reuse approach occupies a large area of the chip. On the other hand, because of its parallel resonant network and knowing that Cgs is proportional to the transistor size, the Qmatch of the CG-LNA would decrease when the technology becomes scaled down, and hence, the bandwidth would show a wideband behavior. Therefore, as the CG-LNA has a constant wideband input impedance (E1/ gm) it can be considered as a good candidate for wideband impedance matching, without using additional components, while preserving area consumption and avoiding from more resistance losses of onchip inductors. Moreover, in addition to providing a simple input matching network in a wide bandwidth, the CG-LNA has more linearity and stability performance, lower power consumption, better input–output isolation, and more immunity to PVT variations [3,12]. Another point of view is that the noise figure of CS-LNA is linearly proportional to the operating frequency and thus increases when the frequency reaches the gigahertz range. On the other hand, the noise figure in the CG-LNA is approximately independent of the operating frequency. However, it depends on the device size and process parameters, and also, has an inseparable link with the input matching resistance, 1/gm. While the device transconductance has been fixed by setting 1/gm to 50 Ω, the noise performance of the CG-LNA will be limited by the input matching condition. Thus, utilizing a separation method between the input matching condition and the noise figure
http://dx.doi.org/10.1016/j.vlsi.2015.06.002 0167-9260/& 2015 Published by Elsevier B.V.
Please cite this article as: A. Saberkari, et al., gm-boosted flat gain UWB low noise amplifier with active inductor-based input matching network, INTEGRATION, the VLSI journal (2015), http://dx.doi.org/10.1016/j.vlsi.2015.06.002i
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Fig. 1. Popular topologies for LNA input transistor, (a) common-source, (b) common-gate.
Table 1 Input impedance and quality factor of common-source and common-gate LNAs. Architecture
Zin(s)
Qmatch
Common-source (CS)
g m1 LS 1 S2 þ SðLS þ Lg ÞC gs1 þ ðLS þ Lg ÞC gs1 =ðS=ðLS þ Lg ÞÞ
1 2ωC gs1 RS
S=C gs1 g S2 þ SC m1 þ L
ωC gs1 RS 2
Common-gate (CG)
gs1
1 S C gs1
characteristic such as the resistive feedthrough [13], the gm-boosting technique [4,14], or the combination of CG–CS amplifiers with single input differential output structure [15,16] can improve the performance of CG-LNA. As for the matching network itself, aforementioned LNAs mainly utilize on-chip passive spiral inductors. However, these inductors are very bulky with low and fixed inductance, low quality factor and self-resonant frequency, and then, incompatible with low cost standard CMOS processes. It is then preferable to use gyrator-based active inductors, which are more appropriate for reducing size and cost of the chips [17]. Furthermore, the tunability performance of active inductors makes them very attractive in multi-channel communications, as it can be applied in the input matching network of the LNA, creating an active input matching network with tunable resonance frequency. Recently, some CMOS LNA architectures have been proposed based on active inductor [18–20] but suffer from relatively not flat gain over the operating bandwidth, making them unsuitable for UWB applications. In this paper, a flat gain gm-boosted CG-LNA structure with an active inductor-based input matching network is presented to decrease the LNA noise characteristic and reduce the total chip area. The paper is organized as follows: Section 2 introduces the basic principle of gm-boosting mechanism. In Section 3, the active inductor is explained and its equivalent circuit parameters extracted. The design approach with final proposed circuit is discussed in Section 4. Noise analysis is performed in Section 5. Finally, circuit characterization and conclusion are in Sections 6 and 7, respectively.
2. gm-boosting mechanism in LNA To maintain the benefits of the common-gate topology and overcome its limitations, a gm-boosting technique has been applied to the CG-LNA to disconnect the strong coupling between input matching and noise figure characteristic, causing a reduction in both noise and
power losses. As mentioned before, the noise factor of CG-LNA is confined by 1/gm due to input matching condition. Fig. 2(a) shows a basic CG-LNA configuration with its noise sources. As the gate-induced noise is insignificant and usually negligible in CG-LNA, the dominant noise sources are the thermal channel noise of transistor, ind, and the noise current of source resistance, ins. Thus, the noise factor can be obtained as: 2 2 i2 nd : 1 þ 1g Rs i2 nd 1 m F ¼ 1þ ¼ 1 þ ð1Þ 2 i2 ns g m Rs i2 ns : 1 þgmgRsRs m
By substituting the equivalent relations for i2 nd and i2 ns , Eq. (1) can be rewritten as: 2 4KTγg d0 Δf 1 F ¼ 1þ 4KTGs Δf g m Rs γg γ ¼ 1 þ 2d0 ¼ 1 þ ð2Þ α g m Rs ¼ 1 g m Rs where K and T are the Boltzmann constant and absolute temperature, respectively. gd0 is the zero-bias output conductance of the transistor, γ is the thermal channel noise coefficient of the MOS transistor, and Δf is the bandwidth. The conductance Gs is equal to 1/Rs. The parameter α ¼gm/gd0 is equal to unity for long channel devices and has a lower value when the channel length scales down. Both α and γ are bias-dependent parameters. Due to the input matching condition expressed as gmRS ¼1, gm cannot be increased arbitrarily to reduce the noise factor. Nevertheless, it is still possible to improve the noise performance by decoupling input matching and noise figure. As shown in Eq. (3), this aim can be achieved by increasing the effective transconductance of the device at the source terminal, while remaining gd0 unchanged. As shown in Fig. 2(b), this can be reached by inserting at the input of the device, an inverting gain block, A, between the gate and source terminals and thus, boosting the effective transconductance by a factor of (1þ A) [21]. With this, new input matching condition, (1þA) gmRS ¼1, helps improving the noise factor as follow: 2 4KTγg d0 Δf 1 F ¼ 1þ 4KTGs Δf ð1 þ AÞg m Rs γg d0 γ ¼ 1þ ¼ 1 þ ð3Þ αð1 þ AÞð1 þ AÞgm Rs ¼ 1 ð1 þ AÞ2 g m 2 Rs From Eq. (3), it is clear that the noise factor is now reduced by a factor of (1 þ A). Additionally, a lower bias current is needed in the gm-boosted CG-LNA in comparison to the conventional one,
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Fig. 2. CG-LNA configuration, (a) conventional, (b) with gm-boosting.
Fig. 3. Gyrator-C based active inductor and its equivalent circuits.
resulting in less channel noise of the input transistor. One way to achieve the inverting gain would be using a pair of cross coupling capacitors. However, it requires a differential configuration [4,22].
Thus, although this approach has lower noise contribution due to using passive reactive components, it needs a differential structure for LNA, and hence, a differential RF input signal has to be
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generated through a balun stage which will occupy a large chip area. In this paper, as shown in Fig. 2(b), a common-source amplifier is used as inverting gain block.
3. Active inductor As pointed out, passive spiral inductors suffer from many drawbacks such as low and non-tunable self-resonant frequency, low and fixed inductance value, and large silicon area. On the other hand, gyrator-based active inductors offer a number of unique advantages such as small area, large and tunable inductance value and selfresonant frequency, and compatibility with standard CMOS technology. Fig. 3(a) shows the block diagram of an active inductor consisting of two back-to-back connected positive and negative transconductors and a capacitor at the output terminal as a gyrator-C network [23]. This network exhibits an inductive behavior at its input terminal, but due to the parasitic capacitance and the finite output impedance of the transconductors, this behavior remains inductive only within a narrow frequency range. Active inductors are available in both single-ended and differential pair. As in the proposed LNA, a single-ended inductor was needed for the input matching network as shown in Fig. 3(b) [24]. According to Fig. 3(c) and carrying out a small signal analysis, the input admittance of the active inductor is given by: Y in ¼
SC gs þ g m 1 ¼ þ SRC gs þ 1 R Sð
1 RC gs 1 g m 1=RÞ þ gm 1=R
ð4Þ
On the other hand, as shown in Fig. 3(d), the obtained input admittance can be modeled by a parallel RL circuit with the input
admittance given by: 0
Y in ¼ Gp þ
1 LS þ Rs
ð5Þ
where Gp ¼ 1/Rp and Rse are defined as parallel and series resistance with inductor L, respectively. By substituting the corresponding terms in (4) and (5), the parameters of the RL equivalent circuit can be extracted as: Rp ¼ R UL ¼
R2 C gs R U Rse ¼ Rg m 1 Rgm 1
ð6Þ
The zero and pole frequencies of the input admittance of the active inductor are at ωz ¼ 1=RC gs and ωp ¼ g m =C gs , respectively. In order to obtain an inductance effect, Rse should be positive and Rgm should be greater than unity. The latter condition also ensures that ωz o ωp while the circuit will have an inductive behavior in the frequency range of ωz o ω oωp . 4. LNA circuit topology The circuit schematic of the proposed gm-boosted LNA is shown in Fig. 4. It consists of two stages along with a buffer; the first one (M1, M2, and Mactive), the input stage, is a common-gate configuration with gm-boosting approach and active input impedance matching network. The common-gate transistor M1 with low input impedance provides a relatively frequency-independent noise factor. Also, canceling the Miller effect of its gate–drain capacitance provides better isolation against output return signal. The common-source transistor M2 with resistor RD forms the inverting gain block between the gate and source terminals of M1 to boost its transconductance with a factor
Fig. 4. Proposed gm-boosted LNA with active input impedance matching network.
Please cite this article as: A. Saberkari, et al., gm-boosted flat gain UWB low noise amplifier with active inductor-based input matching network, INTEGRATION, the VLSI journal (2015), http://dx.doi.org/10.1016/j.vlsi.2015.06.002i
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of A¼gm2RD without increasing the bias current and transistor size. Resistors RB1 and RB2 and coupling capacitors CB1 and CB2 constitute the bias network of M1 and M2. The active inductor of the input matching network has been realized by Mactive and R. For proper operation, the zero and pole frequencies (ωz, ωp) of the active inductor circuit should be equal to the lowest and highest operating frequency, respectively. According to (6), it is obvious that increasing R will increase the inductance value, and therefore, using a tunable component like a voltage-controlled resistor allows changing the resonance frequency, an attractive option for multi-channel communications. It has to be noted that the
5
matching condition is achieved by a conjugation between active inductor and CG stage; the active inductor is used to cancel the capacitive effects at the input terminal and the gm-boosted CG structure guaranties the real part matching. The second stage of the LNA, the gain stage, includes a commonsource transistor, M3, to increase the power gain and a source follower transistor, Mbuffer, to act as buffer stage. The coupling capacitors, CB3 and CB4, and bias resistors, RB3 and RB4, form the bias network of the above transistors. Due to UWB bandwidth requirements, it is very important to have a flat power gain over the entire frequency range. Therefore, resistor
Fig. 5. (a) The segmented proposed LNA with passive inductor, (b) noise sources of the first stage, (c) noise sources of the second stage.
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RL1 and inductor Lshunt have been added as shunt-peaking to enhance the bandwidth and provide a smooth gain [25]. Note that the small value of the inductor (Lshunt ¼2.9 nH) is much smaller than the inductor of the input impedance matching network, and hence, will not occupy a large chip area. Although, replacing this spiral inductor with an active one will decrease the chip area, the required voltage headroom, power losses, and noise figure will be increased, and consequently, using a spiral inductor will be more suitable.
F ¼ 1þ
γ 1 γ 1þA 1 Aþ2 2 4 þ 4g m1 RD þ g m1 RD ð Þ þ α 1þA α A Aþ1 A RL1 g m1 ð1 þAÞ ð8Þ
γ 1 γ 1þA 1 Aþ2 2 4 þ 4g m1 RD þ g m1 RD ð Þ þ F ¼ 1þ α 1þA α A Aþ1 A RL1 g m1 ð1 þAÞ |fflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl{zfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl} Stage 1
1 γ 1 1 þ4 þ α g m1 g m3 R2L1 1 þ A ðg m3 RL1 Þ2 g m1 RL2 1 þ A |fflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl{zfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl} 4
Stage 2
5. Noise analysis As shown in Fig. 5(a), the circuit has been segmented into two blocks for the purpose of noise analysis. As first analysis, the active inductor was replaced by its passive counterpart, Lopt. Fig. 5(b) shows the noise sources of the first stage namely, the thermal noise sources of RS, RD, and RL1, as well as the thermal channel noise of transistors M1 and M2. Similarly, the second stage noise sources are from transistor M3 and resistor RL2, as illustrated in Fig. 5(c). The noise of the buffer stage is not included in this analysis, as it has not any significant influence on the overall noise performance of the LNA. As mentioned above, the input impedance matching condition GmRS ¼1, with Gm ¼(1þA)gm1 and A¼gm2RD, allows obtaining the noise factor of the LNA as (7). Here, the contribution of the second stage noise is very small and can be neglected. Hence, the total noise factor can be expressed as (8). If the active inductor is considered in the noise analysis, the noise contribution of the active inductor elements should be added to the noise sources of the first stage namely, the channel noise of Mactive, the channel noise of the transistor which provides the bias current IB (with transconductance of gmB), and the thermal noise of R, while other noise sources are kept unchanged, as shown in Fig. 6. As a consequence, the total noise factor of the proposed LNA can be written as (9). As it can be seen, the noise contribution from the active inductor network is reduced by a factor of (1 þ A) and can be then neglected; same for the second stage noise, as already mentioned. γ 1 γ 1þA 1 Aþ2 2 4 F ¼ 1þ þ 4g m1 RD þ g m1 RD ð Þ þ α 1þA α A Aþ1 A RL1 g m1 ð1 þ AÞ |fflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl{zfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl} Stage1
1 γ 1 1 þ4 þ α g m1 g m3 R2L1 1 þA ðg m3 RL1 Þ2 g m1 RL2 1 þ A |fflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl{zfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl} 4
ð7Þ
þ
g2 γ g m;active þ g mB 1 1 þ R m;active α 1þA g m1 g m1 1 þA |fflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl{zfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl}
ð9Þ
Active Inductor
6. Simulation results The proposed 1.8 V common-gate LNA with active inductorbased input matching network was designed and simulated using the HSPICE-RF simulator in BSIM3V3 0.18 mm TSMC RF CMOS process. The design parameter values are listed in Table 2. The simulated forward gain (S21), noise figure (NF), input return loss (S11), and reverse isolation (S12) of the LNA are depicted in Fig. 7. As it can be seen, a smooth forward gain of 12.17 0.7 dB has been obtained over the operating frequency range of 3.1–10.6 GHz along with a noise figure in the range of 4.56–4.7 dB. Additionally, the input return loss and reverse isolation are greater than 9.5 dB and 56.1 dB, respectively. Furthermore, we investigated the two particular bands of 3– 5 GHz and 4.8–6 GHz, used for wireless personal area network (WPAN) according to IEEE 802.15.3a standard [2] and wireless local area network (WLAN) according to IEEE 802.11a standard [3], respectively. As reported in Table 3, the proposed circuit exhibits Table 2 Design parameter values. Transistor W/L [mm/mm]
Resistor [Ω]
Capacitor [F]
Inductor [H]
M1, M3 ¼ 30/0.18 M2 ¼ 100/0.18 Mactive ¼10/0.18
RB1, RB2, RB3 ¼15k RL1 ¼220, RL2 ¼ 750 RD ¼180, RS ¼ 50 R¼ 200k
C1, CB1, CB2 ¼20p CB3, Cout ¼10p
LShunt ¼ 2.9n
Stage2
Fig. 6. The added noise sources to the first stage due to the active inductor of input matching network.
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Fig. 7. Characteristics of the proposed LNA, (a) gain (S21), (b) noise figure (NF), (c) input return loss (S11), (d) reverse isolation (S12).
excellent performance used in WPAN/WLAN receivers. Also, the active inductor-based input matching network yields proper input return loss without occupying a large area. If a passive spiral inductor was used in the input matching network, it would occupy an area about 0.13 mm2 while the area needed by the active inductor is only about 234 mm2. The total chip area (including 2.9 nH spiral inductor and all other elements) is about 0.095 mm2. In order to highlight the contribution of the gm-booster stage on the total noise figure of the LNA, noise contribution of the transistor M2 and resistor RD are canceled by keeping their temperature at 0 K. Fig. 8 shows the noise figure of the LNA from this point of view in comparison with the case of considering the gm-booster noise, which reveals a difference of 0.11 dB, confirming that the gm-booster stage has a little impact on the total noise figure of the LNA. Similarly, for considering the active inductor influence on the noise performance of the LNA, noise contribution of the active inductor elements are canceled by keeping their temperature at 0 K. Accordingly, a noise simulation was performed in comparison with the case of considering the active inductor noise. The result, shown in Fig. 9, indicates a maximum difference of 0.12 dB over the entire frequency range, stabilizing the theoretical analysis. By applying two tones at 5 GHz frequency with 100 MHz spacing, 1-dB compression point (P1 dB), second-order and third-order input intercept points (IIP2 and IIP3) of the LNA are given in Fig. 10. The LNA has reached to a P1 dB of 27.2 dBm, IIP3 of 12.5 dBm, and IIP2 of þ4 dBm. Monte Carlo analysis was performed on the proposed LNA in order to consider the effect of channel length, threshold voltage, and gateoxide thickness mismatch of all transistors on parameters of NF, S21 and S11. Fig. 11 demonstrates the aforementioned parameters histogram for 75% tolerance with a uniform distribution and 100 iterations on the channel length of all transistors in three different frequencies. The horizontal axis is divided into five groups; each of
Table 3 LNA characteristics in two frequency ranges. BW (GHz)
3–5
4.8–6
NF (dB) S21 (dB) S11 (dB)
4.56–4.59 12.7 7 0.1 o 9.43
4.56–4.57 12.6 7 0.0 o 11.3
Fig. 8. Noise figure of the proposed LNA with assuming the booster stage as noiseless (ideal) and noisy (non-ideal) one.
them indicates the deviation from the ideal mode. The vertical axis indicates the number of iterations that a specific deviation happens. For the noise figure, the maximum deviation from the ideal mode due to the 75% tolerance on the channel length of all transistors is 0.08– 0.1 dB at 10.6 GHz frequency, which occurs on 2% of samples. For the
Please cite this article as: A. Saberkari, et al., gm-boosted flat gain UWB low noise amplifier with active inductor-based input matching network, INTEGRATION, the VLSI journal (2015), http://dx.doi.org/10.1016/j.vlsi.2015.06.002i
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forward gain, the maximum deviation is between 0.3 and 0.4 dB at 10.6 GHz, occurring on 6% of samples. Finally, for the input return loss, 1% of samples at 3.1 GHz frequency have the maximum deviation between 0.4–0.5 dB and 5% of samples at 5 GHz frequency have the same maximum deviation. Fig. 12 shows the circuit parameters histogram for a tolerance on the threshold voltage of all transistors based on Pelgrom's model in three different frequencies with a Gaussian distribution and 100 iterations. In this case, the horizontal axis is divided into 4 groups, indicating the deviation from the ideal mode. For the noise figure, the maximum deviation from the ideal mode due to the threshold voltage mismatch of all transistors is 0.01– 0.02 dB at 3.1, 5, and 10.6 GHz frequencies, which occurs on 1%, 5%, and 8% of samples, respectively. For the forward gain, the maximum deviation is between 0.05 and 0.1 dB at 3.1 GHz, 5 GHz and 10.6 GHz,
Fig. 9. Noise figure of the proposed LNA while the noise sources of the active inductor are enabled and disabled.
occurring on 40%, 38% and 15% of samples, respectively. Finally, for the input return loss, 9% of samples at 3.1 GHz frequency have the maximum deviation between 0.15 and 0.2 dB, 8% of samples at 5 GHz frequency, and 4% of samples at 10.6 GHz frequency have the same maximum deviation. Additionally, Monte Carlo analysis at the same three frequencies on the aforementioned parameters of the proposed LNA due to the mismatch on the gate-oxide thickness of all transistors with a Gaussian distribution and 100 iterations is shown in Fig. 13. For the noise figure, the maximum deviation from the ideal mode is 0.3– 0.4 dB at 10.6 GHz frequency, which occurs on 4% of samples. For the forward gain, the maximum deviation is between 1.2 and 1.5 dB at 3.1 GHz, occurring on 8% of samples. Finally, for the input return loss, 17% of samples at 5 GHz frequency have the maximum deviation between 1.2 and 1.5 dB. In Table 4, the performance of the proposed LNA is compared to recent published works. It highlights the fact that despite of the active inductor, which can inherently increase the power dissipation and noise of the gm-boosted CG-LNA, the designed circuit exhibits a flat and smooth gain while its power consumption is lower than in [11,18,26], and comparable to the one reported in [19,27]. Moreover, the noise figure is in the range of 4.56–4.7 dB, i.e., only 0.14 dB of variation over the entire 7.5 GHz bandwidth. Although the power consumption of the LNA in [4] is less than the proposed one, its gain is not flat and even though it used a passive inductor, its noise figure is high and increases with frequency. In [11,18], the gain is also not flat and the circuits consume more than 14 and 16 mW power, respectively. Although, passive inductors are used in [26], its noise figure is higher than the proposed one. Additionally, it shows large gain variations and high power consumption of 23 mW. The input return loss in [27] is high and its noise figure increases with frequency, particularly in the band of 3–5 GHz.
Fig. 10. Linearity performance (a) power gain versus input power for deriving 1-dB compression point, (b) main and third-order intermodulation signals for deriving IIP3, and (c) main and second-order intermodulation signals for deriving IIP2.
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Fig. 11. Histogram of NF, S21 and S11 resulted from Monte Carlo analysis at different frequencies for 7 5% tolerance on the channel length of all transistors. The horizontal axis is divided into five groups, indicating the deviation from the ideal mode and the vertical axis indicates the number of iterations that a specific deviation happens.
Fig. 12. Histogram of NF, S21 and S11 resulted from Monte Carlo analysis at different frequencies for mismatch on the threshold voltage of all transistors based on Pelgrom's model. The horizontal axis is divided into four groups, indicating the deviation from the ideal mode and the vertical axis indicates the number of iterations that a specific deviation happens.
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Fig. 13. Histogram of NF, S21 and S11 resulted from Monte Carlo analysis at different frequencies for mismatch on the gate-oxide thickness of all transistors. The horizontal axis is divided into five groups, indicating the deviation from the ideal mode and the vertical axis indicates the number of iterations that a specific deviation happens.
Table 4 Performance summary of the proposed LNA and recent works. Ref.
[4]
Data Architecture Design Method Technology (lm) Power supply (V) BW (GHz) NF (dB) S21 (dB) S11 (dB) Pdiss (mW)
Simulated Measured CG-LNA CS-LNA gm-boosting passive inductor Passive inductor 0.18 0.18 1.5 1.5 2–14 3.1–10.6 2.7–6.2 2.8–4.7 8–10 13.5–15.6 o 10 o 10 9 14.1
n
[11]
[18]
[19]
[26]
[27]
This work
Simulated CS-LNA Active inductor 0.09 1.2 2–11 2.2–3.4 16.5n o 12 16.5
Simulated CS-LNA Active inductor 0.13 1.5 2–11.2 2.2–4 11–12 o 10 13.5
Measured CG-LNA Passive inductor 0.18 1.8 3.1–10.6 4.5–6.2 13.2** o 9.5 23
Simulated CG-LNA Passive inductor 0.18 0.9 3–5 2.1–4.3 16.7 7 0.15 o 5 13
Simulated CG-LNA gm-boosting active inductor 0.18 1.8 3.1–10.6 4.56–4.7 12.17 0.7 o 9.5 13.6
Average gain. Maximum gain.
nn
7. Conclusion An ultra-wideband CMOS LNA utilizing an active inductor in the input matching network is presented. A common-gate structure with gm-boosting approach has been used as the core of the LNA due to its better input matching characteristic in ultra-wideband and relatively frequency independent noise figure. Furthermore, a common-source amplifier has been used as feedback path to boost the gm of the common-gate stage to reduce the noise specification of the LNA. It also decreases the noise contribution of the active inductor. The proposed structure was designed and simulated in BSIM3V3 0.18 mm RF CMOS process in 3.1–10.6 GHz frequency range and 1.8 V supply voltage and the results show that the proposed LNA has reached a flat forward gain of 12.170.7 dB, a reverse isolation of less than 56.1 dB, an input return loss of less than 9.5 dB, and a noise figure of 4.56– 4.7 dB over the entire frequency band, while the total power
dissipation including the output buffer is 13.6 mW. Furthermore, using the active inductor in the input matching network allows reducing the chip area by a factor of approximately 1580. The total chip area (including 2.9 nH spiral inductor and all other elements) is about 0.095 mm2.
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technical program committee (TPC) member of the IEEE Latin American Symposium on Circuits and Systems (LASCAS'13, LASCAS'14, and LASCAS'15) and IEEE International Conference on Emerging Technologies and Factory Automation (ETFA'14), and also the organizing committee member of the IEEE International Conference on Pattern Recognition and Image Analysis (IPRIA'15) and IEEE International ISC Conference on Information Security and Cryptology (ISCISC'15). He has served as a reviewer for the IEEE Transactions on Electron Devices, Electronics Letters, Analog Integrated Circuits and Signal Processing, Wiley International Journal of Circuit Theory and Applications, International Journal of Electronics, Elsevier Microelectronics Journal, Elsevier integration, the VLSI Journal, Journal of Circuits, Systems, and Computers, Electronics and Electrical Engineering, International Journal for the Computation and Mathematics in Electrical and Electronic Engineering, Journal of Low Power Electronics, International Journal of Signal and Data Processing, Iranian Journal of Electrical and Computer Engineering, and also ISCAS, MWSCAS, ICECS, LASCAS, ECCTD, ETFA, and ISWTA conferences. His fields of interest include the areas of Analog, RF, and Mixed-Signal Microelectronics with particular interest in On-Chip Power Management Circuits, Analog Circuits for Energy Harvesting Applications and Biomedical Implants, Linear and Low-Dropout Regulators, Current-Mode Circuit Design, CMOS LNAs and Mixers, RF Power Amplifiers, and Low-Power and Low-Voltage Integrated Circuits. Dr. Saberkari is a member of IEEE Solid-State Circuits and Circuits and Systems societies.
Shima Kazemi is currently an M.Sc. student in Electrical Engineering at University of Guilan, Rasht, Iran. She works on CMOS LNA based on active inductors toward her M.Sc.
Vahideh Shirmohammadli received the B.Sc. degree in Electrical Engineering from University of Guilan, Rasht, Iran, in 2013 and is currently an M.Sc. student in Electrical Engineering at University of Guilan, Rasht, Iran. Her fields of interest include On-Chip Power Management Circuits, specially Low-Dropout Regulators, CMOS LNAs, and RF Power Amplifiers.
M.C.E. Yagoub received the Dipl.-Ing. degree in Electronics and the Magister degree in Telecommunications, both from the École Nationale Polytechnique, Algiers, Algeria, in 1979 and 1987, respectively, and the Ph.D. degree from the Institut National Polytechnique, Toulouse, France, in 1994. After a few years working in industry, he joined the Institute of Electronics, Université des Sciences et de la Technologie Houari Boumédiene, Algiers, Algeria, first as a Lecturer during 1983–1991 and then as Assistant Professor from 1994– 1999. From 1999 to 2001, he was a visiting scholar with the Department of Electronics, Carleton University, Ottawa, Canada, working on neural applications in microwave areas. In 2001, he joined the School of Electrical Engineering and Computer Science, University of Ottawa, Ottawa, Canada, where he is currently a Professor. His research interests include RF/microwave CAD, RFID design, neural networks for high frequency applications, planar antennas, and applied electromagnetics. He has authored or co-authored 2 books and over 350 publications in these topics in international journals and refereed conferences. Dr. Yagoub is a senior member of the IEEE Microwave Theory and Techniques Society, a member of the Professional Engineers of Ontario, Canada, and a member of the Ordre des ingénieurs du Québec, Canada.
Alireza Saberkari (S'09–M'11) received the B.Sc. degree in Electrical Engineering from Iran University of Science and Technology (IUST), Tehran/University of Guilan, Rasht, Iran, in 2002 and the M.Sc. and Ph.D. degrees both in Electrical Engineering from Iran University of Science and Technology (IUST), Tehran, Iran, in 2004 and 2010, respectively (all with honors). Since 2010, he has been with the Department of Electrical Engineering at University of Guilan as an Assistant Professor. During the period 2008–2009, he joined the group of Energy Processing Integrated Circuits (EPIC), Department of Electronics Engineering, Technical University of Catalunya (UPC), Barcelona, Spain, as a Visiting Scholar and worked on “CMOS Linear Low-Dropout Regulators for Wideband-Tracking LinearAssisted Scheme” and “RF Transmitter Architectures Considering Wideband Adaptive Supply of RF PA”. He has authored or co-authored more than 50 international scientific publications including journals and conference proceedings. He was the
Please cite this article as: A. Saberkari, et al., gm-boosted flat gain UWB low noise amplifier with active inductor-based input matching network, INTEGRATION, the VLSI journal (2015), http://dx.doi.org/10.1016/j.vlsi.2015.06.002i