Gold wire weakening in the thermosonic bonding of the first bond

World abstracts on microelectronics and reliability goods, are evolving rapidly. They demand higher complexity and higher performance circuits and components. At the same time, many of these industry segments are being driven to shrink size, weight, and power dissipation. Standard low cost packaging approaches such as thru-hole PCB and chip and wire hybrids, can no longer efficiently interconnect these more complex circuits. These industry segments are being forced to turn to new higher performance packaging approaches such as SMT, MCM and COB. This paper will describe an innovative embedded chip MCM technology that eliminates high cost structures, as well as materials and processes in current thin film MCM technologies. A plastic encapsulated multichip technology has been developed in which an epoxy encapsulant is molded around bare die to form the MCM substrate. This new MCM process readily scales-up to high volume production and is inherently high yielding, while maintaining all of the performance advantages of the GE developed overlay HDI process. This paper will describe the thermal, mechanical, and chemical stability issues that drove this development, the process used to fabricate the modules, and the cost and yield advantages associated with this structure.

Gold wire weakening in the thermosonic bonding of the first bond. SHZE J. HU, RICHARD K. S. LIM and G. Y. SOW. IEEE Transactions on Components, Packaging and Manufacturing Technology, Part A, 18(1), 230 (March 1995). Factors that are likely to weaken gold wire during thermosonic wirebonding of the first bond on the die pad are studied. The studies show that weakening is due mainly to the gold club ball formation, grain growth of wire, neckdown formation, tie-bar severance, and the wire-scratching phenomenon. Gold club ball formation can be eliminated by long tail length and wire grain size after recrystallization, can be reduced by low current supplied and short spark time during the EFO excitation. Neckdown and tie-bar severance can be removed by introducing reverse loop and ensuring no indexing problem during the wirebonding process. Wire scratching and dragging due to inside chamfer can be eliminated when the capillary for bonding is not too worn out.

Large format fabrication--a practical approach to low cot MCM-D. GEORGE WHITE, ERIC PERFECTO, DALE MCHERRON, THOMAS DEMERCURIO, THOMAS REDMOND and MAURICE NORCOTT. IEEE Transactions on Components, Packaging and Manufacturing Technology, Part B, 18(1), 37 (February 1995). The IBM Microelectronics Division at East Fishkill has recently demonstrated the fabrication of thin films for MCM-D on large area panels, 300 mm × 300 mm in size. Fabrication of the thin films was accomplished on IBM's 300 mm development line using immersion development of photosensitive polyimide for via formation and electrolytic plating to define wiring and terminal metal levels. One

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plane pair of thin films was constructed on Corning glass 7059 panels for 35 ~m lines on 85 ~tm pitch. In addition, two metal-dielectric levels with 13 lam lines on 25 i.tm pitch have also been demonstrated. The 25 ~m pitch represents the most aggressive groundrule practiced in electronic packaging today. The successful production of electrically good substrates at a high yield from a 300mm panel provides a gateway to significant cost reductions of future MCM-D products. In this paper we will discuss the processes and equipment used to fabricate two different test vehicles, as well as some of the cost and yield considerations associated with large area panel processing for M C M - D packages.

A micromachined array probe card----characterization. MARK BEILEY, JUSTIN LEUNG and S. SIMON WONG. IEEE Transactions on Components, Packaging and Manufacturing Technology, Part B, 18(1), 184 (February 1995). An array probe card fabricated on a silicon wafer for high performance and high pin count applications is characterized. The probe card is capable of providing a very large number of probe tips (>1000) that offer a contact resistance of less than 2f~. A novel approach to replacing the mechanical scrubbing motion with an electrical breakdown process is presented. The probe card is capable of operating at elevated temperatures for extended periods of time, offers alternative probe tip configurations, and is capable of probing a variety of pad metals. Controlled impedance (50 f~) striplines that run all the way to the probe tips offer a delay time of 68 ps/cm, 3 GHz bandwidth, and far-end cross-talk of - 4 9 dB/cm at a pitch of 32 ~tm.

Assembly-level reliability: a methodology for effective manufacturing of IC packages. L. T. NGUYEN, J. R. F I N N E L L and K. M. SINGH. IEEE Transactions on Reliability, 44(1), 14 (March 1995). This paper discusses the general methodology of assembly level reliability (ALR) as part of a corporate effort at designing reliability into the whole assembly process of integrated circuit (IC) packages. Semiconductor packages with assembly-induced defects sometimes do escape detection due to a variety of reasons. Trying to eliminate this problem by approaching it piecemeal may result only in single process optimization, but does not guarantee full assembly line balancing for error-free production. ALR is a systematic four-prong approach which uses a combination of techniques for synergistic effects. (1) Problems of immediate needs have to be addressed and contained. (2) The proper steps must then be taken to ensure that similar isssues do not resurface. (3) Design-for-manufacturability principles must be applied; e.g. the design of the package can be simplified to reduce the number of assembly steps, increase throughput and cut cost. (4) Qualification methodologies have to be revisited. Less expensive but well-characterized test chips can be introduced in lieu of actual devices. Accelerated testing with a good understanding of the failure mechanisms