Si superlattices on silicon-on-insulator substrates for multi-bridge channel field effect transistors

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Journal of Crystal Growth 283 (2005) 57–67 www.elsevier.com/locate/jcrysgro

Growth of SiGe/Si superlattices on silicon-on-insulator substrates for multi-bridge channel field effect transistors J.M. Hartmanna,, P. Holligera, F. Laugiera, G. Rollanda, A. Suhma, T. Ernsta, T. Billona, N. Vullietb a

CEA-DRT, LETI/D2NT & DPTS, CEA/GRE - 17, Avenue des Martyrs, 38054 Grenoble Cedex 9, France b STMicroelectronics, 850 Rue Jean Monnet, 38 926 Crolles Cedex, France Received 2 May 2005; accepted 23 May 2005 Available online 26 July 2005 Communicated by R. Kern

Abstract We have studied in reduced pressure chemical vapor deposition the growth kinetics of Si and Si0.8Ge0.2 on bulk Si(0 0 1) and on silicon-on-insulator (SOI) (100 nm buried oxide/20 nm Si over-layer) substrates. For this, we have grown miscellaneous Si/Si0.8Ge0.2 superlattices on both types of substrates that we have studied mainly in secondary ions mass spectrometry but also in X-ray diffraction. Systematic Si and SiGe growth rate decreases (together with a Ge concentration increase) occurred on SOI substrates as the stack thickness increased from zero to more than 100 nm. Such phenomena are most likely associated to a decrease of the SOI surface temperature by 12–13 1C compared to bulk. For Si, the growth rate on SOI increased back again towards the bulk value as the stack thickness neared two hundred nanometers. This is linked to a SOI surface temperature that went 5 1C back up. Such a knowledge will be most useful to form in the near future regular superlattices on SOI substrates that will serve as the active regions of multi-bridge channel field effect transistors. Three periods Si/SiGe superlattices with either 20% or 31% of Ge and varying SiGe layer thickness were also grown on bulk Si(0 0 1) to study the critical thickness for plastic relaxation of the compressive strain that builds up in such stacks. r 2005 Elsevier B.V. All rights reserved. PACS: 68.55.
a; 85.40.Ry; 81.15.Aa; 81.15.Gh Keywords: A1. Si and SiGe growth kinetics; A3. Reduced pressure chemical vapour deposition; B2. Bulk and SOI substrates

1. Introduction Corresponding author.

E-mail address: [email protected] (J.M. Hartmann).

In order to meet the high performance requirements of the ITRS roadmap after 2010, a large

0022-0248/$ - see front matter r 2005 Elsevier B.V. All rights reserved. doi:10.1016/j.jcrysgro.2005.05.068

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J.M. Hartmann et al. / Journal of Crystal Growth 283 (2005) 57–67

number of non-classical architectures for metal oxide semiconductor field effect transistors (MOSFETs) have quite recently been proposed, with promising electrical performances. Amongst such architectures are ultra-thin fully depleted siliconon-insulator (SOI) FETs [1,2], double-gate FETs [3], O-FETs [4], silicon-on-nothing (SON) FETs [5,6], multi-bridge-channel (MBC) FETs [7,8], etc. The latter two approaches rely on the epitaxy of SiGe/Si multilayers, on the formation of trenches and most importantly on the high degree of selectivity (versus Si) that can be achieved when dry etching laterally the SiGe layers (with Ge contents above 15%) [9]. In the SON approach, the voids left by the removal of the SiGe buried layer are then filled with SiO2. This leads to the formation of FETs (with localized buried oxide (BOX) layers beneath the Si surface channel/gate stacks) that electrically operate in a fully depleted like regime. In the MBCFET case, the Si slabs left after the selective dry etching of the SiGe layers are then encapsulated by SiO2/TiN gates, leading (after a selective epitaxial growth of Si in the source and drain regions [8]) to the formation of multi-channel devices. MBCFETs offer great potential for ultimate MOSFET downscaling. Indeed, they provide a current density per square unit which is directly proportional to the number of stacked channels, a ‘‘double gate like’’ electrostatic control of each channel by the gate, some self alignment of the channels, gate and junctions, the design flexibility of planar devices, etc. The MBCFETs calling upon some epitaxial growth of SiGe/Si superlattices either on bulk or on SOI substrates, we have thus investigated the specifics of the reduced pressure—chemical vapor deposition (RP-CVD) of Si and SiGe on both types of substrates. Some limited literature data have indeed shown that the Si growth rate can be vastly modified (usually reduced) when switching from bulk to SOI substrates [10–12]. Both the buried oxide thickness and the over-layer thickness seem to have an impact on it [11,12], hinting at changes in the surface temperature depending on the stack. Such variations would (if not corrected) dramatically degrade the period reproducibility of SiGe/Si superlattices grown on SOI substrates. We

have also studied on 3 periods Si/SiGe superlattices with either 20% or 31% of Ge the critical thickness for plastic relaxation of the compressive strain that builds up in such stacks.

2. Experimental details We have used an Epi Centura RP-CVD industrial cluster tool manufactured by applied materials to grow all the structures studied in this paper. The platform is constituted of 6 interconnected chambers: two load-lock chambers that can hold up to twenty five 200 mm wafers, a transfer chamber that acts also as a buffer chamber and contains the robot for wafer transferring, a cooldown—wafer centering chamber and two RPCVD growth chambers. The samples were either grown on lightly p-type doped Si(0 0 1) bulk substrates or on {20 nm Si over-layer/100 nm BOX} SOI substrates. The growth pressure was always 20 Torr. The flow of H2 carrier gas was set at a fixed value of a few tens of standard liters per minute, which was not altered throughout all the experiments. Pure dichlorosilane (SiH2Cl2) was used as the source of Si and germane (GeH4) diluted at 2% in H2 as the source of Ge. Temperature monitoring and control was ensured through the lower pyrometer, i.e. the one which is looking at the backside of the susceptor plate on which the wafer lies. The reading is therefore independent of the nature of the substrate (i.e. bulk or SOI). The high-resolution X-ray diffraction (XRD) experiments were performed on a Panalytical X’pert diffractometer. The secondary ion mass spectrometry (SIMS) measurements were carried out on a Cameca IMS 5f apparatus. Cs+ primary ions were used for silicon and germanium depth profiling, with an impact energy of the order of 1 keV. The atomic masses monitored were those of Cs2Si+ (133  2 þ 28 ¼ 294 amu) and Cs2Ge+ (133  2 þ 70 ¼ 336 amu) [13]. Tapping-mode atomic force microscopy (AFM) images were acquired on a DI 3100 tool. Finally, the crosssectional scanning electron microscopy (SEM) images were acquired on a Hitachi S5000 microscope after a brief diluted Secco revelation of the SiGe layers.

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3. The samples grown In order to quantify the changes occurring when switching from bulk to SOI, we have grown on both types of substrates miscellaneous {Si0.8Ge0.2/ Si} superlattices (see Table 1). The nominal Si0.8Ge0.2 layer thickness was comprised in between 14 and 28 nm. Meanwhile, the nominal Si layer thickness was in the 9–32 nm range. Care was taken in every case to stay below the critical thickness of plastic relaxation [14] both of the individual compressively strained Si0.8Ge0.2 layers and of the overall {Si0.8Ge0.2/Si} stacks by adjusting the total number of periods (in-between 3 and 5). An additional 5 nm of Si (compared to the Si spacers) was added to every Si cap in order to account for Si consumption during the future processing of MBCFETs. The Si0.8Ge0.2 layers were grown at 650 1C using a SiH2Cl2 (F(SiH2Cl2)/F(H2) ¼ 0.0025) and GeH4 (F(GeH4)/F(H2) ¼ 8.33  10
5) chemistry [12]. Such a low growth temperature indeed enables to grow quite thick layers without any elastic relaxation of the strain through the formation of surface undulations [15,16]. Even for the superlattices with the thickest Si0.8Ge0.2 layers (types I, II and IV of Table 1), the resulting surfaces as imaged in tapping mode AFM were very smooth, with a root mean square roughness and a Z range ð¼ Zmax:2Z min :Þ at most equal to 0.8 A˚ (7 A˚) for 5 mm  5 mm images. The precise Ge concentration (using those mass flows) was checked in XRD on a simple Si buffer/Si0.8Ge0.2/Si cap stack grown on a bulk Si(0 0 1) substrate [17]: it is equal to 20.2%. Table 1 The nominal structure of the miscellaneous {Si0.80Ge0.20/Si} superlattices grown on bulk Si(0 0 1) and on SOI substrates Sample type

Number of periods

Nominal Si0.80Ge0.20 layer thickness (on bulk) (nm)

Nominal Si layer thickness (on bulk) (nm)

I II III IV V

3 3 3 4 5

28 24 9 20 14

11 31 32 9 32

~~ 130 130 nm nm

SiGe 23 nm SiGe 23 nm SiGe 23 nm SiGe 23 nm

Si 13 nm Si 8 nm Si 88 nm nm Si Si 8 nm

Si(001) Si(001)

200 nm 200 nm

(a)

SiGe + Si 24 nm Si 6 nm SiGe 15nm nm SiGe15 Si 7 nm SiGe18 nm SiGe 18 nm Si 9 nm SiGe 24nm nm SiGe24 Si Si 20 20 nm nm 100nm nm BOX100

(b)

Si(001) Si(001)

103 103nm nm

120 120nm nm

200 nm 200 nm

Fig. 1. Cross-sectional SEM images of 4 periods {Si0.8Ge0.2/Si} superlattices grown using exactly the same recipe either on a bulk Si(0 0 1) substrate (a) or on a {20 nm Si/100 nm BOX} SOI substrate (b). The Si layers in the stack appear as undulating white stripes.

The Si spacers themselves were grown at 700 1C using SiH2Cl2 (F(SiH2Cl2)/F(H2) ¼ 0.01). Cross-sectional SEM images of one variant (type IV) of those superlattices (SLs) both on bulk and on SOI substrates can be found in Fig. 1. Whereas the individual layer thickness seems fairly constant for the SL grown on a bulk substrate (Fig. 1a), it markedly decrease for the SL grown on the SOI substrate as the thickness increases, which is the first clear indication that the surface temperature does indeed decrease. Cross-sectional SEM is however not especially adapted for precise thickness determination. We have indeed noticed that, most probably due to the diluted Secco etching used for SiGe delineation prior to imaging, the SiGe layer thickness is systematically overestimated and the Si layer thickness under-evaluated for such stacks (compared to XRD and SIMS).

4. The measurement protocol used We have first of all used high resolution XRD in conjunction with SIMS to gain access to the

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individual thickness and Ge concentration of the layers in our SLs grown on bulk Si(0 0 1) wafers. It is indeed quite important to see whether or not the thickness and Ge concentration obtained in SIMS are meaningful. They can indeed suffer from a lack of precision linked to (i) different abrasion rates in Si and SiGe (ii) the convolution in-between the ‘‘real’’ Ge concentration profile and instrumental effects (crater mixing, etc.) (iii) an imperfect relative sensitivity factor (RSF) for the conversion of the GeCs+ 2 ions detected by the SIMS mass spectrometer into a Ge atoms concentration. We have plotted in Fig. 2 an o-2y scan around the (0 0 4) XRD order for the 4 periods superlattice imaged in Fig. 1a. Apart from the Si substrate peak, well defined, evenly spaced superlattice satellite peaks, which come from the periodicity of the stack, are present. We can thus accurately determine the superlattice period p ¼ mðaSi =4Þ þ nða? =4Þ and the mean lattice parameter
SiGe a ¼ ðmaSi þ na? SiGe Þ=ðm þ nÞ, m(n) being the number of Si (SiGe) atomic monolayers. The strained lattice parameter in the [0 0 1] direction of the SiGe layers, a? SiGe , is linked to the unstrained lattice parameter aSiGe through the well-known relationship a? SiGe ¼ aSiGe þ 2c12 =c11 ðaSiGe
aSi Þ. The values adopted for the diamond lattice parameter 4 x (Si0.80Ge0.20 19.95 nm / Si8.85nm) SL + Si cap5 nm

Intensity (hits/s)

104

Si subs.

(004) exp. simul.

1000

0 +1

100

+2 +4

-1 -2

10

1 34

34.5 Omega (°)

Fig. 2. o-2y scan around the (0 0 4) XRD order for the 4 periods superlattice imaged in Fig. 1a, together with its associated dynamical theory simulation.

and the ratio of the elastic constants 2c12 =c11 of Si (Ge) are 5.43105 A˚ (5.65785 A˚) and 0.771 (0.752) [18]. The nonlinearity of the SiGe lattice parameter with the Ge content x [19] is taken into account using aSiGe ðxÞ ¼ 5:43105 þ 0:20050x þ 0:0263x2 . To a very good approximation, we have adopted for 2c12 =c11 ðxÞ a 0.767 value (ratio of the elastic constants for x ¼ 0:2). For a Ge concentration x ¼ ( 0:202 (see Section 3), a? SiGe ¼ 5:5045 A.We therefore have two unknown, m and n, and the two
above-mentioned equations for p and a. Through a careful matching in-between experimental and stimulated profiles (Takagi–Taupin dynamical diffraction theory [20]), we can determine unequivocally the individual thickness of the Si and the SiGe layers in all our stacks grown on bulk Si(0 0 1) substrates. As an illustration, the 4 periods superlattice of Figs. 1a and 2 is characterized by individual Si0.80Ge0.20 (Si) layer thickness of 19.95 nm (8.85 nm). One can also notice in Fig. 2 the presence of marked thickness interference fringes (short arrows pointing downwards in Fig. 2), which are (together with the good match in-between experimental and stimulated profiles) a testimony to the crystalline quality of the stacks (i.e. abrupt interfaces, no plastic strain relaxation). Such characteristics were associated to all the Table 1 superlattices grown on bulk Si(0 0 1) substrates. We have plotted in Fig. 3 the Ge concentration profile (in SIMS) obtained on the Fig. 1a (bulk) and Fig. 1b (SOI) superlattices. A 40 nm SiO2 capping layer was deposited using TEOS at low temperature on all samples prior to any structural characterization in order get rid of the transients occurring during the SIMS profiling of the first few tens nanometers (surface contamination etc). One can in Fig. 3 clearly identify the 4 periods of type IV superlattices, notice the good periodicity of the SL grown on bulk Si(0 0 1) and the decreasing individual layer thickness as the deposited stack gets thicker and thicker on SOI (already visible in Fig. 1b). The layer thickness determination protocol that we have used on every SIMS profile is the following one: we have selected 5  1021 atoms cm
3, i.e. 10% of Ge in the SiGe layers, as our thickness measurement concentration. With such a value,

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Si or SOI subs.

1021 SiGe / Si SL 20

10

40 nm TEOS

1019

Bulk SOI

SiGe growth rate (nm min.-1)

Ge atoms conc. (cm-3)

1022 11

Bulk - SIMS Bulk - XRD SOI - SIMS

10

9

1018 8

50

100 150 Depth (nm)

200

Fig. 3. SIMS profile of the Ge atoms concentration inside the 4 periods superlattices grown on bulk and on SOI substrates using exactly the same recipe (same samples as in Fig. 1a and b). The doted line corresponds to the Ge concentration value we have selected in order to extract the individual layer thickness in all the samples.

the individual layer thickness coming from SIMS are pretty close to the ones obtained in XRD. As an example, we have for the Fig. 1a superlattice grown on bulk Si(0 0 1) individual SiGe layer thickness in-between 19.4 and 19.7 nm (19.95 nm in XRD) and Si layer thickness in-between 8.8 nm and 9.2 nm (8.85 nm in XRD). We thus have established a SIMS measurement protocol that yields precise layer thickness (and thus growth rate) both on bulk Si(0 0 1) and on SOI substrates. We are in the next section going to use it on every SL in order to quantify the effects of SOI substrates on the growth kinetics of Si and SiGe.

5. The Si and SiGe growth kinetics on bulk Si(0 0 1) and on SOI 5.1. The SiGe growth kinetics We have plotted in Fig. 4a the growth rate associated to the SiGe layers grown either on bulk Si(0 0 1) or on SOI substrates, this as a function of the thickness deposited. Type I, II and IV superlattices were used for such an assessment (i.e. the

0

20

(a)

40 60 80 100 Thickness deposited (nm)

120

140

21.5

Ge concentration (%)

0

21

20 (b)

Bulk - SIMS SOI - SIMS

20.5

0

20

40 60 80 100 Thickness deposited (nm)

120

Fig. 4. (a) Growth rates and (b) Ge concentrations associated to SiGe layers grown either on bulk Si(0 0 1) or on SOI, this as a function of the deposited thickness. SIMS or XRD were used for growth rate determination on bulk.

ones with the thickest SiGe layers). What should first of all be highlighted is that a quite good agreement does exist on bulk in-between the SiGe growth rates obtained from SIMS and the XRD ones (although the XRD ones are slightly higher). Second, there is a definite decrease on SOI of the SiGe growth rate (from 11 down to 8.5 nm min
1) as the deposited thickness increases, in sharp contrast with what is observed on bulk.

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We have plotted in Fig. 4b the Ge concentration inside our type I, II and IV superlattices grown either on bulk or on SOI substrates. The Ge SIMS RSF adopted was such that the mean SIMS Ge concentration for the SiGe layers grown on bulk was equal to 20.2% (i.e. 9.86  1021 Ge atoms/ cm
3). Whereas the Ge concentration of the SiGe layers grown on bulk fluctuates only very slightly around 20.2%, a definite Ge concentration increase occurs (from 20.2% up to 21.4%) as the deposited thickness increases on SOI substrates. This simultaneous decrease of the growth rate and increase of the Ge concentration is most probably a sign of an effective growth temperature that decreases as the deposited thickness increases on SOI. Such a behavior would be in agreement with Ref. [17]. We have used data points coming from Refs. [17] and [21] to plot as a function of the growth temperature the SiGe growth rate and the Ge concentration associated to layers grown on bulk Si(0 0 1) (see Fig. 5). We have then positioned the SiGe growth rates and Ge concentrations we had obtained on SOI (see Fig. 4) on those data curves, in order to determine the effective surface growth temperature. For a target growth tempera-

60

ture equal to 650 1C, we have a gradual decrease of the SOI surface temperature from 648 1C down to 635 1C (from the growth rate) and from 651 1C down to 638 1C (from the Ge concentration), i.e. a 13 1C drop, as the deposited thickness increases from zero up to slightly more than 100 nm (hatched region in Fig. 5).

5.2. The Si growth kinetics We have plotted in Fig. 6 the growth rate associated to the Si layers grown either on bulk Si(0 0 1) or on SOI substrates, this as a function of the thickness deposited. Type II, III and V superlattices were used for such an assessment (i.e. the ones with the thickest Si layers). Once again, a quite good agreement does exist on bulk in-between the Si growth rates obtained from SIMS and the XRD ones, although the SIMS ones are higher. As for SiGe, a definite Si growth rate decrease (from 2.6 down to 1.85 nm min
1) occurs on SOI as the deposited thickness increases from zero up to more than 100 nm, in marked contrast with what is observed on bulk. What is especially interesting however is that, for thicker stacks, the

30

40 30

20

20 15 10

Si growth rate (nm min.-1)

25

Ge concentration (%)

SiGe growth rate (nm min.-1)

2.8 50 2.6

2.4

Bulk - SIMS Bulk - XRD SOI - SIMS

2.2

2 0 550

600 650 700 Growth temperature (°C)

10 750

Fig. 5. SiGe growth rates (circles) and Ge concentration (squares) associated to SiGe layers grown either on bulk Si(0 0 1) (full symbols) or on SOI (open symbols), this as a function of the effective growth temperature. F(SiH2Cl2)/ F(H2) ¼ 0.0025, (F(GeH4)/F(H2) ¼ 8.33  10
5 and P ¼ 20 Torr for all data points.

1.8

0

50

100 150 Thickness deposited (nm)

200

Fig. 6. Growth rates associated to Si layers grown either on bulk Si(0 0 1) or on SOI, this as a function of the deposited thickness. SIMS or XRD were used for growth rate determination on bulk.

ARTICLE IN PRESS J.M. Hartmann et al. / Journal of Crystal Growth 283 (2005) 57–67

Si growth rate increases back again (2.15 nm min
1 for slightly less than 200 nm) towards the bulk value. Such a behavior, very similar to what was previously obtained on patterned SOI wafers [12], is quite logical: for really thick stacks, the influence of the buried oxide gets less and less marked, and we go back to a bulk-like configuration. In analogy with the Fig. 5 approach, we have used data points coming from Refs. [12] and [22] to plot the growth rates associated to Si layers deposited on bulk Si(0 0 1) as a function of the growth temperature (see Fig. 7). We have then positioned the Si growth rates we had obtained on SOI (see Fig. 5) on this data curve, in order to determine the effective surface growth temperature. For a target growth temperature of 700 1C, we have a gradual decrease of the SOI surface temperature from 703 1C down to 691 1C, i.e. a 12 1C drop, as the deposited thickness increases from zero up to slightly more than 100 nm. Such a value is in full agreement with the 13 1C drop obtained for SiGe in Section 5.1. The SOI surface growth temperature then increases back to 696 1C (i.e. a 5 1C re-increase) as the deposited thickness approaches 200 nm.

5

Si growth rate (nm min.-1)

4 Si GR - bulk Si GR - SOI 3

2

1

0 650

675 700 Growth temperature (°C)

725

Fig. 7. Growth rates associated to Si layers grown either on bulk Si(0 0 1) (full symbols) or on SOI (open symbols), this as a function of the effective growth temperature. F(SiH2Cl2)/ F(H2) ¼ 0.01 and P ¼ 20 Torr for all data points.

63

6. The critical thickness for plastic relaxation in three periods Si/SiGe superlattices 6.1. Experimental results The fact that the dry etching selectivity of SiGe versus Si increases as the Ge content increases [9] has led to the adoption of Si0.7Ge0.3 layers in the SON process [5,6]. We have therefore decided to determine for Ge concentrations either equal to 20% or 31% the critical thickness for plastic relaxation in 3 periods {SiGe/Si} superlattices grown on bulk Si(0 0 1). We might indeed end up being forced by the subsequent process steps used in MBCFETs to use SiGe/Si multilayers with a Ge concentration equal to 30% instead of 20%. We have thus grown 3 periods {Si0.8Ge0.2/Si} and 3 periods {Si0.69Ge0.31/Si} superlattices with 22 nm thick Si spacers (and caps) in every case and varying Si0.8Ge0.2 or Si0.69Ge0.31 thickness. The thickness studied for Si0.8Ge0.2 were 25, 30, 35 and 40 nm (40 nm is more or less the maximum thickness for MBCFET integration purposes). The thickness probed for Si0.69Ge0.31 were 20, 24.5, 29 and 33.5 nm. The stacks were grown using exactly the same process than the one described in Section 3 (i.e. 650 1C for SiGe and 700 1C for Si), the only difference being for Si0.69Ge0.31 the higher F(GeH4)/F(H2) mass-flow used (2.917  10
4), leading to a higher growth rate (36.0 nm min
1). We have plotted in Fig. 8a (8b) the conventional Omega-2Theta scans around the (004) diffraction order for the 3 periods {Si0.69Ge0.31/Si} superlattices (the 3 periods {Si0.80Ge0.20/Si} superlattices) with varying SiGe layer thickness. What can very clearly be seen in Fig. 8a is that for 29.1 and 33.5 nm of Si0.69Ge0.31, there is a very clear loss of the well-defined superlattice satellite peaks and interference fringes. This is most probably related to the generation of misfit and threading dislocations in the stacks, combined (as will be seen in Fig. 9) with some elastic relaxation of the strain through some undulations of the Si0.69Ge0.31/Si interfaces. By contrast, for lower Si0.69Ge0.31 layer thickness (either 24.6 or 20.4 nm), well defined peaks are obtained. As far as the 3 periods {Si0.80Ge0.20/Si} superlattices are concerned (see Fig. 8b), well defined peaks are observed even for

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3 x {SiGe 31% / Si) SL 7

10

Intensity (hits/s)

106 105

(004)

33.5nm 29.1nm 24.6nm 20.4nm

104 1000 100 10 1

33

33.5

(a)

34 Omega (°)

34.5

35

3x {SiGe 20% / Si) SL

108 107 Intensity (hits/s)

106

39.8nm 34.7nm 29.8nm 24.9nm

105 104 1000 100 10 1 33.5

(b)

34

34.5

35

We have imaged the surface of all those samples in AFM (see Fig. 9). The Si surface of the Si0.69Ge0.31/Si superlattice with 20.4 nm of Si0.69Ge0.31 is smooth (Fig. 9a), as attested by its surface root mean square (rms) roughness (0.87 A˚). The one with 24.6 nm of Si0.69Ge0.31 is also smooth (rms ¼ 0.91 A˚), although some hints of a surface cross-hatch can be seen in the right hand part of Fig. 9b. By contrast, a definite crosshatch pattern is obtained for 29.1 and 33.5 nm of Si0.69Ge0.31 (Fig. 9c and d), with surface rms roughness equal to 2.76 and 2.02 A˚, respectively. We have plotted in Fig. 9e an AFM image of the Si surface of the 3 periods Si0.80Ge0.20/Si superlattice with 39.8 nm of Si0.80Ge0.20, which is really smooth (rms ¼ 0.83 A˚). Knowing that a surface cross-hatch is usually obtained for SiGe virtual substrates [23] (i.e. nearly fully relaxed SiGe layers with misfit and threading dislocations in their midst), it is therefore tempting based on the XRD results of Fig. 8a and on Fig. 9a–d results to put the critical thickness for plastic relaxation in 3 periods {Si0.69Ge0.31/Si} superlattices (with 22 nm Si layers) at around 25 nm of Si0.69Ge0.31. By contrast, for 3 periods {Si0.80Ge0.20/Si} superlattices (also with 22 nm Si layers), Si0.80Ge0.20 layers as thick as 39.8 nm do not lead to any significant plastic relaxation of the strain (as seen in Figs. 8b and 9e). 6.2. Critical analysis

Omega (°)

Fig. 8. Top: Conventional Omega-2Theta scans around the (0 0 4) diffraction order for the 3 periods {Si0.69Ge0.31/Si} superlattices with a Si layer thickness equal to 22 nm and varying Si0.69Ge0.31 layer thickness (see the figure insert). Bottom: Conventional Omega-2Theta scans around the (0 0 4) diffraction order for the 3 periods {Si0.80Ge0.20/Si} superlattices with a Si layer thickness equal to 22 nm and varying Si0.80Ge0.20 layer thickness (see the figure insert). XRD profiles have been shifted up (for clarity purposes) as the SiGe layer thickness increases in both plots.

39.8 nm of Si0.80Ge0.20, which must mean that no significant plastic relaxation had occurred in those stacks.

Let us now do some simple critical analysis of the results versus literature values for compressive SiGe grown on top of Si(0 0 1) [14]. The thickest 3 periods Si0.80Ge0.20/Si superlattice (i.e. the one with 22 nm of Si and 39.8 nm of Si0.8Ge0.2) can be approximated by a 185 nm thick Si0.87Ge0.13 alloy, for which the metastable critical thickness for plastic relaxation as determined by People and Bean [24] is of the order of 500 nm. The metastable critical thickness for plastic relaxation of a single Si0.8Ge0.2 layer itself is around 180 nm (versus 40 nm in our case). It is thus logical that our thickest 3 periods Si0.80Ge0.20/Si superlattice does not present any significant sign of plastic relaxation.

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(a)

0.0

(b)

2.50

5.0 0.0

2.50

5.0

2.5

5.0

(d)

(c)

0.0

65

2.5

5.0 0.0 5.0

5.0 nm 2.5 nm

2.5

(e)

0.0

0.0 nm

0.0 2.5 µm

5.0

Fig. 9. (a–d) 5 mm  5 mm AFM images of the surface of the 3 periods {Si0.69Ge0.31/Si} superlattices with a Si layer thickness equal to 22 nm and a Si0.69Ge0.31 layer thickness equal either to 20.4 nm (a), 24.6 nm (b), 29.1 nm (c) or 33.5 nm (d), (e) 5 mm  5 mm AFM image of the surface of the 3 periods {Si0.80Ge0.20/Si} superlattice with a Si layer thickness equal to 22 nm and a Si0.80Ge0.20 layer thickness equal to 39.8 nm. The image sides are more or less along the /1 0 0S directions and the depth scale is the same for all images.

On the other hand, let us suppose based on Section 6.1 results that a 3 periods {Si0.69Ge0.31/Si} superlattice with 22 nm Si layers and around 25 nm of Si0.69Ge0.31 is close to plastic relaxation. Such a superlattice can be approximated by a 140 nm thick Si0.83Ge0.17 alloy, for which the metastable critical thickness for plastic relaxation as determined by People and Bean [24] is around 260 nm. Similarly, the People and Bean metastable critical thickness for plastic relaxation of a single Si0.69Ge0.31 layer itself is around 60 nm (versus 25 nm in our case). It would thus seem that (with our growth protocol)

the People and Bean curve is too optimistic for our {Si0.69Ge0.31/Si} superlattices. On the other hand, the critical thickness for plastic relaxation of the strain for a Si0.83Ge0.17 alloy or a single Si0.69Ge0.31 layer through the mechanical equilibrium theory of Matthews et al. [25] are much lower than in our case: 16 nm or 8 nm. Such a critical analysis retrospectively highlights the need for the Section 6.1 study, i.e. the acquisition for each growth condition and stack of a specific critical thickness for plastic relaxation data bank.

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7. Conclusion The aim being to grow in the near future regular Si/SiGe superlattices that will serve as the core of multi bridge channel field effect transistors, we have studied in reduced pressure chemical vapor deposition the growth kinetics of Si and Si0.8Ge0.2 on bulk Si(0 0 1) and on SOI (100 nm buried oxide/ 20 nm Si over-layer) substrates. We have for this grown miscellaneous Si/ Si0.8Ge0.2 superlattices (in-between 3 and 5 periods, Si0.8Ge0.2 (Si) layer thickness in-between 14 and 28 nm (9 and 32 nm)) on both types of substrates using a dichlorosilane+germane gaseous chemistry. The growth temperatures adopted (650 1C for Si0.8Ge0.2, 700 1C for Si) were such that no elastic or plastic relaxation of the strain occurred in those stacks, as attested by X-ray diffraction and atomic force microscopy. The individual layer thickness as well as the Ge concentration, determined by secondary ions mass spectrometry, were cross-checked on bulk wafers with XRD, with a good agreement in-between the two techniques. Whereas the growth rates and Ge concentration were as expected nearly constant on bulk Si(0 0 1), a sharp decrease of the Si and SiGe growth rate (from 2.6 down to 1.85 nm min
1 and from 11 down to 8.5 nm min
1), together with an increase of the Ge concentration (from 20.2% up to 21.4%) occurred on SOI as the deposited thickness increased from zero up to more than 100 nm. Such behaviors are most likely associated to a 12–13 1C drop in the SOI surface temperature as growth proceeds. For even thicker stacks, the Si growth rate on SOI increased back up to 2.15 nm min
1 (5 1C re-increase of the surface temperature) for slightly less than 200 nm deposited. Such a trend is linked to the fact that for really thick stacks on SOI, we converge towards a bulk-like configuration. Finally, we have investigated through a combined XRD and AFM study the critical thickness for plastic relaxation in 3 periods SiGe/Si superlattices grown on bulk Si(0 0 1) with a Ge content equal either to 20 or to 31%. The Si layer thickness being in all cases 22 nm, we have found a critical thickness for plastic relaxation of the order of

25 nm for Si0.69Ge0.31. By contrast, even for Si0.80Ge0.20 layers as thick as 39.8 nm, no detectable plastic relaxation occurred. This work, carried out inside the NaNoTec and the Si Technology Platform Departments of LETI, CEA-Grenoble, was funded in part by the Alliance (STMicroelectronics, Philips and Freescale Semiconductors) and by the European NanoCMOS IST Project. J.M. Fabri and M. Burdin are gratefully acknowledged for the SEM images and for the XRD experiments, respectively. The authors would also like to express their thanks to G. Rabille´ and S. Rousseau for their help in operating and maintaining the Epi Centura.

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