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Guard change: what the new Z280 can actually do
(Texas lnstrum. Inc., Dallas, TX, USA) 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25-27 Feb. 1987 (Coral Gables, FL, USA: Lewis Winner, Feb. 1987), pp. 202203, 402 A 32-b LISP processor has been integrated onto a I cm • 1 cm chip in a 1.25 lam DLM CMOS process. The chip contains 553687 transistors including 6 RAMs totaling 114-Kb, has 224 pins, and is packaged in a custom pin grid array. The processor implements a microcoded architecture compatible with an earlier LISP design. Microcode is contained in up to 32K X 64 b of external vMtable control store. The execution unit consists primarily of an ALU and 32-b barrel shifter/ masker. Booth's algorithm allows a 2 X 32-b multiply microinstruction. A IK • 32-b RAM (A-memory) provides one source for the execution unit. The PDL memory stores the top IK words of stack on chip, eliminating virtual memory references otherwise required to access these variables or store them during function cells. Separate adders compute effective addresses for common macroinstruction addressing modes using virtual memory and the on-chip stack. Dispatch memory contains branch tables that allow an up-to-128-way microinstruction branch to run as quickly as a simple jump. A macroinstruction prefetch unit prefetches up to four 16-b macroinstructions ahead, and statically follows branches. (2 refs.) A CMOS chip pair for digital TV S SUZUKI, K KAWAI, K MURAMATSU, T MAKINO, S SAYI (Toshiba Microelectron. Center, Kawasaki, Japan) 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25-27 Feb. 1987 (Coral Gables, FL, USA: Lewis Winner, Feb. 1987), pp. 204205, 403 A pair of CMOS chips that provide the baseband functions required for digital TV and meet the above requirements of high picture quality and flexibility for fine colour-tuning is described. The first chip is an 8-b video processor with a 2H dynamic RAM delay-line that provides the signal processing for the luminance and colour signals, while the second chip serves as a phase-lock-loop clamp and deflection and horizontal and vertical synch controller. To accommodate the 195K transistors in ~'o plastic packages, a 1.5 lam double-layer metal CMOS technology has been selected. These integrated circuits were designed to operate at 4 fse of the NTSC/PAL system (14.3 MHz/17.7 MHz). Combinational logic is used. (2 refs.) Pipelined VLSI systolic array and algorithm for digital filtering R E SIFERD (Dept. of Electr. Syst. Eng., Wright State Univ., Dayton, OH, USA) Int. J. Mini & MicrocompuL (USA), vol. 9, no. 1, pp. 2022 (1987) The signal processing task for the finite impulse response filter is particularly suited to a pipeline systolic
array. An algorithm is presented for a linear phase FIR filter signal processing task using a pipelined array of highly concurrent VLSI processors. Pipelining, combined x~ith concurrent processing at eae~ stage, leads to a highly efficient architecture with regard to maximising throughput and filter frequency. (7 refs.) Novel systolic architecture of fast biased polynominal transform S S WANG, T P LIN, J L WU (Dept. of Electr. Eng.,, Tatung Inst. of Technol., Taipei, Taiwan) Int. J. Mini & MicrocompuL (USA), vol. 9, no. 1, pp.~2831 (1987) A highly regular systolic architecture for fast biased polynominal transform is developed. The architecture is very suited for VLSI implementation due to its regularity, modularity and local interconnection. Finally, a scheme of prime-length 2D convolver based on fast biased polynominal transform is proposed. It is demonstrated that there is considerable simplification in this architecture as compred to the conventional parallel-pipeline approach. (7 refs.) A microprocessor subsystem for calculating crosscorrelation functions H JANOCHA, A HAUPT (Hannover Univ, Germany) Elektronik(Germany), vol. 36, no. 13, pp. 111-112, 114116 (26 June 1987). In German. The article sketches the mathematical basis of the problem of calculating crnss-correlation functions of series of observations, and describes the use of the 8086 microprocessor for this purpose. It analyses the neccssary mathematical algorithms, derives a general specification for the necessary hardware, and describes the realisation of the practical system with the help of a signal processor from the TI TMS 320 family. The performance ofthe system is discussed and possibilities of further improved devices using other signal processors are indicated. (9 refs.) C.J.O.G. VLSl-architectures for reai-timc-mnltitask-operating systems G KLEIN-HESSLING Elektronik (Germany), vol. 36, no. 16, pp. 52-58 (7 Aug. 1987). In German. Real-time-operating systems for universal processors are not always fast enough to meet special demands. The author demonstrates that the reaction time can be shortened by use of additional hardware on the chip. The explanations are centered on modular architectures for realisation of the task scheduling and the design of the register banL (11 refs.) K.A.K. Guard change: what the new Z280 can actually do Elektron. Prax. (Germany), vol. 22, no. 6, pp. 34-36, 41-42 (June 1987). In German. The architecture of the 161bit microprocessor operating with an extended addressing and using two operational modes for a system or user is discussed. Additional devices are connectable to the CPLI and the MMIJ, and
5[5
two different bus systems are included, one providing the burst mode run. The operational speed of the Z280 is enhanced by the cache memory, and the CPU with the programmable peripheral device on the chip allows the control processes to be carded out. LG.
The fast microprocessor [32-bit microprocessor Am2900] L NACHTMANN Chip (Germany), no. 7, pp. 36-38 (July 1987). In German. The design operates with the three-address RISC architecture using a large set of local and global registers. The local register addressing is carded out through the stack for intermediate storage based on the principle of propagation time-stack-cache memory. In addition, register banking ensures rapid context change. The risk of interferences is minimised with the fourstage pipelining, while speed of the process is enhanced with the virtual storage and with the arithmetic unit-
I.G.
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A BiCMOS image signal processor ~ith line memories Y KOBAYASHI, T FUKUSHIMA, S MIURA, M KANASAKI, K HIRASAWA (Hitachi Res. Lab., Ibaraki, Japan), K ASADA, J IDE,4~'YAMASAKI, Y TANIHARA 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25-27 Feb. 1987 (Coral Gables, FL, USA: Lewis Winner, Feb. 1987), pp. 182183, 392 The processor has been designed to perform twodimensional basic image processing, but with t~'o updated modifications. To achieve real-time processing of up to 512 • 512 pixel noninterlaced TV images, the processor has been fabricated by a 1.8 lam BiCMOS process to provide a 25 MHz/pixel operating frequency. Additionally, the device has a stand-alone capability as a one-chip image processor. Two line memories have been integrated on the chip and a time division method is implemented. As a result, spatial image operations such as a 3 • 3 spatial convolution can be carded out without additional circuitry. (2 refs.)
array. An algorithm is presented for a linear phase FIR filter signal processing task using a pipelined array of highly concurrent VLSI processors. Pipelining, combined x~ith concurrent processing at eae~ stage, leads to a highly efficient architecture with regard to maximising throughput and filter frequency. (7 refs.) Novel systolic architecture of fast biased polynominal transform S S WANG, T P LIN, J L WU (Dept. of Electr. Eng.,, Tatung Inst. of Technol., Taipei, Taiwan) Int. J. Mini & MicrocompuL (USA), vol. 9, no. 1, pp.~2831 (1987) A highly regular systolic architecture for fast biased polynominal transform is developed. The architecture is very suited for VLSI implementation due to its regularity, modularity and local interconnection. Finally, a scheme of prime-length 2D convolver based on fast biased polynominal transform is proposed. It is demonstrated that there is considerable simplification in this architecture as compred to the conventional parallel-pipeline approach. (7 refs.) A microprocessor subsystem for calculating crosscorrelation functions H JANOCHA, A HAUPT (Hannover Univ, Germany) Elektronik(Germany), vol. 36, no. 13, pp. 111-112, 114116 (26 June 1987). In German. The article sketches the mathematical basis of the problem of calculating crnss-correlation functions of series of observations, and describes the use of the 8086 microprocessor for this purpose. It analyses the neccssary mathematical algorithms, derives a general specification for the necessary hardware, and describes the realisation of the practical system with the help of a signal processor from the TI TMS 320 family. The performance ofthe system is discussed and possibilities of further improved devices using other signal processors are indicated. (9 refs.) C.J.O.G. VLSl-architectures for reai-timc-mnltitask-operating systems G KLEIN-HESSLING Elektronik (Germany), vol. 36, no. 16, pp. 52-58 (7 Aug. 1987). In German. Real-time-operating systems for universal processors are not always fast enough to meet special demands. The author demonstrates that the reaction time can be shortened by use of additional hardware on the chip. The explanations are centered on modular architectures for realisation of the task scheduling and the design of the register banL (11 refs.) K.A.K. Guard change: what the new Z280 can actually do Elektron. Prax. (Germany), vol. 22, no. 6, pp. 34-36, 41-42 (June 1987). In German. The architecture of the 161bit microprocessor operating with an extended addressing and using two operational modes for a system or user is discussed. Additional devices are connectable to the CPLI and the MMIJ, and
5[5
two different bus systems are included, one providing the burst mode run. The operational speed of the Z280 is enhanced by the cache memory, and the CPU with the programmable peripheral device on the chip allows the control processes to be carded out. LG.
The fast microprocessor [32-bit microprocessor Am2900] L NACHTMANN Chip (Germany), no. 7, pp. 36-38 (July 1987). In German. The design operates with the three-address RISC architecture using a large set of local and global registers. The local register addressing is carded out through the stack for intermediate storage based on the principle of propagation time-stack-cache memory. In addition, register banking ensures rapid context change. The risk of interferences is minimised with the fourstage pipelining, while speed of the process is enhanced with the virtual storage and with the arithmetic unit-
I.G.
56
A BiCMOS image signal processor ~ith line memories Y KOBAYASHI, T FUKUSHIMA, S MIURA, M KANASAKI, K HIRASAWA (Hitachi Res. Lab., Ibaraki, Japan), K ASADA, J IDE,4~'YAMASAKI, Y TANIHARA 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25-27 Feb. 1987 (Coral Gables, FL, USA: Lewis Winner, Feb. 1987), pp. 182183, 392 The processor has been designed to perform twodimensional basic image processing, but with t~'o updated modifications. To achieve real-time processing of up to 512 • 512 pixel noninterlaced TV images, the processor has been fabricated by a 1.8 lam BiCMOS process to provide a 25 MHz/pixel operating frequency. Additionally, the device has a stand-alone capability as a one-chip image processor. Two line memories have been integrated on the chip and a time division method is implemented. As a result, spatial image operations such as a 3 • 3 spatial convolution can be carded out without additional circuitry. (2 refs.)